target-openrisc/cpu.h

   1 /*
   2  * OpenRISC virtual CPU header.
   3  *
   4  * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef CPU_OPENRISC_H
  21 #define CPU_OPENRISC_H
  22
  23 #define TARGET_LONG_BITS 32
  24 #define ELF_MACHINE    EM_OPENRISC
  25
  26 #define CPUArchState struct CPUOpenRISCState
  27
  28 /* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl.  */
  29 struct OpenRISCCPU;
  30
  31 #include "config.h"
  32 #include "qemu-common.h"
  33 #include "cpu-defs.h"
  34 #include "softfloat.h"
  35 #include "qemu/cpu.h"
  36 #include "error.h"
  37
  38 #define TYPE_OPENRISC_CPU "or32-cpu"
  39
  40 #define OPENRISC_CPU_CLASS(klass) \
  41     OBJECT_CLASS_CHECK(OpenRISCCPUClass, (klass), TYPE_OPENRISC_CPU)
  42 #define OPENRISC_CPU(obj) \
  43     OBJECT_CHECK(OpenRISCCPU, (obj), TYPE_OPENRISC_CPU)
  44 #define OPENRISC_CPU_GET_CLASS(obj) \
  45     OBJECT_GET_CLASS(OpenRISCCPUClass, (obj), TYPE_OPENRISC_CPU)
  46
  47 /**
  48  * OpenRISCCPUClass:
  49  * @parent_reset: The parent class' reset handler.
  50  *
  51  * A OpenRISC CPU model.
  52  */
  53 typedef struct OpenRISCCPUClass {
  54     /*< private >*/
  55     CPUClass parent_class;
  56     /*< public >*/
  57
  58     void (*parent_reset)(CPUState *cpu);
  59 } OpenRISCCPUClass;
  60
  61 #define NB_MMU_MODES    3
  62
  63 enum {
  64     MMU_NOMMU_IDX = 0,
  65     MMU_SUPERVISOR_IDX = 1,
  66     MMU_USER_IDX = 2,
  67 };
  68
  69 #define TARGET_PAGE_BITS 13
  70
  71 #define TARGET_PHYS_ADDR_SPACE_BITS 32
  72 #define TARGET_VIRT_ADDR_SPACE_BITS 32
  73
  74 #define SET_FP_CAUSE(reg, v)    do {\
  75                                     (reg) = ((reg) & ~(0x3f << 12)) | \
  76                                             ((v & 0x3f) << 12);\
  77                                 } while (0)
  78 #define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
  79 #define UPDATE_FP_FLAGS(reg, v)   do {\
  80                                       (reg) |= ((v & 0x1f) << 2);\
  81                                   } while (0)
  82
  83 /* Internal flags, delay slot flag */
  84 #define D_FLAG    1
  85
  86 /* Registers */
  87 enum {
  88     R0 = 0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10,
  89     R11, R12, R13, R14, R15, R16, R17, R18, R19, R20,
  90     R21, R22, R23, R24, R25, R26, R27, R28, R29, R30,
  91     R31
  92 };
  93
  94 /* Register aliases */
  95 enum {
  96     R_ZERO = R0,
  97     R_SP = R1,
  98     R_FP = R2,
  99     R_LR = R9,
 100     R_RV = R11,
 101     R_RVH = R12
 102 };
 103
 104 /* Unit presece register */
 105 enum {
 106     UPR_UP = (1 << 0),
 107     UPR_DCP = (1 << 1),
 108     UPR_ICP = (1 << 2),
 109     UPR_DMP = (1 << 3),
 110     UPR_IMP = (1 << 4),
 111     UPR_MP = (1 << 5),
 112     UPR_DUP = (1 << 6),
 113     UPR_PCUR = (1 << 7),
 114     UPR_PMP = (1 << 8),
 115     UPR_PICP = (1 << 9),
 116     UPR_TTP = (1 << 10),
 117     UPR_CUP = (255 << 24),
 118 };
 119
 120 /* CPU configure register */
 121 enum {
 122     CPUCFGR_NSGF = (15 << 0),
 123     CPUCFGR_CGF = (1 << 4),
 124     CPUCFGR_OB32S = (1 << 5),
 125     CPUCFGR_OB64S = (1 << 6),
 126     CPUCFGR_OF32S = (1 << 7),
 127     CPUCFGR_OF64S = (1 << 8),
 128     CPUCFGR_OV64S = (1 << 9),
 129 };
 130
 131 /* DMMU configure register */
 132 enum {
 133     DMMUCFGR_NTW = (3 << 0),
 134     DMMUCFGR_NTS = (7 << 2),
 135     DMMUCFGR_NAE = (7 << 5),
 136     DMMUCFGR_CRI = (1 << 8),
 137     DMMUCFGR_PRI = (1 << 9),
 138     DMMUCFGR_TEIRI = (1 << 10),
 139     DMMUCFGR_HTR = (1 << 11),
 140 };
 141
 142 /* IMMU configure register */
 143 enum {
 144     IMMUCFGR_NTW = (3 << 0),
 145     IMMUCFGR_NTS = (7 << 2),
 146     IMMUCFGR_NAE = (7 << 5),
 147     IMMUCFGR_CRI = (1 << 8),
 148     IMMUCFGR_PRI = (1 << 9),
 149     IMMUCFGR_TEIRI = (1 << 10),
 150     IMMUCFGR_HTR = (1 << 11),
 151 };
 152
 153 /* Float point control status register */
 154 enum {
 155     FPCSR_FPEE = 1,
 156     FPCSR_RM = (3 << 1),
 157     FPCSR_OVF = (1 << 3),
 158     FPCSR_UNF = (1 << 4),
 159     FPCSR_SNF = (1 << 5),
 160     FPCSR_QNF = (1 << 6),
 161     FPCSR_ZF = (1 << 7),
 162     FPCSR_IXF = (1 << 8),
 163     FPCSR_IVF = (1 << 9),
 164     FPCSR_INF = (1 << 10),
 165     FPCSR_DZF = (1 << 11),
 166 };
 167
 168 /* Exceptions indices */
 169 enum {
 170     EXCP_RESET    = 0x1,
 171     EXCP_BUSERR   = 0x2,
 172     EXCP_DPF      = 0x3,
 173     EXCP_IPF      = 0x4,
 174     EXCP_TICK     = 0x5,
 175     EXCP_ALIGN    = 0x6,
 176     EXCP_ILLEGAL  = 0x7,
 177     EXCP_INT      = 0x8,
 178     EXCP_DTLBMISS = 0x9,
 179     EXCP_ITLBMISS = 0xa,
 180     EXCP_RANGE    = 0xb,
 181     EXCP_SYSCALL  = 0xc,
 182     EXCP_FPE      = 0xd,
 183     EXCP_TRAP     = 0xe,
 184     EXCP_NR,
 185 };
 186
 187 /* Supervisor register */
 188 enum {
 189     SR_SM = (1 << 0),
 190     SR_TEE = (1 << 1),
 191     SR_IEE = (1 << 2),
 192     SR_DCE = (1 << 3),
 193     SR_ICE = (1 << 4),
 194     SR_DME = (1 << 5),
 195     SR_IME = (1 << 6),
 196     SR_LEE = (1 << 7),
 197     SR_CE  = (1 << 8),
 198     SR_F   = (1 << 9),
 199     SR_CY  = (1 << 10),
 200     SR_OV  = (1 << 11),
 201     SR_OVE = (1 << 12),
 202     SR_DSX = (1 << 13),
 203     SR_EPH = (1 << 14),
 204     SR_FO  = (1 << 15),
 205     SR_SUMRA = (1 << 16),
 206     SR_SCE = (1 << 17),
 207 };
 208
 209 /* OpenRISC Hardware Capabilities */
 210 enum {
 211     OPENRISC_FEATURE_NSGF = (15 << 0),
 212     OPENRISC_FEATURE_CGF = (1 << 4),
 213     OPENRISC_FEATURE_OB32S = (1 << 5),
 214     OPENRISC_FEATURE_OB64S = (1 << 6),
 215     OPENRISC_FEATURE_OF32S = (1 << 7),
 216     OPENRISC_FEATURE_OF64S = (1 << 8),
 217     OPENRISC_FEATURE_OV64S = (1 << 9),
 218 };
 219
 220 /* TLB size */
 221 enum {
 222     DTLB_WAYS = 1,
 223     DTLB_SIZE = 64,
 224     DTLB_MASK = (DTLB_SIZE-1),
 225     ITLB_WAYS = 1,
 226     ITLB_SIZE = 64,
 227     ITLB_MASK = (ITLB_SIZE-1),
 228 };
 229
 230 /* TLB prot */
 231 enum {
 232     URE = (1 << 6),
 233     UWE = (1 << 7),
 234     SRE = (1 << 8),
 235     SWE = (1 << 9),
 236
 237     SXE = (1 << 6),
 238     UXE = (1 << 7),
 239 };
 240
 241 /* check if tlb available */
 242 enum {
 243     TLBRET_INVALID = -3,
 244     TLBRET_NOMATCH = -2,
 245     TLBRET_BADADDR = -1,
 246     TLBRET_MATCH = 0
 247 };
 248
 249 typedef struct OpenRISCTLBEntry {
 250     uint32_t mr;
 251     uint32_t tr;
 252 } OpenRISCTLBEntry;
 253
 254 #ifndef CONFIG_USER_ONLY
 255 typedef struct CPUOpenRISCTLBContext {
 256     OpenRISCTLBEntry itlb[ITLB_WAYS][ITLB_SIZE];
 257     OpenRISCTLBEntry dtlb[DTLB_WAYS][DTLB_SIZE];
 258
 259     int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu,
 260                                          target_phys_addr_t *physical,
 261                                          int *prot,
 262                                          target_ulong address, int rw);
 263     int (*cpu_openrisc_map_address_data)(struct OpenRISCCPU *cpu,
 264                                          target_phys_addr_t *physical,
 265                                          int *prot,
 266                                          target_ulong address, int rw);
 267 } CPUOpenRISCTLBContext;
 268 #endif
 269
 270 typedef struct CPUOpenRISCState {
 271     target_ulong gpr[32];     /* General registers */
 272     target_ulong pc;          /* Program counter */
 273     target_ulong npc;         /* Next PC */
 274     target_ulong ppc;         /* Prev PC */
 275     target_ulong jmp_pc;      /* Jump PC */
 276
 277     target_ulong machi;       /* Multiply register MACHI */
 278     target_ulong maclo;       /* Multiply register MACLO */
 279
 280     target_ulong fpmaddhi;    /* Multiply and add float register FPMADDHI */
 281     target_ulong fpmaddlo;    /* Multiply and add float register FPMADDLO */
 282
 283     target_ulong epcr;        /* Exception PC register */
 284     target_ulong eear;        /* Exception EA register */
 285
 286     uint32_t sr;              /* Supervisor register */
 287     uint32_t vr;              /* Version register */
 288     uint32_t upr;             /* Unit presence register */
 289     uint32_t cpucfgr;         /* CPU configure register */
 290     uint32_t dmmucfgr;        /* DMMU configure register */
 291     uint32_t immucfgr;        /* IMMU configure register */
 292     uint32_t esr;             /* Exception supervisor register */
 293     uint32_t fpcsr;           /* Float register */
 294     float_status fp_status;
 295
 296     uint32_t flags;           /* cpu_flags, we only use it for exception
 297                                  in solt so far.  */
 298     uint32_t btaken;          /* the SR_F bit */
 299
 300     CPU_COMMON
 301
 302 #ifndef CONFIG_USER_ONLY
 303     CPUOpenRISCTLBContext * tlb;
 304
 305     struct QEMUTimer *timer;
 306     uint32_t ttmr;          /* Timer tick mode register */
 307     uint32_t ttcr;          /* Timer tick count register */
 308
 309     uint32_t picmr;         /* Interrupt mask register */
 310     uint32_t picsr;         /* Interrupt contrl register*/
 311 #endif
 312 } CPUOpenRISCState;
 313
 314 /**
 315  * OpenRISCCPU:
 316  * @env: #CPUOpenRISCState
 317  *
 318  * A OpenRISC CPU.
 319  */
 320 typedef struct OpenRISCCPU {
 321     /*< private >*/
 322     CPUState parent_obj;
 323     /*< public >*/
 324
 325     CPUOpenRISCState env;
 326
 327     uint32_t feature;       /* CPU Capabilities */
 328 } OpenRISCCPU;
 329
 330 static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpenRISCState *env)
 331 {
 332     return OPENRISC_CPU(container_of(env, OpenRISCCPU, env));
 333 }
 334
 335 #define ENV_GET_CPU(e) CPU(openrisc_env_get_cpu(e))
 336
 337 OpenRISCCPU *cpu_openrisc_init(const char *cpu_model);
 338 void openrisc_cpu_realize(Object *obj, Error **errp);
 339
 340 void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf);
 341 int cpu_openrisc_exec(CPUOpenRISCState *s);
 342 void do_interrupt(CPUOpenRISCState *env);
 343 void openrisc_translate_init(void);
 344 int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env,
 345                                   target_ulong address,
 346                                   int rw, int mmu_idx);
 347
 348 #define cpu_list cpu_openrisc_list
 349 #define cpu_exec cpu_openrisc_exec
 350 #define cpu_gen_code cpu_openrisc_gen_code
 351 #define cpu_handle_mmu_fault cpu_openrisc_handle_mmu_fault
 352
 353 #ifndef CONFIG_USER_ONLY
 354 void cpu_openrisc_mmu_init(OpenRISCCPU *cpu);
 355 int cpu_openrisc_get_phys_nommu(OpenRISCCPU *cpu,
 356                                 target_phys_addr_t *physical,
 357                                 int *prot, target_ulong address, int rw);
 358 int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu,
 359                                target_phys_addr_t *physical,
 360                                int *prot, target_ulong address, int rw);
 361 int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu,
 362                                target_phys_addr_t *physical,
 363                                int *prot, target_ulong address, int rw);
 364 #endif
 365
 366 static inline CPUOpenRISCState *cpu_init(const char *cpu_model)
 367 {
 368     OpenRISCCPU *cpu = cpu_openrisc_init(cpu_model);
 369     if (cpu) {
 370         return &cpu->env;
 371     }
 372     return NULL;
 373 }
 374
 375 #include "cpu-all.h"
 376
 377 static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env,
 378                                         target_ulong *pc,
 379                                         target_ulong *cs_base, int *flags)
 380 {
 381     *pc = env->pc;
 382     *cs_base = 0;
 383     /* D_FLAG -- branch instruction exception */
 384     *flags = (env->flags & D_FLAG);
 385 }
 386
 387 static inline int cpu_mmu_index(CPUOpenRISCState *env)
 388 {
 389     if (!(env->sr & SR_IME)) {
 390         return MMU_NOMMU_IDX;
 391     }
 392     return (env->sr & SR_SM) == 0 ? MMU_USER_IDX : MMU_SUPERVISOR_IDX;
 393 }
 394
 395 static inline bool cpu_has_work(CPUOpenRISCState *env)
 396 {
 397     return true;
 398 }
 399
 400 #include "exec-all.h"
 401
 402 static inline target_ulong cpu_get_pc(CPUOpenRISCState *env)
 403 {
 404     return env->pc;
 405 }
 406
 407 static inline void cpu_pc_from_tb(CPUOpenRISCState *env, TranslationBlock *tb)
 408 {
 409     env->pc = tb->pc;
 410 }
 411
 412 #endif /* CPU_OPENRISC_H */