target-openrisc/cpu.h

   1 /*
   2  * OpenRISC virtual CPU header.
   3  *
   4  * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef CPU_OPENRISC_H
  21 #define CPU_OPENRISC_H
  22
  23 #define TARGET_LONG_BITS 32
  24 #define ELF_MACHINE    EM_OPENRISC
  25
  26 #define CPUArchState struct CPUOpenRISCState
  27
  28 #include "config.h"
  29 #include "qemu-common.h"
  30 #include "cpu-defs.h"
  31 #include "softfloat.h"
  32 #include "qemu/cpu.h"
  33 #include "error.h"
  34
  35 #define TYPE_OPENRISC_CPU "or32-cpu"
  36
  37 #define OPENRISC_CPU_CLASS(klass) \
  38     OBJECT_CLASS_CHECK(OpenRISCCPUClass, (klass), TYPE_OPENRISC_CPU)
  39 #define OPENRISC_CPU(obj) \
  40     OBJECT_CHECK(OpenRISCCPU, (obj), TYPE_OPENRISC_CPU)
  41 #define OPENRISC_CPU_GET_CLASS(obj) \
  42     OBJECT_GET_CLASS(OpenRISCCPUClass, (obj), TYPE_OPENRISC_CPU)
  43
  44 /**
  45  * OpenRISCCPUClass:
  46  * @parent_reset: The parent class' reset handler.
  47  *
  48  * A OpenRISC CPU model.
  49  */
  50 typedef struct OpenRISCCPUClass {
  51     /*< private >*/
  52     CPUClass parent_class;
  53     /*< public >*/
  54
  55     void (*parent_reset)(CPUState *cpu);
  56 } OpenRISCCPUClass;
  57
  58 #define NB_MMU_MODES    3
  59
  60 #define TARGET_PAGE_BITS 13
  61
  62 #define TARGET_PHYS_ADDR_SPACE_BITS 32
  63 #define TARGET_VIRT_ADDR_SPACE_BITS 32
  64
  65 #define SET_FP_CAUSE(reg, v)    do {\
  66                                     (reg) = ((reg) & ~(0x3f << 12)) | \
  67                                             ((v & 0x3f) << 12);\
  68                                 } while (0)
  69 #define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
  70 #define UPDATE_FP_FLAGS(reg, v)   do {\
  71                                       (reg) |= ((v & 0x1f) << 2);\
  72                                   } while (0)
  73
  74 /* Internal flags, delay slot flag */
  75 #define D_FLAG    1
  76
  77 /* Registers */
  78 enum {
  79     R0 = 0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10,
  80     R11, R12, R13, R14, R15, R16, R17, R18, R19, R20,
  81     R21, R22, R23, R24, R25, R26, R27, R28, R29, R30,
  82     R31
  83 };
  84
  85 /* Register aliases */
  86 enum {
  87     R_ZERO = R0,
  88     R_SP = R1,
  89     R_FP = R2,
  90     R_LR = R9,
  91     R_RV = R11,
  92     R_RVH = R12
  93 };
  94
  95 /* Unit presece register */
  96 enum {
  97     UPR_UP = (1 << 0),
  98     UPR_DCP = (1 << 1),
  99     UPR_ICP = (1 << 2),
 100     UPR_DMP = (1 << 3),
 101     UPR_IMP = (1 << 4),
 102     UPR_MP = (1 << 5),
 103     UPR_DUP = (1 << 6),
 104     UPR_PCUR = (1 << 7),
 105     UPR_PMP = (1 << 8),
 106     UPR_PICP = (1 << 9),
 107     UPR_TTP = (1 << 10),
 108     UPR_CUP = (255 << 24),
 109 };
 110
 111 /* CPU configure register */
 112 enum {
 113     CPUCFGR_NSGF = (15 << 0),
 114     CPUCFGR_CGF = (1 << 4),
 115     CPUCFGR_OB32S = (1 << 5),
 116     CPUCFGR_OB64S = (1 << 6),
 117     CPUCFGR_OF32S = (1 << 7),
 118     CPUCFGR_OF64S = (1 << 8),
 119     CPUCFGR_OV64S = (1 << 9),
 120 };
 121
 122 /* DMMU configure register */
 123 enum {
 124     DMMUCFGR_NTW = (3 << 0),
 125     DMMUCFGR_NTS = (7 << 2),
 126     DMMUCFGR_NAE = (7 << 5),
 127     DMMUCFGR_CRI = (1 << 8),
 128     DMMUCFGR_PRI = (1 << 9),
 129     DMMUCFGR_TEIRI = (1 << 10),
 130     DMMUCFGR_HTR = (1 << 11),
 131 };
 132
 133 /* IMMU configure register */
 134 enum {
 135     IMMUCFGR_NTW = (3 << 0),
 136     IMMUCFGR_NTS = (7 << 2),
 137     IMMUCFGR_NAE = (7 << 5),
 138     IMMUCFGR_CRI = (1 << 8),
 139     IMMUCFGR_PRI = (1 << 9),
 140     IMMUCFGR_TEIRI = (1 << 10),
 141     IMMUCFGR_HTR = (1 << 11),
 142 };
 143
 144 /* Float point control status register */
 145 enum {
 146     FPCSR_FPEE = 1,
 147     FPCSR_RM = (3 << 1),
 148     FPCSR_OVF = (1 << 3),
 149     FPCSR_UNF = (1 << 4),
 150     FPCSR_SNF = (1 << 5),
 151     FPCSR_QNF = (1 << 6),
 152     FPCSR_ZF = (1 << 7),
 153     FPCSR_IXF = (1 << 8),
 154     FPCSR_IVF = (1 << 9),
 155     FPCSR_INF = (1 << 10),
 156     FPCSR_DZF = (1 << 11),
 157 };
 158
 159 /* Exceptions indices */
 160 enum {
 161     EXCP_RESET    = 0x1,
 162     EXCP_BUSERR   = 0x2,
 163     EXCP_DPF      = 0x3,
 164     EXCP_IPF      = 0x4,
 165     EXCP_TICK     = 0x5,
 166     EXCP_ALIGN    = 0x6,
 167     EXCP_ILLEGAL  = 0x7,
 168     EXCP_INT      = 0x8,
 169     EXCP_DTLBMISS = 0x9,
 170     EXCP_ITLBMISS = 0xa,
 171     EXCP_RANGE    = 0xb,
 172     EXCP_SYSCALL  = 0xc,
 173     EXCP_FPE      = 0xd,
 174     EXCP_TRAP     = 0xe,
 175     EXCP_NR,
 176 };
 177
 178 /* Supervisor register */
 179 enum {
 180     SR_SM = (1 << 0),
 181     SR_TEE = (1 << 1),
 182     SR_IEE = (1 << 2),
 183     SR_DCE = (1 << 3),
 184     SR_ICE = (1 << 4),
 185     SR_DME = (1 << 5),
 186     SR_IME = (1 << 6),
 187     SR_LEE = (1 << 7),
 188     SR_CE  = (1 << 8),
 189     SR_F   = (1 << 9),
 190     SR_CY  = (1 << 10),
 191     SR_OV  = (1 << 11),
 192     SR_OVE = (1 << 12),
 193     SR_DSX = (1 << 13),
 194     SR_EPH = (1 << 14),
 195     SR_FO  = (1 << 15),
 196     SR_SUMRA = (1 << 16),
 197     SR_SCE = (1 << 17),
 198 };
 199
 200 /* OpenRISC Hardware Capabilities */
 201 enum {
 202     OPENRISC_FEATURE_NSGF = (15 << 0),
 203     OPENRISC_FEATURE_CGF = (1 << 4),
 204     OPENRISC_FEATURE_OB32S = (1 << 5),
 205     OPENRISC_FEATURE_OB64S = (1 << 6),
 206     OPENRISC_FEATURE_OF32S = (1 << 7),
 207     OPENRISC_FEATURE_OF64S = (1 << 8),
 208     OPENRISC_FEATURE_OV64S = (1 << 9),
 209 };
 210
 211 typedef struct CPUOpenRISCState {
 212     target_ulong gpr[32];     /* General registers */
 213     target_ulong pc;          /* Program counter */
 214     target_ulong npc;         /* Next PC */
 215     target_ulong ppc;         /* Prev PC */
 216     target_ulong jmp_pc;      /* Jump PC */
 217
 218     target_ulong machi;       /* Multiply register MACHI */
 219     target_ulong maclo;       /* Multiply register MACLO */
 220
 221     target_ulong fpmaddhi;    /* Multiply and add float register FPMADDHI */
 222     target_ulong fpmaddlo;    /* Multiply and add float register FPMADDLO */
 223
 224     target_ulong epcr;        /* Exception PC register */
 225     target_ulong eear;        /* Exception EA register */
 226
 227     uint32_t sr;              /* Supervisor register */
 228     uint32_t vr;              /* Version register */
 229     uint32_t upr;             /* Unit presence register */
 230     uint32_t cpucfgr;         /* CPU configure register */
 231     uint32_t dmmucfgr;        /* DMMU configure register */
 232     uint32_t immucfgr;        /* IMMU configure register */
 233     uint32_t esr;             /* Exception supervisor register */
 234     uint32_t fpcsr;           /* Float register */
 235     float_status fp_status;
 236
 237     uint32_t flags;           /* cpu_flags, we only use it for exception
 238                                  in solt so far.  */
 239     uint32_t btaken;          /* the SR_F bit */
 240
 241     CPU_COMMON
 242
 243 #ifndef CONFIG_USER_ONLY
 244     struct QEMUTimer *timer;
 245     uint32_t ttmr;          /* Timer tick mode register */
 246     uint32_t ttcr;          /* Timer tick count register */
 247
 248     uint32_t picmr;         /* Interrupt mask register */
 249     uint32_t picsr;         /* Interrupt contrl register*/
 250 #endif
 251 } CPUOpenRISCState;
 252
 253 /**
 254  * OpenRISCCPU:
 255  * @env: #CPUOpenRISCState
 256  *
 257  * A OpenRISC CPU.
 258  */
 259 typedef struct OpenRISCCPU {
 260     /*< private >*/
 261     CPUState parent_obj;
 262     /*< public >*/
 263
 264     CPUOpenRISCState env;
 265
 266     uint32_t feature;       /* CPU Capabilities */
 267 } OpenRISCCPU;
 268
 269 static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpenRISCState *env)
 270 {
 271     return OPENRISC_CPU(container_of(env, OpenRISCCPU, env));
 272 }
 273
 274 #define ENV_GET_CPU(e) CPU(openrisc_env_get_cpu(e))
 275
 276 OpenRISCCPU *cpu_openrisc_init(const char *cpu_model);
 277 void openrisc_cpu_realize(Object *obj, Error **errp);
 278
 279 void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf);
 280 int cpu_openrisc_exec(CPUOpenRISCState *s);
 281 void do_interrupt(CPUOpenRISCState *env);
 282 void openrisc_translate_init(void);
 283
 284 #define cpu_list cpu_openrisc_list
 285 #define cpu_exec cpu_openrisc_exec
 286 #define cpu_gen_code cpu_openrisc_gen_code
 287
 288 #ifndef CONFIG_USER_ONLY
 289 void cpu_openrisc_mmu_init(OpenRISCCPU *cpu);
 290 #endif
 291
 292 static inline CPUOpenRISCState *cpu_init(const char *cpu_model)
 293 {
 294     OpenRISCCPU *cpu = cpu_openrisc_init(cpu_model);
 295     if (cpu) {
 296         return &cpu->env;
 297     }
 298     return NULL;
 299 }
 300
 301 #include "cpu-all.h"
 302
 303 static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env,
 304                                         target_ulong *pc,
 305                                         target_ulong *cs_base, int *flags)
 306 {
 307     *pc = env->pc;
 308     *cs_base = 0;
 309     /* D_FLAG -- branch instruction exception */
 310     *flags = (env->flags & D_FLAG);
 311 }
 312
 313 static inline int cpu_mmu_index(CPUOpenRISCState *env)
 314 {
 315     return 0;
 316 }
 317
 318 static inline bool cpu_has_work(CPUOpenRISCState *env)
 319 {
 320     return true;
 321 }
 322
 323 #include "exec-all.h"
 324
 325 static inline target_ulong cpu_get_pc(CPUOpenRISCState *env)
 326 {
 327     return env->pc;
 328 }
 329
 330 static inline void cpu_pc_from_tb(CPUOpenRISCState *env, TranslationBlock *tb)
 331 {
 332     env->pc = tb->pc;
 333 }
 334
 335 #endif /* CPU_OPENRISC_H */