4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
5 * Feng Gao <gf91597@gmail.com>
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 #include "exec/exec-all.h"
23 #include "disas/disas.h"
25 #include "qemu-common.h"
28 #include "qemu/bitops.h"
34 #define OPENRISC_DISAS
37 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
39 # define LOG_DIS(...) do { } while (0)
42 typedef struct DisasContext
{
44 target_ulong pc
, ppc
, npc
;
45 uint32_t tb_flags
, synced_flags
, flags
;
48 int singlestep_enabled
;
49 uint32_t delayed_branch
;
52 static TCGv_ptr cpu_env
;
54 static TCGv cpu_R
[32];
56 static TCGv jmp_pc
; /* l.jr/l.jalr temp pc */
59 static TCGv_i32 env_btaken
; /* bf/bnf , F flag taken */
60 static TCGv_i32 fpcsr
;
61 static TCGv machi
, maclo
;
62 static TCGv fpmaddhi
, fpmaddlo
;
63 static TCGv_i32 env_flags
;
64 #include "exec/gen-icount.h"
66 void openrisc_translate_init(void)
68 static const char * const regnames
[] = {
69 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
70 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
71 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
72 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
76 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
77 cpu_sr
= tcg_global_mem_new(TCG_AREG0
,
78 offsetof(CPUOpenRISCState
, sr
), "sr");
79 env_flags
= tcg_global_mem_new_i32(TCG_AREG0
,
80 offsetof(CPUOpenRISCState
, flags
),
82 cpu_pc
= tcg_global_mem_new(TCG_AREG0
,
83 offsetof(CPUOpenRISCState
, pc
), "pc");
84 cpu_npc
= tcg_global_mem_new(TCG_AREG0
,
85 offsetof(CPUOpenRISCState
, npc
), "npc");
86 cpu_ppc
= tcg_global_mem_new(TCG_AREG0
,
87 offsetof(CPUOpenRISCState
, ppc
), "ppc");
88 jmp_pc
= tcg_global_mem_new(TCG_AREG0
,
89 offsetof(CPUOpenRISCState
, jmp_pc
), "jmp_pc");
90 env_btaken
= tcg_global_mem_new_i32(TCG_AREG0
,
91 offsetof(CPUOpenRISCState
, btaken
),
93 fpcsr
= tcg_global_mem_new_i32(TCG_AREG0
,
94 offsetof(CPUOpenRISCState
, fpcsr
),
96 machi
= tcg_global_mem_new(TCG_AREG0
,
97 offsetof(CPUOpenRISCState
, machi
),
99 maclo
= tcg_global_mem_new(TCG_AREG0
,
100 offsetof(CPUOpenRISCState
, maclo
),
102 fpmaddhi
= tcg_global_mem_new(TCG_AREG0
,
103 offsetof(CPUOpenRISCState
, fpmaddhi
),
105 fpmaddlo
= tcg_global_mem_new(TCG_AREG0
,
106 offsetof(CPUOpenRISCState
, fpmaddlo
),
108 for (i
= 0; i
< 32; i
++) {
109 cpu_R
[i
] = tcg_global_mem_new(TCG_AREG0
,
110 offsetof(CPUOpenRISCState
, gpr
[i
]),
115 /* Writeback SR_F transaltion-space to execution-space. */
116 static inline void wb_SR_F(void)
120 label
= gen_new_label();
121 tcg_gen_andi_tl(cpu_sr
, cpu_sr
, ~SR_F
);
122 tcg_gen_brcondi_tl(TCG_COND_EQ
, env_btaken
, 0, label
);
123 tcg_gen_ori_tl(cpu_sr
, cpu_sr
, SR_F
);
124 gen_set_label(label
);
127 static inline int zero_extend(unsigned int val
, int width
)
129 return val
& ((1 << width
) - 1);
132 static inline int sign_extend(unsigned int val
, int width
)
137 val
<<= TARGET_LONG_BITS
- width
;
140 sval
>>= TARGET_LONG_BITS
- width
;
144 static inline void gen_sync_flags(DisasContext
*dc
)
146 /* Sync the tb dependent flag between translate and runtime. */
147 if (dc
->tb_flags
!= dc
->synced_flags
) {
148 tcg_gen_movi_tl(env_flags
, dc
->tb_flags
);
149 dc
->synced_flags
= dc
->tb_flags
;
153 static void gen_exception(DisasContext
*dc
, unsigned int excp
)
155 TCGv_i32 tmp
= tcg_const_i32(excp
);
156 gen_helper_exception(cpu_env
, tmp
);
157 tcg_temp_free_i32(tmp
);
160 static void gen_illegal_exception(DisasContext
*dc
)
162 tcg_gen_movi_tl(cpu_pc
, dc
->pc
);
163 gen_exception(dc
, EXCP_ILLEGAL
);
164 dc
->is_jmp
= DISAS_UPDATE
;
167 /* not used yet, open it when we need or64. */
168 /*#ifdef TARGET_OPENRISC64
169 static void check_ob64s(DisasContext *dc)
171 if (!(dc->flags & CPUCFGR_OB64S)) {
172 gen_illegal_exception(dc);
176 static void check_of64s(DisasContext *dc)
178 if (!(dc->flags & CPUCFGR_OF64S)) {
179 gen_illegal_exception(dc);
183 static void check_ov64s(DisasContext *dc)
185 if (!(dc->flags & CPUCFGR_OV64S)) {
186 gen_illegal_exception(dc);
191 static void gen_goto_tb(DisasContext
*dc
, int n
, target_ulong dest
)
193 TranslationBlock
*tb
;
195 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) &&
196 likely(!dc
->singlestep_enabled
)) {
197 tcg_gen_movi_tl(cpu_pc
, dest
);
199 tcg_gen_exit_tb((uintptr_t)tb
+ n
);
201 tcg_gen_movi_tl(cpu_pc
, dest
);
202 if (dc
->singlestep_enabled
) {
203 gen_exception(dc
, EXCP_DEBUG
);
209 static void gen_jump(DisasContext
*dc
, uint32_t imm
, uint32_t reg
, uint32_t op0
)
212 int lab
= gen_new_label();
213 TCGv sr_f
= tcg_temp_new();
214 /* N26, 26bits imm */
215 tmp_pc
= sign_extend((imm
<<2), 26) + dc
->pc
;
216 tcg_gen_andi_tl(sr_f
, cpu_sr
, SR_F
);
218 if (op0
== 0x00) { /* l.j */
219 tcg_gen_movi_tl(jmp_pc
, tmp_pc
);
220 } else if (op0
== 0x01) { /* l.jal */
221 tcg_gen_movi_tl(cpu_R
[9], (dc
->pc
+ 8));
222 tcg_gen_movi_tl(jmp_pc
, tmp_pc
);
223 } else if (op0
== 0x03) { /* l.bnf */
224 tcg_gen_movi_tl(jmp_pc
, dc
->pc
+8);
225 tcg_gen_brcondi_i32(TCG_COND_EQ
, sr_f
, SR_F
, lab
);
226 tcg_gen_movi_tl(jmp_pc
, tmp_pc
);
228 } else if (op0
== 0x04) { /* l.bf */
229 tcg_gen_movi_tl(jmp_pc
, dc
->pc
+8);
230 tcg_gen_brcondi_i32(TCG_COND_NE
, sr_f
, SR_F
, lab
);
231 tcg_gen_movi_tl(jmp_pc
, tmp_pc
);
233 } else if (op0
== 0x11) { /* l.jr */
234 tcg_gen_mov_tl(jmp_pc
, cpu_R
[reg
]);
235 } else if (op0
== 0x12) { /* l.jalr */
236 tcg_gen_movi_tl(cpu_R
[9], (dc
->pc
+ 8));
237 tcg_gen_mov_tl(jmp_pc
, cpu_R
[reg
]);
239 gen_illegal_exception(dc
);
243 dc
->delayed_branch
= 2;
244 dc
->tb_flags
|= D_FLAG
;
248 static void dec_calc(DisasContext
*dc
, uint32_t insn
)
250 uint32_t op0
, op1
, op2
;
252 op0
= extract32(insn
, 0, 4);
253 op1
= extract32(insn
, 8, 2);
254 op2
= extract32(insn
, 6, 2);
255 ra
= extract32(insn
, 16, 5);
256 rb
= extract32(insn
, 11, 5);
257 rd
= extract32(insn
, 21, 5);
262 case 0x00: /* l.add */
263 LOG_DIS("l.add r%d, r%d, r%d\n", rd
, ra
, rb
);
265 int lab
= gen_new_label();
266 TCGv_i64 ta
= tcg_temp_new_i64();
267 TCGv_i64 tb
= tcg_temp_new_i64();
268 TCGv_i64 td
= tcg_temp_local_new_i64();
269 TCGv_i32 res
= tcg_temp_local_new_i32();
270 TCGv_i32 sr_ove
= tcg_temp_local_new_i32();
271 tcg_gen_extu_i32_i64(ta
, cpu_R
[ra
]);
272 tcg_gen_extu_i32_i64(tb
, cpu_R
[rb
]);
273 tcg_gen_add_i64(td
, ta
, tb
);
274 tcg_gen_trunc_i64_i32(res
, td
);
275 tcg_gen_shri_i64(td
, td
, 31);
276 tcg_gen_andi_i64(td
, td
, 0x3);
277 /* Jump to lab when no overflow. */
278 tcg_gen_brcondi_i64(TCG_COND_EQ
, td
, 0x0, lab
);
279 tcg_gen_brcondi_i64(TCG_COND_EQ
, td
, 0x3, lab
);
280 tcg_gen_ori_i32(cpu_sr
, cpu_sr
, (SR_OV
| SR_CY
));
281 tcg_gen_andi_i32(sr_ove
, cpu_sr
, SR_OVE
);
282 tcg_gen_brcondi_i32(TCG_COND_NE
, sr_ove
, SR_OVE
, lab
);
283 gen_exception(dc
, EXCP_RANGE
);
285 tcg_gen_mov_i32(cpu_R
[rd
], res
);
286 tcg_temp_free_i64(ta
);
287 tcg_temp_free_i64(tb
);
288 tcg_temp_free_i64(td
);
289 tcg_temp_free_i32(res
);
290 tcg_temp_free_i32(sr_ove
);
294 gen_illegal_exception(dc
);
299 case 0x0001: /* l.addc */
302 LOG_DIS("l.addc r%d, r%d, r%d\n", rd
, ra
, rb
);
304 int lab
= gen_new_label();
305 TCGv_i64 ta
= tcg_temp_new_i64();
306 TCGv_i64 tb
= tcg_temp_new_i64();
307 TCGv_i64 tcy
= tcg_temp_local_new_i64();
308 TCGv_i64 td
= tcg_temp_local_new_i64();
309 TCGv_i32 res
= tcg_temp_local_new_i32();
310 TCGv_i32 sr_cy
= tcg_temp_local_new_i32();
311 TCGv_i32 sr_ove
= tcg_temp_local_new_i32();
312 tcg_gen_extu_i32_i64(ta
, cpu_R
[ra
]);
313 tcg_gen_extu_i32_i64(tb
, cpu_R
[rb
]);
314 tcg_gen_andi_i32(sr_cy
, cpu_sr
, SR_CY
);
315 tcg_gen_extu_i32_i64(tcy
, sr_cy
);
316 tcg_gen_shri_i64(tcy
, tcy
, 10);
317 tcg_gen_add_i64(td
, ta
, tb
);
318 tcg_gen_add_i64(td
, td
, tcy
);
319 tcg_gen_trunc_i64_i32(res
, td
);
320 tcg_gen_shri_i64(td
, td
, 32);
321 tcg_gen_andi_i64(td
, td
, 0x3);
322 /* Jump to lab when no overflow. */
323 tcg_gen_brcondi_i64(TCG_COND_EQ
, td
, 0x0, lab
);
324 tcg_gen_brcondi_i64(TCG_COND_EQ
, td
, 0x3, lab
);
325 tcg_gen_ori_i32(cpu_sr
, cpu_sr
, (SR_OV
| SR_CY
));
326 tcg_gen_andi_i32(sr_ove
, cpu_sr
, SR_OVE
);
327 tcg_gen_brcondi_i32(TCG_COND_NE
, sr_ove
, SR_OVE
, lab
);
328 gen_exception(dc
, EXCP_RANGE
);
330 tcg_gen_mov_i32(cpu_R
[rd
], res
);
331 tcg_temp_free_i64(ta
);
332 tcg_temp_free_i64(tb
);
333 tcg_temp_free_i64(tcy
);
334 tcg_temp_free_i64(td
);
335 tcg_temp_free_i32(res
);
336 tcg_temp_free_i32(sr_cy
);
337 tcg_temp_free_i32(sr_ove
);
341 gen_illegal_exception(dc
);
346 case 0x0002: /* l.sub */
349 LOG_DIS("l.sub r%d, r%d, r%d\n", rd
, ra
, rb
);
351 int lab
= gen_new_label();
352 TCGv_i64 ta
= tcg_temp_new_i64();
353 TCGv_i64 tb
= tcg_temp_new_i64();
354 TCGv_i64 td
= tcg_temp_local_new_i64();
355 TCGv_i32 res
= tcg_temp_local_new_i32();
356 TCGv_i32 sr_ove
= tcg_temp_local_new_i32();
358 tcg_gen_extu_i32_i64(ta
, cpu_R
[ra
]);
359 tcg_gen_extu_i32_i64(tb
, cpu_R
[rb
]);
360 tcg_gen_sub_i64(td
, ta
, tb
);
361 tcg_gen_trunc_i64_i32(res
, td
);
362 tcg_gen_shri_i64(td
, td
, 31);
363 tcg_gen_andi_i64(td
, td
, 0x3);
364 /* Jump to lab when no overflow. */
365 tcg_gen_brcondi_i64(TCG_COND_EQ
, td
, 0x0, lab
);
366 tcg_gen_brcondi_i64(TCG_COND_EQ
, td
, 0x3, lab
);
367 tcg_gen_ori_i32(cpu_sr
, cpu_sr
, (SR_OV
| SR_CY
));
368 tcg_gen_andi_i32(sr_ove
, cpu_sr
, SR_OVE
);
369 tcg_gen_brcondi_i32(TCG_COND_NE
, sr_ove
, SR_OVE
, lab
);
370 gen_exception(dc
, EXCP_RANGE
);
372 tcg_gen_mov_i32(cpu_R
[rd
], res
);
373 tcg_temp_free_i64(ta
);
374 tcg_temp_free_i64(tb
);
375 tcg_temp_free_i64(td
);
376 tcg_temp_free_i32(res
);
377 tcg_temp_free_i32(sr_ove
);
381 gen_illegal_exception(dc
);
386 case 0x0003: /* l.and */
389 LOG_DIS("l.and r%d, r%d, r%d\n", rd
, ra
, rb
);
390 tcg_gen_and_tl(cpu_R
[rd
], cpu_R
[ra
], cpu_R
[rb
]);
393 gen_illegal_exception(dc
);
398 case 0x0004: /* l.or */
401 LOG_DIS("l.or r%d, r%d, r%d\n", rd
, ra
, rb
);
402 tcg_gen_or_tl(cpu_R
[rd
], cpu_R
[ra
], cpu_R
[rb
]);
405 gen_illegal_exception(dc
);
412 case 0x00: /* l.xor */
413 LOG_DIS("l.xor r%d, r%d, r%d\n", rd
, ra
, rb
);
414 tcg_gen_xor_tl(cpu_R
[rd
], cpu_R
[ra
], cpu_R
[rb
]);
417 gen_illegal_exception(dc
);
424 case 0x03: /* l.mul */
425 LOG_DIS("l.mul r%d, r%d, r%d\n", rd
, ra
, rb
);
426 if (ra
!= 0 && rb
!= 0) {
427 gen_helper_mul32(cpu_R
[rd
], cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
429 tcg_gen_movi_tl(cpu_R
[rd
], 0x0);
433 gen_illegal_exception(dc
);
440 case 0x03: /* l.div */
441 LOG_DIS("l.div r%d, r%d, r%d\n", rd
, ra
, rb
);
443 int lab0
= gen_new_label();
444 int lab1
= gen_new_label();
445 int lab2
= gen_new_label();
446 int lab3
= gen_new_label();
447 TCGv_i32 sr_ove
= tcg_temp_local_new_i32();
449 tcg_gen_ori_tl(cpu_sr
, cpu_sr
, (SR_OV
| SR_CY
));
450 tcg_gen_andi_tl(sr_ove
, cpu_sr
, SR_OVE
);
451 tcg_gen_brcondi_tl(TCG_COND_NE
, sr_ove
, SR_OVE
, lab0
);
452 gen_exception(dc
, EXCP_RANGE
);
455 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_R
[rb
],
457 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_R
[ra
],
459 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_R
[rb
],
462 tcg_gen_ori_tl(cpu_sr
, cpu_sr
, (SR_OV
| SR_CY
));
463 tcg_gen_andi_tl(sr_ove
, cpu_sr
, SR_OVE
);
464 tcg_gen_brcondi_tl(TCG_COND_NE
, sr_ove
, SR_OVE
, lab3
);
465 gen_exception(dc
, EXCP_RANGE
);
467 tcg_gen_div_tl(cpu_R
[rd
], cpu_R
[ra
], cpu_R
[rb
]);
470 tcg_temp_free_i32(sr_ove
);
475 gen_illegal_exception(dc
);
482 case 0x03: /* l.divu */
483 LOG_DIS("l.divu r%d, r%d, r%d\n", rd
, ra
, rb
);
485 int lab0
= gen_new_label();
486 int lab1
= gen_new_label();
487 int lab2
= gen_new_label();
488 TCGv_i32 sr_ove
= tcg_temp_local_new_i32();
490 tcg_gen_ori_tl(cpu_sr
, cpu_sr
, (SR_OV
| SR_CY
));
491 tcg_gen_andi_tl(sr_ove
, cpu_sr
, SR_OVE
);
492 tcg_gen_brcondi_tl(TCG_COND_NE
, sr_ove
, SR_OVE
, lab0
);
493 gen_exception(dc
, EXCP_RANGE
);
496 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_R
[rb
],
498 tcg_gen_ori_tl(cpu_sr
, cpu_sr
, (SR_OV
| SR_CY
));
499 tcg_gen_andi_tl(sr_ove
, cpu_sr
, SR_OVE
);
500 tcg_gen_brcondi_tl(TCG_COND_NE
, sr_ove
, SR_OVE
, lab2
);
501 gen_exception(dc
, EXCP_RANGE
);
503 tcg_gen_divu_tl(cpu_R
[rd
], cpu_R
[ra
], cpu_R
[rb
]);
506 tcg_temp_free_i32(sr_ove
);
511 gen_illegal_exception(dc
);
518 case 0x03: /* l.mulu */
519 LOG_DIS("l.mulu r%d, r%d, r%d\n", rd
, ra
, rb
);
520 if (rb
!= 0 && ra
!= 0) {
521 TCGv_i64 result
= tcg_temp_local_new_i64();
522 TCGv_i64 tra
= tcg_temp_local_new_i64();
523 TCGv_i64 trb
= tcg_temp_local_new_i64();
524 TCGv_i64 high
= tcg_temp_new_i64();
525 TCGv_i32 sr_ove
= tcg_temp_local_new_i32();
526 int lab
= gen_new_label();
527 /* Calculate the each result. */
528 tcg_gen_extu_i32_i64(tra
, cpu_R
[ra
]);
529 tcg_gen_extu_i32_i64(trb
, cpu_R
[rb
]);
530 tcg_gen_mul_i64(result
, tra
, trb
);
531 tcg_temp_free_i64(tra
);
532 tcg_temp_free_i64(trb
);
533 tcg_gen_shri_i64(high
, result
, TARGET_LONG_BITS
);
534 /* Overflow or not. */
535 tcg_gen_brcondi_i64(TCG_COND_EQ
, high
, 0x00000000, lab
);
536 tcg_gen_ori_tl(cpu_sr
, cpu_sr
, (SR_OV
| SR_CY
));
537 tcg_gen_andi_tl(sr_ove
, cpu_sr
, SR_OVE
);
538 tcg_gen_brcondi_tl(TCG_COND_NE
, sr_ove
, SR_OVE
, lab
);
539 gen_exception(dc
, EXCP_RANGE
);
541 tcg_temp_free_i64(high
);
542 tcg_gen_trunc_i64_tl(cpu_R
[rd
], result
);
543 tcg_temp_free_i64(result
);
544 tcg_temp_free_i32(sr_ove
);
546 tcg_gen_movi_tl(cpu_R
[rd
], 0);
551 gen_illegal_exception(dc
);
558 case 0x00: /* l.cmov */
559 LOG_DIS("l.cmov r%d, r%d, r%d\n", rd
, ra
, rb
);
561 int lab
= gen_new_label();
562 TCGv res
= tcg_temp_local_new();
563 TCGv sr_f
= tcg_temp_new();
564 tcg_gen_andi_tl(sr_f
, cpu_sr
, SR_F
);
565 tcg_gen_mov_tl(res
, cpu_R
[rb
]);
566 tcg_gen_brcondi_tl(TCG_COND_NE
, sr_f
, SR_F
, lab
);
567 tcg_gen_mov_tl(res
, cpu_R
[ra
]);
569 tcg_gen_mov_tl(cpu_R
[rd
], res
);
576 gen_illegal_exception(dc
);
583 case 0x00: /* l.ff1 */
584 LOG_DIS("l.ff1 r%d, r%d, r%d\n", rd
, ra
, rb
);
585 gen_helper_ff1(cpu_R
[rd
], cpu_R
[ra
]);
587 case 0x01: /* l.fl1 */
588 LOG_DIS("l.fl1 r%d, r%d, r%d\n", rd
, ra
, rb
);
589 gen_helper_fl1(cpu_R
[rd
], cpu_R
[ra
]);
593 gen_illegal_exception(dc
);
602 case 0x00: /* l.sll */
603 LOG_DIS("l.sll r%d, r%d, r%d\n", rd
, ra
, rb
);
604 tcg_gen_shl_tl(cpu_R
[rd
], cpu_R
[ra
], cpu_R
[rb
]);
606 case 0x01: /* l.srl */
607 LOG_DIS("l.srl r%d, r%d, r%d\n", rd
, ra
, rb
);
608 tcg_gen_shr_tl(cpu_R
[rd
], cpu_R
[ra
], cpu_R
[rb
]);
610 case 0x02: /* l.sra */
611 LOG_DIS("l.sra r%d, r%d, r%d\n", rd
, ra
, rb
);
612 tcg_gen_sar_tl(cpu_R
[rd
], cpu_R
[ra
], cpu_R
[rb
]);
614 case 0x03: /* l.ror */
615 LOG_DIS("l.ror r%d, r%d, r%d\n", rd
, ra
, rb
);
616 tcg_gen_rotr_tl(cpu_R
[rd
], cpu_R
[ra
], cpu_R
[rb
]);
620 gen_illegal_exception(dc
);
626 gen_illegal_exception(dc
);
635 case 0x00: /* l.exths */
636 LOG_DIS("l.exths r%d, r%d\n", rd
, ra
);
637 tcg_gen_ext16s_tl(cpu_R
[rd
], cpu_R
[ra
]);
639 case 0x01: /* l.extbs */
640 LOG_DIS("l.extbs r%d, r%d\n", rd
, ra
);
641 tcg_gen_ext8s_tl(cpu_R
[rd
], cpu_R
[ra
]);
643 case 0x02: /* l.exthz */
644 LOG_DIS("l.exthz r%d, r%d\n", rd
, ra
);
645 tcg_gen_ext16u_tl(cpu_R
[rd
], cpu_R
[ra
]);
647 case 0x03: /* l.extbz */
648 LOG_DIS("l.extbz r%d, r%d\n", rd
, ra
);
649 tcg_gen_ext8u_tl(cpu_R
[rd
], cpu_R
[ra
]);
653 gen_illegal_exception(dc
);
659 gen_illegal_exception(dc
);
668 case 0x00: /* l.extws */
669 LOG_DIS("l.extws r%d, r%d\n", rd
, ra
);
670 tcg_gen_ext32s_tl(cpu_R
[rd
], cpu_R
[ra
]);
672 case 0x01: /* l.extwz */
673 LOG_DIS("l.extwz r%d, r%d\n", rd
, ra
);
674 tcg_gen_ext32u_tl(cpu_R
[rd
], cpu_R
[ra
]);
678 gen_illegal_exception(dc
);
684 gen_illegal_exception(dc
);
690 gen_illegal_exception(dc
);
695 static void dec_misc(DisasContext
*dc
, uint32_t insn
)
699 #ifdef OPENRISC_DISAS
702 uint32_t I16
, I5
, I11
, N26
, tmp
;
703 op0
= extract32(insn
, 26, 6);
704 op1
= extract32(insn
, 24, 2);
705 ra
= extract32(insn
, 16, 5);
706 rb
= extract32(insn
, 11, 5);
707 rd
= extract32(insn
, 21, 5);
708 #ifdef OPENRISC_DISAS
709 L6
= extract32(insn
, 5, 6);
710 K5
= extract32(insn
, 0, 5);
712 I16
= extract32(insn
, 0, 16);
713 I5
= extract32(insn
, 21, 5);
714 I11
= extract32(insn
, 0, 11);
715 N26
= extract32(insn
, 0, 26);
716 tmp
= (I5
<<11) + I11
;
720 LOG_DIS("l.j %d\n", N26
);
721 gen_jump(dc
, N26
, 0, op0
);
724 case 0x01: /* l.jal */
725 LOG_DIS("l.jal %d\n", N26
);
726 gen_jump(dc
, N26
, 0, op0
);
729 case 0x03: /* l.bnf */
730 LOG_DIS("l.bnf %d\n", N26
);
731 gen_jump(dc
, N26
, 0, op0
);
734 case 0x04: /* l.bf */
735 LOG_DIS("l.bf %d\n", N26
);
736 gen_jump(dc
, N26
, 0, op0
);
741 case 0x01: /* l.nop */
742 LOG_DIS("l.nop %d\n", I16
);
746 gen_illegal_exception(dc
);
751 case 0x11: /* l.jr */
752 LOG_DIS("l.jr r%d\n", rb
);
753 gen_jump(dc
, 0, rb
, op0
);
756 case 0x12: /* l.jalr */
757 LOG_DIS("l.jalr r%d\n", rb
);
758 gen_jump(dc
, 0, rb
, op0
);
761 case 0x13: /* l.maci */
762 LOG_DIS("l.maci %d, r%d, %d\n", I5
, ra
, I11
);
764 TCGv_i64 t1
= tcg_temp_new_i64();
765 TCGv_i64 t2
= tcg_temp_new_i64();
766 TCGv_i32 dst
= tcg_temp_new_i32();
767 TCGv ttmp
= tcg_const_tl(tmp
);
768 tcg_gen_mul_tl(dst
, cpu_R
[ra
], ttmp
);
769 tcg_gen_ext_i32_i64(t1
, dst
);
770 tcg_gen_concat_i32_i64(t2
, maclo
, machi
);
771 tcg_gen_add_i64(t2
, t2
, t1
);
772 tcg_gen_trunc_i64_i32(maclo
, t2
);
773 tcg_gen_shri_i64(t2
, t2
, 32);
774 tcg_gen_trunc_i64_i32(machi
, t2
);
775 tcg_temp_free_i32(dst
);
777 tcg_temp_free_i64(t1
);
778 tcg_temp_free_i64(t2
);
782 case 0x09: /* l.rfe */
785 #if defined(CONFIG_USER_ONLY)
788 if (dc
->mem_idx
== MMU_USER_IDX
) {
789 gen_illegal_exception(dc
);
792 gen_helper_rfe(cpu_env
);
793 dc
->is_jmp
= DISAS_UPDATE
;
798 case 0x1c: /* l.cust1 */
799 LOG_DIS("l.cust1\n");
802 case 0x1d: /* l.cust2 */
803 LOG_DIS("l.cust2\n");
806 case 0x1e: /* l.cust3 */
807 LOG_DIS("l.cust3\n");
810 case 0x1f: /* l.cust4 */
811 LOG_DIS("l.cust4\n");
814 case 0x3c: /* l.cust5 */
815 LOG_DIS("l.cust5 r%d, r%d, r%d, %d, %d\n", rd
, ra
, rb
, L6
, K5
);
818 case 0x3d: /* l.cust6 */
819 LOG_DIS("l.cust6\n");
822 case 0x3e: /* l.cust7 */
823 LOG_DIS("l.cust7\n");
826 case 0x3f: /* l.cust8 */
827 LOG_DIS("l.cust8\n");
830 /* not used yet, open it when we need or64. */
831 /*#ifdef TARGET_OPENRISC64
833 LOG_DIS("l.ld r%d, r%d, %d\n", rd, ra, I16);
836 TCGv_i64 t0 = tcg_temp_new_i64();
837 tcg_gen_addi_i64(t0, cpu_R[ra], sign_extend(I16, 16));
838 tcg_gen_qemu_ld64(cpu_R[rd], t0, dc->mem_idx);
839 tcg_temp_free_i64(t0);
844 case 0x21: /* l.lwz */
845 LOG_DIS("l.lwz r%d, r%d, %d\n", rd
, ra
, I16
);
847 TCGv t0
= tcg_temp_new();
848 tcg_gen_addi_tl(t0
, cpu_R
[ra
], sign_extend(I16
, 16));
849 tcg_gen_qemu_ld32u(cpu_R
[rd
], t0
, dc
->mem_idx
);
854 case 0x22: /* l.lws */
855 LOG_DIS("l.lws r%d, r%d, %d\n", rd
, ra
, I16
);
857 TCGv t0
= tcg_temp_new();
858 tcg_gen_addi_tl(t0
, cpu_R
[ra
], sign_extend(I16
, 16));
859 tcg_gen_qemu_ld32s(cpu_R
[rd
], t0
, dc
->mem_idx
);
864 case 0x23: /* l.lbz */
865 LOG_DIS("l.lbz r%d, r%d, %d\n", rd
, ra
, I16
);
867 TCGv t0
= tcg_temp_new();
868 tcg_gen_addi_tl(t0
, cpu_R
[ra
], sign_extend(I16
, 16));
869 tcg_gen_qemu_ld8u(cpu_R
[rd
], t0
, dc
->mem_idx
);
874 case 0x24: /* l.lbs */
875 LOG_DIS("l.lbs r%d, r%d, %d\n", rd
, ra
, I16
);
877 TCGv t0
= tcg_temp_new();
878 tcg_gen_addi_tl(t0
, cpu_R
[ra
], sign_extend(I16
, 16));
879 tcg_gen_qemu_ld8s(cpu_R
[rd
], t0
, dc
->mem_idx
);
884 case 0x25: /* l.lhz */
885 LOG_DIS("l.lhz r%d, r%d, %d\n", rd
, ra
, I16
);
887 TCGv t0
= tcg_temp_new();
888 tcg_gen_addi_tl(t0
, cpu_R
[ra
], sign_extend(I16
, 16));
889 tcg_gen_qemu_ld16u(cpu_R
[rd
], t0
, dc
->mem_idx
);
894 case 0x26: /* l.lhs */
895 LOG_DIS("l.lhs r%d, r%d, %d\n", rd
, ra
, I16
);
897 TCGv t0
= tcg_temp_new();
898 tcg_gen_addi_tl(t0
, cpu_R
[ra
], sign_extend(I16
, 16));
899 tcg_gen_qemu_ld16s(cpu_R
[rd
], t0
, dc
->mem_idx
);
904 case 0x27: /* l.addi */
905 LOG_DIS("l.addi r%d, r%d, %d\n", rd
, ra
, I16
);
908 tcg_gen_mov_tl(cpu_R
[rd
], cpu_R
[ra
]);
910 int lab
= gen_new_label();
911 TCGv_i64 ta
= tcg_temp_new_i64();
912 TCGv_i64 td
= tcg_temp_local_new_i64();
913 TCGv_i32 res
= tcg_temp_local_new_i32();
914 TCGv_i32 sr_ove
= tcg_temp_local_new_i32();
915 tcg_gen_extu_i32_i64(ta
, cpu_R
[ra
]);
916 tcg_gen_addi_i64(td
, ta
, sign_extend(I16
, 16));
917 tcg_gen_trunc_i64_i32(res
, td
);
918 tcg_gen_shri_i64(td
, td
, 32);
919 tcg_gen_andi_i64(td
, td
, 0x3);
920 /* Jump to lab when no overflow. */
921 tcg_gen_brcondi_i64(TCG_COND_EQ
, td
, 0x0, lab
);
922 tcg_gen_brcondi_i64(TCG_COND_EQ
, td
, 0x3, lab
);
923 tcg_gen_ori_i32(cpu_sr
, cpu_sr
, (SR_OV
| SR_CY
));
924 tcg_gen_andi_i32(sr_ove
, cpu_sr
, SR_OVE
);
925 tcg_gen_brcondi_i32(TCG_COND_NE
, sr_ove
, SR_OVE
, lab
);
926 gen_exception(dc
, EXCP_RANGE
);
928 tcg_gen_mov_i32(cpu_R
[rd
], res
);
929 tcg_temp_free_i64(ta
);
930 tcg_temp_free_i64(td
);
931 tcg_temp_free_i32(res
);
932 tcg_temp_free_i32(sr_ove
);
937 case 0x28: /* l.addic */
938 LOG_DIS("l.addic r%d, r%d, %d\n", rd
, ra
, I16
);
940 int lab
= gen_new_label();
941 TCGv_i64 ta
= tcg_temp_new_i64();
942 TCGv_i64 td
= tcg_temp_local_new_i64();
943 TCGv_i64 tcy
= tcg_temp_local_new_i64();
944 TCGv_i32 res
= tcg_temp_local_new_i32();
945 TCGv_i32 sr_cy
= tcg_temp_local_new_i32();
946 TCGv_i32 sr_ove
= tcg_temp_local_new_i32();
947 tcg_gen_extu_i32_i64(ta
, cpu_R
[ra
]);
948 tcg_gen_andi_i32(sr_cy
, cpu_sr
, SR_CY
);
949 tcg_gen_shri_i32(sr_cy
, sr_cy
, 10);
950 tcg_gen_extu_i32_i64(tcy
, sr_cy
);
951 tcg_gen_addi_i64(td
, ta
, sign_extend(I16
, 16));
952 tcg_gen_add_i64(td
, td
, tcy
);
953 tcg_gen_trunc_i64_i32(res
, td
);
954 tcg_gen_shri_i64(td
, td
, 32);
955 tcg_gen_andi_i64(td
, td
, 0x3);
956 /* Jump to lab when no overflow. */
957 tcg_gen_brcondi_i64(TCG_COND_EQ
, td
, 0x0, lab
);
958 tcg_gen_brcondi_i64(TCG_COND_EQ
, td
, 0x3, lab
);
959 tcg_gen_ori_i32(cpu_sr
, cpu_sr
, (SR_OV
| SR_CY
));
960 tcg_gen_andi_i32(sr_ove
, cpu_sr
, SR_OVE
);
961 tcg_gen_brcondi_i32(TCG_COND_NE
, sr_ove
, SR_OVE
, lab
);
962 gen_exception(dc
, EXCP_RANGE
);
964 tcg_gen_mov_i32(cpu_R
[rd
], res
);
965 tcg_temp_free_i64(ta
);
966 tcg_temp_free_i64(td
);
967 tcg_temp_free_i64(tcy
);
968 tcg_temp_free_i32(res
);
969 tcg_temp_free_i32(sr_cy
);
970 tcg_temp_free_i32(sr_ove
);
974 case 0x29: /* l.andi */
975 LOG_DIS("l.andi r%d, r%d, %d\n", rd
, ra
, I16
);
976 tcg_gen_andi_tl(cpu_R
[rd
], cpu_R
[ra
], zero_extend(I16
, 16));
979 case 0x2a: /* l.ori */
980 LOG_DIS("l.ori r%d, r%d, %d\n", rd
, ra
, I16
);
981 tcg_gen_ori_tl(cpu_R
[rd
], cpu_R
[ra
], zero_extend(I16
, 16));
984 case 0x2b: /* l.xori */
985 LOG_DIS("l.xori r%d, r%d, %d\n", rd
, ra
, I16
);
986 tcg_gen_xori_tl(cpu_R
[rd
], cpu_R
[ra
], sign_extend(I16
, 16));
989 case 0x2c: /* l.muli */
990 LOG_DIS("l.muli r%d, r%d, %d\n", rd
, ra
, I16
);
991 if (ra
!= 0 && I16
!= 0) {
992 TCGv_i32 im
= tcg_const_i32(I16
);
993 gen_helper_mul32(cpu_R
[rd
], cpu_env
, cpu_R
[ra
], im
);
994 tcg_temp_free_i32(im
);
996 tcg_gen_movi_tl(cpu_R
[rd
], 0x0);
1000 case 0x2d: /* l.mfspr */
1001 LOG_DIS("l.mfspr r%d, r%d, %d\n", rd
, ra
, I16
);
1003 #if defined(CONFIG_USER_ONLY)
1006 TCGv_i32 ti
= tcg_const_i32(I16
);
1007 if (dc
->mem_idx
== MMU_USER_IDX
) {
1008 gen_illegal_exception(dc
);
1011 gen_helper_mfspr(cpu_R
[rd
], cpu_env
, cpu_R
[rd
], cpu_R
[ra
], ti
);
1012 tcg_temp_free_i32(ti
);
1017 case 0x30: /* l.mtspr */
1018 LOG_DIS("l.mtspr %d, r%d, r%d, %d\n", I5
, ra
, rb
, I11
);
1020 #if defined(CONFIG_USER_ONLY)
1023 TCGv_i32 im
= tcg_const_i32(tmp
);
1024 if (dc
->mem_idx
== MMU_USER_IDX
) {
1025 gen_illegal_exception(dc
);
1028 gen_helper_mtspr(cpu_env
, cpu_R
[ra
], cpu_R
[rb
], im
);
1029 tcg_temp_free_i32(im
);
1034 /* not used yet, open it when we need or64. */
1035 /*#ifdef TARGET_OPENRISC64
1037 LOG_DIS("l.sd %d, r%d, r%d, %d\n", I5, ra, rb, I11);
1040 TCGv_i64 t0 = tcg_temp_new_i64();
1041 tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16));
1042 tcg_gen_qemu_st64(cpu_R[rb], t0, dc->mem_idx);
1043 tcg_temp_free_i64(t0);
1048 case 0x35: /* l.sw */
1049 LOG_DIS("l.sw %d, r%d, r%d, %d\n", I5
, ra
, rb
, I11
);
1051 TCGv t0
= tcg_temp_new();
1052 tcg_gen_addi_tl(t0
, cpu_R
[ra
], sign_extend(tmp
, 16));
1053 tcg_gen_qemu_st32(cpu_R
[rb
], t0
, dc
->mem_idx
);
1058 case 0x36: /* l.sb */
1059 LOG_DIS("l.sb %d, r%d, r%d, %d\n", I5
, ra
, rb
, I11
);
1061 TCGv t0
= tcg_temp_new();
1062 tcg_gen_addi_tl(t0
, cpu_R
[ra
], sign_extend(tmp
, 16));
1063 tcg_gen_qemu_st8(cpu_R
[rb
], t0
, dc
->mem_idx
);
1068 case 0x37: /* l.sh */
1069 LOG_DIS("l.sh %d, r%d, r%d, %d\n", I5
, ra
, rb
, I11
);
1071 TCGv t0
= tcg_temp_new();
1072 tcg_gen_addi_tl(t0
, cpu_R
[ra
], sign_extend(tmp
, 16));
1073 tcg_gen_qemu_st16(cpu_R
[rb
], t0
, dc
->mem_idx
);
1079 gen_illegal_exception(dc
);
1084 static void dec_mac(DisasContext
*dc
, uint32_t insn
)
1088 op0
= extract32(insn
, 0, 4);
1089 ra
= extract32(insn
, 16, 5);
1090 rb
= extract32(insn
, 11, 5);
1093 case 0x0001: /* l.mac */
1094 LOG_DIS("l.mac r%d, r%d\n", ra
, rb
);
1096 TCGv_i32 t0
= tcg_temp_new_i32();
1097 TCGv_i64 t1
= tcg_temp_new_i64();
1098 TCGv_i64 t2
= tcg_temp_new_i64();
1099 tcg_gen_mul_tl(t0
, cpu_R
[ra
], cpu_R
[rb
]);
1100 tcg_gen_ext_i32_i64(t1
, t0
);
1101 tcg_gen_concat_i32_i64(t2
, maclo
, machi
);
1102 tcg_gen_add_i64(t2
, t2
, t1
);
1103 tcg_gen_trunc_i64_i32(maclo
, t2
);
1104 tcg_gen_shri_i64(t2
, t2
, 32);
1105 tcg_gen_trunc_i64_i32(machi
, t2
);
1106 tcg_temp_free_i32(t0
);
1107 tcg_temp_free_i64(t1
);
1108 tcg_temp_free_i64(t2
);
1112 case 0x0002: /* l.msb */
1113 LOG_DIS("l.msb r%d, r%d\n", ra
, rb
);
1115 TCGv_i32 t0
= tcg_temp_new_i32();
1116 TCGv_i64 t1
= tcg_temp_new_i64();
1117 TCGv_i64 t2
= tcg_temp_new_i64();
1118 tcg_gen_mul_tl(t0
, cpu_R
[ra
], cpu_R
[rb
]);
1119 tcg_gen_ext_i32_i64(t1
, t0
);
1120 tcg_gen_concat_i32_i64(t2
, maclo
, machi
);
1121 tcg_gen_sub_i64(t2
, t2
, t1
);
1122 tcg_gen_trunc_i64_i32(maclo
, t2
);
1123 tcg_gen_shri_i64(t2
, t2
, 32);
1124 tcg_gen_trunc_i64_i32(machi
, t2
);
1125 tcg_temp_free_i32(t0
);
1126 tcg_temp_free_i64(t1
);
1127 tcg_temp_free_i64(t2
);
1132 gen_illegal_exception(dc
);
1137 static void dec_logic(DisasContext
*dc
, uint32_t insn
)
1140 uint32_t rd
, ra
, L6
;
1141 op0
= extract32(insn
, 6, 2);
1142 rd
= extract32(insn
, 21, 5);
1143 ra
= extract32(insn
, 16, 5);
1144 L6
= extract32(insn
, 0, 6);
1147 case 0x00: /* l.slli */
1148 LOG_DIS("l.slli r%d, r%d, %d\n", rd
, ra
, L6
);
1149 tcg_gen_shli_tl(cpu_R
[rd
], cpu_R
[ra
], (L6
& 0x1f));
1152 case 0x01: /* l.srli */
1153 LOG_DIS("l.srli r%d, r%d, %d\n", rd
, ra
, L6
);
1154 tcg_gen_shri_tl(cpu_R
[rd
], cpu_R
[ra
], (L6
& 0x1f));
1157 case 0x02: /* l.srai */
1158 LOG_DIS("l.srai r%d, r%d, %d\n", rd
, ra
, L6
);
1159 tcg_gen_sari_tl(cpu_R
[rd
], cpu_R
[ra
], (L6
& 0x1f)); break;
1161 case 0x03: /* l.rori */
1162 LOG_DIS("l.rori r%d, r%d, %d\n", rd
, ra
, L6
);
1163 tcg_gen_rotri_tl(cpu_R
[rd
], cpu_R
[ra
], (L6
& 0x1f));
1167 gen_illegal_exception(dc
);
1172 static void dec_M(DisasContext
*dc
, uint32_t insn
)
1177 op0
= extract32(insn
, 16, 1);
1178 rd
= extract32(insn
, 21, 5);
1179 K16
= extract32(insn
, 0, 16);
1182 case 0x0: /* l.movhi */
1183 LOG_DIS("l.movhi r%d, %d\n", rd
, K16
);
1184 tcg_gen_movi_tl(cpu_R
[rd
], (K16
<< 16));
1187 case 0x1: /* l.macrc */
1188 LOG_DIS("l.macrc r%d\n", rd
);
1189 tcg_gen_mov_tl(cpu_R
[rd
], maclo
);
1190 tcg_gen_movi_tl(maclo
, 0x0);
1191 tcg_gen_movi_tl(machi
, 0x0);
1195 gen_illegal_exception(dc
);
1200 static void dec_comp(DisasContext
*dc
, uint32_t insn
)
1205 op0
= extract32(insn
, 21, 5);
1206 ra
= extract32(insn
, 16, 5);
1207 rb
= extract32(insn
, 11, 5);
1209 tcg_gen_movi_i32(env_btaken
, 0x0);
1210 /* unsigned integers */
1211 tcg_gen_ext32u_tl(cpu_R
[ra
], cpu_R
[ra
]);
1212 tcg_gen_ext32u_tl(cpu_R
[rb
], cpu_R
[rb
]);
1215 case 0x0: /* l.sfeq */
1216 LOG_DIS("l.sfeq r%d, r%d\n", ra
, rb
);
1217 tcg_gen_setcond_tl(TCG_COND_EQ
, env_btaken
, cpu_R
[ra
], cpu_R
[rb
]);
1220 case 0x1: /* l.sfne */
1221 LOG_DIS("l.sfne r%d, r%d\n", ra
, rb
);
1222 tcg_gen_setcond_tl(TCG_COND_NE
, env_btaken
, cpu_R
[ra
], cpu_R
[rb
]);
1225 case 0x2: /* l.sfgtu */
1226 LOG_DIS("l.sfgtu r%d, r%d\n", ra
, rb
);
1227 tcg_gen_setcond_tl(TCG_COND_GTU
, env_btaken
, cpu_R
[ra
], cpu_R
[rb
]);
1230 case 0x3: /* l.sfgeu */
1231 LOG_DIS("l.sfgeu r%d, r%d\n", ra
, rb
);
1232 tcg_gen_setcond_tl(TCG_COND_GEU
, env_btaken
, cpu_R
[ra
], cpu_R
[rb
]);
1235 case 0x4: /* l.sfltu */
1236 LOG_DIS("l.sfltu r%d, r%d\n", ra
, rb
);
1237 tcg_gen_setcond_tl(TCG_COND_LTU
, env_btaken
, cpu_R
[ra
], cpu_R
[rb
]);
1240 case 0x5: /* l.sfleu */
1241 LOG_DIS("l.sfleu r%d, r%d\n", ra
, rb
);
1242 tcg_gen_setcond_tl(TCG_COND_LEU
, env_btaken
, cpu_R
[ra
], cpu_R
[rb
]);
1245 case 0xa: /* l.sfgts */
1246 LOG_DIS("l.sfgts r%d, r%d\n", ra
, rb
);
1247 tcg_gen_setcond_tl(TCG_COND_GT
, env_btaken
, cpu_R
[ra
], cpu_R
[rb
]);
1250 case 0xb: /* l.sfges */
1251 LOG_DIS("l.sfges r%d, r%d\n", ra
, rb
);
1252 tcg_gen_setcond_tl(TCG_COND_GE
, env_btaken
, cpu_R
[ra
], cpu_R
[rb
]);
1255 case 0xc: /* l.sflts */
1256 LOG_DIS("l.sflts r%d, r%d\n", ra
, rb
);
1257 tcg_gen_setcond_tl(TCG_COND_LT
, env_btaken
, cpu_R
[ra
], cpu_R
[rb
]);
1260 case 0xd: /* l.sfles */
1261 LOG_DIS("l.sfles r%d, r%d\n", ra
, rb
);
1262 tcg_gen_setcond_tl(TCG_COND_LE
, env_btaken
, cpu_R
[ra
], cpu_R
[rb
]);
1266 gen_illegal_exception(dc
);
1272 static void dec_compi(DisasContext
*dc
, uint32_t insn
)
1277 op0
= extract32(insn
, 21, 5);
1278 ra
= extract32(insn
, 16, 5);
1279 I16
= extract32(insn
, 0, 16);
1281 tcg_gen_movi_i32(env_btaken
, 0x0);
1282 I16
= sign_extend(I16
, 16);
1285 case 0x0: /* l.sfeqi */
1286 LOG_DIS("l.sfeqi r%d, %d\n", ra
, I16
);
1287 tcg_gen_setcondi_tl(TCG_COND_EQ
, env_btaken
, cpu_R
[ra
], I16
);
1290 case 0x1: /* l.sfnei */
1291 LOG_DIS("l.sfnei r%d, %d\n", ra
, I16
);
1292 tcg_gen_setcondi_tl(TCG_COND_NE
, env_btaken
, cpu_R
[ra
], I16
);
1295 case 0x2: /* l.sfgtui */
1296 LOG_DIS("l.sfgtui r%d, %d\n", ra
, I16
);
1297 tcg_gen_setcondi_tl(TCG_COND_GTU
, env_btaken
, cpu_R
[ra
], I16
);
1300 case 0x3: /* l.sfgeui */
1301 LOG_DIS("l.sfgeui r%d, %d\n", ra
, I16
);
1302 tcg_gen_setcondi_tl(TCG_COND_GEU
, env_btaken
, cpu_R
[ra
], I16
);
1305 case 0x4: /* l.sfltui */
1306 LOG_DIS("l.sfltui r%d, %d\n", ra
, I16
);
1307 tcg_gen_setcondi_tl(TCG_COND_LTU
, env_btaken
, cpu_R
[ra
], I16
);
1310 case 0x5: /* l.sfleui */
1311 LOG_DIS("l.sfleui r%d, %d\n", ra
, I16
);
1312 tcg_gen_setcondi_tl(TCG_COND_LEU
, env_btaken
, cpu_R
[ra
], I16
);
1315 case 0xa: /* l.sfgtsi */
1316 LOG_DIS("l.sfgtsi r%d, %d\n", ra
, I16
);
1317 tcg_gen_setcondi_tl(TCG_COND_GT
, env_btaken
, cpu_R
[ra
], I16
);
1320 case 0xb: /* l.sfgesi */
1321 LOG_DIS("l.sfgesi r%d, %d\n", ra
, I16
);
1322 tcg_gen_setcondi_tl(TCG_COND_GE
, env_btaken
, cpu_R
[ra
], I16
);
1325 case 0xc: /* l.sfltsi */
1326 LOG_DIS("l.sfltsi r%d, %d\n", ra
, I16
);
1327 tcg_gen_setcondi_tl(TCG_COND_LT
, env_btaken
, cpu_R
[ra
], I16
);
1330 case 0xd: /* l.sflesi */
1331 LOG_DIS("l.sflesi r%d, %d\n", ra
, I16
);
1332 tcg_gen_setcondi_tl(TCG_COND_LE
, env_btaken
, cpu_R
[ra
], I16
);
1336 gen_illegal_exception(dc
);
1342 static void dec_sys(DisasContext
*dc
, uint32_t insn
)
1345 #ifdef OPENRISC_DISAS
1348 op0
= extract32(insn
, 16, 8);
1349 #ifdef OPENRISC_DISAS
1350 K16
= extract32(insn
, 0, 16);
1354 case 0x000: /* l.sys */
1355 LOG_DIS("l.sys %d\n", K16
);
1356 tcg_gen_movi_tl(cpu_pc
, dc
->pc
);
1357 gen_exception(dc
, EXCP_SYSCALL
);
1358 dc
->is_jmp
= DISAS_UPDATE
;
1361 case 0x100: /* l.trap */
1362 LOG_DIS("l.trap %d\n", K16
);
1363 #if defined(CONFIG_USER_ONLY)
1366 if (dc
->mem_idx
== MMU_USER_IDX
) {
1367 gen_illegal_exception(dc
);
1370 tcg_gen_movi_tl(cpu_pc
, dc
->pc
);
1371 gen_exception(dc
, EXCP_TRAP
);
1375 case 0x300: /* l.csync */
1376 LOG_DIS("l.csync\n");
1377 #if defined(CONFIG_USER_ONLY)
1380 if (dc
->mem_idx
== MMU_USER_IDX
) {
1381 gen_illegal_exception(dc
);
1387 case 0x200: /* l.msync */
1388 LOG_DIS("l.msync\n");
1389 #if defined(CONFIG_USER_ONLY)
1392 if (dc
->mem_idx
== MMU_USER_IDX
) {
1393 gen_illegal_exception(dc
);
1399 case 0x270: /* l.psync */
1400 LOG_DIS("l.psync\n");
1401 #if defined(CONFIG_USER_ONLY)
1404 if (dc
->mem_idx
== MMU_USER_IDX
) {
1405 gen_illegal_exception(dc
);
1412 gen_illegal_exception(dc
);
1417 static void dec_float(DisasContext
*dc
, uint32_t insn
)
1420 uint32_t ra
, rb
, rd
;
1421 op0
= extract32(insn
, 0, 8);
1422 ra
= extract32(insn
, 16, 5);
1423 rb
= extract32(insn
, 11, 5);
1424 rd
= extract32(insn
, 21, 5);
1427 case 0x00: /* lf.add.s */
1428 LOG_DIS("lf.add.s r%d, r%d, r%d\n", rd
, ra
, rb
);
1429 gen_helper_float_add_s(cpu_R
[rd
], cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1432 case 0x01: /* lf.sub.s */
1433 LOG_DIS("lf.sub.s r%d, r%d, r%d\n", rd
, ra
, rb
);
1434 gen_helper_float_sub_s(cpu_R
[rd
], cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1438 case 0x02: /* lf.mul.s */
1439 LOG_DIS("lf.mul.s r%d, r%d, r%d\n", rd
, ra
, rb
);
1440 if (ra
!= 0 && rb
!= 0) {
1441 gen_helper_float_mul_s(cpu_R
[rd
], cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1443 tcg_gen_ori_tl(fpcsr
, fpcsr
, FPCSR_ZF
);
1444 tcg_gen_movi_i32(cpu_R
[rd
], 0x0);
1448 case 0x03: /* lf.div.s */
1449 LOG_DIS("lf.div.s r%d, r%d, r%d\n", rd
, ra
, rb
);
1450 gen_helper_float_div_s(cpu_R
[rd
], cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1453 case 0x04: /* lf.itof.s */
1454 LOG_DIS("lf.itof r%d, r%d\n", rd
, ra
);
1455 gen_helper_itofs(cpu_R
[rd
], cpu_env
, cpu_R
[ra
]);
1458 case 0x05: /* lf.ftoi.s */
1459 LOG_DIS("lf.ftoi r%d, r%d\n", rd
, ra
);
1460 gen_helper_ftois(cpu_R
[rd
], cpu_env
, cpu_R
[ra
]);
1463 case 0x06: /* lf.rem.s */
1464 LOG_DIS("lf.rem.s r%d, r%d, r%d\n", rd
, ra
, rb
);
1465 gen_helper_float_rem_s(cpu_R
[rd
], cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1468 case 0x07: /* lf.madd.s */
1469 LOG_DIS("lf.madd.s r%d, r%d, r%d\n", rd
, ra
, rb
);
1470 gen_helper_float_muladd_s(cpu_R
[rd
], cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1473 case 0x08: /* lf.sfeq.s */
1474 LOG_DIS("lf.sfeq.s r%d, r%d\n", ra
, rb
);
1475 gen_helper_float_eq_s(env_btaken
, cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1478 case 0x09: /* lf.sfne.s */
1479 LOG_DIS("lf.sfne.s r%d, r%d\n", ra
, rb
);
1480 gen_helper_float_ne_s(env_btaken
, cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1483 case 0x0a: /* lf.sfgt.s */
1484 LOG_DIS("lf.sfgt.s r%d, r%d\n", ra
, rb
);
1485 gen_helper_float_gt_s(env_btaken
, cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1488 case 0x0b: /* lf.sfge.s */
1489 LOG_DIS("lf.sfge.s r%d, r%d\n", ra
, rb
);
1490 gen_helper_float_ge_s(env_btaken
, cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1493 case 0x0c: /* lf.sflt.s */
1494 LOG_DIS("lf.sflt.s r%d, r%d\n", ra
, rb
);
1495 gen_helper_float_lt_s(env_btaken
, cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1498 case 0x0d: /* lf.sfle.s */
1499 LOG_DIS("lf.sfle.s r%d, r%d\n", ra
, rb
);
1500 gen_helper_float_le_s(env_btaken
, cpu_env
, cpu_R
[ra
], cpu_R
[rb
]);
1503 /* not used yet, open it when we need or64. */
1504 /*#ifdef TARGET_OPENRISC64
1506 LOG_DIS("lf.add.d r%d, r%d, r%d\n", rd, ra, rb);
1508 gen_helper_float_add_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1512 LOG_DIS("lf.sub.d r%d, r%d, r%d\n", rd, ra, rb);
1514 gen_helper_float_sub_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1518 LOG_DIS("lf.mul.d r%d, r%d, r%d\n", rd, ra, rb);
1520 if (ra != 0 && rb != 0) {
1521 gen_helper_float_mul_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1523 tcg_gen_ori_tl(fpcsr, fpcsr, FPCSR_ZF);
1524 tcg_gen_movi_i64(cpu_R[rd], 0x0);
1529 LOG_DIS("lf.div.d r%d, r%d, r%d\n", rd, ra, rb);
1531 gen_helper_float_div_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1534 case 0x14: lf.itof.d
1535 LOG_DIS("lf.itof r%d, r%d\n", rd, ra);
1537 gen_helper_itofd(cpu_R[rd], cpu_env, cpu_R[ra]);
1540 case 0x15: lf.ftoi.d
1541 LOG_DIS("lf.ftoi r%d, r%d\n", rd, ra);
1543 gen_helper_ftoid(cpu_R[rd], cpu_env, cpu_R[ra]);
1547 LOG_DIS("lf.rem.d r%d, r%d, r%d\n", rd, ra, rb);
1549 gen_helper_float_rem_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1552 case 0x17: lf.madd.d
1553 LOG_DIS("lf.madd.d r%d, r%d, r%d\n", rd, ra, rb);
1555 gen_helper_float_muladd_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1558 case 0x18: lf.sfeq.d
1559 LOG_DIS("lf.sfeq.d r%d, r%d\n", ra, rb);
1561 gen_helper_float_eq_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1564 case 0x1a: lf.sfgt.d
1565 LOG_DIS("lf.sfgt.d r%d, r%d\n", ra, rb);
1567 gen_helper_float_gt_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1570 case 0x1b: lf.sfge.d
1571 LOG_DIS("lf.sfge.d r%d, r%d\n", ra, rb);
1573 gen_helper_float_ge_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1576 case 0x19: lf.sfne.d
1577 LOG_DIS("lf.sfne.d r%d, r%d\n", ra, rb);
1579 gen_helper_float_ne_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1582 case 0x1c: lf.sflt.d
1583 LOG_DIS("lf.sflt.d r%d, r%d\n", ra, rb);
1585 gen_helper_float_lt_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1588 case 0x1d: lf.sfle.d
1589 LOG_DIS("lf.sfle.d r%d, r%d\n", ra, rb);
1591 gen_helper_float_le_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1596 gen_illegal_exception(dc
);
1602 static void disas_openrisc_insn(DisasContext
*dc
, OpenRISCCPU
*cpu
)
1606 insn
= cpu_ldl_code(&cpu
->env
, dc
->pc
);
1607 op0
= extract32(insn
, 26, 6);
1619 dec_logic(dc
, insn
);
1623 dec_compi(dc
, insn
);
1631 dec_float(dc
, insn
);
1648 static void check_breakpoint(OpenRISCCPU
*cpu
, DisasContext
*dc
)
1652 if (unlikely(!QTAILQ_EMPTY(&cpu
->env
.breakpoints
))) {
1653 QTAILQ_FOREACH(bp
, &cpu
->env
.breakpoints
, entry
) {
1654 if (bp
->pc
== dc
->pc
) {
1655 tcg_gen_movi_tl(cpu_pc
, dc
->pc
);
1656 gen_exception(dc
, EXCP_DEBUG
);
1657 dc
->is_jmp
= DISAS_UPDATE
;
1663 static inline void gen_intermediate_code_internal(OpenRISCCPU
*cpu
,
1664 TranslationBlock
*tb
,
1667 CPUState
*cs
= CPU(cpu
);
1668 struct DisasContext ctx
, *dc
= &ctx
;
1669 uint16_t *gen_opc_end
;
1672 uint32_t next_page_start
;
1679 gen_opc_end
= tcg_ctx
.gen_opc_buf
+ OPC_MAX_SIZE
;
1680 dc
->is_jmp
= DISAS_NEXT
;
1683 dc
->flags
= cpu
->env
.cpucfgr
;
1684 dc
->mem_idx
= cpu_mmu_index(&cpu
->env
);
1685 dc
->synced_flags
= dc
->tb_flags
= tb
->flags
;
1686 dc
->delayed_branch
= !!(dc
->tb_flags
& D_FLAG
);
1687 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
1688 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
1689 qemu_log("-----------------------------------------\n");
1690 log_cpu_state(CPU(cpu
), 0);
1693 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
1696 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
1698 if (max_insns
== 0) {
1699 max_insns
= CF_COUNT_MASK
;
1705 check_breakpoint(cpu
, dc
);
1707 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
1711 tcg_ctx
.gen_opc_instr_start
[k
++] = 0;
1714 tcg_ctx
.gen_opc_pc
[k
] = dc
->pc
;
1715 tcg_ctx
.gen_opc_instr_start
[k
] = 1;
1716 tcg_ctx
.gen_opc_icount
[k
] = num_insns
;
1719 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
1720 tcg_gen_debug_insn_start(dc
->pc
);
1723 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
1726 dc
->ppc
= dc
->pc
- 4;
1727 dc
->npc
= dc
->pc
+ 4;
1728 tcg_gen_movi_tl(cpu_ppc
, dc
->ppc
);
1729 tcg_gen_movi_tl(cpu_npc
, dc
->npc
);
1730 disas_openrisc_insn(dc
, cpu
);
1734 if (dc
->delayed_branch
) {
1735 dc
->delayed_branch
--;
1736 if (!dc
->delayed_branch
) {
1737 dc
->tb_flags
&= ~D_FLAG
;
1739 tcg_gen_mov_tl(cpu_pc
, jmp_pc
);
1740 tcg_gen_mov_tl(cpu_npc
, jmp_pc
);
1741 tcg_gen_movi_tl(jmp_pc
, 0);
1743 dc
->is_jmp
= DISAS_JUMP
;
1747 } while (!dc
->is_jmp
1748 && tcg_ctx
.gen_opc_ptr
< gen_opc_end
1749 && !cs
->singlestep_enabled
1751 && (dc
->pc
< next_page_start
)
1752 && num_insns
< max_insns
);
1754 if (tb
->cflags
& CF_LAST_IO
) {
1757 if (dc
->is_jmp
== DISAS_NEXT
) {
1758 dc
->is_jmp
= DISAS_UPDATE
;
1759 tcg_gen_movi_tl(cpu_pc
, dc
->pc
);
1761 if (unlikely(cs
->singlestep_enabled
)) {
1762 if (dc
->is_jmp
== DISAS_NEXT
) {
1763 tcg_gen_movi_tl(cpu_pc
, dc
->pc
);
1765 gen_exception(dc
, EXCP_DEBUG
);
1767 switch (dc
->is_jmp
) {
1769 gen_goto_tb(dc
, 0, dc
->pc
);
1775 /* indicate that the hash table must be used
1776 to find the next TB */
1780 /* nothing more to generate */
1785 gen_tb_end(tb
, num_insns
);
1786 *tcg_ctx
.gen_opc_ptr
= INDEX_op_end
;
1788 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
1791 tcg_ctx
.gen_opc_instr_start
[k
++] = 0;
1794 tb
->size
= dc
->pc
- pc_start
;
1795 tb
->icount
= num_insns
;
1799 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
1801 log_target_disas(&cpu
->env
, pc_start
, dc
->pc
- pc_start
, 0);
1802 qemu_log("\nisize=%d osize=%td\n",
1803 dc
->pc
- pc_start
, tcg_ctx
.gen_opc_ptr
-
1804 tcg_ctx
.gen_opc_buf
);
1809 void gen_intermediate_code(CPUOpenRISCState
*env
, struct TranslationBlock
*tb
)
1811 gen_intermediate_code_internal(openrisc_env_get_cpu(env
), tb
, 0);
1814 void gen_intermediate_code_pc(CPUOpenRISCState
*env
,
1815 struct TranslationBlock
*tb
)
1817 gen_intermediate_code_internal(openrisc_env_get_cpu(env
), tb
, 1);
1820 void openrisc_cpu_dump_state(CPUState
*cs
, FILE *f
,
1821 fprintf_function cpu_fprintf
,
1824 OpenRISCCPU
*cpu
= OPENRISC_CPU(cs
);
1825 CPUOpenRISCState
*env
= &cpu
->env
;
1828 cpu_fprintf(f
, "PC=%08x\n", env
->pc
);
1829 for (i
= 0; i
< 32; ++i
) {
1830 cpu_fprintf(f
, "R%02d=%08x%c", i
, env
->gpr
[i
],
1831 (i
% 4) == 3 ? '\n' : ' ');
1835 void restore_state_to_opc(CPUOpenRISCState
*env
, TranslationBlock
*tb
,
1838 env
->pc
= tcg_ctx
.gen_opc_pc
[pc_pos
];