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[qemu.git] / target-ppc / cpu.h
1 /*
2 * PowerPC emulation cpu definitions for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #if !defined (__CPU_PPC_H__)
20 #define __CPU_PPC_H__
21
22 #include "config.h"
23 #include "qemu-common.h"
24
25 //#define PPC_EMULATE_32BITS_HYPV
26
27 #if defined (TARGET_PPC64)
28 /* PowerPC 64 definitions */
29 #define TARGET_LONG_BITS 64
30 #define TARGET_PAGE_BITS 12
31
32 /* Note that the official physical address space bits is 62-M where M
33 is implementation dependent. I've not looked up M for the set of
34 cpus we emulate at the system level. */
35 #define TARGET_PHYS_ADDR_SPACE_BITS 62
36
37 /* Note that the PPC environment architecture talks about 80 bit virtual
38 addresses, with segmentation. Obviously that's not all visible to a
39 single process, which is all we're concerned with here. */
40 #ifdef TARGET_ABI32
41 # define TARGET_VIRT_ADDR_SPACE_BITS 32
42 #else
43 # define TARGET_VIRT_ADDR_SPACE_BITS 64
44 #endif
45
46 #define TARGET_PAGE_BITS_16M 24
47
48 #else /* defined (TARGET_PPC64) */
49 /* PowerPC 32 definitions */
50 #define TARGET_LONG_BITS 32
51
52 #if defined(TARGET_PPCEMB)
53 /* Specific definitions for PowerPC embedded */
54 /* BookE have 36 bits physical address space */
55 #if defined(CONFIG_USER_ONLY)
56 /* It looks like a lot of Linux programs assume page size
57 * is 4kB long. This is evil, but we have to deal with it...
58 */
59 #define TARGET_PAGE_BITS 12
60 #else /* defined(CONFIG_USER_ONLY) */
61 /* Pages can be 1 kB small */
62 #define TARGET_PAGE_BITS 10
63 #endif /* defined(CONFIG_USER_ONLY) */
64 #else /* defined(TARGET_PPCEMB) */
65 /* "standard" PowerPC 32 definitions */
66 #define TARGET_PAGE_BITS 12
67 #endif /* defined(TARGET_PPCEMB) */
68
69 #define TARGET_PHYS_ADDR_SPACE_BITS 36
70 #define TARGET_VIRT_ADDR_SPACE_BITS 32
71
72 #endif /* defined (TARGET_PPC64) */
73
74 #define CPUArchState struct CPUPPCState
75
76 #include "exec/cpu-defs.h"
77
78 #include "fpu/softfloat.h"
79
80 #define TARGET_HAS_ICE 1
81
82 #if defined (TARGET_PPC64)
83 #define ELF_MACHINE EM_PPC64
84 #else
85 #define ELF_MACHINE EM_PPC
86 #endif
87
88 /*****************************************************************************/
89 /* MMU model */
90 typedef enum powerpc_mmu_t powerpc_mmu_t;
91 enum powerpc_mmu_t {
92 POWERPC_MMU_UNKNOWN = 0x00000000,
93 /* Standard 32 bits PowerPC MMU */
94 POWERPC_MMU_32B = 0x00000001,
95 /* PowerPC 6xx MMU with software TLB */
96 POWERPC_MMU_SOFT_6xx = 0x00000002,
97 /* PowerPC 74xx MMU with software TLB */
98 POWERPC_MMU_SOFT_74xx = 0x00000003,
99 /* PowerPC 4xx MMU with software TLB */
100 POWERPC_MMU_SOFT_4xx = 0x00000004,
101 /* PowerPC 4xx MMU with software TLB and zones protections */
102 POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
103 /* PowerPC MMU in real mode only */
104 POWERPC_MMU_REAL = 0x00000006,
105 /* Freescale MPC8xx MMU model */
106 POWERPC_MMU_MPC8xx = 0x00000007,
107 /* BookE MMU model */
108 POWERPC_MMU_BOOKE = 0x00000008,
109 /* BookE 2.06 MMU model */
110 POWERPC_MMU_BOOKE206 = 0x00000009,
111 /* PowerPC 601 MMU model (specific BATs format) */
112 POWERPC_MMU_601 = 0x0000000A,
113 #if defined(TARGET_PPC64)
114 #define POWERPC_MMU_64 0x00010000
115 #define POWERPC_MMU_1TSEG 0x00020000
116 #define POWERPC_MMU_AMR 0x00040000
117 /* 64 bits PowerPC MMU */
118 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
119 /* Architecture 2.06 variant */
120 POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
121 | POWERPC_MMU_AMR | 0x00000003,
122 /* Architecture 2.06 "degraded" (no 1T segments) */
123 POWERPC_MMU_2_06a = POWERPC_MMU_64 | POWERPC_MMU_AMR
124 | 0x00000003,
125 /* Architecture 2.06 "degraded" (no 1T segments or AMR) */
126 POWERPC_MMU_2_06d = POWERPC_MMU_64 | 0x00000003,
127 #endif /* defined(TARGET_PPC64) */
128 };
129
130 /*****************************************************************************/
131 /* Exception model */
132 typedef enum powerpc_excp_t powerpc_excp_t;
133 enum powerpc_excp_t {
134 POWERPC_EXCP_UNKNOWN = 0,
135 /* Standard PowerPC exception model */
136 POWERPC_EXCP_STD,
137 /* PowerPC 40x exception model */
138 POWERPC_EXCP_40x,
139 /* PowerPC 601 exception model */
140 POWERPC_EXCP_601,
141 /* PowerPC 602 exception model */
142 POWERPC_EXCP_602,
143 /* PowerPC 603 exception model */
144 POWERPC_EXCP_603,
145 /* PowerPC 603e exception model */
146 POWERPC_EXCP_603E,
147 /* PowerPC G2 exception model */
148 POWERPC_EXCP_G2,
149 /* PowerPC 604 exception model */
150 POWERPC_EXCP_604,
151 /* PowerPC 7x0 exception model */
152 POWERPC_EXCP_7x0,
153 /* PowerPC 7x5 exception model */
154 POWERPC_EXCP_7x5,
155 /* PowerPC 74xx exception model */
156 POWERPC_EXCP_74xx,
157 /* BookE exception model */
158 POWERPC_EXCP_BOOKE,
159 #if defined(TARGET_PPC64)
160 /* PowerPC 970 exception model */
161 POWERPC_EXCP_970,
162 /* POWER7 exception model */
163 POWERPC_EXCP_POWER7,
164 #endif /* defined(TARGET_PPC64) */
165 };
166
167 /*****************************************************************************/
168 /* Exception vectors definitions */
169 enum {
170 POWERPC_EXCP_NONE = -1,
171 /* The 64 first entries are used by the PowerPC embedded specification */
172 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
173 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
174 POWERPC_EXCP_DSI = 2, /* Data storage exception */
175 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
176 POWERPC_EXCP_EXTERNAL = 4, /* External input */
177 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
178 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
179 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
180 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
181 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
182 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
183 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
184 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
185 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
186 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
187 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
188 /* Vectors 16 to 31 are reserved */
189 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
190 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
191 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
192 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
193 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
194 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
195 POWERPC_EXCP_GDOORI = 38, /* Embedded guest doorbell interrupt */
196 POWERPC_EXCP_GDOORCI = 39, /* Embedded guest doorbell critical interrupt*/
197 POWERPC_EXCP_HYPPRIV = 41, /* Embedded hypervisor priv instruction */
198 /* Vectors 42 to 63 are reserved */
199 /* Exceptions defined in the PowerPC server specification */
200 POWERPC_EXCP_RESET = 64, /* System reset exception */
201 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
202 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
203 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
204 POWERPC_EXCP_TRACE = 68, /* Trace exception */
205 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
206 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
207 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
208 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
209 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
210 /* 40x specific exceptions */
211 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
212 /* 601 specific exceptions */
213 POWERPC_EXCP_IO = 75, /* IO error exception */
214 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
215 /* 602 specific exceptions */
216 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
217 /* 602/603 specific exceptions */
218 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
219 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
220 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
221 /* Exceptions available on most PowerPC */
222 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
223 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
224 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
225 POWERPC_EXCP_SMI = 84, /* System management interrupt */
226 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
227 /* 7xx/74xx specific exceptions */
228 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
229 /* 74xx specific exceptions */
230 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
231 /* 970FX specific exceptions */
232 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
233 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
234 /* Freescale embedded cores specific exceptions */
235 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
236 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
237 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
238 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
239 /* EOL */
240 POWERPC_EXCP_NB = 96,
241 /* QEMU exceptions: used internally during code translation */
242 POWERPC_EXCP_STOP = 0x200, /* stop translation */
243 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
244 /* QEMU exceptions: special cases we want to stop translation */
245 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
246 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
247 POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */
248 };
249
250 /* Exceptions error codes */
251 enum {
252 /* Exception subtypes for POWERPC_EXCP_ALIGN */
253 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
254 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
255 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
256 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
257 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
258 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
259 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
260 /* FP exceptions */
261 POWERPC_EXCP_FP = 0x10,
262 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
263 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
264 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
265 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
266 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
267 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
268 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
269 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
270 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
271 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
272 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
273 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
274 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
275 /* Invalid instruction */
276 POWERPC_EXCP_INVAL = 0x20,
277 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
278 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
279 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
280 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
281 /* Privileged instruction */
282 POWERPC_EXCP_PRIV = 0x30,
283 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
284 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
285 /* Trap */
286 POWERPC_EXCP_TRAP = 0x40,
287 };
288
289 /*****************************************************************************/
290 /* Input pins model */
291 typedef enum powerpc_input_t powerpc_input_t;
292 enum powerpc_input_t {
293 PPC_FLAGS_INPUT_UNKNOWN = 0,
294 /* PowerPC 6xx bus */
295 PPC_FLAGS_INPUT_6xx,
296 /* BookE bus */
297 PPC_FLAGS_INPUT_BookE,
298 /* PowerPC 405 bus */
299 PPC_FLAGS_INPUT_405,
300 /* PowerPC 970 bus */
301 PPC_FLAGS_INPUT_970,
302 /* PowerPC POWER7 bus */
303 PPC_FLAGS_INPUT_POWER7,
304 /* PowerPC 401 bus */
305 PPC_FLAGS_INPUT_401,
306 /* Freescale RCPU bus */
307 PPC_FLAGS_INPUT_RCPU,
308 };
309
310 #define PPC_INPUT(env) (env->bus_model)
311
312 /*****************************************************************************/
313 typedef struct opc_handler_t opc_handler_t;
314
315 /*****************************************************************************/
316 /* Types used to describe some PowerPC registers */
317 typedef struct CPUPPCState CPUPPCState;
318 typedef struct ppc_tb_t ppc_tb_t;
319 typedef struct ppc_spr_t ppc_spr_t;
320 typedef struct ppc_dcr_t ppc_dcr_t;
321 typedef union ppc_avr_t ppc_avr_t;
322 typedef union ppc_tlb_t ppc_tlb_t;
323
324 /* SPR access micro-ops generations callbacks */
325 struct ppc_spr_t {
326 void (*uea_read)(void *opaque, int gpr_num, int spr_num);
327 void (*uea_write)(void *opaque, int spr_num, int gpr_num);
328 #if !defined(CONFIG_USER_ONLY)
329 void (*oea_read)(void *opaque, int gpr_num, int spr_num);
330 void (*oea_write)(void *opaque, int spr_num, int gpr_num);
331 void (*hea_read)(void *opaque, int gpr_num, int spr_num);
332 void (*hea_write)(void *opaque, int spr_num, int gpr_num);
333 #endif
334 const char *name;
335 #ifdef CONFIG_KVM
336 /* We (ab)use the fact that all the SPRs will have ids for the
337 * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
338 * don't sync this */
339 uint64_t one_reg_id;
340 #endif
341 };
342
343 /* Altivec registers (128 bits) */
344 union ppc_avr_t {
345 float32 f[4];
346 uint8_t u8[16];
347 uint16_t u16[8];
348 uint32_t u32[4];
349 int8_t s8[16];
350 int16_t s16[8];
351 int32_t s32[4];
352 uint64_t u64[2];
353 };
354
355 #if !defined(CONFIG_USER_ONLY)
356 /* Software TLB cache */
357 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
358 struct ppc6xx_tlb_t {
359 target_ulong pte0;
360 target_ulong pte1;
361 target_ulong EPN;
362 };
363
364 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
365 struct ppcemb_tlb_t {
366 uint64_t RPN;
367 target_ulong EPN;
368 target_ulong PID;
369 target_ulong size;
370 uint32_t prot;
371 uint32_t attr; /* Storage attributes */
372 };
373
374 typedef struct ppcmas_tlb_t {
375 uint32_t mas8;
376 uint32_t mas1;
377 uint64_t mas2;
378 uint64_t mas7_3;
379 } ppcmas_tlb_t;
380
381 union ppc_tlb_t {
382 ppc6xx_tlb_t *tlb6;
383 ppcemb_tlb_t *tlbe;
384 ppcmas_tlb_t *tlbm;
385 };
386
387 /* possible TLB variants */
388 #define TLB_NONE 0
389 #define TLB_6XX 1
390 #define TLB_EMB 2
391 #define TLB_MAS 3
392 #endif
393
394 #define SDR_32_HTABORG 0xFFFF0000UL
395 #define SDR_32_HTABMASK 0x000001FFUL
396
397 #if defined(TARGET_PPC64)
398 #define SDR_64_HTABORG 0xFFFFFFFFFFFC0000ULL
399 #define SDR_64_HTABSIZE 0x000000000000001FULL
400 #endif /* defined(TARGET_PPC64 */
401
402 typedef struct ppc_slb_t ppc_slb_t;
403 struct ppc_slb_t {
404 uint64_t esid;
405 uint64_t vsid;
406 };
407
408 #define MAX_SLB_ENTRIES 64
409 #define SEGMENT_SHIFT_256M 28
410 #define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
411
412 #define SEGMENT_SHIFT_1T 40
413 #define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
414
415
416 /*****************************************************************************/
417 /* Machine state register bits definition */
418 #define MSR_SF 63 /* Sixty-four-bit mode hflags */
419 #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
420 #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
421 #define MSR_SHV 60 /* hypervisor state hflags */
422 #define MSR_CM 31 /* Computation mode for BookE hflags */
423 #define MSR_ICM 30 /* Interrupt computation mode for BookE */
424 #define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
425 #define MSR_GS 28 /* guest state for BookE */
426 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
427 #define MSR_VR 25 /* altivec available x hflags */
428 #define MSR_SPE 25 /* SPE enable for BookE x hflags */
429 #define MSR_AP 23 /* Access privilege state on 602 hflags */
430 #define MSR_SA 22 /* Supervisor access mode on 602 hflags */
431 #define MSR_KEY 19 /* key bit on 603e */
432 #define MSR_POW 18 /* Power management */
433 #define MSR_TGPR 17 /* TGPR usage on 602/603 x */
434 #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
435 #define MSR_ILE 16 /* Interrupt little-endian mode */
436 #define MSR_EE 15 /* External interrupt enable */
437 #define MSR_PR 14 /* Problem state hflags */
438 #define MSR_FP 13 /* Floating point available hflags */
439 #define MSR_ME 12 /* Machine check interrupt enable */
440 #define MSR_FE0 11 /* Floating point exception mode 0 hflags */
441 #define MSR_SE 10 /* Single-step trace enable x hflags */
442 #define MSR_DWE 10 /* Debug wait enable on 405 x */
443 #define MSR_UBLE 10 /* User BTB lock enable on e500 x */
444 #define MSR_BE 9 /* Branch trace enable x hflags */
445 #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
446 #define MSR_FE1 8 /* Floating point exception mode 1 hflags */
447 #define MSR_AL 7 /* AL bit on POWER */
448 #define MSR_EP 6 /* Exception prefix on 601 */
449 #define MSR_IR 5 /* Instruction relocate */
450 #define MSR_DR 4 /* Data relocate */
451 #define MSR_PE 3 /* Protection enable on 403 */
452 #define MSR_PX 2 /* Protection exclusive on 403 x */
453 #define MSR_PMM 2 /* Performance monitor mark on POWER x */
454 #define MSR_RI 1 /* Recoverable interrupt 1 */
455 #define MSR_LE 0 /* Little-endian mode 1 hflags */
456
457 #define LPCR_ILE (1 << (63-38))
458
459 #define msr_sf ((env->msr >> MSR_SF) & 1)
460 #define msr_isf ((env->msr >> MSR_ISF) & 1)
461 #define msr_shv ((env->msr >> MSR_SHV) & 1)
462 #define msr_cm ((env->msr >> MSR_CM) & 1)
463 #define msr_icm ((env->msr >> MSR_ICM) & 1)
464 #define msr_thv ((env->msr >> MSR_THV) & 1)
465 #define msr_gs ((env->msr >> MSR_GS) & 1)
466 #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
467 #define msr_vr ((env->msr >> MSR_VR) & 1)
468 #define msr_spe ((env->msr >> MSR_SPE) & 1)
469 #define msr_ap ((env->msr >> MSR_AP) & 1)
470 #define msr_sa ((env->msr >> MSR_SA) & 1)
471 #define msr_key ((env->msr >> MSR_KEY) & 1)
472 #define msr_pow ((env->msr >> MSR_POW) & 1)
473 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
474 #define msr_ce ((env->msr >> MSR_CE) & 1)
475 #define msr_ile ((env->msr >> MSR_ILE) & 1)
476 #define msr_ee ((env->msr >> MSR_EE) & 1)
477 #define msr_pr ((env->msr >> MSR_PR) & 1)
478 #define msr_fp ((env->msr >> MSR_FP) & 1)
479 #define msr_me ((env->msr >> MSR_ME) & 1)
480 #define msr_fe0 ((env->msr >> MSR_FE0) & 1)
481 #define msr_se ((env->msr >> MSR_SE) & 1)
482 #define msr_dwe ((env->msr >> MSR_DWE) & 1)
483 #define msr_uble ((env->msr >> MSR_UBLE) & 1)
484 #define msr_be ((env->msr >> MSR_BE) & 1)
485 #define msr_de ((env->msr >> MSR_DE) & 1)
486 #define msr_fe1 ((env->msr >> MSR_FE1) & 1)
487 #define msr_al ((env->msr >> MSR_AL) & 1)
488 #define msr_ep ((env->msr >> MSR_EP) & 1)
489 #define msr_ir ((env->msr >> MSR_IR) & 1)
490 #define msr_dr ((env->msr >> MSR_DR) & 1)
491 #define msr_pe ((env->msr >> MSR_PE) & 1)
492 #define msr_px ((env->msr >> MSR_PX) & 1)
493 #define msr_pmm ((env->msr >> MSR_PMM) & 1)
494 #define msr_ri ((env->msr >> MSR_RI) & 1)
495 #define msr_le ((env->msr >> MSR_LE) & 1)
496 /* Hypervisor bit is more specific */
497 #if defined(TARGET_PPC64)
498 #define MSR_HVB (1ULL << MSR_SHV)
499 #define msr_hv msr_shv
500 #else
501 #if defined(PPC_EMULATE_32BITS_HYPV)
502 #define MSR_HVB (1ULL << MSR_THV)
503 #define msr_hv msr_thv
504 #else
505 #define MSR_HVB (0ULL)
506 #define msr_hv (0)
507 #endif
508 #endif
509
510 /* Exception state register bits definition */
511 #define ESR_PIL (1 << (63 - 36)) /* Illegal Instruction */
512 #define ESR_PPR (1 << (63 - 37)) /* Privileged Instruction */
513 #define ESR_PTR (1 << (63 - 38)) /* Trap */
514 #define ESR_FP (1 << (63 - 39)) /* Floating-Point Operation */
515 #define ESR_ST (1 << (63 - 40)) /* Store Operation */
516 #define ESR_AP (1 << (63 - 44)) /* Auxiliary Processor Operation */
517 #define ESR_PUO (1 << (63 - 45)) /* Unimplemented Operation */
518 #define ESR_BO (1 << (63 - 46)) /* Byte Ordering */
519 #define ESR_PIE (1 << (63 - 47)) /* Imprecise exception */
520 #define ESR_DATA (1 << (63 - 53)) /* Data Access (Embedded page table) */
521 #define ESR_TLBI (1 << (63 - 54)) /* TLB Ineligible (Embedded page table) */
522 #define ESR_PT (1 << (63 - 55)) /* Page Table (Embedded page table) */
523 #define ESR_SPV (1 << (63 - 56)) /* SPE/VMX operation */
524 #define ESR_EPID (1 << (63 - 57)) /* External Process ID operation */
525 #define ESR_VLEMI (1 << (63 - 58)) /* VLE operation */
526 #define ESR_MIF (1 << (63 - 62)) /* Misaligned instruction (VLE) */
527
528 enum {
529 POWERPC_FLAG_NONE = 0x00000000,
530 /* Flag for MSR bit 25 signification (VRE/SPE) */
531 POWERPC_FLAG_SPE = 0x00000001,
532 POWERPC_FLAG_VRE = 0x00000002,
533 /* Flag for MSR bit 17 signification (TGPR/CE) */
534 POWERPC_FLAG_TGPR = 0x00000004,
535 POWERPC_FLAG_CE = 0x00000008,
536 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
537 POWERPC_FLAG_SE = 0x00000010,
538 POWERPC_FLAG_DWE = 0x00000020,
539 POWERPC_FLAG_UBLE = 0x00000040,
540 /* Flag for MSR bit 9 signification (BE/DE) */
541 POWERPC_FLAG_BE = 0x00000080,
542 POWERPC_FLAG_DE = 0x00000100,
543 /* Flag for MSR bit 2 signification (PX/PMM) */
544 POWERPC_FLAG_PX = 0x00000200,
545 POWERPC_FLAG_PMM = 0x00000400,
546 /* Flag for special features */
547 /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
548 POWERPC_FLAG_RTC_CLK = 0x00010000,
549 POWERPC_FLAG_BUS_CLK = 0x00020000,
550 /* Has CFAR */
551 POWERPC_FLAG_CFAR = 0x00040000,
552 };
553
554 /*****************************************************************************/
555 /* Floating point status and control register */
556 #define FPSCR_FX 31 /* Floating-point exception summary */
557 #define FPSCR_FEX 30 /* Floating-point enabled exception summary */
558 #define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
559 #define FPSCR_OX 28 /* Floating-point overflow exception */
560 #define FPSCR_UX 27 /* Floating-point underflow exception */
561 #define FPSCR_ZX 26 /* Floating-point zero divide exception */
562 #define FPSCR_XX 25 /* Floating-point inexact exception */
563 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
564 #define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
565 #define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
566 #define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
567 #define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
568 #define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
569 #define FPSCR_FR 18 /* Floating-point fraction rounded */
570 #define FPSCR_FI 17 /* Floating-point fraction inexact */
571 #define FPSCR_C 16 /* Floating-point result class descriptor */
572 #define FPSCR_FL 15 /* Floating-point less than or negative */
573 #define FPSCR_FG 14 /* Floating-point greater than or negative */
574 #define FPSCR_FE 13 /* Floating-point equal or zero */
575 #define FPSCR_FU 12 /* Floating-point unordered or NaN */
576 #define FPSCR_FPCC 12 /* Floating-point condition code */
577 #define FPSCR_FPRF 12 /* Floating-point result flags */
578 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
579 #define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
580 #define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
581 #define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
582 #define FPSCR_OE 6 /* Floating-point overflow exception enable */
583 #define FPSCR_UE 5 /* Floating-point undeflow exception enable */
584 #define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
585 #define FPSCR_XE 3 /* Floating-point inexact exception enable */
586 #define FPSCR_NI 2 /* Floating-point non-IEEE mode */
587 #define FPSCR_RN1 1
588 #define FPSCR_RN 0 /* Floating-point rounding control */
589 #define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
590 #define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
591 #define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
592 #define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
593 #define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
594 #define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
595 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
596 #define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
597 #define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
598 #define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
599 #define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
600 #define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
601 #define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
602 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
603 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
604 #define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
605 #define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
606 #define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
607 #define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
608 #define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
609 #define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
610 #define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
611 #define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
612 /* Invalid operation exception summary */
613 #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
614 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
615 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
616 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
617 (1 << FPSCR_VXCVI)))
618 /* exception summary */
619 #define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
620 /* enabled exception summary */
621 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
622 0x1F)
623
624 /*****************************************************************************/
625 /* Vector status and control register */
626 #define VSCR_NJ 16 /* Vector non-java */
627 #define VSCR_SAT 0 /* Vector saturation */
628 #define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
629 #define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
630
631 /*****************************************************************************/
632 /* BookE e500 MMU registers */
633
634 #define MAS0_NV_SHIFT 0
635 #define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
636
637 #define MAS0_WQ_SHIFT 12
638 #define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
639 /* Write TLB entry regardless of reservation */
640 #define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
641 /* Write TLB entry only already in use */
642 #define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
643 /* Clear TLB entry */
644 #define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
645
646 #define MAS0_HES_SHIFT 14
647 #define MAS0_HES (1 << MAS0_HES_SHIFT)
648
649 #define MAS0_ESEL_SHIFT 16
650 #define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
651
652 #define MAS0_TLBSEL_SHIFT 28
653 #define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
654 #define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
655 #define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
656 #define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
657 #define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
658
659 #define MAS0_ATSEL_SHIFT 31
660 #define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
661 #define MAS0_ATSEL_TLB 0
662 #define MAS0_ATSEL_LRAT MAS0_ATSEL
663
664 #define MAS1_TSIZE_SHIFT 7
665 #define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT)
666
667 #define MAS1_TS_SHIFT 12
668 #define MAS1_TS (1 << MAS1_TS_SHIFT)
669
670 #define MAS1_IND_SHIFT 13
671 #define MAS1_IND (1 << MAS1_IND_SHIFT)
672
673 #define MAS1_TID_SHIFT 16
674 #define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
675
676 #define MAS1_IPROT_SHIFT 30
677 #define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
678
679 #define MAS1_VALID_SHIFT 31
680 #define MAS1_VALID 0x80000000
681
682 #define MAS2_EPN_SHIFT 12
683 #define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT)
684
685 #define MAS2_ACM_SHIFT 6
686 #define MAS2_ACM (1 << MAS2_ACM_SHIFT)
687
688 #define MAS2_VLE_SHIFT 5
689 #define MAS2_VLE (1 << MAS2_VLE_SHIFT)
690
691 #define MAS2_W_SHIFT 4
692 #define MAS2_W (1 << MAS2_W_SHIFT)
693
694 #define MAS2_I_SHIFT 3
695 #define MAS2_I (1 << MAS2_I_SHIFT)
696
697 #define MAS2_M_SHIFT 2
698 #define MAS2_M (1 << MAS2_M_SHIFT)
699
700 #define MAS2_G_SHIFT 1
701 #define MAS2_G (1 << MAS2_G_SHIFT)
702
703 #define MAS2_E_SHIFT 0
704 #define MAS2_E (1 << MAS2_E_SHIFT)
705
706 #define MAS3_RPN_SHIFT 12
707 #define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
708
709 #define MAS3_U0 0x00000200
710 #define MAS3_U1 0x00000100
711 #define MAS3_U2 0x00000080
712 #define MAS3_U3 0x00000040
713 #define MAS3_UX 0x00000020
714 #define MAS3_SX 0x00000010
715 #define MAS3_UW 0x00000008
716 #define MAS3_SW 0x00000004
717 #define MAS3_UR 0x00000002
718 #define MAS3_SR 0x00000001
719 #define MAS3_SPSIZE_SHIFT 1
720 #define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
721
722 #define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
723 #define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
724 #define MAS4_TIDSELD_MASK 0x00030000
725 #define MAS4_TIDSELD_PID0 0x00000000
726 #define MAS4_TIDSELD_PID1 0x00010000
727 #define MAS4_TIDSELD_PID2 0x00020000
728 #define MAS4_TIDSELD_PIDZ 0x00030000
729 #define MAS4_INDD 0x00008000 /* Default IND */
730 #define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
731 #define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
732 #define MAS4_ACMD 0x00000040
733 #define MAS4_VLED 0x00000020
734 #define MAS4_WD 0x00000010
735 #define MAS4_ID 0x00000008
736 #define MAS4_MD 0x00000004
737 #define MAS4_GD 0x00000002
738 #define MAS4_ED 0x00000001
739 #define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
740 #define MAS4_WIMGED_SHIFT 0
741
742 #define MAS5_SGS 0x80000000
743 #define MAS5_SLPID_MASK 0x00000fff
744
745 #define MAS6_SPID0 0x3fff0000
746 #define MAS6_SPID1 0x00007ffe
747 #define MAS6_ISIZE(x) MAS1_TSIZE(x)
748 #define MAS6_SAS 0x00000001
749 #define MAS6_SPID MAS6_SPID0
750 #define MAS6_SIND 0x00000002 /* Indirect page */
751 #define MAS6_SIND_SHIFT 1
752 #define MAS6_SPID_MASK 0x3fff0000
753 #define MAS6_SPID_SHIFT 16
754 #define MAS6_ISIZE_MASK 0x00000f80
755 #define MAS6_ISIZE_SHIFT 7
756
757 #define MAS7_RPN 0xffffffff
758
759 #define MAS8_TGS 0x80000000
760 #define MAS8_VF 0x40000000
761 #define MAS8_TLBPID 0x00000fff
762
763 /* Bit definitions for MMUCFG */
764 #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
765 #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
766 #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
767 #define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
768 #define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
769 #define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
770 #define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
771 #define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
772 #define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
773
774 /* Bit definitions for MMUCSR0 */
775 #define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
776 #define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
777 #define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
778 #define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
779 #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
780 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
781 #define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
782 #define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
783 #define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
784 #define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
785
786 /* TLBnCFG encoding */
787 #define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
788 #define TLBnCFG_HES 0x00002000 /* HW select supported */
789 #define TLBnCFG_AVAIL 0x00004000 /* variable page size */
790 #define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
791 #define TLBnCFG_GTWE 0x00010000 /* Guest can write */
792 #define TLBnCFG_IND 0x00020000 /* IND entries supported */
793 #define TLBnCFG_PT 0x00040000 /* Can load from page table */
794 #define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
795 #define TLBnCFG_MINSIZE_SHIFT 20
796 #define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
797 #define TLBnCFG_MAXSIZE_SHIFT 16
798 #define TLBnCFG_ASSOC 0xff000000 /* Associativity */
799 #define TLBnCFG_ASSOC_SHIFT 24
800
801 /* TLBnPS encoding */
802 #define TLBnPS_4K 0x00000004
803 #define TLBnPS_8K 0x00000008
804 #define TLBnPS_16K 0x00000010
805 #define TLBnPS_32K 0x00000020
806 #define TLBnPS_64K 0x00000040
807 #define TLBnPS_128K 0x00000080
808 #define TLBnPS_256K 0x00000100
809 #define TLBnPS_512K 0x00000200
810 #define TLBnPS_1M 0x00000400
811 #define TLBnPS_2M 0x00000800
812 #define TLBnPS_4M 0x00001000
813 #define TLBnPS_8M 0x00002000
814 #define TLBnPS_16M 0x00004000
815 #define TLBnPS_32M 0x00008000
816 #define TLBnPS_64M 0x00010000
817 #define TLBnPS_128M 0x00020000
818 #define TLBnPS_256M 0x00040000
819 #define TLBnPS_512M 0x00080000
820 #define TLBnPS_1G 0x00100000
821 #define TLBnPS_2G 0x00200000
822 #define TLBnPS_4G 0x00400000
823 #define TLBnPS_8G 0x00800000
824 #define TLBnPS_16G 0x01000000
825 #define TLBnPS_32G 0x02000000
826 #define TLBnPS_64G 0x04000000
827 #define TLBnPS_128G 0x08000000
828 #define TLBnPS_256G 0x10000000
829
830 /* tlbilx action encoding */
831 #define TLBILX_T_ALL 0
832 #define TLBILX_T_TID 1
833 #define TLBILX_T_FULLMATCH 3
834 #define TLBILX_T_CLASS0 4
835 #define TLBILX_T_CLASS1 5
836 #define TLBILX_T_CLASS2 6
837 #define TLBILX_T_CLASS3 7
838
839 /* BookE 2.06 helper defines */
840
841 #define BOOKE206_FLUSH_TLB0 (1 << 0)
842 #define BOOKE206_FLUSH_TLB1 (1 << 1)
843 #define BOOKE206_FLUSH_TLB2 (1 << 2)
844 #define BOOKE206_FLUSH_TLB3 (1 << 3)
845
846 /* number of possible TLBs */
847 #define BOOKE206_MAX_TLBN 4
848
849 /*****************************************************************************/
850 /* Embedded.Processor Control */
851
852 #define DBELL_TYPE_SHIFT 27
853 #define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT)
854 #define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT)
855 #define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT)
856 #define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT)
857 #define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT)
858 #define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT)
859
860 #define DBELL_BRDCAST (1 << 26)
861 #define DBELL_LPIDTAG_SHIFT 14
862 #define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT)
863 #define DBELL_PIRTAG_MASK 0x3fff
864
865 /*****************************************************************************/
866 /* Segment page size information, used by recent hash MMUs
867 * The format of this structure mirrors kvm_ppc_smmu_info
868 */
869
870 #define PPC_PAGE_SIZES_MAX_SZ 8
871
872 struct ppc_one_page_size {
873 uint32_t page_shift; /* Page shift (or 0) */
874 uint32_t pte_enc; /* Encoding in the HPTE (>>12) */
875 };
876
877 struct ppc_one_seg_page_size {
878 uint32_t page_shift; /* Base page shift of segment (or 0) */
879 uint32_t slb_enc; /* SLB encoding for BookS */
880 struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
881 };
882
883 struct ppc_segment_page_sizes {
884 struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
885 };
886
887
888 /*****************************************************************************/
889 /* The whole PowerPC CPU context */
890 #define NB_MMU_MODES 3
891
892 #define PPC_CPU_OPCODES_LEN 0x40
893
894 struct CPUPPCState {
895 /* First are the most commonly used resources
896 * during translated code execution
897 */
898 /* general purpose registers */
899 target_ulong gpr[32];
900 #if !defined(TARGET_PPC64)
901 /* Storage for GPR MSB, used by the SPE extension */
902 target_ulong gprh[32];
903 #endif
904 /* LR */
905 target_ulong lr;
906 /* CTR */
907 target_ulong ctr;
908 /* condition register */
909 uint32_t crf[8];
910 #if defined(TARGET_PPC64)
911 /* CFAR */
912 target_ulong cfar;
913 #endif
914 /* XER (with SO, OV, CA split out) */
915 target_ulong xer;
916 target_ulong so;
917 target_ulong ov;
918 target_ulong ca;
919 /* Reservation address */
920 target_ulong reserve_addr;
921 /* Reservation value */
922 target_ulong reserve_val;
923 /* Reservation store address */
924 target_ulong reserve_ea;
925 /* Reserved store source register and size */
926 target_ulong reserve_info;
927
928 /* Those ones are used in supervisor mode only */
929 /* machine state register */
930 target_ulong msr;
931 /* temporary general purpose registers */
932 target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
933
934 /* Floating point execution context */
935 float_status fp_status;
936 /* floating point registers */
937 float64 fpr[32];
938 /* floating point status and control register */
939 target_ulong fpscr;
940
941 /* Next instruction pointer */
942 target_ulong nip;
943
944 int access_type; /* when a memory exception occurs, the access
945 type is stored here */
946
947 CPU_COMMON
948
949 /* MMU context - only relevant for full system emulation */
950 #if !defined(CONFIG_USER_ONLY)
951 #if defined(TARGET_PPC64)
952 /* PowerPC 64 SLB area */
953 ppc_slb_t slb[MAX_SLB_ENTRIES];
954 int32_t slb_nr;
955 #endif
956 /* segment registers */
957 hwaddr htab_base;
958 hwaddr htab_mask;
959 target_ulong sr[32];
960 /* externally stored hash table */
961 uint8_t *external_htab;
962 /* BATs */
963 uint32_t nb_BATs;
964 target_ulong DBAT[2][8];
965 target_ulong IBAT[2][8];
966 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
967 int32_t nb_tlb; /* Total number of TLB */
968 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
969 int nb_ways; /* Number of ways in the TLB set */
970 int last_way; /* Last used way used to allocate TLB in a LRU way */
971 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
972 int nb_pids; /* Number of available PID registers */
973 int tlb_type; /* Type of TLB we're dealing with */
974 ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
975 /* 403 dedicated access protection registers */
976 target_ulong pb[4];
977 bool tlb_dirty; /* Set to non-zero when modifying TLB */
978 bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
979 #endif
980
981 /* Other registers */
982 /* Special purpose registers */
983 target_ulong spr[1024];
984 ppc_spr_t spr_cb[1024];
985 /* Altivec registers */
986 ppc_avr_t avr[32];
987 uint32_t vscr;
988 /* VSX registers */
989 uint64_t vsr[32];
990 /* SPE registers */
991 uint64_t spe_acc;
992 uint32_t spe_fscr;
993 /* SPE and Altivec can share a status since they will never be used
994 * simultaneously */
995 float_status vec_status;
996
997 /* Internal devices resources */
998 /* Time base and decrementer */
999 ppc_tb_t *tb_env;
1000 /* Device control registers */
1001 ppc_dcr_t *dcr_env;
1002
1003 int dcache_line_size;
1004 int icache_line_size;
1005
1006 /* Those resources are used during exception processing */
1007 /* CPU model definition */
1008 target_ulong msr_mask;
1009 powerpc_mmu_t mmu_model;
1010 powerpc_excp_t excp_model;
1011 powerpc_input_t bus_model;
1012 int bfd_mach;
1013 uint32_t flags;
1014 uint64_t insns_flags;
1015 uint64_t insns_flags2;
1016 #if defined(TARGET_PPC64)
1017 struct ppc_segment_page_sizes sps;
1018 #endif
1019
1020 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1021 uint64_t vpa_addr;
1022 uint64_t slb_shadow_addr, slb_shadow_size;
1023 uint64_t dtl_addr, dtl_size;
1024 #endif /* TARGET_PPC64 */
1025
1026 int error_code;
1027 uint32_t pending_interrupts;
1028 #if !defined(CONFIG_USER_ONLY)
1029 /* This is the IRQ controller, which is implementation dependent
1030 * and only relevant when emulating a complete machine.
1031 */
1032 uint32_t irq_input_state;
1033 void **irq_inputs;
1034 /* Exception vectors */
1035 target_ulong excp_vectors[POWERPC_EXCP_NB];
1036 target_ulong excp_prefix;
1037 target_ulong ivor_mask;
1038 target_ulong ivpr_mask;
1039 target_ulong hreset_vector;
1040 hwaddr mpic_iack;
1041 /* true when the external proxy facility mode is enabled */
1042 bool mpic_proxy;
1043 #endif
1044
1045 /* Those resources are used only during code translation */
1046 /* opcode handlers */
1047 opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1048
1049 /* Those resources are used only in QEMU core */
1050 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
1051 target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
1052 int mmu_idx; /* precomputed MMU index to speed up mem accesses */
1053
1054 /* Power management */
1055 int (*check_pow)(CPUPPCState *env);
1056
1057 #if !defined(CONFIG_USER_ONLY)
1058 void *load_info; /* Holds boot loading state. */
1059 #endif
1060
1061 /* booke timers */
1062
1063 /* Specifies bit locations of the Time Base used to signal a fixed timer
1064 * exception on a transition from 0 to 1. (watchdog or fixed-interval timer)
1065 *
1066 * 0 selects the least significant bit.
1067 * 63 selects the most significant bit.
1068 */
1069 uint8_t fit_period[4];
1070 uint8_t wdt_period[4];
1071 };
1072
1073 #define SET_FIT_PERIOD(a_, b_, c_, d_) \
1074 do { \
1075 env->fit_period[0] = (a_); \
1076 env->fit_period[1] = (b_); \
1077 env->fit_period[2] = (c_); \
1078 env->fit_period[3] = (d_); \
1079 } while (0)
1080
1081 #define SET_WDT_PERIOD(a_, b_, c_, d_) \
1082 do { \
1083 env->wdt_period[0] = (a_); \
1084 env->wdt_period[1] = (b_); \
1085 env->wdt_period[2] = (c_); \
1086 env->wdt_period[3] = (d_); \
1087 } while (0)
1088
1089 #include "cpu-qom.h"
1090
1091 /*****************************************************************************/
1092 PowerPCCPU *cpu_ppc_init(const char *cpu_model);
1093 void ppc_translate_init(void);
1094 int cpu_ppc_exec (CPUPPCState *s);
1095 /* you can call this signal handler from your SIGBUS and SIGSEGV
1096 signal handlers to inform the virtual CPU of exceptions. non zero
1097 is returned if the signal was handled by the virtual CPU. */
1098 int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1099 void *puc);
1100 void ppc_hw_interrupt (CPUPPCState *env);
1101 #if defined(CONFIG_USER_ONLY)
1102 int cpu_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw,
1103 int mmu_idx);
1104 #endif
1105
1106 #if !defined(CONFIG_USER_ONLY)
1107 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
1108 #endif /* !defined(CONFIG_USER_ONLY) */
1109 void ppc_store_msr (CPUPPCState *env, target_ulong value);
1110
1111 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
1112
1113 /* Time-base and decrementer management */
1114 #ifndef NO_CPU_IO_DEFS
1115 uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
1116 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1117 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1118 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
1119 uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
1120 uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1121 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1122 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
1123 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1124 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
1125 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1126 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1127 uint64_t cpu_ppc_load_purr (CPUPPCState *env);
1128 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1129 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1130 #if !defined(CONFIG_USER_ONLY)
1131 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1132 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1133 target_ulong load_40x_pit (CPUPPCState *env);
1134 void store_40x_pit (CPUPPCState *env, target_ulong val);
1135 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
1136 void store_40x_sler (CPUPPCState *env, uint32_t val);
1137 void store_booke_tcr (CPUPPCState *env, target_ulong val);
1138 void store_booke_tsr (CPUPPCState *env, target_ulong val);
1139 void ppc_tlb_invalidate_all (CPUPPCState *env);
1140 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
1141 #endif
1142 #endif
1143
1144 void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
1145
1146 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1147 {
1148 uint64_t gprv;
1149
1150 gprv = env->gpr[gprn];
1151 #if !defined(TARGET_PPC64)
1152 if (env->flags & POWERPC_FLAG_SPE) {
1153 /* If the CPU implements the SPE extension, we have to get the
1154 * high bits of the GPR from the gprh storage area
1155 */
1156 gprv &= 0xFFFFFFFFULL;
1157 gprv |= (uint64_t)env->gprh[gprn] << 32;
1158 }
1159 #endif
1160
1161 return gprv;
1162 }
1163
1164 /* Device control registers */
1165 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1166 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1167
1168 static inline CPUPPCState *cpu_init(const char *cpu_model)
1169 {
1170 PowerPCCPU *cpu = cpu_ppc_init(cpu_model);
1171 if (cpu == NULL) {
1172 return NULL;
1173 }
1174 return &cpu->env;
1175 }
1176
1177 #define cpu_exec cpu_ppc_exec
1178 #define cpu_gen_code cpu_ppc_gen_code
1179 #define cpu_signal_handler cpu_ppc_signal_handler
1180 #define cpu_list ppc_cpu_list
1181
1182 /* MMU modes definitions */
1183 #define MMU_MODE0_SUFFIX _user
1184 #define MMU_MODE1_SUFFIX _kernel
1185 #define MMU_MODE2_SUFFIX _hypv
1186 #define MMU_USER_IDX 0
1187 static inline int cpu_mmu_index (CPUPPCState *env)
1188 {
1189 return env->mmu_idx;
1190 }
1191
1192 #include "exec/cpu-all.h"
1193
1194 /*****************************************************************************/
1195 /* CRF definitions */
1196 #define CRF_LT 3
1197 #define CRF_GT 2
1198 #define CRF_EQ 1
1199 #define CRF_SO 0
1200 #define CRF_CH (1 << CRF_LT)
1201 #define CRF_CL (1 << CRF_GT)
1202 #define CRF_CH_OR_CL (1 << CRF_EQ)
1203 #define CRF_CH_AND_CL (1 << CRF_SO)
1204
1205 /* XER definitions */
1206 #define XER_SO 31
1207 #define XER_OV 30
1208 #define XER_CA 29
1209 #define XER_CMP 8
1210 #define XER_BC 0
1211 #define xer_so (env->so)
1212 #define xer_ov (env->ov)
1213 #define xer_ca (env->ca)
1214 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1215 #define xer_bc ((env->xer >> XER_BC) & 0x7F)
1216
1217 /* SPR definitions */
1218 #define SPR_MQ (0x000)
1219 #define SPR_XER (0x001)
1220 #define SPR_601_VRTCU (0x004)
1221 #define SPR_601_VRTCL (0x005)
1222 #define SPR_601_UDECR (0x006)
1223 #define SPR_LR (0x008)
1224 #define SPR_CTR (0x009)
1225 #define SPR_UAMR (0x00C)
1226 #define SPR_DSCR (0x011)
1227 #define SPR_DSISR (0x012)
1228 #define SPR_DAR (0x013) /* DAE for PowerPC 601 */
1229 #define SPR_601_RTCU (0x014)
1230 #define SPR_601_RTCL (0x015)
1231 #define SPR_DECR (0x016)
1232 #define SPR_SDR1 (0x019)
1233 #define SPR_SRR0 (0x01A)
1234 #define SPR_SRR1 (0x01B)
1235 #define SPR_CFAR (0x01C)
1236 #define SPR_AMR (0x01D)
1237 #define SPR_BOOKE_PID (0x030)
1238 #define SPR_BOOKE_DECAR (0x036)
1239 #define SPR_BOOKE_CSRR0 (0x03A)
1240 #define SPR_BOOKE_CSRR1 (0x03B)
1241 #define SPR_BOOKE_DEAR (0x03D)
1242 #define SPR_BOOKE_ESR (0x03E)
1243 #define SPR_BOOKE_IVPR (0x03F)
1244 #define SPR_MPC_EIE (0x050)
1245 #define SPR_MPC_EID (0x051)
1246 #define SPR_MPC_NRI (0x052)
1247 #define SPR_CTRL (0x088)
1248 #define SPR_MPC_CMPA (0x090)
1249 #define SPR_MPC_CMPB (0x091)
1250 #define SPR_MPC_CMPC (0x092)
1251 #define SPR_MPC_CMPD (0x093)
1252 #define SPR_MPC_ECR (0x094)
1253 #define SPR_MPC_DER (0x095)
1254 #define SPR_MPC_COUNTA (0x096)
1255 #define SPR_MPC_COUNTB (0x097)
1256 #define SPR_UCTRL (0x098)
1257 #define SPR_MPC_CMPE (0x098)
1258 #define SPR_MPC_CMPF (0x099)
1259 #define SPR_MPC_CMPG (0x09A)
1260 #define SPR_MPC_CMPH (0x09B)
1261 #define SPR_MPC_LCTRL1 (0x09C)
1262 #define SPR_MPC_LCTRL2 (0x09D)
1263 #define SPR_UAMOR (0x09D)
1264 #define SPR_MPC_ICTRL (0x09E)
1265 #define SPR_MPC_BAR (0x09F)
1266 #define SPR_VRSAVE (0x100)
1267 #define SPR_USPRG0 (0x100)
1268 #define SPR_USPRG1 (0x101)
1269 #define SPR_USPRG2 (0x102)
1270 #define SPR_USPRG3 (0x103)
1271 #define SPR_USPRG4 (0x104)
1272 #define SPR_USPRG5 (0x105)
1273 #define SPR_USPRG6 (0x106)
1274 #define SPR_USPRG7 (0x107)
1275 #define SPR_VTBL (0x10C)
1276 #define SPR_VTBU (0x10D)
1277 #define SPR_SPRG0 (0x110)
1278 #define SPR_SPRG1 (0x111)
1279 #define SPR_SPRG2 (0x112)
1280 #define SPR_SPRG3 (0x113)
1281 #define SPR_SPRG4 (0x114)
1282 #define SPR_SCOMC (0x114)
1283 #define SPR_SPRG5 (0x115)
1284 #define SPR_SCOMD (0x115)
1285 #define SPR_SPRG6 (0x116)
1286 #define SPR_SPRG7 (0x117)
1287 #define SPR_ASR (0x118)
1288 #define SPR_EAR (0x11A)
1289 #define SPR_TBL (0x11C)
1290 #define SPR_TBU (0x11D)
1291 #define SPR_TBU40 (0x11E)
1292 #define SPR_SVR (0x11E)
1293 #define SPR_BOOKE_PIR (0x11E)
1294 #define SPR_PVR (0x11F)
1295 #define SPR_HSPRG0 (0x130)
1296 #define SPR_BOOKE_DBSR (0x130)
1297 #define SPR_HSPRG1 (0x131)
1298 #define SPR_HDSISR (0x132)
1299 #define SPR_HDAR (0x133)
1300 #define SPR_BOOKE_EPCR (0x133)
1301 #define SPR_SPURR (0x134)
1302 #define SPR_BOOKE_DBCR0 (0x134)
1303 #define SPR_IBCR (0x135)
1304 #define SPR_PURR (0x135)
1305 #define SPR_BOOKE_DBCR1 (0x135)
1306 #define SPR_DBCR (0x136)
1307 #define SPR_HDEC (0x136)
1308 #define SPR_BOOKE_DBCR2 (0x136)
1309 #define SPR_HIOR (0x137)
1310 #define SPR_MBAR (0x137)
1311 #define SPR_RMOR (0x138)
1312 #define SPR_BOOKE_IAC1 (0x138)
1313 #define SPR_HRMOR (0x139)
1314 #define SPR_BOOKE_IAC2 (0x139)
1315 #define SPR_HSRR0 (0x13A)
1316 #define SPR_BOOKE_IAC3 (0x13A)
1317 #define SPR_HSRR1 (0x13B)
1318 #define SPR_BOOKE_IAC4 (0x13B)
1319 #define SPR_LPCR (0x13C)
1320 #define SPR_BOOKE_DAC1 (0x13C)
1321 #define SPR_LPIDR (0x13D)
1322 #define SPR_DABR2 (0x13D)
1323 #define SPR_BOOKE_DAC2 (0x13D)
1324 #define SPR_BOOKE_DVC1 (0x13E)
1325 #define SPR_BOOKE_DVC2 (0x13F)
1326 #define SPR_BOOKE_TSR (0x150)
1327 #define SPR_BOOKE_TCR (0x154)
1328 #define SPR_BOOKE_TLB0PS (0x158)
1329 #define SPR_BOOKE_TLB1PS (0x159)
1330 #define SPR_BOOKE_TLB2PS (0x15A)
1331 #define SPR_BOOKE_TLB3PS (0x15B)
1332 #define SPR_BOOKE_MAS7_MAS3 (0x174)
1333 #define SPR_BOOKE_IVOR0 (0x190)
1334 #define SPR_BOOKE_IVOR1 (0x191)
1335 #define SPR_BOOKE_IVOR2 (0x192)
1336 #define SPR_BOOKE_IVOR3 (0x193)
1337 #define SPR_BOOKE_IVOR4 (0x194)
1338 #define SPR_BOOKE_IVOR5 (0x195)
1339 #define SPR_BOOKE_IVOR6 (0x196)
1340 #define SPR_BOOKE_IVOR7 (0x197)
1341 #define SPR_BOOKE_IVOR8 (0x198)
1342 #define SPR_BOOKE_IVOR9 (0x199)
1343 #define SPR_BOOKE_IVOR10 (0x19A)
1344 #define SPR_BOOKE_IVOR11 (0x19B)
1345 #define SPR_BOOKE_IVOR12 (0x19C)
1346 #define SPR_BOOKE_IVOR13 (0x19D)
1347 #define SPR_BOOKE_IVOR14 (0x19E)
1348 #define SPR_BOOKE_IVOR15 (0x19F)
1349 #define SPR_BOOKE_IVOR38 (0x1B0)
1350 #define SPR_BOOKE_IVOR39 (0x1B1)
1351 #define SPR_BOOKE_IVOR40 (0x1B2)
1352 #define SPR_BOOKE_IVOR41 (0x1B3)
1353 #define SPR_BOOKE_IVOR42 (0x1B4)
1354 #define SPR_BOOKE_SPEFSCR (0x200)
1355 #define SPR_Exxx_BBEAR (0x201)
1356 #define SPR_Exxx_BBTAR (0x202)
1357 #define SPR_Exxx_L1CFG0 (0x203)
1358 #define SPR_Exxx_NPIDR (0x205)
1359 #define SPR_ATBL (0x20E)
1360 #define SPR_ATBU (0x20F)
1361 #define SPR_IBAT0U (0x210)
1362 #define SPR_BOOKE_IVOR32 (0x210)
1363 #define SPR_RCPU_MI_GRA (0x210)
1364 #define SPR_IBAT0L (0x211)
1365 #define SPR_BOOKE_IVOR33 (0x211)
1366 #define SPR_IBAT1U (0x212)
1367 #define SPR_BOOKE_IVOR34 (0x212)
1368 #define SPR_IBAT1L (0x213)
1369 #define SPR_BOOKE_IVOR35 (0x213)
1370 #define SPR_IBAT2U (0x214)
1371 #define SPR_BOOKE_IVOR36 (0x214)
1372 #define SPR_IBAT2L (0x215)
1373 #define SPR_BOOKE_IVOR37 (0x215)
1374 #define SPR_IBAT3U (0x216)
1375 #define SPR_IBAT3L (0x217)
1376 #define SPR_DBAT0U (0x218)
1377 #define SPR_RCPU_L2U_GRA (0x218)
1378 #define SPR_DBAT0L (0x219)
1379 #define SPR_DBAT1U (0x21A)
1380 #define SPR_DBAT1L (0x21B)
1381 #define SPR_DBAT2U (0x21C)
1382 #define SPR_DBAT2L (0x21D)
1383 #define SPR_DBAT3U (0x21E)
1384 #define SPR_DBAT3L (0x21F)
1385 #define SPR_IBAT4U (0x230)
1386 #define SPR_RPCU_BBCMCR (0x230)
1387 #define SPR_MPC_IC_CST (0x230)
1388 #define SPR_Exxx_CTXCR (0x230)
1389 #define SPR_IBAT4L (0x231)
1390 #define SPR_MPC_IC_ADR (0x231)
1391 #define SPR_Exxx_DBCR3 (0x231)
1392 #define SPR_IBAT5U (0x232)
1393 #define SPR_MPC_IC_DAT (0x232)
1394 #define SPR_Exxx_DBCNT (0x232)
1395 #define SPR_IBAT5L (0x233)
1396 #define SPR_IBAT6U (0x234)
1397 #define SPR_IBAT6L (0x235)
1398 #define SPR_IBAT7U (0x236)
1399 #define SPR_IBAT7L (0x237)
1400 #define SPR_DBAT4U (0x238)
1401 #define SPR_RCPU_L2U_MCR (0x238)
1402 #define SPR_MPC_DC_CST (0x238)
1403 #define SPR_Exxx_ALTCTXCR (0x238)
1404 #define SPR_DBAT4L (0x239)
1405 #define SPR_MPC_DC_ADR (0x239)
1406 #define SPR_DBAT5U (0x23A)
1407 #define SPR_BOOKE_MCSRR0 (0x23A)
1408 #define SPR_MPC_DC_DAT (0x23A)
1409 #define SPR_DBAT5L (0x23B)
1410 #define SPR_BOOKE_MCSRR1 (0x23B)
1411 #define SPR_DBAT6U (0x23C)
1412 #define SPR_BOOKE_MCSR (0x23C)
1413 #define SPR_DBAT6L (0x23D)
1414 #define SPR_Exxx_MCAR (0x23D)
1415 #define SPR_DBAT7U (0x23E)
1416 #define SPR_BOOKE_DSRR0 (0x23E)
1417 #define SPR_DBAT7L (0x23F)
1418 #define SPR_BOOKE_DSRR1 (0x23F)
1419 #define SPR_BOOKE_SPRG8 (0x25C)
1420 #define SPR_BOOKE_SPRG9 (0x25D)
1421 #define SPR_BOOKE_MAS0 (0x270)
1422 #define SPR_BOOKE_MAS1 (0x271)
1423 #define SPR_BOOKE_MAS2 (0x272)
1424 #define SPR_BOOKE_MAS3 (0x273)
1425 #define SPR_BOOKE_MAS4 (0x274)
1426 #define SPR_BOOKE_MAS5 (0x275)
1427 #define SPR_BOOKE_MAS6 (0x276)
1428 #define SPR_BOOKE_PID1 (0x279)
1429 #define SPR_BOOKE_PID2 (0x27A)
1430 #define SPR_MPC_DPDR (0x280)
1431 #define SPR_MPC_IMMR (0x288)
1432 #define SPR_BOOKE_TLB0CFG (0x2B0)
1433 #define SPR_BOOKE_TLB1CFG (0x2B1)
1434 #define SPR_BOOKE_TLB2CFG (0x2B2)
1435 #define SPR_BOOKE_TLB3CFG (0x2B3)
1436 #define SPR_BOOKE_EPR (0x2BE)
1437 #define SPR_PERF0 (0x300)
1438 #define SPR_RCPU_MI_RBA0 (0x300)
1439 #define SPR_MPC_MI_CTR (0x300)
1440 #define SPR_PERF1 (0x301)
1441 #define SPR_RCPU_MI_RBA1 (0x301)
1442 #define SPR_PERF2 (0x302)
1443 #define SPR_RCPU_MI_RBA2 (0x302)
1444 #define SPR_MPC_MI_AP (0x302)
1445 #define SPR_MMCRA (0x302)
1446 #define SPR_PERF3 (0x303)
1447 #define SPR_RCPU_MI_RBA3 (0x303)
1448 #define SPR_MPC_MI_EPN (0x303)
1449 #define SPR_PERF4 (0x304)
1450 #define SPR_PERF5 (0x305)
1451 #define SPR_MPC_MI_TWC (0x305)
1452 #define SPR_PERF6 (0x306)
1453 #define SPR_MPC_MI_RPN (0x306)
1454 #define SPR_PERF7 (0x307)
1455 #define SPR_PERF8 (0x308)
1456 #define SPR_RCPU_L2U_RBA0 (0x308)
1457 #define SPR_MPC_MD_CTR (0x308)
1458 #define SPR_PERF9 (0x309)
1459 #define SPR_RCPU_L2U_RBA1 (0x309)
1460 #define SPR_MPC_MD_CASID (0x309)
1461 #define SPR_PERFA (0x30A)
1462 #define SPR_RCPU_L2U_RBA2 (0x30A)
1463 #define SPR_MPC_MD_AP (0x30A)
1464 #define SPR_PERFB (0x30B)
1465 #define SPR_RCPU_L2U_RBA3 (0x30B)
1466 #define SPR_MPC_MD_EPN (0x30B)
1467 #define SPR_PERFC (0x30C)
1468 #define SPR_MPC_MD_TWB (0x30C)
1469 #define SPR_PERFD (0x30D)
1470 #define SPR_MPC_MD_TWC (0x30D)
1471 #define SPR_PERFE (0x30E)
1472 #define SPR_MPC_MD_RPN (0x30E)
1473 #define SPR_PERFF (0x30F)
1474 #define SPR_MPC_MD_TW (0x30F)
1475 #define SPR_UPERF0 (0x310)
1476 #define SPR_UPERF1 (0x311)
1477 #define SPR_UPERF2 (0x312)
1478 #define SPR_UPERF3 (0x313)
1479 #define SPR_UPERF4 (0x314)
1480 #define SPR_UPERF5 (0x315)
1481 #define SPR_UPERF6 (0x316)
1482 #define SPR_UPERF7 (0x317)
1483 #define SPR_UPERF8 (0x318)
1484 #define SPR_UPERF9 (0x319)
1485 #define SPR_UPERFA (0x31A)
1486 #define SPR_UPERFB (0x31B)
1487 #define SPR_UPERFC (0x31C)
1488 #define SPR_UPERFD (0x31D)
1489 #define SPR_UPERFE (0x31E)
1490 #define SPR_UPERFF (0x31F)
1491 #define SPR_RCPU_MI_RA0 (0x320)
1492 #define SPR_MPC_MI_DBCAM (0x320)
1493 #define SPR_RCPU_MI_RA1 (0x321)
1494 #define SPR_MPC_MI_DBRAM0 (0x321)
1495 #define SPR_RCPU_MI_RA2 (0x322)
1496 #define SPR_MPC_MI_DBRAM1 (0x322)
1497 #define SPR_RCPU_MI_RA3 (0x323)
1498 #define SPR_RCPU_L2U_RA0 (0x328)
1499 #define SPR_MPC_MD_DBCAM (0x328)
1500 #define SPR_RCPU_L2U_RA1 (0x329)
1501 #define SPR_MPC_MD_DBRAM0 (0x329)
1502 #define SPR_RCPU_L2U_RA2 (0x32A)
1503 #define SPR_MPC_MD_DBRAM1 (0x32A)
1504 #define SPR_RCPU_L2U_RA3 (0x32B)
1505 #define SPR_440_INV0 (0x370)
1506 #define SPR_440_INV1 (0x371)
1507 #define SPR_440_INV2 (0x372)
1508 #define SPR_440_INV3 (0x373)
1509 #define SPR_440_ITV0 (0x374)
1510 #define SPR_440_ITV1 (0x375)
1511 #define SPR_440_ITV2 (0x376)
1512 #define SPR_440_ITV3 (0x377)
1513 #define SPR_440_CCR1 (0x378)
1514 #define SPR_DCRIPR (0x37B)
1515 #define SPR_PPR (0x380)
1516 #define SPR_750_GQR0 (0x390)
1517 #define SPR_440_DNV0 (0x390)
1518 #define SPR_750_GQR1 (0x391)
1519 #define SPR_440_DNV1 (0x391)
1520 #define SPR_750_GQR2 (0x392)
1521 #define SPR_440_DNV2 (0x392)
1522 #define SPR_750_GQR3 (0x393)
1523 #define SPR_440_DNV3 (0x393)
1524 #define SPR_750_GQR4 (0x394)
1525 #define SPR_440_DTV0 (0x394)
1526 #define SPR_750_GQR5 (0x395)
1527 #define SPR_440_DTV1 (0x395)
1528 #define SPR_750_GQR6 (0x396)
1529 #define SPR_440_DTV2 (0x396)
1530 #define SPR_750_GQR7 (0x397)
1531 #define SPR_440_DTV3 (0x397)
1532 #define SPR_750_THRM4 (0x398)
1533 #define SPR_750CL_HID2 (0x398)
1534 #define SPR_440_DVLIM (0x398)
1535 #define SPR_750_WPAR (0x399)
1536 #define SPR_440_IVLIM (0x399)
1537 #define SPR_750_DMAU (0x39A)
1538 #define SPR_750_DMAL (0x39B)
1539 #define SPR_440_RSTCFG (0x39B)
1540 #define SPR_BOOKE_DCDBTRL (0x39C)
1541 #define SPR_BOOKE_DCDBTRH (0x39D)
1542 #define SPR_BOOKE_ICDBTRL (0x39E)
1543 #define SPR_BOOKE_ICDBTRH (0x39F)
1544 #define SPR_UMMCR2 (0x3A0)
1545 #define SPR_UPMC5 (0x3A1)
1546 #define SPR_UPMC6 (0x3A2)
1547 #define SPR_UBAMR (0x3A7)
1548 #define SPR_UMMCR0 (0x3A8)
1549 #define SPR_UPMC1 (0x3A9)
1550 #define SPR_UPMC2 (0x3AA)
1551 #define SPR_USIAR (0x3AB)
1552 #define SPR_UMMCR1 (0x3AC)
1553 #define SPR_UPMC3 (0x3AD)
1554 #define SPR_UPMC4 (0x3AE)
1555 #define SPR_USDA (0x3AF)
1556 #define SPR_40x_ZPR (0x3B0)
1557 #define SPR_BOOKE_MAS7 (0x3B0)
1558 #define SPR_MMCR2 (0x3B0)
1559 #define SPR_PMC5 (0x3B1)
1560 #define SPR_40x_PID (0x3B1)
1561 #define SPR_PMC6 (0x3B2)
1562 #define SPR_440_MMUCR (0x3B2)
1563 #define SPR_4xx_CCR0 (0x3B3)
1564 #define SPR_BOOKE_EPLC (0x3B3)
1565 #define SPR_405_IAC3 (0x3B4)
1566 #define SPR_BOOKE_EPSC (0x3B4)
1567 #define SPR_405_IAC4 (0x3B5)
1568 #define SPR_405_DVC1 (0x3B6)
1569 #define SPR_405_DVC2 (0x3B7)
1570 #define SPR_BAMR (0x3B7)
1571 #define SPR_MMCR0 (0x3B8)
1572 #define SPR_PMC1 (0x3B9)
1573 #define SPR_40x_SGR (0x3B9)
1574 #define SPR_PMC2 (0x3BA)
1575 #define SPR_40x_DCWR (0x3BA)
1576 #define SPR_SIAR (0x3BB)
1577 #define SPR_405_SLER (0x3BB)
1578 #define SPR_MMCR1 (0x3BC)
1579 #define SPR_405_SU0R (0x3BC)
1580 #define SPR_401_SKR (0x3BC)
1581 #define SPR_PMC3 (0x3BD)
1582 #define SPR_405_DBCR1 (0x3BD)
1583 #define SPR_PMC4 (0x3BE)
1584 #define SPR_SDA (0x3BF)
1585 #define SPR_403_VTBL (0x3CC)
1586 #define SPR_403_VTBU (0x3CD)
1587 #define SPR_DMISS (0x3D0)
1588 #define SPR_DCMP (0x3D1)
1589 #define SPR_HASH1 (0x3D2)
1590 #define SPR_HASH2 (0x3D3)
1591 #define SPR_BOOKE_ICDBDR (0x3D3)
1592 #define SPR_TLBMISS (0x3D4)
1593 #define SPR_IMISS (0x3D4)
1594 #define SPR_40x_ESR (0x3D4)
1595 #define SPR_PTEHI (0x3D5)
1596 #define SPR_ICMP (0x3D5)
1597 #define SPR_40x_DEAR (0x3D5)
1598 #define SPR_PTELO (0x3D6)
1599 #define SPR_RPA (0x3D6)
1600 #define SPR_40x_EVPR (0x3D6)
1601 #define SPR_L3PM (0x3D7)
1602 #define SPR_403_CDBCR (0x3D7)
1603 #define SPR_L3ITCR0 (0x3D8)
1604 #define SPR_TCR (0x3D8)
1605 #define SPR_40x_TSR (0x3D8)
1606 #define SPR_IBR (0x3DA)
1607 #define SPR_40x_TCR (0x3DA)
1608 #define SPR_ESASRR (0x3DB)
1609 #define SPR_40x_PIT (0x3DB)
1610 #define SPR_403_TBL (0x3DC)
1611 #define SPR_403_TBU (0x3DD)
1612 #define SPR_SEBR (0x3DE)
1613 #define SPR_40x_SRR2 (0x3DE)
1614 #define SPR_SER (0x3DF)
1615 #define SPR_40x_SRR3 (0x3DF)
1616 #define SPR_L3OHCR (0x3E8)
1617 #define SPR_L3ITCR1 (0x3E9)
1618 #define SPR_L3ITCR2 (0x3EA)
1619 #define SPR_L3ITCR3 (0x3EB)
1620 #define SPR_HID0 (0x3F0)
1621 #define SPR_40x_DBSR (0x3F0)
1622 #define SPR_HID1 (0x3F1)
1623 #define SPR_IABR (0x3F2)
1624 #define SPR_40x_DBCR0 (0x3F2)
1625 #define SPR_601_HID2 (0x3F2)
1626 #define SPR_Exxx_L1CSR0 (0x3F2)
1627 #define SPR_ICTRL (0x3F3)
1628 #define SPR_HID2 (0x3F3)
1629 #define SPR_750CL_HID4 (0x3F3)
1630 #define SPR_Exxx_L1CSR1 (0x3F3)
1631 #define SPR_440_DBDR (0x3F3)
1632 #define SPR_LDSTDB (0x3F4)
1633 #define SPR_750_TDCL (0x3F4)
1634 #define SPR_40x_IAC1 (0x3F4)
1635 #define SPR_MMUCSR0 (0x3F4)
1636 #define SPR_DABR (0x3F5)
1637 #define DABR_MASK (~(target_ulong)0x7)
1638 #define SPR_Exxx_BUCSR (0x3F5)
1639 #define SPR_40x_IAC2 (0x3F5)
1640 #define SPR_601_HID5 (0x3F5)
1641 #define SPR_40x_DAC1 (0x3F6)
1642 #define SPR_MSSCR0 (0x3F6)
1643 #define SPR_970_HID5 (0x3F6)
1644 #define SPR_MSSSR0 (0x3F7)
1645 #define SPR_MSSCR1 (0x3F7)
1646 #define SPR_DABRX (0x3F7)
1647 #define SPR_40x_DAC2 (0x3F7)
1648 #define SPR_MMUCFG (0x3F7)
1649 #define SPR_LDSTCR (0x3F8)
1650 #define SPR_L2PMCR (0x3F8)
1651 #define SPR_750FX_HID2 (0x3F8)
1652 #define SPR_Exxx_L1FINV0 (0x3F8)
1653 #define SPR_L2CR (0x3F9)
1654 #define SPR_L3CR (0x3FA)
1655 #define SPR_750_TDCH (0x3FA)
1656 #define SPR_IABR2 (0x3FA)
1657 #define SPR_40x_DCCR (0x3FA)
1658 #define SPR_ICTC (0x3FB)
1659 #define SPR_40x_ICCR (0x3FB)
1660 #define SPR_THRM1 (0x3FC)
1661 #define SPR_403_PBL1 (0x3FC)
1662 #define SPR_SP (0x3FD)
1663 #define SPR_THRM2 (0x3FD)
1664 #define SPR_403_PBU1 (0x3FD)
1665 #define SPR_604_HID13 (0x3FD)
1666 #define SPR_LT (0x3FE)
1667 #define SPR_THRM3 (0x3FE)
1668 #define SPR_RCPU_FPECR (0x3FE)
1669 #define SPR_403_PBL2 (0x3FE)
1670 #define SPR_PIR (0x3FF)
1671 #define SPR_403_PBU2 (0x3FF)
1672 #define SPR_601_HID15 (0x3FF)
1673 #define SPR_604_HID15 (0x3FF)
1674 #define SPR_E500_SVR (0x3FF)
1675
1676 /* Disable MAS Interrupt Updates for Hypervisor */
1677 #define EPCR_DMIUH (1 << 22)
1678 /* Disable Guest TLB Management Instructions */
1679 #define EPCR_DGTMI (1 << 23)
1680 /* Guest Interrupt Computation Mode */
1681 #define EPCR_GICM (1 << 24)
1682 /* Interrupt Computation Mode */
1683 #define EPCR_ICM (1 << 25)
1684 /* Disable Embedded Hypervisor Debug */
1685 #define EPCR_DUVD (1 << 26)
1686 /* Instruction Storage Interrupt Directed to Guest State */
1687 #define EPCR_ISIGS (1 << 27)
1688 /* Data Storage Interrupt Directed to Guest State */
1689 #define EPCR_DSIGS (1 << 28)
1690 /* Instruction TLB Error Interrupt Directed to Guest State */
1691 #define EPCR_ITLBGS (1 << 29)
1692 /* Data TLB Error Interrupt Directed to Guest State */
1693 #define EPCR_DTLBGS (1 << 30)
1694 /* External Input Interrupt Directed to Guest State */
1695 #define EPCR_EXTGS (1 << 31)
1696
1697 /*****************************************************************************/
1698 /* PowerPC Instructions types definitions */
1699 enum {
1700 PPC_NONE = 0x0000000000000000ULL,
1701 /* PowerPC base instructions set */
1702 PPC_INSNS_BASE = 0x0000000000000001ULL,
1703 /* integer operations instructions */
1704 #define PPC_INTEGER PPC_INSNS_BASE
1705 /* flow control instructions */
1706 #define PPC_FLOW PPC_INSNS_BASE
1707 /* virtual memory instructions */
1708 #define PPC_MEM PPC_INSNS_BASE
1709 /* ld/st with reservation instructions */
1710 #define PPC_RES PPC_INSNS_BASE
1711 /* spr/msr access instructions */
1712 #define PPC_MISC PPC_INSNS_BASE
1713 /* Deprecated instruction sets */
1714 /* Original POWER instruction set */
1715 PPC_POWER = 0x0000000000000002ULL,
1716 /* POWER2 instruction set extension */
1717 PPC_POWER2 = 0x0000000000000004ULL,
1718 /* Power RTC support */
1719 PPC_POWER_RTC = 0x0000000000000008ULL,
1720 /* Power-to-PowerPC bridge (601) */
1721 PPC_POWER_BR = 0x0000000000000010ULL,
1722 /* 64 bits PowerPC instruction set */
1723 PPC_64B = 0x0000000000000020ULL,
1724 /* New 64 bits extensions (PowerPC 2.0x) */
1725 PPC_64BX = 0x0000000000000040ULL,
1726 /* 64 bits hypervisor extensions */
1727 PPC_64H = 0x0000000000000080ULL,
1728 /* New wait instruction (PowerPC 2.0x) */
1729 PPC_WAIT = 0x0000000000000100ULL,
1730 /* Time base mftb instruction */
1731 PPC_MFTB = 0x0000000000000200ULL,
1732
1733 /* Fixed-point unit extensions */
1734 /* PowerPC 602 specific */
1735 PPC_602_SPEC = 0x0000000000000400ULL,
1736 /* isel instruction */
1737 PPC_ISEL = 0x0000000000000800ULL,
1738 /* popcntb instruction */
1739 PPC_POPCNTB = 0x0000000000001000ULL,
1740 /* string load / store */
1741 PPC_STRING = 0x0000000000002000ULL,
1742
1743 /* Floating-point unit extensions */
1744 /* Optional floating point instructions */
1745 PPC_FLOAT = 0x0000000000010000ULL,
1746 /* New floating-point extensions (PowerPC 2.0x) */
1747 PPC_FLOAT_EXT = 0x0000000000020000ULL,
1748 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
1749 PPC_FLOAT_FRES = 0x0000000000080000ULL,
1750 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
1751 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
1752 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
1753 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
1754
1755 /* Vector/SIMD extensions */
1756 /* Altivec support */
1757 PPC_ALTIVEC = 0x0000000001000000ULL,
1758 /* PowerPC 2.03 SPE extension */
1759 PPC_SPE = 0x0000000002000000ULL,
1760 /* PowerPC 2.03 SPE single-precision floating-point extension */
1761 PPC_SPE_SINGLE = 0x0000000004000000ULL,
1762 /* PowerPC 2.03 SPE double-precision floating-point extension */
1763 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
1764
1765 /* Optional memory control instructions */
1766 PPC_MEM_TLBIA = 0x0000000010000000ULL,
1767 PPC_MEM_TLBIE = 0x0000000020000000ULL,
1768 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
1769 /* sync instruction */
1770 PPC_MEM_SYNC = 0x0000000080000000ULL,
1771 /* eieio instruction */
1772 PPC_MEM_EIEIO = 0x0000000100000000ULL,
1773
1774 /* Cache control instructions */
1775 PPC_CACHE = 0x0000000200000000ULL,
1776 /* icbi instruction */
1777 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1778 /* dcbz instruction */
1779 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1780 /* dcba instruction */
1781 PPC_CACHE_DCBA = 0x0000002000000000ULL,
1782 /* Freescale cache locking instructions */
1783 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1784
1785 /* MMU related extensions */
1786 /* external control instructions */
1787 PPC_EXTERN = 0x0000010000000000ULL,
1788 /* segment register access instructions */
1789 PPC_SEGMENT = 0x0000020000000000ULL,
1790 /* PowerPC 6xx TLB management instructions */
1791 PPC_6xx_TLB = 0x0000040000000000ULL,
1792 /* PowerPC 74xx TLB management instructions */
1793 PPC_74xx_TLB = 0x0000080000000000ULL,
1794 /* PowerPC 40x TLB management instructions */
1795 PPC_40x_TLB = 0x0000100000000000ULL,
1796 /* segment register access instructions for PowerPC 64 "bridge" */
1797 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1798 /* SLB management */
1799 PPC_SLBI = 0x0000400000000000ULL,
1800
1801 /* Embedded PowerPC dedicated instructions */
1802 PPC_WRTEE = 0x0001000000000000ULL,
1803 /* PowerPC 40x exception model */
1804 PPC_40x_EXCP = 0x0002000000000000ULL,
1805 /* PowerPC 405 Mac instructions */
1806 PPC_405_MAC = 0x0004000000000000ULL,
1807 /* PowerPC 440 specific instructions */
1808 PPC_440_SPEC = 0x0008000000000000ULL,
1809 /* BookE (embedded) PowerPC specification */
1810 PPC_BOOKE = 0x0010000000000000ULL,
1811 /* mfapidi instruction */
1812 PPC_MFAPIDI = 0x0020000000000000ULL,
1813 /* tlbiva instruction */
1814 PPC_TLBIVA = 0x0040000000000000ULL,
1815 /* tlbivax instruction */
1816 PPC_TLBIVAX = 0x0080000000000000ULL,
1817 /* PowerPC 4xx dedicated instructions */
1818 PPC_4xx_COMMON = 0x0100000000000000ULL,
1819 /* PowerPC 40x ibct instructions */
1820 PPC_40x_ICBT = 0x0200000000000000ULL,
1821 /* rfmci is not implemented in all BookE PowerPC */
1822 PPC_RFMCI = 0x0400000000000000ULL,
1823 /* rfdi instruction */
1824 PPC_RFDI = 0x0800000000000000ULL,
1825 /* DCR accesses */
1826 PPC_DCR = 0x1000000000000000ULL,
1827 /* DCR extended accesse */
1828 PPC_DCRX = 0x2000000000000000ULL,
1829 /* user-mode DCR access, implemented in PowerPC 460 */
1830 PPC_DCRUX = 0x4000000000000000ULL,
1831 /* popcntw and popcntd instructions */
1832 PPC_POPCNTWD = 0x8000000000000000ULL,
1833
1834 #define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
1835 | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
1836 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
1837 | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
1838 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
1839 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
1840 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
1841 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
1842 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
1843 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
1844 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
1845 | PPC_MEM_SYNC | PPC_MEM_EIEIO \
1846 | PPC_CACHE | PPC_CACHE_ICBI \
1847 | PPC_CACHE_DCBZ \
1848 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
1849 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
1850 | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
1851 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
1852 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
1853 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
1854 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
1855 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
1856 | PPC_POPCNTWD)
1857
1858 /* extended type values */
1859
1860 /* BookE 2.06 PowerPC specification */
1861 PPC2_BOOKE206 = 0x0000000000000001ULL,
1862 /* VSX (extensions to Altivec / VMX) */
1863 PPC2_VSX = 0x0000000000000002ULL,
1864 /* Decimal Floating Point (DFP) */
1865 PPC2_DFP = 0x0000000000000004ULL,
1866 /* Embedded.Processor Control */
1867 PPC2_PRCNTL = 0x0000000000000008ULL,
1868 /* Byte-reversed, indexed, double-word load and store */
1869 PPC2_DBRX = 0x0000000000000010ULL,
1870 /* Book I 2.05 PowerPC specification */
1871 PPC2_ISA205 = 0x0000000000000020ULL,
1872
1873 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_DBRX | PPC2_ISA205)
1874 };
1875
1876 /*****************************************************************************/
1877 /* Memory access type :
1878 * may be needed for precise access rights control and precise exceptions.
1879 */
1880 enum {
1881 /* 1 bit to define user level / supervisor access */
1882 ACCESS_USER = 0x00,
1883 ACCESS_SUPER = 0x01,
1884 /* Type of instruction that generated the access */
1885 ACCESS_CODE = 0x10, /* Code fetch access */
1886 ACCESS_INT = 0x20, /* Integer load/store access */
1887 ACCESS_FLOAT = 0x30, /* floating point load/store access */
1888 ACCESS_RES = 0x40, /* load/store with reservation */
1889 ACCESS_EXT = 0x50, /* external access */
1890 ACCESS_CACHE = 0x60, /* Cache manipulation */
1891 };
1892
1893 /* Hardware interruption sources:
1894 * all those exception can be raised simulteaneously
1895 */
1896 /* Input pins definitions */
1897 enum {
1898 /* 6xx bus input pins */
1899 PPC6xx_INPUT_HRESET = 0,
1900 PPC6xx_INPUT_SRESET = 1,
1901 PPC6xx_INPUT_CKSTP_IN = 2,
1902 PPC6xx_INPUT_MCP = 3,
1903 PPC6xx_INPUT_SMI = 4,
1904 PPC6xx_INPUT_INT = 5,
1905 PPC6xx_INPUT_TBEN = 6,
1906 PPC6xx_INPUT_WAKEUP = 7,
1907 PPC6xx_INPUT_NB,
1908 };
1909
1910 enum {
1911 /* Embedded PowerPC input pins */
1912 PPCBookE_INPUT_HRESET = 0,
1913 PPCBookE_INPUT_SRESET = 1,
1914 PPCBookE_INPUT_CKSTP_IN = 2,
1915 PPCBookE_INPUT_MCP = 3,
1916 PPCBookE_INPUT_SMI = 4,
1917 PPCBookE_INPUT_INT = 5,
1918 PPCBookE_INPUT_CINT = 6,
1919 PPCBookE_INPUT_NB,
1920 };
1921
1922 enum {
1923 /* PowerPC E500 input pins */
1924 PPCE500_INPUT_RESET_CORE = 0,
1925 PPCE500_INPUT_MCK = 1,
1926 PPCE500_INPUT_CINT = 3,
1927 PPCE500_INPUT_INT = 4,
1928 PPCE500_INPUT_DEBUG = 6,
1929 PPCE500_INPUT_NB,
1930 };
1931
1932 enum {
1933 /* PowerPC 40x input pins */
1934 PPC40x_INPUT_RESET_CORE = 0,
1935 PPC40x_INPUT_RESET_CHIP = 1,
1936 PPC40x_INPUT_RESET_SYS = 2,
1937 PPC40x_INPUT_CINT = 3,
1938 PPC40x_INPUT_INT = 4,
1939 PPC40x_INPUT_HALT = 5,
1940 PPC40x_INPUT_DEBUG = 6,
1941 PPC40x_INPUT_NB,
1942 };
1943
1944 enum {
1945 /* RCPU input pins */
1946 PPCRCPU_INPUT_PORESET = 0,
1947 PPCRCPU_INPUT_HRESET = 1,
1948 PPCRCPU_INPUT_SRESET = 2,
1949 PPCRCPU_INPUT_IRQ0 = 3,
1950 PPCRCPU_INPUT_IRQ1 = 4,
1951 PPCRCPU_INPUT_IRQ2 = 5,
1952 PPCRCPU_INPUT_IRQ3 = 6,
1953 PPCRCPU_INPUT_IRQ4 = 7,
1954 PPCRCPU_INPUT_IRQ5 = 8,
1955 PPCRCPU_INPUT_IRQ6 = 9,
1956 PPCRCPU_INPUT_IRQ7 = 10,
1957 PPCRCPU_INPUT_NB,
1958 };
1959
1960 #if defined(TARGET_PPC64)
1961 enum {
1962 /* PowerPC 970 input pins */
1963 PPC970_INPUT_HRESET = 0,
1964 PPC970_INPUT_SRESET = 1,
1965 PPC970_INPUT_CKSTP = 2,
1966 PPC970_INPUT_TBEN = 3,
1967 PPC970_INPUT_MCP = 4,
1968 PPC970_INPUT_INT = 5,
1969 PPC970_INPUT_THINT = 6,
1970 PPC970_INPUT_NB,
1971 };
1972
1973 enum {
1974 /* POWER7 input pins */
1975 POWER7_INPUT_INT = 0,
1976 /* POWER7 probably has other inputs, but we don't care about them
1977 * for any existing machine. We can wire these up when we need
1978 * them */
1979 POWER7_INPUT_NB,
1980 };
1981 #endif
1982
1983 /* Hardware exceptions definitions */
1984 enum {
1985 /* External hardware exception sources */
1986 PPC_INTERRUPT_RESET = 0, /* Reset exception */
1987 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
1988 PPC_INTERRUPT_MCK, /* Machine check exception */
1989 PPC_INTERRUPT_EXT, /* External interrupt */
1990 PPC_INTERRUPT_SMI, /* System management interrupt */
1991 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
1992 PPC_INTERRUPT_DEBUG, /* External debug exception */
1993 PPC_INTERRUPT_THERM, /* Thermal exception */
1994 /* Internal hardware exception sources */
1995 PPC_INTERRUPT_DECR, /* Decrementer exception */
1996 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
1997 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
1998 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
1999 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
2000 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
2001 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
2002 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
2003 };
2004
2005 /* CPU should be reset next, restart from scratch afterwards */
2006 #define CPU_INTERRUPT_RESET CPU_INTERRUPT_TGT_INT_0
2007
2008 /*****************************************************************************/
2009
2010 static inline target_ulong cpu_read_xer(CPUPPCState *env)
2011 {
2012 return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) | (env->ca << XER_CA);
2013 }
2014
2015 static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer)
2016 {
2017 env->so = (xer >> XER_SO) & 1;
2018 env->ov = (xer >> XER_OV) & 1;
2019 env->ca = (xer >> XER_CA) & 1;
2020 env->xer = xer & ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA));
2021 }
2022
2023 static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2024 target_ulong *cs_base, int *flags)
2025 {
2026 *pc = env->nip;
2027 *cs_base = 0;
2028 *flags = env->hflags;
2029 }
2030
2031 #if !defined(CONFIG_USER_ONLY)
2032 static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2033 {
2034 uintptr_t tlbml = (uintptr_t)tlbm;
2035 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2036
2037 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2038 }
2039
2040 static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2041 {
2042 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2043 int r = tlbncfg & TLBnCFG_N_ENTRY;
2044 return r;
2045 }
2046
2047 static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2048 {
2049 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2050 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2051 return r;
2052 }
2053
2054 static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2055 {
2056 int id = booke206_tlbm_id(env, tlbm);
2057 int end = 0;
2058 int i;
2059
2060 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2061 end += booke206_tlb_size(env, i);
2062 if (id < end) {
2063 return i;
2064 }
2065 }
2066
2067 cpu_abort(env, "Unknown TLBe: %d\n", id);
2068 return 0;
2069 }
2070
2071 static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2072 {
2073 int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2074 int tlbid = booke206_tlbm_id(env, tlb);
2075 return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2076 }
2077
2078 static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2079 target_ulong ea, int way)
2080 {
2081 int r;
2082 uint32_t ways = booke206_tlb_ways(env, tlbn);
2083 int ways_bits = ffs(ways) - 1;
2084 int tlb_bits = ffs(booke206_tlb_size(env, tlbn)) - 1;
2085 int i;
2086
2087 way &= ways - 1;
2088 ea >>= MAS2_EPN_SHIFT;
2089 ea &= (1 << (tlb_bits - ways_bits)) - 1;
2090 r = (ea << ways_bits) | way;
2091
2092 if (r >= booke206_tlb_size(env, tlbn)) {
2093 return NULL;
2094 }
2095
2096 /* bump up to tlbn index */
2097 for (i = 0; i < tlbn; i++) {
2098 r += booke206_tlb_size(env, i);
2099 }
2100
2101 return &env->tlb.tlbm[r];
2102 }
2103
2104 /* returns bitmap of supported page sizes for a given TLB */
2105 static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2106 {
2107 bool mav2 = false;
2108 uint32_t ret = 0;
2109
2110 if (mav2) {
2111 ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2112 } else {
2113 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2114 uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2115 uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2116 int i;
2117 for (i = min; i <= max; i++) {
2118 ret |= (1 << (i << 1));
2119 }
2120 }
2121
2122 return ret;
2123 }
2124
2125 #endif
2126
2127 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2128 {
2129 if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2130 return msr & (1ULL << MSR_CM);
2131 }
2132
2133 return msr & (1ULL << MSR_SF);
2134 }
2135
2136 extern void (*cpu_ppc_hypercall)(PowerPCCPU *);
2137
2138 static inline bool cpu_has_work(CPUState *cpu)
2139 {
2140 PowerPCCPU *ppc_cpu = POWERPC_CPU(cpu);
2141 CPUPPCState *env = &ppc_cpu->env;
2142
2143 return msr_ee && (cpu->interrupt_request & CPU_INTERRUPT_HARD);
2144 }
2145
2146 #include "exec/exec-all.h"
2147
2148 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
2149
2150 #endif /* !defined (__CPU_PPC_H__) */
Qemu copy for testing