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1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24 */
25
26 #include "dis-asm.h"
27 #include "gdbstub.h"
28 #include <kvm.h>
29 #include "kvm_ppc.h"
30
31 //#define PPC_DUMP_CPU
32 //#define PPC_DEBUG_SPR
33 //#define PPC_DUMP_SPR_ACCESSES
34 #if defined(CONFIG_USER_ONLY)
35 #define TODO_USER_ONLY 1
36 #endif
37
38 /* For user-mode emulation, we don't emulate any IRQ controller */
39 #if defined(CONFIG_USER_ONLY)
40 #define PPC_IRQ_INIT_FN(name) \
41 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
42 { \
43 }
44 #else
45 #define PPC_IRQ_INIT_FN(name) \
46 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
47 #endif
48
49 PPC_IRQ_INIT_FN(40x);
50 PPC_IRQ_INIT_FN(6xx);
51 PPC_IRQ_INIT_FN(970);
52 PPC_IRQ_INIT_FN(POWER7);
53 PPC_IRQ_INIT_FN(e500);
54
55 /* Generic callbacks:
56 * do nothing but store/retrieve spr value
57 */
58 static void spr_read_generic (void *opaque, int gprn, int sprn)
59 {
60 gen_load_spr(cpu_gpr[gprn], sprn);
61 #ifdef PPC_DUMP_SPR_ACCESSES
62 {
63 TCGv_i32 t0 = tcg_const_i32(sprn);
64 gen_helper_load_dump_spr(t0);
65 tcg_temp_free_i32(t0);
66 }
67 #endif
68 }
69
70 static void spr_write_generic (void *opaque, int sprn, int gprn)
71 {
72 gen_store_spr(sprn, cpu_gpr[gprn]);
73 #ifdef PPC_DUMP_SPR_ACCESSES
74 {
75 TCGv_i32 t0 = tcg_const_i32(sprn);
76 gen_helper_store_dump_spr(t0);
77 tcg_temp_free_i32(t0);
78 }
79 #endif
80 }
81
82 #if !defined(CONFIG_USER_ONLY)
83 static void spr_write_clear (void *opaque, int sprn, int gprn)
84 {
85 TCGv t0 = tcg_temp_new();
86 TCGv t1 = tcg_temp_new();
87 gen_load_spr(t0, sprn);
88 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
89 tcg_gen_and_tl(t0, t0, t1);
90 gen_store_spr(sprn, t0);
91 tcg_temp_free(t0);
92 tcg_temp_free(t1);
93 }
94 #endif
95
96 /* SPR common to all PowerPC */
97 /* XER */
98 static void spr_read_xer (void *opaque, int gprn, int sprn)
99 {
100 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);
101 }
102
103 static void spr_write_xer (void *opaque, int sprn, int gprn)
104 {
105 tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);
106 }
107
108 /* LR */
109 static void spr_read_lr (void *opaque, int gprn, int sprn)
110 {
111 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
112 }
113
114 static void spr_write_lr (void *opaque, int sprn, int gprn)
115 {
116 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
117 }
118
119 /* CFAR */
120 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
121 static void spr_read_cfar (void *opaque, int gprn, int sprn)
122 {
123 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
124 }
125
126 static void spr_write_cfar (void *opaque, int sprn, int gprn)
127 {
128 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
129 }
130 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
131
132 /* CTR */
133 static void spr_read_ctr (void *opaque, int gprn, int sprn)
134 {
135 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
136 }
137
138 static void spr_write_ctr (void *opaque, int sprn, int gprn)
139 {
140 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
141 }
142
143 /* User read access to SPR */
144 /* USPRx */
145 /* UMMCRx */
146 /* UPMCx */
147 /* USIA */
148 /* UDECR */
149 static void spr_read_ureg (void *opaque, int gprn, int sprn)
150 {
151 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
152 }
153
154 /* SPR common to all non-embedded PowerPC */
155 /* DECR */
156 #if !defined(CONFIG_USER_ONLY)
157 static void spr_read_decr (void *opaque, int gprn, int sprn)
158 {
159 if (use_icount) {
160 gen_io_start();
161 }
162 gen_helper_load_decr(cpu_gpr[gprn]);
163 if (use_icount) {
164 gen_io_end();
165 gen_stop_exception(opaque);
166 }
167 }
168
169 static void spr_write_decr (void *opaque, int sprn, int gprn)
170 {
171 if (use_icount) {
172 gen_io_start();
173 }
174 gen_helper_store_decr(cpu_gpr[gprn]);
175 if (use_icount) {
176 gen_io_end();
177 gen_stop_exception(opaque);
178 }
179 }
180 #endif
181
182 /* SPR common to all non-embedded PowerPC, except 601 */
183 /* Time base */
184 static void spr_read_tbl (void *opaque, int gprn, int sprn)
185 {
186 if (use_icount) {
187 gen_io_start();
188 }
189 gen_helper_load_tbl(cpu_gpr[gprn]);
190 if (use_icount) {
191 gen_io_end();
192 gen_stop_exception(opaque);
193 }
194 }
195
196 static void spr_read_tbu (void *opaque, int gprn, int sprn)
197 {
198 if (use_icount) {
199 gen_io_start();
200 }
201 gen_helper_load_tbu(cpu_gpr[gprn]);
202 if (use_icount) {
203 gen_io_end();
204 gen_stop_exception(opaque);
205 }
206 }
207
208 __attribute__ (( unused ))
209 static void spr_read_atbl (void *opaque, int gprn, int sprn)
210 {
211 gen_helper_load_atbl(cpu_gpr[gprn]);
212 }
213
214 __attribute__ (( unused ))
215 static void spr_read_atbu (void *opaque, int gprn, int sprn)
216 {
217 gen_helper_load_atbu(cpu_gpr[gprn]);
218 }
219
220 #if !defined(CONFIG_USER_ONLY)
221 static void spr_write_tbl (void *opaque, int sprn, int gprn)
222 {
223 if (use_icount) {
224 gen_io_start();
225 }
226 gen_helper_store_tbl(cpu_gpr[gprn]);
227 if (use_icount) {
228 gen_io_end();
229 gen_stop_exception(opaque);
230 }
231 }
232
233 static void spr_write_tbu (void *opaque, int sprn, int gprn)
234 {
235 if (use_icount) {
236 gen_io_start();
237 }
238 gen_helper_store_tbu(cpu_gpr[gprn]);
239 if (use_icount) {
240 gen_io_end();
241 gen_stop_exception(opaque);
242 }
243 }
244
245 __attribute__ (( unused ))
246 static void spr_write_atbl (void *opaque, int sprn, int gprn)
247 {
248 gen_helper_store_atbl(cpu_gpr[gprn]);
249 }
250
251 __attribute__ (( unused ))
252 static void spr_write_atbu (void *opaque, int sprn, int gprn)
253 {
254 gen_helper_store_atbu(cpu_gpr[gprn]);
255 }
256
257 #if defined(TARGET_PPC64)
258 __attribute__ (( unused ))
259 static void spr_read_purr (void *opaque, int gprn, int sprn)
260 {
261 gen_helper_load_purr(cpu_gpr[gprn]);
262 }
263 #endif
264 #endif
265
266 #if !defined(CONFIG_USER_ONLY)
267 /* IBAT0U...IBAT0U */
268 /* IBAT0L...IBAT7L */
269 static void spr_read_ibat (void *opaque, int gprn, int sprn)
270 {
271 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
272 }
273
274 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
275 {
276 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
277 }
278
279 static void spr_write_ibatu (void *opaque, int sprn, int gprn)
280 {
281 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
282 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
283 tcg_temp_free_i32(t0);
284 }
285
286 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
287 {
288 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
289 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
290 tcg_temp_free_i32(t0);
291 }
292
293 static void spr_write_ibatl (void *opaque, int sprn, int gprn)
294 {
295 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
296 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
297 tcg_temp_free_i32(t0);
298 }
299
300 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
301 {
302 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
303 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
304 tcg_temp_free_i32(t0);
305 }
306
307 /* DBAT0U...DBAT7U */
308 /* DBAT0L...DBAT7L */
309 static void spr_read_dbat (void *opaque, int gprn, int sprn)
310 {
311 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
312 }
313
314 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
315 {
316 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
317 }
318
319 static void spr_write_dbatu (void *opaque, int sprn, int gprn)
320 {
321 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
322 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
323 tcg_temp_free_i32(t0);
324 }
325
326 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
327 {
328 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
329 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
330 tcg_temp_free_i32(t0);
331 }
332
333 static void spr_write_dbatl (void *opaque, int sprn, int gprn)
334 {
335 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
336 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
337 tcg_temp_free_i32(t0);
338 }
339
340 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
341 {
342 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
343 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
344 tcg_temp_free_i32(t0);
345 }
346
347 /* SDR1 */
348 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
349 {
350 gen_helper_store_sdr1(cpu_gpr[gprn]);
351 }
352
353 /* 64 bits PowerPC specific SPRs */
354 /* ASR */
355 #if defined(TARGET_PPC64)
356 static void spr_read_hior (void *opaque, int gprn, int sprn)
357 {
358 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
359 }
360
361 static void spr_write_hior (void *opaque, int sprn, int gprn)
362 {
363 TCGv t0 = tcg_temp_new();
364 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
365 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
366 tcg_temp_free(t0);
367 }
368
369 static void spr_read_asr (void *opaque, int gprn, int sprn)
370 {
371 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, asr));
372 }
373
374 static void spr_write_asr (void *opaque, int sprn, int gprn)
375 {
376 gen_helper_store_asr(cpu_gpr[gprn]);
377 }
378 #endif
379 #endif
380
381 /* PowerPC 601 specific registers */
382 /* RTC */
383 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
384 {
385 gen_helper_load_601_rtcl(cpu_gpr[gprn]);
386 }
387
388 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
389 {
390 gen_helper_load_601_rtcu(cpu_gpr[gprn]);
391 }
392
393 #if !defined(CONFIG_USER_ONLY)
394 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
395 {
396 gen_helper_store_601_rtcu(cpu_gpr[gprn]);
397 }
398
399 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
400 {
401 gen_helper_store_601_rtcl(cpu_gpr[gprn]);
402 }
403
404 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
405 {
406 DisasContext *ctx = opaque;
407
408 gen_helper_store_hid0_601(cpu_gpr[gprn]);
409 /* Must stop the translation as endianness may have changed */
410 gen_stop_exception(ctx);
411 }
412 #endif
413
414 /* Unified bats */
415 #if !defined(CONFIG_USER_ONLY)
416 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
417 {
418 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
419 }
420
421 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
422 {
423 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
424 gen_helper_store_601_batl(t0, cpu_gpr[gprn]);
425 tcg_temp_free_i32(t0);
426 }
427
428 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
429 {
430 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
431 gen_helper_store_601_batu(t0, cpu_gpr[gprn]);
432 tcg_temp_free_i32(t0);
433 }
434 #endif
435
436 /* PowerPC 40x specific registers */
437 #if !defined(CONFIG_USER_ONLY)
438 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
439 {
440 gen_helper_load_40x_pit(cpu_gpr[gprn]);
441 }
442
443 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
444 {
445 gen_helper_store_40x_pit(cpu_gpr[gprn]);
446 }
447
448 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
449 {
450 DisasContext *ctx = opaque;
451
452 gen_helper_store_40x_dbcr0(cpu_gpr[gprn]);
453 /* We must stop translation as we may have rebooted */
454 gen_stop_exception(ctx);
455 }
456
457 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
458 {
459 gen_helper_store_40x_sler(cpu_gpr[gprn]);
460 }
461
462 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
463 {
464 gen_helper_store_booke_tcr(cpu_gpr[gprn]);
465 }
466
467 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
468 {
469 gen_helper_store_booke_tsr(cpu_gpr[gprn]);
470 }
471 #endif
472
473 /* PowerPC 403 specific registers */
474 /* PBL1 / PBU1 / PBL2 / PBU2 */
475 #if !defined(CONFIG_USER_ONLY)
476 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
477 {
478 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
479 }
480
481 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
482 {
483 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
484 gen_helper_store_403_pbr(t0, cpu_gpr[gprn]);
485 tcg_temp_free_i32(t0);
486 }
487
488 static void spr_write_pir (void *opaque, int sprn, int gprn)
489 {
490 TCGv t0 = tcg_temp_new();
491 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
492 gen_store_spr(SPR_PIR, t0);
493 tcg_temp_free(t0);
494 }
495 #endif
496
497 /* SPE specific registers */
498 static void spr_read_spefscr (void *opaque, int gprn, int sprn)
499 {
500 TCGv_i32 t0 = tcg_temp_new_i32();
501 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
502 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
503 tcg_temp_free_i32(t0);
504 }
505
506 static void spr_write_spefscr (void *opaque, int sprn, int gprn)
507 {
508 TCGv_i32 t0 = tcg_temp_new_i32();
509 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
510 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
511 tcg_temp_free_i32(t0);
512 }
513
514 #if !defined(CONFIG_USER_ONLY)
515 /* Callback used to write the exception vector base */
516 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
517 {
518 TCGv t0 = tcg_temp_new();
519 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
520 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
521 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
522 gen_store_spr(sprn, t0);
523 tcg_temp_free(t0);
524 }
525
526 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
527 {
528 DisasContext *ctx = opaque;
529 int sprn_offs;
530
531 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
532 sprn_offs = sprn - SPR_BOOKE_IVOR0;
533 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
534 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
535 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
536 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
537 } else {
538 printf("Trying to write an unknown exception vector %d %03x\n",
539 sprn, sprn);
540 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
541 return;
542 }
543
544 TCGv t0 = tcg_temp_new();
545 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
546 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
547 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
548 gen_store_spr(sprn, t0);
549 tcg_temp_free(t0);
550 }
551 #endif
552
553 static inline void vscr_init (CPUPPCState *env, uint32_t val)
554 {
555 env->vscr = val;
556 /* Altivec always uses round-to-nearest */
557 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
558 set_flush_to_zero(vscr_nj, &env->vec_status);
559 }
560
561 #if defined(CONFIG_USER_ONLY)
562 #define spr_register(env, num, name, uea_read, uea_write, \
563 oea_read, oea_write, initial_value) \
564 do { \
565 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
566 } while (0)
567 static inline void _spr_register (CPUPPCState *env, int num,
568 const char *name,
569 void (*uea_read)(void *opaque, int gprn, int sprn),
570 void (*uea_write)(void *opaque, int sprn, int gprn),
571 target_ulong initial_value)
572 #else
573 static inline void spr_register (CPUPPCState *env, int num,
574 const char *name,
575 void (*uea_read)(void *opaque, int gprn, int sprn),
576 void (*uea_write)(void *opaque, int sprn, int gprn),
577 void (*oea_read)(void *opaque, int gprn, int sprn),
578 void (*oea_write)(void *opaque, int sprn, int gprn),
579 target_ulong initial_value)
580 #endif
581 {
582 ppc_spr_t *spr;
583
584 spr = &env->spr_cb[num];
585 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
586 #if !defined(CONFIG_USER_ONLY)
587 spr->oea_read != NULL || spr->oea_write != NULL ||
588 #endif
589 spr->uea_read != NULL || spr->uea_write != NULL) {
590 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
591 exit(1);
592 }
593 #if defined(PPC_DEBUG_SPR)
594 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
595 name, initial_value);
596 #endif
597 spr->name = name;
598 spr->uea_read = uea_read;
599 spr->uea_write = uea_write;
600 #if !defined(CONFIG_USER_ONLY)
601 spr->oea_read = oea_read;
602 spr->oea_write = oea_write;
603 #endif
604 env->spr[num] = initial_value;
605 }
606
607 /* Generic PowerPC SPRs */
608 static void gen_spr_generic (CPUPPCState *env)
609 {
610 /* Integer processing */
611 spr_register(env, SPR_XER, "XER",
612 &spr_read_xer, &spr_write_xer,
613 &spr_read_xer, &spr_write_xer,
614 0x00000000);
615 /* Branch contol */
616 spr_register(env, SPR_LR, "LR",
617 &spr_read_lr, &spr_write_lr,
618 &spr_read_lr, &spr_write_lr,
619 0x00000000);
620 spr_register(env, SPR_CTR, "CTR",
621 &spr_read_ctr, &spr_write_ctr,
622 &spr_read_ctr, &spr_write_ctr,
623 0x00000000);
624 /* Interrupt processing */
625 spr_register(env, SPR_SRR0, "SRR0",
626 SPR_NOACCESS, SPR_NOACCESS,
627 &spr_read_generic, &spr_write_generic,
628 0x00000000);
629 spr_register(env, SPR_SRR1, "SRR1",
630 SPR_NOACCESS, SPR_NOACCESS,
631 &spr_read_generic, &spr_write_generic,
632 0x00000000);
633 /* Processor control */
634 spr_register(env, SPR_SPRG0, "SPRG0",
635 SPR_NOACCESS, SPR_NOACCESS,
636 &spr_read_generic, &spr_write_generic,
637 0x00000000);
638 spr_register(env, SPR_SPRG1, "SPRG1",
639 SPR_NOACCESS, SPR_NOACCESS,
640 &spr_read_generic, &spr_write_generic,
641 0x00000000);
642 spr_register(env, SPR_SPRG2, "SPRG2",
643 SPR_NOACCESS, SPR_NOACCESS,
644 &spr_read_generic, &spr_write_generic,
645 0x00000000);
646 spr_register(env, SPR_SPRG3, "SPRG3",
647 SPR_NOACCESS, SPR_NOACCESS,
648 &spr_read_generic, &spr_write_generic,
649 0x00000000);
650 }
651
652 /* SPR common to all non-embedded PowerPC, including 601 */
653 static void gen_spr_ne_601 (CPUPPCState *env)
654 {
655 /* Exception processing */
656 spr_register(env, SPR_DSISR, "DSISR",
657 SPR_NOACCESS, SPR_NOACCESS,
658 &spr_read_generic, &spr_write_generic,
659 0x00000000);
660 spr_register(env, SPR_DAR, "DAR",
661 SPR_NOACCESS, SPR_NOACCESS,
662 &spr_read_generic, &spr_write_generic,
663 0x00000000);
664 /* Timer */
665 spr_register(env, SPR_DECR, "DECR",
666 SPR_NOACCESS, SPR_NOACCESS,
667 &spr_read_decr, &spr_write_decr,
668 0x00000000);
669 /* Memory management */
670 spr_register(env, SPR_SDR1, "SDR1",
671 SPR_NOACCESS, SPR_NOACCESS,
672 &spr_read_generic, &spr_write_sdr1,
673 0x00000000);
674 }
675
676 /* BATs 0-3 */
677 static void gen_low_BATs (CPUPPCState *env)
678 {
679 #if !defined(CONFIG_USER_ONLY)
680 spr_register(env, SPR_IBAT0U, "IBAT0U",
681 SPR_NOACCESS, SPR_NOACCESS,
682 &spr_read_ibat, &spr_write_ibatu,
683 0x00000000);
684 spr_register(env, SPR_IBAT0L, "IBAT0L",
685 SPR_NOACCESS, SPR_NOACCESS,
686 &spr_read_ibat, &spr_write_ibatl,
687 0x00000000);
688 spr_register(env, SPR_IBAT1U, "IBAT1U",
689 SPR_NOACCESS, SPR_NOACCESS,
690 &spr_read_ibat, &spr_write_ibatu,
691 0x00000000);
692 spr_register(env, SPR_IBAT1L, "IBAT1L",
693 SPR_NOACCESS, SPR_NOACCESS,
694 &spr_read_ibat, &spr_write_ibatl,
695 0x00000000);
696 spr_register(env, SPR_IBAT2U, "IBAT2U",
697 SPR_NOACCESS, SPR_NOACCESS,
698 &spr_read_ibat, &spr_write_ibatu,
699 0x00000000);
700 spr_register(env, SPR_IBAT2L, "IBAT2L",
701 SPR_NOACCESS, SPR_NOACCESS,
702 &spr_read_ibat, &spr_write_ibatl,
703 0x00000000);
704 spr_register(env, SPR_IBAT3U, "IBAT3U",
705 SPR_NOACCESS, SPR_NOACCESS,
706 &spr_read_ibat, &spr_write_ibatu,
707 0x00000000);
708 spr_register(env, SPR_IBAT3L, "IBAT3L",
709 SPR_NOACCESS, SPR_NOACCESS,
710 &spr_read_ibat, &spr_write_ibatl,
711 0x00000000);
712 spr_register(env, SPR_DBAT0U, "DBAT0U",
713 SPR_NOACCESS, SPR_NOACCESS,
714 &spr_read_dbat, &spr_write_dbatu,
715 0x00000000);
716 spr_register(env, SPR_DBAT0L, "DBAT0L",
717 SPR_NOACCESS, SPR_NOACCESS,
718 &spr_read_dbat, &spr_write_dbatl,
719 0x00000000);
720 spr_register(env, SPR_DBAT1U, "DBAT1U",
721 SPR_NOACCESS, SPR_NOACCESS,
722 &spr_read_dbat, &spr_write_dbatu,
723 0x00000000);
724 spr_register(env, SPR_DBAT1L, "DBAT1L",
725 SPR_NOACCESS, SPR_NOACCESS,
726 &spr_read_dbat, &spr_write_dbatl,
727 0x00000000);
728 spr_register(env, SPR_DBAT2U, "DBAT2U",
729 SPR_NOACCESS, SPR_NOACCESS,
730 &spr_read_dbat, &spr_write_dbatu,
731 0x00000000);
732 spr_register(env, SPR_DBAT2L, "DBAT2L",
733 SPR_NOACCESS, SPR_NOACCESS,
734 &spr_read_dbat, &spr_write_dbatl,
735 0x00000000);
736 spr_register(env, SPR_DBAT3U, "DBAT3U",
737 SPR_NOACCESS, SPR_NOACCESS,
738 &spr_read_dbat, &spr_write_dbatu,
739 0x00000000);
740 spr_register(env, SPR_DBAT3L, "DBAT3L",
741 SPR_NOACCESS, SPR_NOACCESS,
742 &spr_read_dbat, &spr_write_dbatl,
743 0x00000000);
744 env->nb_BATs += 4;
745 #endif
746 }
747
748 /* BATs 4-7 */
749 static void gen_high_BATs (CPUPPCState *env)
750 {
751 #if !defined(CONFIG_USER_ONLY)
752 spr_register(env, SPR_IBAT4U, "IBAT4U",
753 SPR_NOACCESS, SPR_NOACCESS,
754 &spr_read_ibat_h, &spr_write_ibatu_h,
755 0x00000000);
756 spr_register(env, SPR_IBAT4L, "IBAT4L",
757 SPR_NOACCESS, SPR_NOACCESS,
758 &spr_read_ibat_h, &spr_write_ibatl_h,
759 0x00000000);
760 spr_register(env, SPR_IBAT5U, "IBAT5U",
761 SPR_NOACCESS, SPR_NOACCESS,
762 &spr_read_ibat_h, &spr_write_ibatu_h,
763 0x00000000);
764 spr_register(env, SPR_IBAT5L, "IBAT5L",
765 SPR_NOACCESS, SPR_NOACCESS,
766 &spr_read_ibat_h, &spr_write_ibatl_h,
767 0x00000000);
768 spr_register(env, SPR_IBAT6U, "IBAT6U",
769 SPR_NOACCESS, SPR_NOACCESS,
770 &spr_read_ibat_h, &spr_write_ibatu_h,
771 0x00000000);
772 spr_register(env, SPR_IBAT6L, "IBAT6L",
773 SPR_NOACCESS, SPR_NOACCESS,
774 &spr_read_ibat_h, &spr_write_ibatl_h,
775 0x00000000);
776 spr_register(env, SPR_IBAT7U, "IBAT7U",
777 SPR_NOACCESS, SPR_NOACCESS,
778 &spr_read_ibat_h, &spr_write_ibatu_h,
779 0x00000000);
780 spr_register(env, SPR_IBAT7L, "IBAT7L",
781 SPR_NOACCESS, SPR_NOACCESS,
782 &spr_read_ibat_h, &spr_write_ibatl_h,
783 0x00000000);
784 spr_register(env, SPR_DBAT4U, "DBAT4U",
785 SPR_NOACCESS, SPR_NOACCESS,
786 &spr_read_dbat_h, &spr_write_dbatu_h,
787 0x00000000);
788 spr_register(env, SPR_DBAT4L, "DBAT4L",
789 SPR_NOACCESS, SPR_NOACCESS,
790 &spr_read_dbat_h, &spr_write_dbatl_h,
791 0x00000000);
792 spr_register(env, SPR_DBAT5U, "DBAT5U",
793 SPR_NOACCESS, SPR_NOACCESS,
794 &spr_read_dbat_h, &spr_write_dbatu_h,
795 0x00000000);
796 spr_register(env, SPR_DBAT5L, "DBAT5L",
797 SPR_NOACCESS, SPR_NOACCESS,
798 &spr_read_dbat_h, &spr_write_dbatl_h,
799 0x00000000);
800 spr_register(env, SPR_DBAT6U, "DBAT6U",
801 SPR_NOACCESS, SPR_NOACCESS,
802 &spr_read_dbat_h, &spr_write_dbatu_h,
803 0x00000000);
804 spr_register(env, SPR_DBAT6L, "DBAT6L",
805 SPR_NOACCESS, SPR_NOACCESS,
806 &spr_read_dbat_h, &spr_write_dbatl_h,
807 0x00000000);
808 spr_register(env, SPR_DBAT7U, "DBAT7U",
809 SPR_NOACCESS, SPR_NOACCESS,
810 &spr_read_dbat_h, &spr_write_dbatu_h,
811 0x00000000);
812 spr_register(env, SPR_DBAT7L, "DBAT7L",
813 SPR_NOACCESS, SPR_NOACCESS,
814 &spr_read_dbat_h, &spr_write_dbatl_h,
815 0x00000000);
816 env->nb_BATs += 4;
817 #endif
818 }
819
820 /* Generic PowerPC time base */
821 static void gen_tbl (CPUPPCState *env)
822 {
823 spr_register(env, SPR_VTBL, "TBL",
824 &spr_read_tbl, SPR_NOACCESS,
825 &spr_read_tbl, SPR_NOACCESS,
826 0x00000000);
827 spr_register(env, SPR_TBL, "TBL",
828 &spr_read_tbl, SPR_NOACCESS,
829 &spr_read_tbl, &spr_write_tbl,
830 0x00000000);
831 spr_register(env, SPR_VTBU, "TBU",
832 &spr_read_tbu, SPR_NOACCESS,
833 &spr_read_tbu, SPR_NOACCESS,
834 0x00000000);
835 spr_register(env, SPR_TBU, "TBU",
836 &spr_read_tbu, SPR_NOACCESS,
837 &spr_read_tbu, &spr_write_tbu,
838 0x00000000);
839 }
840
841 /* Softare table search registers */
842 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
843 {
844 #if !defined(CONFIG_USER_ONLY)
845 env->nb_tlb = nb_tlbs;
846 env->nb_ways = nb_ways;
847 env->id_tlbs = 1;
848 env->tlb_type = TLB_6XX;
849 spr_register(env, SPR_DMISS, "DMISS",
850 SPR_NOACCESS, SPR_NOACCESS,
851 &spr_read_generic, SPR_NOACCESS,
852 0x00000000);
853 spr_register(env, SPR_DCMP, "DCMP",
854 SPR_NOACCESS, SPR_NOACCESS,
855 &spr_read_generic, SPR_NOACCESS,
856 0x00000000);
857 spr_register(env, SPR_HASH1, "HASH1",
858 SPR_NOACCESS, SPR_NOACCESS,
859 &spr_read_generic, SPR_NOACCESS,
860 0x00000000);
861 spr_register(env, SPR_HASH2, "HASH2",
862 SPR_NOACCESS, SPR_NOACCESS,
863 &spr_read_generic, SPR_NOACCESS,
864 0x00000000);
865 spr_register(env, SPR_IMISS, "IMISS",
866 SPR_NOACCESS, SPR_NOACCESS,
867 &spr_read_generic, SPR_NOACCESS,
868 0x00000000);
869 spr_register(env, SPR_ICMP, "ICMP",
870 SPR_NOACCESS, SPR_NOACCESS,
871 &spr_read_generic, SPR_NOACCESS,
872 0x00000000);
873 spr_register(env, SPR_RPA, "RPA",
874 SPR_NOACCESS, SPR_NOACCESS,
875 &spr_read_generic, &spr_write_generic,
876 0x00000000);
877 #endif
878 }
879
880 /* SPR common to MPC755 and G2 */
881 static void gen_spr_G2_755 (CPUPPCState *env)
882 {
883 /* SGPRs */
884 spr_register(env, SPR_SPRG4, "SPRG4",
885 SPR_NOACCESS, SPR_NOACCESS,
886 &spr_read_generic, &spr_write_generic,
887 0x00000000);
888 spr_register(env, SPR_SPRG5, "SPRG5",
889 SPR_NOACCESS, SPR_NOACCESS,
890 &spr_read_generic, &spr_write_generic,
891 0x00000000);
892 spr_register(env, SPR_SPRG6, "SPRG6",
893 SPR_NOACCESS, SPR_NOACCESS,
894 &spr_read_generic, &spr_write_generic,
895 0x00000000);
896 spr_register(env, SPR_SPRG7, "SPRG7",
897 SPR_NOACCESS, SPR_NOACCESS,
898 &spr_read_generic, &spr_write_generic,
899 0x00000000);
900 }
901
902 /* SPR common to all 7xx PowerPC implementations */
903 static void gen_spr_7xx (CPUPPCState *env)
904 {
905 /* Breakpoints */
906 /* XXX : not implemented */
907 spr_register(env, SPR_DABR, "DABR",
908 SPR_NOACCESS, SPR_NOACCESS,
909 &spr_read_generic, &spr_write_generic,
910 0x00000000);
911 /* XXX : not implemented */
912 spr_register(env, SPR_IABR, "IABR",
913 SPR_NOACCESS, SPR_NOACCESS,
914 &spr_read_generic, &spr_write_generic,
915 0x00000000);
916 /* Cache management */
917 /* XXX : not implemented */
918 spr_register(env, SPR_ICTC, "ICTC",
919 SPR_NOACCESS, SPR_NOACCESS,
920 &spr_read_generic, &spr_write_generic,
921 0x00000000);
922 /* Performance monitors */
923 /* XXX : not implemented */
924 spr_register(env, SPR_MMCR0, "MMCR0",
925 SPR_NOACCESS, SPR_NOACCESS,
926 &spr_read_generic, &spr_write_generic,
927 0x00000000);
928 /* XXX : not implemented */
929 spr_register(env, SPR_MMCR1, "MMCR1",
930 SPR_NOACCESS, SPR_NOACCESS,
931 &spr_read_generic, &spr_write_generic,
932 0x00000000);
933 /* XXX : not implemented */
934 spr_register(env, SPR_PMC1, "PMC1",
935 SPR_NOACCESS, SPR_NOACCESS,
936 &spr_read_generic, &spr_write_generic,
937 0x00000000);
938 /* XXX : not implemented */
939 spr_register(env, SPR_PMC2, "PMC2",
940 SPR_NOACCESS, SPR_NOACCESS,
941 &spr_read_generic, &spr_write_generic,
942 0x00000000);
943 /* XXX : not implemented */
944 spr_register(env, SPR_PMC3, "PMC3",
945 SPR_NOACCESS, SPR_NOACCESS,
946 &spr_read_generic, &spr_write_generic,
947 0x00000000);
948 /* XXX : not implemented */
949 spr_register(env, SPR_PMC4, "PMC4",
950 SPR_NOACCESS, SPR_NOACCESS,
951 &spr_read_generic, &spr_write_generic,
952 0x00000000);
953 /* XXX : not implemented */
954 spr_register(env, SPR_SIAR, "SIAR",
955 SPR_NOACCESS, SPR_NOACCESS,
956 &spr_read_generic, SPR_NOACCESS,
957 0x00000000);
958 /* XXX : not implemented */
959 spr_register(env, SPR_UMMCR0, "UMMCR0",
960 &spr_read_ureg, SPR_NOACCESS,
961 &spr_read_ureg, SPR_NOACCESS,
962 0x00000000);
963 /* XXX : not implemented */
964 spr_register(env, SPR_UMMCR1, "UMMCR1",
965 &spr_read_ureg, SPR_NOACCESS,
966 &spr_read_ureg, SPR_NOACCESS,
967 0x00000000);
968 /* XXX : not implemented */
969 spr_register(env, SPR_UPMC1, "UPMC1",
970 &spr_read_ureg, SPR_NOACCESS,
971 &spr_read_ureg, SPR_NOACCESS,
972 0x00000000);
973 /* XXX : not implemented */
974 spr_register(env, SPR_UPMC2, "UPMC2",
975 &spr_read_ureg, SPR_NOACCESS,
976 &spr_read_ureg, SPR_NOACCESS,
977 0x00000000);
978 /* XXX : not implemented */
979 spr_register(env, SPR_UPMC3, "UPMC3",
980 &spr_read_ureg, SPR_NOACCESS,
981 &spr_read_ureg, SPR_NOACCESS,
982 0x00000000);
983 /* XXX : not implemented */
984 spr_register(env, SPR_UPMC4, "UPMC4",
985 &spr_read_ureg, SPR_NOACCESS,
986 &spr_read_ureg, SPR_NOACCESS,
987 0x00000000);
988 /* XXX : not implemented */
989 spr_register(env, SPR_USIAR, "USIAR",
990 &spr_read_ureg, SPR_NOACCESS,
991 &spr_read_ureg, SPR_NOACCESS,
992 0x00000000);
993 /* External access control */
994 /* XXX : not implemented */
995 spr_register(env, SPR_EAR, "EAR",
996 SPR_NOACCESS, SPR_NOACCESS,
997 &spr_read_generic, &spr_write_generic,
998 0x00000000);
999 }
1000
1001 static void gen_spr_thrm (CPUPPCState *env)
1002 {
1003 /* Thermal management */
1004 /* XXX : not implemented */
1005 spr_register(env, SPR_THRM1, "THRM1",
1006 SPR_NOACCESS, SPR_NOACCESS,
1007 &spr_read_generic, &spr_write_generic,
1008 0x00000000);
1009 /* XXX : not implemented */
1010 spr_register(env, SPR_THRM2, "THRM2",
1011 SPR_NOACCESS, SPR_NOACCESS,
1012 &spr_read_generic, &spr_write_generic,
1013 0x00000000);
1014 /* XXX : not implemented */
1015 spr_register(env, SPR_THRM3, "THRM3",
1016 SPR_NOACCESS, SPR_NOACCESS,
1017 &spr_read_generic, &spr_write_generic,
1018 0x00000000);
1019 }
1020
1021 /* SPR specific to PowerPC 604 implementation */
1022 static void gen_spr_604 (CPUPPCState *env)
1023 {
1024 /* Processor identification */
1025 spr_register(env, SPR_PIR, "PIR",
1026 SPR_NOACCESS, SPR_NOACCESS,
1027 &spr_read_generic, &spr_write_pir,
1028 0x00000000);
1029 /* Breakpoints */
1030 /* XXX : not implemented */
1031 spr_register(env, SPR_IABR, "IABR",
1032 SPR_NOACCESS, SPR_NOACCESS,
1033 &spr_read_generic, &spr_write_generic,
1034 0x00000000);
1035 /* XXX : not implemented */
1036 spr_register(env, SPR_DABR, "DABR",
1037 SPR_NOACCESS, SPR_NOACCESS,
1038 &spr_read_generic, &spr_write_generic,
1039 0x00000000);
1040 /* Performance counters */
1041 /* XXX : not implemented */
1042 spr_register(env, SPR_MMCR0, "MMCR0",
1043 SPR_NOACCESS, SPR_NOACCESS,
1044 &spr_read_generic, &spr_write_generic,
1045 0x00000000);
1046 /* XXX : not implemented */
1047 spr_register(env, SPR_PMC1, "PMC1",
1048 SPR_NOACCESS, SPR_NOACCESS,
1049 &spr_read_generic, &spr_write_generic,
1050 0x00000000);
1051 /* XXX : not implemented */
1052 spr_register(env, SPR_PMC2, "PMC2",
1053 SPR_NOACCESS, SPR_NOACCESS,
1054 &spr_read_generic, &spr_write_generic,
1055 0x00000000);
1056 /* XXX : not implemented */
1057 spr_register(env, SPR_SIAR, "SIAR",
1058 SPR_NOACCESS, SPR_NOACCESS,
1059 &spr_read_generic, SPR_NOACCESS,
1060 0x00000000);
1061 /* XXX : not implemented */
1062 spr_register(env, SPR_SDA, "SDA",
1063 SPR_NOACCESS, SPR_NOACCESS,
1064 &spr_read_generic, SPR_NOACCESS,
1065 0x00000000);
1066 /* External access control */
1067 /* XXX : not implemented */
1068 spr_register(env, SPR_EAR, "EAR",
1069 SPR_NOACCESS, SPR_NOACCESS,
1070 &spr_read_generic, &spr_write_generic,
1071 0x00000000);
1072 }
1073
1074 /* SPR specific to PowerPC 603 implementation */
1075 static void gen_spr_603 (CPUPPCState *env)
1076 {
1077 /* External access control */
1078 /* XXX : not implemented */
1079 spr_register(env, SPR_EAR, "EAR",
1080 SPR_NOACCESS, SPR_NOACCESS,
1081 &spr_read_generic, &spr_write_generic,
1082 0x00000000);
1083 }
1084
1085 /* SPR specific to PowerPC G2 implementation */
1086 static void gen_spr_G2 (CPUPPCState *env)
1087 {
1088 /* Memory base address */
1089 /* MBAR */
1090 /* XXX : not implemented */
1091 spr_register(env, SPR_MBAR, "MBAR",
1092 SPR_NOACCESS, SPR_NOACCESS,
1093 &spr_read_generic, &spr_write_generic,
1094 0x00000000);
1095 /* Exception processing */
1096 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1097 SPR_NOACCESS, SPR_NOACCESS,
1098 &spr_read_generic, &spr_write_generic,
1099 0x00000000);
1100 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1101 SPR_NOACCESS, SPR_NOACCESS,
1102 &spr_read_generic, &spr_write_generic,
1103 0x00000000);
1104 /* Breakpoints */
1105 /* XXX : not implemented */
1106 spr_register(env, SPR_DABR, "DABR",
1107 SPR_NOACCESS, SPR_NOACCESS,
1108 &spr_read_generic, &spr_write_generic,
1109 0x00000000);
1110 /* XXX : not implemented */
1111 spr_register(env, SPR_DABR2, "DABR2",
1112 SPR_NOACCESS, SPR_NOACCESS,
1113 &spr_read_generic, &spr_write_generic,
1114 0x00000000);
1115 /* XXX : not implemented */
1116 spr_register(env, SPR_IABR, "IABR",
1117 SPR_NOACCESS, SPR_NOACCESS,
1118 &spr_read_generic, &spr_write_generic,
1119 0x00000000);
1120 /* XXX : not implemented */
1121 spr_register(env, SPR_IABR2, "IABR2",
1122 SPR_NOACCESS, SPR_NOACCESS,
1123 &spr_read_generic, &spr_write_generic,
1124 0x00000000);
1125 /* XXX : not implemented */
1126 spr_register(env, SPR_IBCR, "IBCR",
1127 SPR_NOACCESS, SPR_NOACCESS,
1128 &spr_read_generic, &spr_write_generic,
1129 0x00000000);
1130 /* XXX : not implemented */
1131 spr_register(env, SPR_DBCR, "DBCR",
1132 SPR_NOACCESS, SPR_NOACCESS,
1133 &spr_read_generic, &spr_write_generic,
1134 0x00000000);
1135 }
1136
1137 /* SPR specific to PowerPC 602 implementation */
1138 static void gen_spr_602 (CPUPPCState *env)
1139 {
1140 /* ESA registers */
1141 /* XXX : not implemented */
1142 spr_register(env, SPR_SER, "SER",
1143 SPR_NOACCESS, SPR_NOACCESS,
1144 &spr_read_generic, &spr_write_generic,
1145 0x00000000);
1146 /* XXX : not implemented */
1147 spr_register(env, SPR_SEBR, "SEBR",
1148 SPR_NOACCESS, SPR_NOACCESS,
1149 &spr_read_generic, &spr_write_generic,
1150 0x00000000);
1151 /* XXX : not implemented */
1152 spr_register(env, SPR_ESASRR, "ESASRR",
1153 SPR_NOACCESS, SPR_NOACCESS,
1154 &spr_read_generic, &spr_write_generic,
1155 0x00000000);
1156 /* Floating point status */
1157 /* XXX : not implemented */
1158 spr_register(env, SPR_SP, "SP",
1159 SPR_NOACCESS, SPR_NOACCESS,
1160 &spr_read_generic, &spr_write_generic,
1161 0x00000000);
1162 /* XXX : not implemented */
1163 spr_register(env, SPR_LT, "LT",
1164 SPR_NOACCESS, SPR_NOACCESS,
1165 &spr_read_generic, &spr_write_generic,
1166 0x00000000);
1167 /* Watchdog timer */
1168 /* XXX : not implemented */
1169 spr_register(env, SPR_TCR, "TCR",
1170 SPR_NOACCESS, SPR_NOACCESS,
1171 &spr_read_generic, &spr_write_generic,
1172 0x00000000);
1173 /* Interrupt base */
1174 spr_register(env, SPR_IBR, "IBR",
1175 SPR_NOACCESS, SPR_NOACCESS,
1176 &spr_read_generic, &spr_write_generic,
1177 0x00000000);
1178 /* XXX : not implemented */
1179 spr_register(env, SPR_IABR, "IABR",
1180 SPR_NOACCESS, SPR_NOACCESS,
1181 &spr_read_generic, &spr_write_generic,
1182 0x00000000);
1183 }
1184
1185 /* SPR specific to PowerPC 601 implementation */
1186 static void gen_spr_601 (CPUPPCState *env)
1187 {
1188 /* Multiplication/division register */
1189 /* MQ */
1190 spr_register(env, SPR_MQ, "MQ",
1191 &spr_read_generic, &spr_write_generic,
1192 &spr_read_generic, &spr_write_generic,
1193 0x00000000);
1194 /* RTC registers */
1195 spr_register(env, SPR_601_RTCU, "RTCU",
1196 SPR_NOACCESS, SPR_NOACCESS,
1197 SPR_NOACCESS, &spr_write_601_rtcu,
1198 0x00000000);
1199 spr_register(env, SPR_601_VRTCU, "RTCU",
1200 &spr_read_601_rtcu, SPR_NOACCESS,
1201 &spr_read_601_rtcu, SPR_NOACCESS,
1202 0x00000000);
1203 spr_register(env, SPR_601_RTCL, "RTCL",
1204 SPR_NOACCESS, SPR_NOACCESS,
1205 SPR_NOACCESS, &spr_write_601_rtcl,
1206 0x00000000);
1207 spr_register(env, SPR_601_VRTCL, "RTCL",
1208 &spr_read_601_rtcl, SPR_NOACCESS,
1209 &spr_read_601_rtcl, SPR_NOACCESS,
1210 0x00000000);
1211 /* Timer */
1212 #if 0 /* ? */
1213 spr_register(env, SPR_601_UDECR, "UDECR",
1214 &spr_read_decr, SPR_NOACCESS,
1215 &spr_read_decr, SPR_NOACCESS,
1216 0x00000000);
1217 #endif
1218 /* External access control */
1219 /* XXX : not implemented */
1220 spr_register(env, SPR_EAR, "EAR",
1221 SPR_NOACCESS, SPR_NOACCESS,
1222 &spr_read_generic, &spr_write_generic,
1223 0x00000000);
1224 /* Memory management */
1225 #if !defined(CONFIG_USER_ONLY)
1226 spr_register(env, SPR_IBAT0U, "IBAT0U",
1227 SPR_NOACCESS, SPR_NOACCESS,
1228 &spr_read_601_ubat, &spr_write_601_ubatu,
1229 0x00000000);
1230 spr_register(env, SPR_IBAT0L, "IBAT0L",
1231 SPR_NOACCESS, SPR_NOACCESS,
1232 &spr_read_601_ubat, &spr_write_601_ubatl,
1233 0x00000000);
1234 spr_register(env, SPR_IBAT1U, "IBAT1U",
1235 SPR_NOACCESS, SPR_NOACCESS,
1236 &spr_read_601_ubat, &spr_write_601_ubatu,
1237 0x00000000);
1238 spr_register(env, SPR_IBAT1L, "IBAT1L",
1239 SPR_NOACCESS, SPR_NOACCESS,
1240 &spr_read_601_ubat, &spr_write_601_ubatl,
1241 0x00000000);
1242 spr_register(env, SPR_IBAT2U, "IBAT2U",
1243 SPR_NOACCESS, SPR_NOACCESS,
1244 &spr_read_601_ubat, &spr_write_601_ubatu,
1245 0x00000000);
1246 spr_register(env, SPR_IBAT2L, "IBAT2L",
1247 SPR_NOACCESS, SPR_NOACCESS,
1248 &spr_read_601_ubat, &spr_write_601_ubatl,
1249 0x00000000);
1250 spr_register(env, SPR_IBAT3U, "IBAT3U",
1251 SPR_NOACCESS, SPR_NOACCESS,
1252 &spr_read_601_ubat, &spr_write_601_ubatu,
1253 0x00000000);
1254 spr_register(env, SPR_IBAT3L, "IBAT3L",
1255 SPR_NOACCESS, SPR_NOACCESS,
1256 &spr_read_601_ubat, &spr_write_601_ubatl,
1257 0x00000000);
1258 env->nb_BATs = 4;
1259 #endif
1260 }
1261
1262 static void gen_spr_74xx (CPUPPCState *env)
1263 {
1264 /* Processor identification */
1265 spr_register(env, SPR_PIR, "PIR",
1266 SPR_NOACCESS, SPR_NOACCESS,
1267 &spr_read_generic, &spr_write_pir,
1268 0x00000000);
1269 /* XXX : not implemented */
1270 spr_register(env, SPR_MMCR2, "MMCR2",
1271 SPR_NOACCESS, SPR_NOACCESS,
1272 &spr_read_generic, &spr_write_generic,
1273 0x00000000);
1274 /* XXX : not implemented */
1275 spr_register(env, SPR_UMMCR2, "UMMCR2",
1276 &spr_read_ureg, SPR_NOACCESS,
1277 &spr_read_ureg, SPR_NOACCESS,
1278 0x00000000);
1279 /* XXX: not implemented */
1280 spr_register(env, SPR_BAMR, "BAMR",
1281 SPR_NOACCESS, SPR_NOACCESS,
1282 &spr_read_generic, &spr_write_generic,
1283 0x00000000);
1284 /* XXX : not implemented */
1285 spr_register(env, SPR_MSSCR0, "MSSCR0",
1286 SPR_NOACCESS, SPR_NOACCESS,
1287 &spr_read_generic, &spr_write_generic,
1288 0x00000000);
1289 /* Hardware implementation registers */
1290 /* XXX : not implemented */
1291 spr_register(env, SPR_HID0, "HID0",
1292 SPR_NOACCESS, SPR_NOACCESS,
1293 &spr_read_generic, &spr_write_generic,
1294 0x00000000);
1295 /* XXX : not implemented */
1296 spr_register(env, SPR_HID1, "HID1",
1297 SPR_NOACCESS, SPR_NOACCESS,
1298 &spr_read_generic, &spr_write_generic,
1299 0x00000000);
1300 /* Altivec */
1301 spr_register(env, SPR_VRSAVE, "VRSAVE",
1302 &spr_read_generic, &spr_write_generic,
1303 &spr_read_generic, &spr_write_generic,
1304 0x00000000);
1305 /* XXX : not implemented */
1306 spr_register(env, SPR_L2CR, "L2CR",
1307 SPR_NOACCESS, SPR_NOACCESS,
1308 &spr_read_generic, &spr_write_generic,
1309 0x00000000);
1310 /* Not strictly an SPR */
1311 vscr_init(env, 0x00010000);
1312 }
1313
1314 static void gen_l3_ctrl (CPUPPCState *env)
1315 {
1316 /* L3CR */
1317 /* XXX : not implemented */
1318 spr_register(env, SPR_L3CR, "L3CR",
1319 SPR_NOACCESS, SPR_NOACCESS,
1320 &spr_read_generic, &spr_write_generic,
1321 0x00000000);
1322 /* L3ITCR0 */
1323 /* XXX : not implemented */
1324 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1325 SPR_NOACCESS, SPR_NOACCESS,
1326 &spr_read_generic, &spr_write_generic,
1327 0x00000000);
1328 /* L3PM */
1329 /* XXX : not implemented */
1330 spr_register(env, SPR_L3PM, "L3PM",
1331 SPR_NOACCESS, SPR_NOACCESS,
1332 &spr_read_generic, &spr_write_generic,
1333 0x00000000);
1334 }
1335
1336 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1337 {
1338 #if !defined(CONFIG_USER_ONLY)
1339 env->nb_tlb = nb_tlbs;
1340 env->nb_ways = nb_ways;
1341 env->id_tlbs = 1;
1342 env->tlb_type = TLB_6XX;
1343 /* XXX : not implemented */
1344 spr_register(env, SPR_PTEHI, "PTEHI",
1345 SPR_NOACCESS, SPR_NOACCESS,
1346 &spr_read_generic, &spr_write_generic,
1347 0x00000000);
1348 /* XXX : not implemented */
1349 spr_register(env, SPR_PTELO, "PTELO",
1350 SPR_NOACCESS, SPR_NOACCESS,
1351 &spr_read_generic, &spr_write_generic,
1352 0x00000000);
1353 /* XXX : not implemented */
1354 spr_register(env, SPR_TLBMISS, "TLBMISS",
1355 SPR_NOACCESS, SPR_NOACCESS,
1356 &spr_read_generic, &spr_write_generic,
1357 0x00000000);
1358 #endif
1359 }
1360
1361 #if !defined(CONFIG_USER_ONLY)
1362 static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
1363 {
1364 TCGv t0 = tcg_temp_new();
1365
1366 tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256);
1367 gen_store_spr(sprn, t0);
1368 tcg_temp_free(t0);
1369 }
1370
1371 static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
1372 {
1373 TCGv_i32 t0 = tcg_const_i32(sprn);
1374 gen_helper_booke206_tlbflush(t0);
1375 tcg_temp_free_i32(t0);
1376 }
1377
1378 static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
1379 {
1380 TCGv_i32 t0 = tcg_const_i32(sprn);
1381 gen_helper_booke_setpid(t0, cpu_gpr[gprn]);
1382 tcg_temp_free_i32(t0);
1383 }
1384 #endif
1385
1386 static void gen_spr_usprgh (CPUPPCState *env)
1387 {
1388 spr_register(env, SPR_USPRG4, "USPRG4",
1389 &spr_read_ureg, SPR_NOACCESS,
1390 &spr_read_ureg, SPR_NOACCESS,
1391 0x00000000);
1392 spr_register(env, SPR_USPRG5, "USPRG5",
1393 &spr_read_ureg, SPR_NOACCESS,
1394 &spr_read_ureg, SPR_NOACCESS,
1395 0x00000000);
1396 spr_register(env, SPR_USPRG6, "USPRG6",
1397 &spr_read_ureg, SPR_NOACCESS,
1398 &spr_read_ureg, SPR_NOACCESS,
1399 0x00000000);
1400 spr_register(env, SPR_USPRG7, "USPRG7",
1401 &spr_read_ureg, SPR_NOACCESS,
1402 &spr_read_ureg, SPR_NOACCESS,
1403 0x00000000);
1404 }
1405
1406 /* PowerPC BookE SPR */
1407 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1408 {
1409 const char *ivor_names[64] = {
1410 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1411 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1412 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1413 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1414 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1415 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1416 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1417 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1418 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1419 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1420 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1421 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1422 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1423 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1424 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1425 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1426 };
1427 #define SPR_BOOKE_IVORxx (-1)
1428 int ivor_sprn[64] = {
1429 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1430 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1431 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1432 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1433 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1434 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1435 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1436 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1437 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1438 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1439 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1440 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1441 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1442 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1443 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1444 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1445 };
1446 int i;
1447
1448 /* Interrupt processing */
1449 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1450 SPR_NOACCESS, SPR_NOACCESS,
1451 &spr_read_generic, &spr_write_generic,
1452 0x00000000);
1453 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1454 SPR_NOACCESS, SPR_NOACCESS,
1455 &spr_read_generic, &spr_write_generic,
1456 0x00000000);
1457 /* Debug */
1458 /* XXX : not implemented */
1459 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1460 SPR_NOACCESS, SPR_NOACCESS,
1461 &spr_read_generic, &spr_write_generic,
1462 0x00000000);
1463 /* XXX : not implemented */
1464 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1465 SPR_NOACCESS, SPR_NOACCESS,
1466 &spr_read_generic, &spr_write_generic,
1467 0x00000000);
1468 /* XXX : not implemented */
1469 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1470 SPR_NOACCESS, SPR_NOACCESS,
1471 &spr_read_generic, &spr_write_generic,
1472 0x00000000);
1473 /* XXX : not implemented */
1474 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1475 SPR_NOACCESS, SPR_NOACCESS,
1476 &spr_read_generic, &spr_write_generic,
1477 0x00000000);
1478 /* XXX : not implemented */
1479 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1480 SPR_NOACCESS, SPR_NOACCESS,
1481 &spr_read_generic, &spr_write_generic,
1482 0x00000000);
1483 /* XXX : not implemented */
1484 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1485 SPR_NOACCESS, SPR_NOACCESS,
1486 &spr_read_generic, &spr_write_generic,
1487 0x00000000);
1488 /* XXX : not implemented */
1489 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1490 SPR_NOACCESS, SPR_NOACCESS,
1491 &spr_read_generic, &spr_write_generic,
1492 0x00000000);
1493 /* XXX : not implemented */
1494 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1495 SPR_NOACCESS, SPR_NOACCESS,
1496 &spr_read_generic, &spr_write_clear,
1497 0x00000000);
1498 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1499 SPR_NOACCESS, SPR_NOACCESS,
1500 &spr_read_generic, &spr_write_generic,
1501 0x00000000);
1502 spr_register(env, SPR_BOOKE_ESR, "ESR",
1503 SPR_NOACCESS, SPR_NOACCESS,
1504 &spr_read_generic, &spr_write_generic,
1505 0x00000000);
1506 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1507 SPR_NOACCESS, SPR_NOACCESS,
1508 &spr_read_generic, &spr_write_excp_prefix,
1509 0x00000000);
1510 /* Exception vectors */
1511 for (i = 0; i < 64; i++) {
1512 if (ivor_mask & (1ULL << i)) {
1513 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1514 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1515 exit(1);
1516 }
1517 spr_register(env, ivor_sprn[i], ivor_names[i],
1518 SPR_NOACCESS, SPR_NOACCESS,
1519 &spr_read_generic, &spr_write_excp_vector,
1520 0x00000000);
1521 }
1522 }
1523 spr_register(env, SPR_BOOKE_PID, "PID",
1524 SPR_NOACCESS, SPR_NOACCESS,
1525 &spr_read_generic, &spr_write_booke_pid,
1526 0x00000000);
1527 spr_register(env, SPR_BOOKE_TCR, "TCR",
1528 SPR_NOACCESS, SPR_NOACCESS,
1529 &spr_read_generic, &spr_write_booke_tcr,
1530 0x00000000);
1531 spr_register(env, SPR_BOOKE_TSR, "TSR",
1532 SPR_NOACCESS, SPR_NOACCESS,
1533 &spr_read_generic, &spr_write_booke_tsr,
1534 0x00000000);
1535 /* Timer */
1536 spr_register(env, SPR_DECR, "DECR",
1537 SPR_NOACCESS, SPR_NOACCESS,
1538 &spr_read_decr, &spr_write_decr,
1539 0x00000000);
1540 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1541 SPR_NOACCESS, SPR_NOACCESS,
1542 SPR_NOACCESS, &spr_write_generic,
1543 0x00000000);
1544 /* SPRGs */
1545 spr_register(env, SPR_USPRG0, "USPRG0",
1546 &spr_read_generic, &spr_write_generic,
1547 &spr_read_generic, &spr_write_generic,
1548 0x00000000);
1549 spr_register(env, SPR_SPRG4, "SPRG4",
1550 SPR_NOACCESS, SPR_NOACCESS,
1551 &spr_read_generic, &spr_write_generic,
1552 0x00000000);
1553 spr_register(env, SPR_SPRG5, "SPRG5",
1554 SPR_NOACCESS, SPR_NOACCESS,
1555 &spr_read_generic, &spr_write_generic,
1556 0x00000000);
1557 spr_register(env, SPR_SPRG6, "SPRG6",
1558 SPR_NOACCESS, SPR_NOACCESS,
1559 &spr_read_generic, &spr_write_generic,
1560 0x00000000);
1561 spr_register(env, SPR_SPRG7, "SPRG7",
1562 SPR_NOACCESS, SPR_NOACCESS,
1563 &spr_read_generic, &spr_write_generic,
1564 0x00000000);
1565 }
1566
1567 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1568 uint32_t maxsize, uint32_t flags,
1569 uint32_t nentries)
1570 {
1571 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1572 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1573 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1574 flags | nentries;
1575 }
1576
1577 /* BookE 2.06 storage control registers */
1578 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1579 uint32_t *tlbncfg)
1580 {
1581 #if !defined(CONFIG_USER_ONLY)
1582 const char *mas_names[8] = {
1583 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1584 };
1585 int mas_sprn[8] = {
1586 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1587 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1588 };
1589 int i;
1590
1591 /* TLB assist registers */
1592 /* XXX : not implemented */
1593 for (i = 0; i < 8; i++) {
1594 if (mas_mask & (1 << i)) {
1595 spr_register(env, mas_sprn[i], mas_names[i],
1596 SPR_NOACCESS, SPR_NOACCESS,
1597 &spr_read_generic, &spr_write_generic,
1598 0x00000000);
1599 }
1600 }
1601 if (env->nb_pids > 1) {
1602 /* XXX : not implemented */
1603 spr_register(env, SPR_BOOKE_PID1, "PID1",
1604 SPR_NOACCESS, SPR_NOACCESS,
1605 &spr_read_generic, &spr_write_booke_pid,
1606 0x00000000);
1607 }
1608 if (env->nb_pids > 2) {
1609 /* XXX : not implemented */
1610 spr_register(env, SPR_BOOKE_PID2, "PID2",
1611 SPR_NOACCESS, SPR_NOACCESS,
1612 &spr_read_generic, &spr_write_booke_pid,
1613 0x00000000);
1614 }
1615 /* XXX : not implemented */
1616 spr_register(env, SPR_MMUCFG, "MMUCFG",
1617 SPR_NOACCESS, SPR_NOACCESS,
1618 &spr_read_generic, SPR_NOACCESS,
1619 0x00000000); /* TOFIX */
1620 switch (env->nb_ways) {
1621 case 4:
1622 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1623 SPR_NOACCESS, SPR_NOACCESS,
1624 &spr_read_generic, SPR_NOACCESS,
1625 tlbncfg[3]);
1626 /* Fallthru */
1627 case 3:
1628 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1629 SPR_NOACCESS, SPR_NOACCESS,
1630 &spr_read_generic, SPR_NOACCESS,
1631 tlbncfg[2]);
1632 /* Fallthru */
1633 case 2:
1634 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1635 SPR_NOACCESS, SPR_NOACCESS,
1636 &spr_read_generic, SPR_NOACCESS,
1637 tlbncfg[1]);
1638 /* Fallthru */
1639 case 1:
1640 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1641 SPR_NOACCESS, SPR_NOACCESS,
1642 &spr_read_generic, SPR_NOACCESS,
1643 tlbncfg[0]);
1644 /* Fallthru */
1645 case 0:
1646 default:
1647 break;
1648 }
1649 #endif
1650
1651 gen_spr_usprgh(env);
1652 }
1653
1654 /* SPR specific to PowerPC 440 implementation */
1655 static void gen_spr_440 (CPUPPCState *env)
1656 {
1657 /* Cache control */
1658 /* XXX : not implemented */
1659 spr_register(env, SPR_440_DNV0, "DNV0",
1660 SPR_NOACCESS, SPR_NOACCESS,
1661 &spr_read_generic, &spr_write_generic,
1662 0x00000000);
1663 /* XXX : not implemented */
1664 spr_register(env, SPR_440_DNV1, "DNV1",
1665 SPR_NOACCESS, SPR_NOACCESS,
1666 &spr_read_generic, &spr_write_generic,
1667 0x00000000);
1668 /* XXX : not implemented */
1669 spr_register(env, SPR_440_DNV2, "DNV2",
1670 SPR_NOACCESS, SPR_NOACCESS,
1671 &spr_read_generic, &spr_write_generic,
1672 0x00000000);
1673 /* XXX : not implemented */
1674 spr_register(env, SPR_440_DNV3, "DNV3",
1675 SPR_NOACCESS, SPR_NOACCESS,
1676 &spr_read_generic, &spr_write_generic,
1677 0x00000000);
1678 /* XXX : not implemented */
1679 spr_register(env, SPR_440_DTV0, "DTV0",
1680 SPR_NOACCESS, SPR_NOACCESS,
1681 &spr_read_generic, &spr_write_generic,
1682 0x00000000);
1683 /* XXX : not implemented */
1684 spr_register(env, SPR_440_DTV1, "DTV1",
1685 SPR_NOACCESS, SPR_NOACCESS,
1686 &spr_read_generic, &spr_write_generic,
1687 0x00000000);
1688 /* XXX : not implemented */
1689 spr_register(env, SPR_440_DTV2, "DTV2",
1690 SPR_NOACCESS, SPR_NOACCESS,
1691 &spr_read_generic, &spr_write_generic,
1692 0x00000000);
1693 /* XXX : not implemented */
1694 spr_register(env, SPR_440_DTV3, "DTV3",
1695 SPR_NOACCESS, SPR_NOACCESS,
1696 &spr_read_generic, &spr_write_generic,
1697 0x00000000);
1698 /* XXX : not implemented */
1699 spr_register(env, SPR_440_DVLIM, "DVLIM",
1700 SPR_NOACCESS, SPR_NOACCESS,
1701 &spr_read_generic, &spr_write_generic,
1702 0x00000000);
1703 /* XXX : not implemented */
1704 spr_register(env, SPR_440_INV0, "INV0",
1705 SPR_NOACCESS, SPR_NOACCESS,
1706 &spr_read_generic, &spr_write_generic,
1707 0x00000000);
1708 /* XXX : not implemented */
1709 spr_register(env, SPR_440_INV1, "INV1",
1710 SPR_NOACCESS, SPR_NOACCESS,
1711 &spr_read_generic, &spr_write_generic,
1712 0x00000000);
1713 /* XXX : not implemented */
1714 spr_register(env, SPR_440_INV2, "INV2",
1715 SPR_NOACCESS, SPR_NOACCESS,
1716 &spr_read_generic, &spr_write_generic,
1717 0x00000000);
1718 /* XXX : not implemented */
1719 spr_register(env, SPR_440_INV3, "INV3",
1720 SPR_NOACCESS, SPR_NOACCESS,
1721 &spr_read_generic, &spr_write_generic,
1722 0x00000000);
1723 /* XXX : not implemented */
1724 spr_register(env, SPR_440_ITV0, "ITV0",
1725 SPR_NOACCESS, SPR_NOACCESS,
1726 &spr_read_generic, &spr_write_generic,
1727 0x00000000);
1728 /* XXX : not implemented */
1729 spr_register(env, SPR_440_ITV1, "ITV1",
1730 SPR_NOACCESS, SPR_NOACCESS,
1731 &spr_read_generic, &spr_write_generic,
1732 0x00000000);
1733 /* XXX : not implemented */
1734 spr_register(env, SPR_440_ITV2, "ITV2",
1735 SPR_NOACCESS, SPR_NOACCESS,
1736 &spr_read_generic, &spr_write_generic,
1737 0x00000000);
1738 /* XXX : not implemented */
1739 spr_register(env, SPR_440_ITV3, "ITV3",
1740 SPR_NOACCESS, SPR_NOACCESS,
1741 &spr_read_generic, &spr_write_generic,
1742 0x00000000);
1743 /* XXX : not implemented */
1744 spr_register(env, SPR_440_IVLIM, "IVLIM",
1745 SPR_NOACCESS, SPR_NOACCESS,
1746 &spr_read_generic, &spr_write_generic,
1747 0x00000000);
1748 /* Cache debug */
1749 /* XXX : not implemented */
1750 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1751 SPR_NOACCESS, SPR_NOACCESS,
1752 &spr_read_generic, SPR_NOACCESS,
1753 0x00000000);
1754 /* XXX : not implemented */
1755 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1756 SPR_NOACCESS, SPR_NOACCESS,
1757 &spr_read_generic, SPR_NOACCESS,
1758 0x00000000);
1759 /* XXX : not implemented */
1760 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1761 SPR_NOACCESS, SPR_NOACCESS,
1762 &spr_read_generic, SPR_NOACCESS,
1763 0x00000000);
1764 /* XXX : not implemented */
1765 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1766 SPR_NOACCESS, SPR_NOACCESS,
1767 &spr_read_generic, SPR_NOACCESS,
1768 0x00000000);
1769 /* XXX : not implemented */
1770 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1771 SPR_NOACCESS, SPR_NOACCESS,
1772 &spr_read_generic, SPR_NOACCESS,
1773 0x00000000);
1774 /* XXX : not implemented */
1775 spr_register(env, SPR_440_DBDR, "DBDR",
1776 SPR_NOACCESS, SPR_NOACCESS,
1777 &spr_read_generic, &spr_write_generic,
1778 0x00000000);
1779 /* Processor control */
1780 spr_register(env, SPR_4xx_CCR0, "CCR0",
1781 SPR_NOACCESS, SPR_NOACCESS,
1782 &spr_read_generic, &spr_write_generic,
1783 0x00000000);
1784 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1785 SPR_NOACCESS, SPR_NOACCESS,
1786 &spr_read_generic, SPR_NOACCESS,
1787 0x00000000);
1788 /* Storage control */
1789 spr_register(env, SPR_440_MMUCR, "MMUCR",
1790 SPR_NOACCESS, SPR_NOACCESS,
1791 &spr_read_generic, &spr_write_generic,
1792 0x00000000);
1793 }
1794
1795 /* SPR shared between PowerPC 40x implementations */
1796 static void gen_spr_40x (CPUPPCState *env)
1797 {
1798 /* Cache */
1799 /* not emulated, as QEMU do not emulate caches */
1800 spr_register(env, SPR_40x_DCCR, "DCCR",
1801 SPR_NOACCESS, SPR_NOACCESS,
1802 &spr_read_generic, &spr_write_generic,
1803 0x00000000);
1804 /* not emulated, as QEMU do not emulate caches */
1805 spr_register(env, SPR_40x_ICCR, "ICCR",
1806 SPR_NOACCESS, SPR_NOACCESS,
1807 &spr_read_generic, &spr_write_generic,
1808 0x00000000);
1809 /* not emulated, as QEMU do not emulate caches */
1810 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1811 SPR_NOACCESS, SPR_NOACCESS,
1812 &spr_read_generic, SPR_NOACCESS,
1813 0x00000000);
1814 /* Exception */
1815 spr_register(env, SPR_40x_DEAR, "DEAR",
1816 SPR_NOACCESS, SPR_NOACCESS,
1817 &spr_read_generic, &spr_write_generic,
1818 0x00000000);
1819 spr_register(env, SPR_40x_ESR, "ESR",
1820 SPR_NOACCESS, SPR_NOACCESS,
1821 &spr_read_generic, &spr_write_generic,
1822 0x00000000);
1823 spr_register(env, SPR_40x_EVPR, "EVPR",
1824 SPR_NOACCESS, SPR_NOACCESS,
1825 &spr_read_generic, &spr_write_excp_prefix,
1826 0x00000000);
1827 spr_register(env, SPR_40x_SRR2, "SRR2",
1828 &spr_read_generic, &spr_write_generic,
1829 &spr_read_generic, &spr_write_generic,
1830 0x00000000);
1831 spr_register(env, SPR_40x_SRR3, "SRR3",
1832 &spr_read_generic, &spr_write_generic,
1833 &spr_read_generic, &spr_write_generic,
1834 0x00000000);
1835 /* Timers */
1836 spr_register(env, SPR_40x_PIT, "PIT",
1837 SPR_NOACCESS, SPR_NOACCESS,
1838 &spr_read_40x_pit, &spr_write_40x_pit,
1839 0x00000000);
1840 spr_register(env, SPR_40x_TCR, "TCR",
1841 SPR_NOACCESS, SPR_NOACCESS,
1842 &spr_read_generic, &spr_write_booke_tcr,
1843 0x00000000);
1844 spr_register(env, SPR_40x_TSR, "TSR",
1845 SPR_NOACCESS, SPR_NOACCESS,
1846 &spr_read_generic, &spr_write_booke_tsr,
1847 0x00000000);
1848 }
1849
1850 /* SPR specific to PowerPC 405 implementation */
1851 static void gen_spr_405 (CPUPPCState *env)
1852 {
1853 /* MMU */
1854 spr_register(env, SPR_40x_PID, "PID",
1855 SPR_NOACCESS, SPR_NOACCESS,
1856 &spr_read_generic, &spr_write_generic,
1857 0x00000000);
1858 spr_register(env, SPR_4xx_CCR0, "CCR0",
1859 SPR_NOACCESS, SPR_NOACCESS,
1860 &spr_read_generic, &spr_write_generic,
1861 0x00700000);
1862 /* Debug interface */
1863 /* XXX : not implemented */
1864 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1865 SPR_NOACCESS, SPR_NOACCESS,
1866 &spr_read_generic, &spr_write_40x_dbcr0,
1867 0x00000000);
1868 /* XXX : not implemented */
1869 spr_register(env, SPR_405_DBCR1, "DBCR1",
1870 SPR_NOACCESS, SPR_NOACCESS,
1871 &spr_read_generic, &spr_write_generic,
1872 0x00000000);
1873 /* XXX : not implemented */
1874 spr_register(env, SPR_40x_DBSR, "DBSR",
1875 SPR_NOACCESS, SPR_NOACCESS,
1876 &spr_read_generic, &spr_write_clear,
1877 /* Last reset was system reset */
1878 0x00000300);
1879 /* XXX : not implemented */
1880 spr_register(env, SPR_40x_DAC1, "DAC1",
1881 SPR_NOACCESS, SPR_NOACCESS,
1882 &spr_read_generic, &spr_write_generic,
1883 0x00000000);
1884 spr_register(env, SPR_40x_DAC2, "DAC2",
1885 SPR_NOACCESS, SPR_NOACCESS,
1886 &spr_read_generic, &spr_write_generic,
1887 0x00000000);
1888 /* XXX : not implemented */
1889 spr_register(env, SPR_405_DVC1, "DVC1",
1890 SPR_NOACCESS, SPR_NOACCESS,
1891 &spr_read_generic, &spr_write_generic,
1892 0x00000000);
1893 /* XXX : not implemented */
1894 spr_register(env, SPR_405_DVC2, "DVC2",
1895 SPR_NOACCESS, SPR_NOACCESS,
1896 &spr_read_generic, &spr_write_generic,
1897 0x00000000);
1898 /* XXX : not implemented */
1899 spr_register(env, SPR_40x_IAC1, "IAC1",
1900 SPR_NOACCESS, SPR_NOACCESS,
1901 &spr_read_generic, &spr_write_generic,
1902 0x00000000);
1903 spr_register(env, SPR_40x_IAC2, "IAC2",
1904 SPR_NOACCESS, SPR_NOACCESS,
1905 &spr_read_generic, &spr_write_generic,
1906 0x00000000);
1907 /* XXX : not implemented */
1908 spr_register(env, SPR_405_IAC3, "IAC3",
1909 SPR_NOACCESS, SPR_NOACCESS,
1910 &spr_read_generic, &spr_write_generic,
1911 0x00000000);
1912 /* XXX : not implemented */
1913 spr_register(env, SPR_405_IAC4, "IAC4",
1914 SPR_NOACCESS, SPR_NOACCESS,
1915 &spr_read_generic, &spr_write_generic,
1916 0x00000000);
1917 /* Storage control */
1918 /* XXX: TODO: not implemented */
1919 spr_register(env, SPR_405_SLER, "SLER",
1920 SPR_NOACCESS, SPR_NOACCESS,
1921 &spr_read_generic, &spr_write_40x_sler,
1922 0x00000000);
1923 spr_register(env, SPR_40x_ZPR, "ZPR",
1924 SPR_NOACCESS, SPR_NOACCESS,
1925 &spr_read_generic, &spr_write_generic,
1926 0x00000000);
1927 /* XXX : not implemented */
1928 spr_register(env, SPR_405_SU0R, "SU0R",
1929 SPR_NOACCESS, SPR_NOACCESS,
1930 &spr_read_generic, &spr_write_generic,
1931 0x00000000);
1932 /* SPRG */
1933 spr_register(env, SPR_USPRG0, "USPRG0",
1934 &spr_read_ureg, SPR_NOACCESS,
1935 &spr_read_ureg, SPR_NOACCESS,
1936 0x00000000);
1937 spr_register(env, SPR_SPRG4, "SPRG4",
1938 SPR_NOACCESS, SPR_NOACCESS,
1939 &spr_read_generic, &spr_write_generic,
1940 0x00000000);
1941 spr_register(env, SPR_SPRG5, "SPRG5",
1942 SPR_NOACCESS, SPR_NOACCESS,
1943 spr_read_generic, &spr_write_generic,
1944 0x00000000);
1945 spr_register(env, SPR_SPRG6, "SPRG6",
1946 SPR_NOACCESS, SPR_NOACCESS,
1947 spr_read_generic, &spr_write_generic,
1948 0x00000000);
1949 spr_register(env, SPR_SPRG7, "SPRG7",
1950 SPR_NOACCESS, SPR_NOACCESS,
1951 spr_read_generic, &spr_write_generic,
1952 0x00000000);
1953 gen_spr_usprgh(env);
1954 }
1955
1956 /* SPR shared between PowerPC 401 & 403 implementations */
1957 static void gen_spr_401_403 (CPUPPCState *env)
1958 {
1959 /* Time base */
1960 spr_register(env, SPR_403_VTBL, "TBL",
1961 &spr_read_tbl, SPR_NOACCESS,
1962 &spr_read_tbl, SPR_NOACCESS,
1963 0x00000000);
1964 spr_register(env, SPR_403_TBL, "TBL",
1965 SPR_NOACCESS, SPR_NOACCESS,
1966 SPR_NOACCESS, &spr_write_tbl,
1967 0x00000000);
1968 spr_register(env, SPR_403_VTBU, "TBU",
1969 &spr_read_tbu, SPR_NOACCESS,
1970 &spr_read_tbu, SPR_NOACCESS,
1971 0x00000000);
1972 spr_register(env, SPR_403_TBU, "TBU",
1973 SPR_NOACCESS, SPR_NOACCESS,
1974 SPR_NOACCESS, &spr_write_tbu,
1975 0x00000000);
1976 /* Debug */
1977 /* not emulated, as QEMU do not emulate caches */
1978 spr_register(env, SPR_403_CDBCR, "CDBCR",
1979 SPR_NOACCESS, SPR_NOACCESS,
1980 &spr_read_generic, &spr_write_generic,
1981 0x00000000);
1982 }
1983
1984 /* SPR specific to PowerPC 401 implementation */
1985 static void gen_spr_401 (CPUPPCState *env)
1986 {
1987 /* Debug interface */
1988 /* XXX : not implemented */
1989 spr_register(env, SPR_40x_DBCR0, "DBCR",
1990 SPR_NOACCESS, SPR_NOACCESS,
1991 &spr_read_generic, &spr_write_40x_dbcr0,
1992 0x00000000);
1993 /* XXX : not implemented */
1994 spr_register(env, SPR_40x_DBSR, "DBSR",
1995 SPR_NOACCESS, SPR_NOACCESS,
1996 &spr_read_generic, &spr_write_clear,
1997 /* Last reset was system reset */
1998 0x00000300);
1999 /* XXX : not implemented */
2000 spr_register(env, SPR_40x_DAC1, "DAC",
2001 SPR_NOACCESS, SPR_NOACCESS,
2002 &spr_read_generic, &spr_write_generic,
2003 0x00000000);
2004 /* XXX : not implemented */
2005 spr_register(env, SPR_40x_IAC1, "IAC",
2006 SPR_NOACCESS, SPR_NOACCESS,
2007 &spr_read_generic, &spr_write_generic,
2008 0x00000000);
2009 /* Storage control */
2010 /* XXX: TODO: not implemented */
2011 spr_register(env, SPR_405_SLER, "SLER",
2012 SPR_NOACCESS, SPR_NOACCESS,
2013 &spr_read_generic, &spr_write_40x_sler,
2014 0x00000000);
2015 /* not emulated, as QEMU never does speculative access */
2016 spr_register(env, SPR_40x_SGR, "SGR",
2017 SPR_NOACCESS, SPR_NOACCESS,
2018 &spr_read_generic, &spr_write_generic,
2019 0xFFFFFFFF);
2020 /* not emulated, as QEMU do not emulate caches */
2021 spr_register(env, SPR_40x_DCWR, "DCWR",
2022 SPR_NOACCESS, SPR_NOACCESS,
2023 &spr_read_generic, &spr_write_generic,
2024 0x00000000);
2025 }
2026
2027 static void gen_spr_401x2 (CPUPPCState *env)
2028 {
2029 gen_spr_401(env);
2030 spr_register(env, SPR_40x_PID, "PID",
2031 SPR_NOACCESS, SPR_NOACCESS,
2032 &spr_read_generic, &spr_write_generic,
2033 0x00000000);
2034 spr_register(env, SPR_40x_ZPR, "ZPR",
2035 SPR_NOACCESS, SPR_NOACCESS,
2036 &spr_read_generic, &spr_write_generic,
2037 0x00000000);
2038 }
2039
2040 /* SPR specific to PowerPC 403 implementation */
2041 static void gen_spr_403 (CPUPPCState *env)
2042 {
2043 /* Debug interface */
2044 /* XXX : not implemented */
2045 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2046 SPR_NOACCESS, SPR_NOACCESS,
2047 &spr_read_generic, &spr_write_40x_dbcr0,
2048 0x00000000);
2049 /* XXX : not implemented */
2050 spr_register(env, SPR_40x_DBSR, "DBSR",
2051 SPR_NOACCESS, SPR_NOACCESS,
2052 &spr_read_generic, &spr_write_clear,
2053 /* Last reset was system reset */
2054 0x00000300);
2055 /* XXX : not implemented */
2056 spr_register(env, SPR_40x_DAC1, "DAC1",
2057 SPR_NOACCESS, SPR_NOACCESS,
2058 &spr_read_generic, &spr_write_generic,
2059 0x00000000);
2060 /* XXX : not implemented */
2061 spr_register(env, SPR_40x_DAC2, "DAC2",
2062 SPR_NOACCESS, SPR_NOACCESS,
2063 &spr_read_generic, &spr_write_generic,
2064 0x00000000);
2065 /* XXX : not implemented */
2066 spr_register(env, SPR_40x_IAC1, "IAC1",
2067 SPR_NOACCESS, SPR_NOACCESS,
2068 &spr_read_generic, &spr_write_generic,
2069 0x00000000);
2070 /* XXX : not implemented */
2071 spr_register(env, SPR_40x_IAC2, "IAC2",
2072 SPR_NOACCESS, SPR_NOACCESS,
2073 &spr_read_generic, &spr_write_generic,
2074 0x00000000);
2075 }
2076
2077 static void gen_spr_403_real (CPUPPCState *env)
2078 {
2079 spr_register(env, SPR_403_PBL1, "PBL1",
2080 SPR_NOACCESS, SPR_NOACCESS,
2081 &spr_read_403_pbr, &spr_write_403_pbr,
2082 0x00000000);
2083 spr_register(env, SPR_403_PBU1, "PBU1",
2084 SPR_NOACCESS, SPR_NOACCESS,
2085 &spr_read_403_pbr, &spr_write_403_pbr,
2086 0x00000000);
2087 spr_register(env, SPR_403_PBL2, "PBL2",
2088 SPR_NOACCESS, SPR_NOACCESS,
2089 &spr_read_403_pbr, &spr_write_403_pbr,
2090 0x00000000);
2091 spr_register(env, SPR_403_PBU2, "PBU2",
2092 SPR_NOACCESS, SPR_NOACCESS,
2093 &spr_read_403_pbr, &spr_write_403_pbr,
2094 0x00000000);
2095 }
2096
2097 static void gen_spr_403_mmu (CPUPPCState *env)
2098 {
2099 /* MMU */
2100 spr_register(env, SPR_40x_PID, "PID",
2101 SPR_NOACCESS, SPR_NOACCESS,
2102 &spr_read_generic, &spr_write_generic,
2103 0x00000000);
2104 spr_register(env, SPR_40x_ZPR, "ZPR",
2105 SPR_NOACCESS, SPR_NOACCESS,
2106 &spr_read_generic, &spr_write_generic,
2107 0x00000000);
2108 }
2109
2110 /* SPR specific to PowerPC compression coprocessor extension */
2111 static void gen_spr_compress (CPUPPCState *env)
2112 {
2113 /* XXX : not implemented */
2114 spr_register(env, SPR_401_SKR, "SKR",
2115 SPR_NOACCESS, SPR_NOACCESS,
2116 &spr_read_generic, &spr_write_generic,
2117 0x00000000);
2118 }
2119
2120 #if defined (TARGET_PPC64)
2121 /* SPR specific to PowerPC 620 */
2122 static void gen_spr_620 (CPUPPCState *env)
2123 {
2124 /* Processor identification */
2125 spr_register(env, SPR_PIR, "PIR",
2126 SPR_NOACCESS, SPR_NOACCESS,
2127 &spr_read_generic, &spr_write_pir,
2128 0x00000000);
2129 spr_register(env, SPR_ASR, "ASR",
2130 SPR_NOACCESS, SPR_NOACCESS,
2131 &spr_read_asr, &spr_write_asr,
2132 0x00000000);
2133 /* Breakpoints */
2134 /* XXX : not implemented */
2135 spr_register(env, SPR_IABR, "IABR",
2136 SPR_NOACCESS, SPR_NOACCESS,
2137 &spr_read_generic, &spr_write_generic,
2138 0x00000000);
2139 /* XXX : not implemented */
2140 spr_register(env, SPR_DABR, "DABR",
2141 SPR_NOACCESS, SPR_NOACCESS,
2142 &spr_read_generic, &spr_write_generic,
2143 0x00000000);
2144 /* XXX : not implemented */
2145 spr_register(env, SPR_SIAR, "SIAR",
2146 SPR_NOACCESS, SPR_NOACCESS,
2147 &spr_read_generic, SPR_NOACCESS,
2148 0x00000000);
2149 /* XXX : not implemented */
2150 spr_register(env, SPR_SDA, "SDA",
2151 SPR_NOACCESS, SPR_NOACCESS,
2152 &spr_read_generic, SPR_NOACCESS,
2153 0x00000000);
2154 /* XXX : not implemented */
2155 spr_register(env, SPR_620_PMC1R, "PMC1",
2156 SPR_NOACCESS, SPR_NOACCESS,
2157 &spr_read_generic, SPR_NOACCESS,
2158 0x00000000);
2159 spr_register(env, SPR_620_PMC1W, "PMC1",
2160 SPR_NOACCESS, SPR_NOACCESS,
2161 SPR_NOACCESS, &spr_write_generic,
2162 0x00000000);
2163 /* XXX : not implemented */
2164 spr_register(env, SPR_620_PMC2R, "PMC2",
2165 SPR_NOACCESS, SPR_NOACCESS,
2166 &spr_read_generic, SPR_NOACCESS,
2167 0x00000000);
2168 spr_register(env, SPR_620_PMC2W, "PMC2",
2169 SPR_NOACCESS, SPR_NOACCESS,
2170 SPR_NOACCESS, &spr_write_generic,
2171 0x00000000);
2172 /* XXX : not implemented */
2173 spr_register(env, SPR_620_MMCR0R, "MMCR0",
2174 SPR_NOACCESS, SPR_NOACCESS,
2175 &spr_read_generic, SPR_NOACCESS,
2176 0x00000000);
2177 spr_register(env, SPR_620_MMCR0W, "MMCR0",
2178 SPR_NOACCESS, SPR_NOACCESS,
2179 SPR_NOACCESS, &spr_write_generic,
2180 0x00000000);
2181 /* External access control */
2182 /* XXX : not implemented */
2183 spr_register(env, SPR_EAR, "EAR",
2184 SPR_NOACCESS, SPR_NOACCESS,
2185 &spr_read_generic, &spr_write_generic,
2186 0x00000000);
2187 #if 0 // XXX: check this
2188 /* XXX : not implemented */
2189 spr_register(env, SPR_620_PMR0, "PMR0",
2190 SPR_NOACCESS, SPR_NOACCESS,
2191 &spr_read_generic, &spr_write_generic,
2192 0x00000000);
2193 /* XXX : not implemented */
2194 spr_register(env, SPR_620_PMR1, "PMR1",
2195 SPR_NOACCESS, SPR_NOACCESS,
2196 &spr_read_generic, &spr_write_generic,
2197 0x00000000);
2198 /* XXX : not implemented */
2199 spr_register(env, SPR_620_PMR2, "PMR2",
2200 SPR_NOACCESS, SPR_NOACCESS,
2201 &spr_read_generic, &spr_write_generic,
2202 0x00000000);
2203 /* XXX : not implemented */
2204 spr_register(env, SPR_620_PMR3, "PMR3",
2205 SPR_NOACCESS, SPR_NOACCESS,
2206 &spr_read_generic, &spr_write_generic,
2207 0x00000000);
2208 /* XXX : not implemented */
2209 spr_register(env, SPR_620_PMR4, "PMR4",
2210 SPR_NOACCESS, SPR_NOACCESS,
2211 &spr_read_generic, &spr_write_generic,
2212 0x00000000);
2213 /* XXX : not implemented */
2214 spr_register(env, SPR_620_PMR5, "PMR5",
2215 SPR_NOACCESS, SPR_NOACCESS,
2216 &spr_read_generic, &spr_write_generic,
2217 0x00000000);
2218 /* XXX : not implemented */
2219 spr_register(env, SPR_620_PMR6, "PMR6",
2220 SPR_NOACCESS, SPR_NOACCESS,
2221 &spr_read_generic, &spr_write_generic,
2222 0x00000000);
2223 /* XXX : not implemented */
2224 spr_register(env, SPR_620_PMR7, "PMR7",
2225 SPR_NOACCESS, SPR_NOACCESS,
2226 &spr_read_generic, &spr_write_generic,
2227 0x00000000);
2228 /* XXX : not implemented */
2229 spr_register(env, SPR_620_PMR8, "PMR8",
2230 SPR_NOACCESS, SPR_NOACCESS,
2231 &spr_read_generic, &spr_write_generic,
2232 0x00000000);
2233 /* XXX : not implemented */
2234 spr_register(env, SPR_620_PMR9, "PMR9",
2235 SPR_NOACCESS, SPR_NOACCESS,
2236 &spr_read_generic, &spr_write_generic,
2237 0x00000000);
2238 /* XXX : not implemented */
2239 spr_register(env, SPR_620_PMRA, "PMR10",
2240 SPR_NOACCESS, SPR_NOACCESS,
2241 &spr_read_generic, &spr_write_generic,
2242 0x00000000);
2243 /* XXX : not implemented */
2244 spr_register(env, SPR_620_PMRB, "PMR11",
2245 SPR_NOACCESS, SPR_NOACCESS,
2246 &spr_read_generic, &spr_write_generic,
2247 0x00000000);
2248 /* XXX : not implemented */
2249 spr_register(env, SPR_620_PMRC, "PMR12",
2250 SPR_NOACCESS, SPR_NOACCESS,
2251 &spr_read_generic, &spr_write_generic,
2252 0x00000000);
2253 /* XXX : not implemented */
2254 spr_register(env, SPR_620_PMRD, "PMR13",
2255 SPR_NOACCESS, SPR_NOACCESS,
2256 &spr_read_generic, &spr_write_generic,
2257 0x00000000);
2258 /* XXX : not implemented */
2259 spr_register(env, SPR_620_PMRE, "PMR14",
2260 SPR_NOACCESS, SPR_NOACCESS,
2261 &spr_read_generic, &spr_write_generic,
2262 0x00000000);
2263 /* XXX : not implemented */
2264 spr_register(env, SPR_620_PMRF, "PMR15",
2265 SPR_NOACCESS, SPR_NOACCESS,
2266 &spr_read_generic, &spr_write_generic,
2267 0x00000000);
2268 #endif
2269 /* XXX : not implemented */
2270 spr_register(env, SPR_620_BUSCSR, "BUSCSR",
2271 SPR_NOACCESS, SPR_NOACCESS,
2272 &spr_read_generic, &spr_write_generic,
2273 0x00000000);
2274 /* XXX : not implemented */
2275 spr_register(env, SPR_620_L2CR, "L2CR",
2276 SPR_NOACCESS, SPR_NOACCESS,
2277 &spr_read_generic, &spr_write_generic,
2278 0x00000000);
2279 /* XXX : not implemented */
2280 spr_register(env, SPR_620_L2SR, "L2SR",
2281 SPR_NOACCESS, SPR_NOACCESS,
2282 &spr_read_generic, &spr_write_generic,
2283 0x00000000);
2284 }
2285 #endif /* defined (TARGET_PPC64) */
2286
2287 static void gen_spr_5xx_8xx (CPUPPCState *env)
2288 {
2289 /* Exception processing */
2290 spr_register(env, SPR_DSISR, "DSISR",
2291 SPR_NOACCESS, SPR_NOACCESS,
2292 &spr_read_generic, &spr_write_generic,
2293 0x00000000);
2294 spr_register(env, SPR_DAR, "DAR",
2295 SPR_NOACCESS, SPR_NOACCESS,
2296 &spr_read_generic, &spr_write_generic,
2297 0x00000000);
2298 /* Timer */
2299 spr_register(env, SPR_DECR, "DECR",
2300 SPR_NOACCESS, SPR_NOACCESS,
2301 &spr_read_decr, &spr_write_decr,
2302 0x00000000);
2303 /* XXX : not implemented */
2304 spr_register(env, SPR_MPC_EIE, "EIE",
2305 SPR_NOACCESS, SPR_NOACCESS,
2306 &spr_read_generic, &spr_write_generic,
2307 0x00000000);
2308 /* XXX : not implemented */
2309 spr_register(env, SPR_MPC_EID, "EID",
2310 SPR_NOACCESS, SPR_NOACCESS,
2311 &spr_read_generic, &spr_write_generic,
2312 0x00000000);
2313 /* XXX : not implemented */
2314 spr_register(env, SPR_MPC_NRI, "NRI",
2315 SPR_NOACCESS, SPR_NOACCESS,
2316 &spr_read_generic, &spr_write_generic,
2317 0x00000000);
2318 /* XXX : not implemented */
2319 spr_register(env, SPR_MPC_CMPA, "CMPA",
2320 SPR_NOACCESS, SPR_NOACCESS,
2321 &spr_read_generic, &spr_write_generic,
2322 0x00000000);
2323 /* XXX : not implemented */
2324 spr_register(env, SPR_MPC_CMPB, "CMPB",
2325 SPR_NOACCESS, SPR_NOACCESS,
2326 &spr_read_generic, &spr_write_generic,
2327 0x00000000);
2328 /* XXX : not implemented */
2329 spr_register(env, SPR_MPC_CMPC, "CMPC",
2330 SPR_NOACCESS, SPR_NOACCESS,
2331 &spr_read_generic, &spr_write_generic,
2332 0x00000000);
2333 /* XXX : not implemented */
2334 spr_register(env, SPR_MPC_CMPD, "CMPD",
2335 SPR_NOACCESS, SPR_NOACCESS,
2336 &spr_read_generic, &spr_write_generic,
2337 0x00000000);
2338 /* XXX : not implemented */
2339 spr_register(env, SPR_MPC_ECR, "ECR",
2340 SPR_NOACCESS, SPR_NOACCESS,
2341 &spr_read_generic, &spr_write_generic,
2342 0x00000000);
2343 /* XXX : not implemented */
2344 spr_register(env, SPR_MPC_DER, "DER",
2345 SPR_NOACCESS, SPR_NOACCESS,
2346 &spr_read_generic, &spr_write_generic,
2347 0x00000000);
2348 /* XXX : not implemented */
2349 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2350 SPR_NOACCESS, SPR_NOACCESS,
2351 &spr_read_generic, &spr_write_generic,
2352 0x00000000);
2353 /* XXX : not implemented */
2354 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2355 SPR_NOACCESS, SPR_NOACCESS,
2356 &spr_read_generic, &spr_write_generic,
2357 0x00000000);
2358 /* XXX : not implemented */
2359 spr_register(env, SPR_MPC_CMPE, "CMPE",
2360 SPR_NOACCESS, SPR_NOACCESS,
2361 &spr_read_generic, &spr_write_generic,
2362 0x00000000);
2363 /* XXX : not implemented */
2364 spr_register(env, SPR_MPC_CMPF, "CMPF",
2365 SPR_NOACCESS, SPR_NOACCESS,
2366 &spr_read_generic, &spr_write_generic,
2367 0x00000000);
2368 /* XXX : not implemented */
2369 spr_register(env, SPR_MPC_CMPG, "CMPG",
2370 SPR_NOACCESS, SPR_NOACCESS,
2371 &spr_read_generic, &spr_write_generic,
2372 0x00000000);
2373 /* XXX : not implemented */
2374 spr_register(env, SPR_MPC_CMPH, "CMPH",
2375 SPR_NOACCESS, SPR_NOACCESS,
2376 &spr_read_generic, &spr_write_generic,
2377 0x00000000);
2378 /* XXX : not implemented */
2379 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2380 SPR_NOACCESS, SPR_NOACCESS,
2381 &spr_read_generic, &spr_write_generic,
2382 0x00000000);
2383 /* XXX : not implemented */
2384 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2385 SPR_NOACCESS, SPR_NOACCESS,
2386 &spr_read_generic, &spr_write_generic,
2387 0x00000000);
2388 /* XXX : not implemented */
2389 spr_register(env, SPR_MPC_BAR, "BAR",
2390 SPR_NOACCESS, SPR_NOACCESS,
2391 &spr_read_generic, &spr_write_generic,
2392 0x00000000);
2393 /* XXX : not implemented */
2394 spr_register(env, SPR_MPC_DPDR, "DPDR",
2395 SPR_NOACCESS, SPR_NOACCESS,
2396 &spr_read_generic, &spr_write_generic,
2397 0x00000000);
2398 /* XXX : not implemented */
2399 spr_register(env, SPR_MPC_IMMR, "IMMR",
2400 SPR_NOACCESS, SPR_NOACCESS,
2401 &spr_read_generic, &spr_write_generic,
2402 0x00000000);
2403 }
2404
2405 static void gen_spr_5xx (CPUPPCState *env)
2406 {
2407 /* XXX : not implemented */
2408 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2409 SPR_NOACCESS, SPR_NOACCESS,
2410 &spr_read_generic, &spr_write_generic,
2411 0x00000000);
2412 /* XXX : not implemented */
2413 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2414 SPR_NOACCESS, SPR_NOACCESS,
2415 &spr_read_generic, &spr_write_generic,
2416 0x00000000);
2417 /* XXX : not implemented */
2418 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2419 SPR_NOACCESS, SPR_NOACCESS,
2420 &spr_read_generic, &spr_write_generic,
2421 0x00000000);
2422 /* XXX : not implemented */
2423 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2424 SPR_NOACCESS, SPR_NOACCESS,
2425 &spr_read_generic, &spr_write_generic,
2426 0x00000000);
2427 /* XXX : not implemented */
2428 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2429 SPR_NOACCESS, SPR_NOACCESS,
2430 &spr_read_generic, &spr_write_generic,
2431 0x00000000);
2432 /* XXX : not implemented */
2433 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2434 SPR_NOACCESS, SPR_NOACCESS,
2435 &spr_read_generic, &spr_write_generic,
2436 0x00000000);
2437 /* XXX : not implemented */
2438 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2439 SPR_NOACCESS, SPR_NOACCESS,
2440 &spr_read_generic, &spr_write_generic,
2441 0x00000000);
2442 /* XXX : not implemented */
2443 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2444 SPR_NOACCESS, SPR_NOACCESS,
2445 &spr_read_generic, &spr_write_generic,
2446 0x00000000);
2447 /* XXX : not implemented */
2448 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2449 SPR_NOACCESS, SPR_NOACCESS,
2450 &spr_read_generic, &spr_write_generic,
2451 0x00000000);
2452 /* XXX : not implemented */
2453 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2454 SPR_NOACCESS, SPR_NOACCESS,
2455 &spr_read_generic, &spr_write_generic,
2456 0x00000000);
2457 /* XXX : not implemented */
2458 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2459 SPR_NOACCESS, SPR_NOACCESS,
2460 &spr_read_generic, &spr_write_generic,
2461 0x00000000);
2462 /* XXX : not implemented */
2463 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2464 SPR_NOACCESS, SPR_NOACCESS,
2465 &spr_read_generic, &spr_write_generic,
2466 0x00000000);
2467 /* XXX : not implemented */
2468 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2469 SPR_NOACCESS, SPR_NOACCESS,
2470 &spr_read_generic, &spr_write_generic,
2471 0x00000000);
2472 /* XXX : not implemented */
2473 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2474 SPR_NOACCESS, SPR_NOACCESS,
2475 &spr_read_generic, &spr_write_generic,
2476 0x00000000);
2477 /* XXX : not implemented */
2478 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2479 SPR_NOACCESS, SPR_NOACCESS,
2480 &spr_read_generic, &spr_write_generic,
2481 0x00000000);
2482 /* XXX : not implemented */
2483 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2484 SPR_NOACCESS, SPR_NOACCESS,
2485 &spr_read_generic, &spr_write_generic,
2486 0x00000000);
2487 /* XXX : not implemented */
2488 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2489 SPR_NOACCESS, SPR_NOACCESS,
2490 &spr_read_generic, &spr_write_generic,
2491 0x00000000);
2492 /* XXX : not implemented */
2493 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2494 SPR_NOACCESS, SPR_NOACCESS,
2495 &spr_read_generic, &spr_write_generic,
2496 0x00000000);
2497 /* XXX : not implemented */
2498 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2499 SPR_NOACCESS, SPR_NOACCESS,
2500 &spr_read_generic, &spr_write_generic,
2501 0x00000000);
2502 /* XXX : not implemented */
2503 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2504 SPR_NOACCESS, SPR_NOACCESS,
2505 &spr_read_generic, &spr_write_generic,
2506 0x00000000);
2507 /* XXX : not implemented */
2508 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2509 SPR_NOACCESS, SPR_NOACCESS,
2510 &spr_read_generic, &spr_write_generic,
2511 0x00000000);
2512 }
2513
2514 static void gen_spr_8xx (CPUPPCState *env)
2515 {
2516 /* XXX : not implemented */
2517 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2518 SPR_NOACCESS, SPR_NOACCESS,
2519 &spr_read_generic, &spr_write_generic,
2520 0x00000000);
2521 /* XXX : not implemented */
2522 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2523 SPR_NOACCESS, SPR_NOACCESS,
2524 &spr_read_generic, &spr_write_generic,
2525 0x00000000);
2526 /* XXX : not implemented */
2527 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2528 SPR_NOACCESS, SPR_NOACCESS,
2529 &spr_read_generic, &spr_write_generic,
2530 0x00000000);
2531 /* XXX : not implemented */
2532 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2533 SPR_NOACCESS, SPR_NOACCESS,
2534 &spr_read_generic, &spr_write_generic,
2535 0x00000000);
2536 /* XXX : not implemented */
2537 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2538 SPR_NOACCESS, SPR_NOACCESS,
2539 &spr_read_generic, &spr_write_generic,
2540 0x00000000);
2541 /* XXX : not implemented */
2542 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2543 SPR_NOACCESS, SPR_NOACCESS,
2544 &spr_read_generic, &spr_write_generic,
2545 0x00000000);
2546 /* XXX : not implemented */
2547 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2548 SPR_NOACCESS, SPR_NOACCESS,
2549 &spr_read_generic, &spr_write_generic,
2550 0x00000000);
2551 /* XXX : not implemented */
2552 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2553 SPR_NOACCESS, SPR_NOACCESS,
2554 &spr_read_generic, &spr_write_generic,
2555 0x00000000);
2556 /* XXX : not implemented */
2557 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2558 SPR_NOACCESS, SPR_NOACCESS,
2559 &spr_read_generic, &spr_write_generic,
2560 0x00000000);
2561 /* XXX : not implemented */
2562 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2563 SPR_NOACCESS, SPR_NOACCESS,
2564 &spr_read_generic, &spr_write_generic,
2565 0x00000000);
2566 /* XXX : not implemented */
2567 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2568 SPR_NOACCESS, SPR_NOACCESS,
2569 &spr_read_generic, &spr_write_generic,
2570 0x00000000);
2571 /* XXX : not implemented */
2572 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2573 SPR_NOACCESS, SPR_NOACCESS,
2574 &spr_read_generic, &spr_write_generic,
2575 0x00000000);
2576 /* XXX : not implemented */
2577 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2578 SPR_NOACCESS, SPR_NOACCESS,
2579 &spr_read_generic, &spr_write_generic,
2580 0x00000000);
2581 /* XXX : not implemented */
2582 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2583 SPR_NOACCESS, SPR_NOACCESS,
2584 &spr_read_generic, &spr_write_generic,
2585 0x00000000);
2586 /* XXX : not implemented */
2587 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2588 SPR_NOACCESS, SPR_NOACCESS,
2589 &spr_read_generic, &spr_write_generic,
2590 0x00000000);
2591 /* XXX : not implemented */
2592 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2593 SPR_NOACCESS, SPR_NOACCESS,
2594 &spr_read_generic, &spr_write_generic,
2595 0x00000000);
2596 /* XXX : not implemented */
2597 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2598 SPR_NOACCESS, SPR_NOACCESS,
2599 &spr_read_generic, &spr_write_generic,
2600 0x00000000);
2601 /* XXX : not implemented */
2602 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2603 SPR_NOACCESS, SPR_NOACCESS,
2604 &spr_read_generic, &spr_write_generic,
2605 0x00000000);
2606 /* XXX : not implemented */
2607 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2608 SPR_NOACCESS, SPR_NOACCESS,
2609 &spr_read_generic, &spr_write_generic,
2610 0x00000000);
2611 /* XXX : not implemented */
2612 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2613 SPR_NOACCESS, SPR_NOACCESS,
2614 &spr_read_generic, &spr_write_generic,
2615 0x00000000);
2616 /* XXX : not implemented */
2617 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2618 SPR_NOACCESS, SPR_NOACCESS,
2619 &spr_read_generic, &spr_write_generic,
2620 0x00000000);
2621 /* XXX : not implemented */
2622 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2623 SPR_NOACCESS, SPR_NOACCESS,
2624 &spr_read_generic, &spr_write_generic,
2625 0x00000000);
2626 /* XXX : not implemented */
2627 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2628 SPR_NOACCESS, SPR_NOACCESS,
2629 &spr_read_generic, &spr_write_generic,
2630 0x00000000);
2631 /* XXX : not implemented */
2632 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2633 SPR_NOACCESS, SPR_NOACCESS,
2634 &spr_read_generic, &spr_write_generic,
2635 0x00000000);
2636 /* XXX : not implemented */
2637 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2638 SPR_NOACCESS, SPR_NOACCESS,
2639 &spr_read_generic, &spr_write_generic,
2640 0x00000000);
2641 }
2642
2643 // XXX: TODO
2644 /*
2645 * AMR => SPR 29 (Power 2.04)
2646 * CTRL => SPR 136 (Power 2.04)
2647 * CTRL => SPR 152 (Power 2.04)
2648 * SCOMC => SPR 276 (64 bits ?)
2649 * SCOMD => SPR 277 (64 bits ?)
2650 * TBU40 => SPR 286 (Power 2.04 hypv)
2651 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2652 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2653 * HDSISR => SPR 306 (Power 2.04 hypv)
2654 * HDAR => SPR 307 (Power 2.04 hypv)
2655 * PURR => SPR 309 (Power 2.04 hypv)
2656 * HDEC => SPR 310 (Power 2.04 hypv)
2657 * HIOR => SPR 311 (hypv)
2658 * RMOR => SPR 312 (970)
2659 * HRMOR => SPR 313 (Power 2.04 hypv)
2660 * HSRR0 => SPR 314 (Power 2.04 hypv)
2661 * HSRR1 => SPR 315 (Power 2.04 hypv)
2662 * LPCR => SPR 316 (970)
2663 * LPIDR => SPR 317 (970)
2664 * EPR => SPR 702 (Power 2.04 emb)
2665 * perf => 768-783 (Power 2.04)
2666 * perf => 784-799 (Power 2.04)
2667 * PPR => SPR 896 (Power 2.04)
2668 * EPLC => SPR 947 (Power 2.04 emb)
2669 * EPSC => SPR 948 (Power 2.04 emb)
2670 * DABRX => 1015 (Power 2.04 hypv)
2671 * FPECR => SPR 1022 (?)
2672 * ... and more (thermal management, performance counters, ...)
2673 */
2674
2675 /*****************************************************************************/
2676 /* Exception vectors models */
2677 static void init_excp_4xx_real (CPUPPCState *env)
2678 {
2679 #if !defined(CONFIG_USER_ONLY)
2680 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2681 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2682 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2683 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2684 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2685 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2686 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2687 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2688 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2689 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2690 env->hreset_excp_prefix = 0x00000000UL;
2691 env->ivor_mask = 0x0000FFF0UL;
2692 env->ivpr_mask = 0xFFFF0000UL;
2693 /* Hardware reset vector */
2694 env->hreset_vector = 0xFFFFFFFCUL;
2695 #endif
2696 }
2697
2698 static void init_excp_4xx_softmmu (CPUPPCState *env)
2699 {
2700 #if !defined(CONFIG_USER_ONLY)
2701 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2702 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2703 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2704 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2705 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2706 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2707 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2708 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2709 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2710 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2711 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2712 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2713 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2714 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2715 env->hreset_excp_prefix = 0x00000000UL;
2716 env->ivor_mask = 0x0000FFF0UL;
2717 env->ivpr_mask = 0xFFFF0000UL;
2718 /* Hardware reset vector */
2719 env->hreset_vector = 0xFFFFFFFCUL;
2720 #endif
2721 }
2722
2723 static void init_excp_MPC5xx (CPUPPCState *env)
2724 {
2725 #if !defined(CONFIG_USER_ONLY)
2726 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2727 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2728 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2729 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2730 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2731 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2732 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2733 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2734 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2735 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2736 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2737 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2738 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2739 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2740 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2741 env->hreset_excp_prefix = 0x00000000UL;
2742 env->ivor_mask = 0x0000FFF0UL;
2743 env->ivpr_mask = 0xFFFF0000UL;
2744 /* Hardware reset vector */
2745 env->hreset_vector = 0xFFFFFFFCUL;
2746 #endif
2747 }
2748
2749 static void init_excp_MPC8xx (CPUPPCState *env)
2750 {
2751 #if !defined(CONFIG_USER_ONLY)
2752 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2753 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2754 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2755 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2756 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2757 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2758 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2759 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2760 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2761 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2762 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2763 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2764 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2765 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2766 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2767 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2768 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2769 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2770 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2771 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2772 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2773 env->hreset_excp_prefix = 0x00000000UL;
2774 env->ivor_mask = 0x0000FFF0UL;
2775 env->ivpr_mask = 0xFFFF0000UL;
2776 /* Hardware reset vector */
2777 env->hreset_vector = 0xFFFFFFFCUL;
2778 #endif
2779 }
2780
2781 static void init_excp_G2 (CPUPPCState *env)
2782 {
2783 #if !defined(CONFIG_USER_ONLY)
2784 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2785 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2786 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2787 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2788 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2789 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2790 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2791 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2792 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2793 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2794 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2795 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2796 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2797 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2798 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2799 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2800 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2801 env->hreset_excp_prefix = 0x00000000UL;
2802 /* Hardware reset vector */
2803 env->hreset_vector = 0xFFFFFFFCUL;
2804 #endif
2805 }
2806
2807 static void init_excp_e200 (CPUPPCState *env)
2808 {
2809 #if !defined(CONFIG_USER_ONLY)
2810 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2811 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2812 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2813 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2814 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2815 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2816 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2817 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2818 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2819 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2820 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2821 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2822 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2823 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2824 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2825 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2826 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2827 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2828 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2829 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2830 env->hreset_excp_prefix = 0x00000000UL;
2831 env->ivor_mask = 0x0000FFF7UL;
2832 env->ivpr_mask = 0xFFFF0000UL;
2833 /* Hardware reset vector */
2834 env->hreset_vector = 0xFFFFFFFCUL;
2835 #endif
2836 }
2837
2838 static void init_excp_BookE (CPUPPCState *env)
2839 {
2840 #if !defined(CONFIG_USER_ONLY)
2841 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2842 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2843 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2844 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2845 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2846 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2847 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2848 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2849 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2850 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2851 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2852 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2853 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2854 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2855 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2856 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2857 env->hreset_excp_prefix = 0x00000000UL;
2858 env->ivor_mask = 0x0000FFE0UL;
2859 env->ivpr_mask = 0xFFFF0000UL;
2860 /* Hardware reset vector */
2861 env->hreset_vector = 0xFFFFFFFCUL;
2862 #endif
2863 }
2864
2865 static void init_excp_601 (CPUPPCState *env)
2866 {
2867 #if !defined(CONFIG_USER_ONLY)
2868 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2869 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2870 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2871 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2872 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2873 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2874 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2875 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2876 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2877 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2878 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2879 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2880 env->hreset_excp_prefix = 0xFFF00000UL;
2881 /* Hardware reset vector */
2882 env->hreset_vector = 0x00000100UL;
2883 #endif
2884 }
2885
2886 static void init_excp_602 (CPUPPCState *env)
2887 {
2888 #if !defined(CONFIG_USER_ONLY)
2889 /* XXX: exception prefix has a special behavior on 602 */
2890 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2891 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2892 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2893 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2894 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2895 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2896 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2897 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2898 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2899 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2900 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2901 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2902 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2903 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2904 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2905 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2906 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2907 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2908 env->hreset_excp_prefix = 0xFFF00000UL;
2909 /* Hardware reset vector */
2910 env->hreset_vector = 0xFFFFFFFCUL;
2911 #endif
2912 }
2913
2914 static void init_excp_603 (CPUPPCState *env)
2915 {
2916 #if !defined(CONFIG_USER_ONLY)
2917 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2918 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2919 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2920 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2921 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2922 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2923 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2924 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2925 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2926 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2927 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2928 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2929 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2930 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2931 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2932 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2933 env->hreset_excp_prefix = 0x00000000UL;
2934 /* Hardware reset vector */
2935 env->hreset_vector = 0xFFFFFFFCUL;
2936 #endif
2937 }
2938
2939 static void init_excp_604 (CPUPPCState *env)
2940 {
2941 #if !defined(CONFIG_USER_ONLY)
2942 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2943 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2944 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2945 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2946 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2947 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2948 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2949 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2950 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2951 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2952 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2953 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2954 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2955 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2956 env->hreset_excp_prefix = 0xFFF00000UL;
2957 /* Hardware reset vector */
2958 env->hreset_vector = 0x00000100UL;
2959 #endif
2960 }
2961
2962 #if defined(TARGET_PPC64)
2963 static void init_excp_620 (CPUPPCState *env)
2964 {
2965 #if !defined(CONFIG_USER_ONLY)
2966 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2967 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2968 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2969 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2970 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2971 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2972 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2973 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2974 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2975 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2976 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2977 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2978 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2979 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2980 env->hreset_excp_prefix = 0xFFF00000UL;
2981 /* Hardware reset vector */
2982 env->hreset_vector = 0x0000000000000100ULL;
2983 #endif
2984 }
2985 #endif /* defined(TARGET_PPC64) */
2986
2987 static void init_excp_7x0 (CPUPPCState *env)
2988 {
2989 #if !defined(CONFIG_USER_ONLY)
2990 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2991 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2992 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2993 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2994 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2995 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2996 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2997 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2998 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2999 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3000 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3001 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3002 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3003 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3004 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3005 env->hreset_excp_prefix = 0x00000000UL;
3006 /* Hardware reset vector */
3007 env->hreset_vector = 0xFFFFFFFCUL;
3008 #endif
3009 }
3010
3011 static void init_excp_750cl (CPUPPCState *env)
3012 {
3013 #if !defined(CONFIG_USER_ONLY)
3014 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3015 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3016 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3017 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3018 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3019 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3020 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3021 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3022 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3023 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3024 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3025 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3026 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3027 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3028 env->hreset_excp_prefix = 0x00000000UL;
3029 /* Hardware reset vector */
3030 env->hreset_vector = 0xFFFFFFFCUL;
3031 #endif
3032 }
3033
3034 static void init_excp_750cx (CPUPPCState *env)
3035 {
3036 #if !defined(CONFIG_USER_ONLY)
3037 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3038 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3039 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3040 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3041 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3042 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3043 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3044 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3045 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3046 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3047 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3048 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3049 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3050 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3051 env->hreset_excp_prefix = 0x00000000UL;
3052 /* Hardware reset vector */
3053 env->hreset_vector = 0xFFFFFFFCUL;
3054 #endif
3055 }
3056
3057 /* XXX: Check if this is correct */
3058 static void init_excp_7x5 (CPUPPCState *env)
3059 {
3060 #if !defined(CONFIG_USER_ONLY)
3061 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3062 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3063 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3064 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3065 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3066 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3067 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3068 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3069 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3070 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3071 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3072 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3073 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3074 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3075 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3076 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3077 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3078 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3079 env->hreset_excp_prefix = 0x00000000UL;
3080 /* Hardware reset vector */
3081 env->hreset_vector = 0xFFFFFFFCUL;
3082 #endif
3083 }
3084
3085 static void init_excp_7400 (CPUPPCState *env)
3086 {
3087 #if !defined(CONFIG_USER_ONLY)
3088 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3089 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3090 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3091 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3092 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3093 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3094 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3095 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3096 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3097 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3098 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3099 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3100 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3101 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3102 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3103 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3104 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3105 env->hreset_excp_prefix = 0x00000000UL;
3106 /* Hardware reset vector */
3107 env->hreset_vector = 0xFFFFFFFCUL;
3108 #endif
3109 }
3110
3111 static void init_excp_7450 (CPUPPCState *env)
3112 {
3113 #if !defined(CONFIG_USER_ONLY)
3114 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3115 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3116 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3117 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3118 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3119 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3120 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3121 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3122 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3123 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3124 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3125 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3126 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3127 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3128 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3129 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3130 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3131 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3132 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3133 env->hreset_excp_prefix = 0x00000000UL;
3134 /* Hardware reset vector */
3135 env->hreset_vector = 0xFFFFFFFCUL;
3136 #endif
3137 }
3138
3139 #if defined (TARGET_PPC64)
3140 static void init_excp_970 (CPUPPCState *env)
3141 {
3142 #if !defined(CONFIG_USER_ONLY)
3143 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3144 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3145 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3146 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3147 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3148 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3149 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3150 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3151 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3152 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3153 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3154 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3155 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3156 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3157 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3158 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3159 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3160 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3161 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3162 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3163 env->hreset_excp_prefix = 0x00000000FFF00000ULL;
3164 /* Hardware reset vector */
3165 env->hreset_vector = 0x0000000000000100ULL;
3166 #endif
3167 }
3168
3169 static void init_excp_POWER7 (CPUPPCState *env)
3170 {
3171 #if !defined(CONFIG_USER_ONLY)
3172 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3173 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3174 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3175 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3176 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3177 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3178 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3179 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3180 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3181 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3182 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3183 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3184 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3185 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3186 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3187 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3188 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3189 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3190 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3191 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3192 env->hreset_excp_prefix = 0;
3193 /* Hardware reset vector */
3194 env->hreset_vector = 0x0000000000000100ULL;
3195 #endif
3196 }
3197 #endif
3198
3199 /*****************************************************************************/
3200 /* Power management enable checks */
3201 static int check_pow_none (CPUPPCState *env)
3202 {
3203 return 0;
3204 }
3205
3206 static int check_pow_nocheck (CPUPPCState *env)
3207 {
3208 return 1;
3209 }
3210
3211 static int check_pow_hid0 (CPUPPCState *env)
3212 {
3213 if (env->spr[SPR_HID0] & 0x00E00000)
3214 return 1;
3215
3216 return 0;
3217 }
3218
3219 static int check_pow_hid0_74xx (CPUPPCState *env)
3220 {
3221 if (env->spr[SPR_HID0] & 0x00600000)
3222 return 1;
3223
3224 return 0;
3225 }
3226
3227 /*****************************************************************************/
3228 /* PowerPC implementations definitions */
3229
3230 /* PowerPC 401 */
3231 #define POWERPC_INSNS_401 (PPC_INSNS_BASE | PPC_STRING | \
3232 PPC_WRTEE | PPC_DCR | \
3233 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3234 PPC_CACHE_DCBZ | \
3235 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3236 PPC_4xx_COMMON | PPC_40x_EXCP)
3237 #define POWERPC_INSNS2_401 (PPC_NONE)
3238 #define POWERPC_MSRM_401 (0x00000000000FD201ULL)
3239 #define POWERPC_MMU_401 (POWERPC_MMU_REAL)
3240 #define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
3241 #define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
3242 #define POWERPC_BFDM_401 (bfd_mach_ppc_403)
3243 #define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3244 POWERPC_FLAG_BUS_CLK)
3245 #define check_pow_401 check_pow_nocheck
3246
3247 static void init_proc_401 (CPUPPCState *env)
3248 {
3249 gen_spr_40x(env);
3250 gen_spr_401_403(env);
3251 gen_spr_401(env);
3252 init_excp_4xx_real(env);
3253 env->dcache_line_size = 32;
3254 env->icache_line_size = 32;
3255 /* Allocate hardware IRQ controller */
3256 ppc40x_irq_init(env);
3257
3258 SET_FIT_PERIOD(12, 16, 20, 24);
3259 SET_WDT_PERIOD(16, 20, 24, 28);
3260 }
3261
3262 /* PowerPC 401x2 */
3263 #define POWERPC_INSNS_401x2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3264 PPC_DCR | PPC_WRTEE | \
3265 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3266 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3267 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3268 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3269 PPC_4xx_COMMON | PPC_40x_EXCP)
3270 #define POWERPC_INSNS2_401x2 (PPC_NONE)
3271 #define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
3272 #define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
3273 #define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
3274 #define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
3275 #define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
3276 #define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3277 POWERPC_FLAG_BUS_CLK)
3278 #define check_pow_401x2 check_pow_nocheck
3279
3280 static void init_proc_401x2 (CPUPPCState *env)
3281 {
3282 gen_spr_40x(env);
3283 gen_spr_401_403(env);
3284 gen_spr_401x2(env);
3285 gen_spr_compress(env);
3286 /* Memory management */
3287 #if !defined(CONFIG_USER_ONLY)
3288 env->nb_tlb = 64;
3289 env->nb_ways = 1;
3290 env->id_tlbs = 0;
3291 env->tlb_type = TLB_EMB;
3292 #endif
3293 init_excp_4xx_softmmu(env);
3294 env->dcache_line_size = 32;
3295 env->icache_line_size = 32;
3296 /* Allocate hardware IRQ controller */
3297 ppc40x_irq_init(env);
3298
3299 SET_FIT_PERIOD(12, 16, 20, 24);
3300 SET_WDT_PERIOD(16, 20, 24, 28);
3301 }
3302
3303 /* PowerPC 401x3 */
3304 #define POWERPC_INSNS_401x3 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3305 PPC_DCR | PPC_WRTEE | \
3306 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3307 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3308 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3309 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3310 PPC_4xx_COMMON | PPC_40x_EXCP)
3311 #define POWERPC_INSNS2_401x3 (PPC_NONE)
3312 #define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
3313 #define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
3314 #define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
3315 #define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
3316 #define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
3317 #define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3318 POWERPC_FLAG_BUS_CLK)
3319 #define check_pow_401x3 check_pow_nocheck
3320
3321 __attribute__ (( unused ))
3322 static void init_proc_401x3 (CPUPPCState *env)
3323 {
3324 gen_spr_40x(env);
3325 gen_spr_401_403(env);
3326 gen_spr_401(env);
3327 gen_spr_401x2(env);
3328 gen_spr_compress(env);
3329 init_excp_4xx_softmmu(env);
3330 env->dcache_line_size = 32;
3331 env->icache_line_size = 32;
3332 /* Allocate hardware IRQ controller */
3333 ppc40x_irq_init(env);
3334
3335 SET_FIT_PERIOD(12, 16, 20, 24);
3336 SET_WDT_PERIOD(16, 20, 24, 28);
3337 }
3338
3339 /* IOP480 */
3340 #define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING | \
3341 PPC_DCR | PPC_WRTEE | \
3342 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3343 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3344 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3345 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3346 PPC_4xx_COMMON | PPC_40x_EXCP)
3347 #define POWERPC_INSNS2_IOP480 (PPC_NONE)
3348 #define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
3349 #define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
3350 #define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
3351 #define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
3352 #define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
3353 #define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3354 POWERPC_FLAG_BUS_CLK)
3355 #define check_pow_IOP480 check_pow_nocheck
3356
3357 static void init_proc_IOP480 (CPUPPCState *env)
3358 {
3359 gen_spr_40x(env);
3360 gen_spr_401_403(env);
3361 gen_spr_401x2(env);
3362 gen_spr_compress(env);
3363 /* Memory management */
3364 #if !defined(CONFIG_USER_ONLY)
3365 env->nb_tlb = 64;
3366 env->nb_ways = 1;
3367 env->id_tlbs = 0;
3368 env->tlb_type = TLB_EMB;
3369 #endif
3370 init_excp_4xx_softmmu(env);
3371 env->dcache_line_size = 32;
3372 env->icache_line_size = 32;
3373 /* Allocate hardware IRQ controller */
3374 ppc40x_irq_init(env);
3375
3376 SET_FIT_PERIOD(8, 12, 16, 20);
3377 SET_WDT_PERIOD(16, 20, 24, 28);
3378 }
3379
3380 /* PowerPC 403 */
3381 #define POWERPC_INSNS_403 (PPC_INSNS_BASE | PPC_STRING | \
3382 PPC_DCR | PPC_WRTEE | \
3383 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3384 PPC_CACHE_DCBZ | \
3385 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3386 PPC_4xx_COMMON | PPC_40x_EXCP)
3387 #define POWERPC_INSNS2_403 (PPC_NONE)
3388 #define POWERPC_MSRM_403 (0x000000000007D00DULL)
3389 #define POWERPC_MMU_403 (POWERPC_MMU_REAL)
3390 #define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
3391 #define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
3392 #define POWERPC_BFDM_403 (bfd_mach_ppc_403)
3393 #define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3394 POWERPC_FLAG_BUS_CLK)
3395 #define check_pow_403 check_pow_nocheck
3396
3397 static void init_proc_403 (CPUPPCState *env)
3398 {
3399 gen_spr_40x(env);
3400 gen_spr_401_403(env);
3401 gen_spr_403(env);
3402 gen_spr_403_real(env);
3403 init_excp_4xx_real(env);
3404 env->dcache_line_size = 32;
3405 env->icache_line_size = 32;
3406 /* Allocate hardware IRQ controller */
3407 ppc40x_irq_init(env);
3408
3409 SET_FIT_PERIOD(8, 12, 16, 20);
3410 SET_WDT_PERIOD(16, 20, 24, 28);
3411 }
3412
3413 /* PowerPC 403 GCX */
3414 #define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING | \
3415 PPC_DCR | PPC_WRTEE | \
3416 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3417 PPC_CACHE_DCBZ | \
3418 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3419 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3420 PPC_4xx_COMMON | PPC_40x_EXCP)
3421 #define POWERPC_INSNS2_403GCX (PPC_NONE)
3422 #define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
3423 #define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
3424 #define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
3425 #define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
3426 #define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
3427 #define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3428 POWERPC_FLAG_BUS_CLK)
3429 #define check_pow_403GCX check_pow_nocheck
3430
3431 static void init_proc_403GCX (CPUPPCState *env)
3432 {
3433 gen_spr_40x(env);
3434 gen_spr_401_403(env);
3435 gen_spr_403(env);
3436 gen_spr_403_real(env);
3437 gen_spr_403_mmu(env);
3438 /* Bus access control */
3439 /* not emulated, as QEMU never does speculative access */
3440 spr_register(env, SPR_40x_SGR, "SGR",
3441 SPR_NOACCESS, SPR_NOACCESS,
3442 &spr_read_generic, &spr_write_generic,
3443 0xFFFFFFFF);
3444 /* not emulated, as QEMU do not emulate caches */
3445 spr_register(env, SPR_40x_DCWR, "DCWR",
3446 SPR_NOACCESS, SPR_NOACCESS,
3447 &spr_read_generic, &spr_write_generic,
3448 0x00000000);
3449 /* Memory management */
3450 #if !defined(CONFIG_USER_ONLY)
3451 env->nb_tlb = 64;
3452 env->nb_ways = 1;
3453 env->id_tlbs = 0;
3454 env->tlb_type = TLB_EMB;
3455 #endif
3456 init_excp_4xx_softmmu(env);
3457 env->dcache_line_size = 32;
3458 env->icache_line_size = 32;
3459 /* Allocate hardware IRQ controller */
3460 ppc40x_irq_init(env);
3461
3462 SET_FIT_PERIOD(8, 12, 16, 20);
3463 SET_WDT_PERIOD(16, 20, 24, 28);
3464 }
3465
3466 /* PowerPC 405 */
3467 #define POWERPC_INSNS_405 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3468 PPC_DCR | PPC_WRTEE | \
3469 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3470 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3471 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3472 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3473 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
3474 #define POWERPC_INSNS2_405 (PPC_NONE)
3475 #define POWERPC_MSRM_405 (0x000000000006E630ULL)
3476 #define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
3477 #define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
3478 #define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
3479 #define POWERPC_BFDM_405 (bfd_mach_ppc_403)
3480 #define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3481 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3482 #define check_pow_405 check_pow_nocheck
3483
3484 static void init_proc_405 (CPUPPCState *env)
3485 {
3486 /* Time base */
3487 gen_tbl(env);
3488 gen_spr_40x(env);
3489 gen_spr_405(env);
3490 /* Bus access control */
3491 /* not emulated, as QEMU never does speculative access */
3492 spr_register(env, SPR_40x_SGR, "SGR",
3493 SPR_NOACCESS, SPR_NOACCESS,
3494 &spr_read_generic, &spr_write_generic,
3495 0xFFFFFFFF);
3496 /* not emulated, as QEMU do not emulate caches */
3497 spr_register(env, SPR_40x_DCWR, "DCWR",
3498 SPR_NOACCESS, SPR_NOACCESS,
3499 &spr_read_generic, &spr_write_generic,
3500 0x00000000);
3501 /* Memory management */
3502 #if !defined(CONFIG_USER_ONLY)
3503 env->nb_tlb = 64;
3504 env->nb_ways = 1;
3505 env->id_tlbs = 0;
3506 env->tlb_type = TLB_EMB;
3507 #endif
3508 init_excp_4xx_softmmu(env);
3509 env->dcache_line_size = 32;
3510 env->icache_line_size = 32;
3511 /* Allocate hardware IRQ controller */
3512 ppc40x_irq_init(env);
3513
3514 SET_FIT_PERIOD(8, 12, 16, 20);
3515 SET_WDT_PERIOD(16, 20, 24, 28);
3516 }
3517
3518 /* PowerPC 440 EP */
3519 #define POWERPC_INSNS_440EP (PPC_INSNS_BASE | PPC_STRING | \
3520 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
3521 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
3522 PPC_FLOAT_STFIWX | \
3523 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3524 PPC_CACHE | PPC_CACHE_ICBI | \
3525 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3526 PPC_MEM_TLBSYNC | PPC_MFTB | \
3527 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3528 PPC_440_SPEC)
3529 #define POWERPC_INSNS2_440EP (PPC_NONE)
3530 #define POWERPC_MSRM_440EP (0x000000000006FF30ULL)
3531 #define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
3532 #define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
3533 #define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
3534 #define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
3535 #define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3536 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3537 #define check_pow_440EP check_pow_nocheck
3538
3539 static void init_proc_440EP (CPUPPCState *env)
3540 {
3541 /* Time base */
3542 gen_tbl(env);
3543 gen_spr_BookE(env, 0x000000000000FFFFULL);
3544 gen_spr_440(env);
3545 gen_spr_usprgh(env);
3546 /* Processor identification */
3547 spr_register(env, SPR_BOOKE_PIR, "PIR",
3548 SPR_NOACCESS, SPR_NOACCESS,
3549 &spr_read_generic, &spr_write_pir,
3550 0x00000000);
3551 /* XXX : not implemented */
3552 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3553 SPR_NOACCESS, SPR_NOACCESS,
3554 &spr_read_generic, &spr_write_generic,
3555 0x00000000);
3556 /* XXX : not implemented */
3557 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3558 SPR_NOACCESS, SPR_NOACCESS,
3559 &spr_read_generic, &spr_write_generic,
3560 0x00000000);
3561 /* XXX : not implemented */
3562 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3563 SPR_NOACCESS, SPR_NOACCESS,
3564 &spr_read_generic, &spr_write_generic,
3565 0x00000000);
3566 /* XXX : not implemented */
3567 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3568 SPR_NOACCESS, SPR_NOACCESS,
3569 &spr_read_generic, &spr_write_generic,
3570 0x00000000);
3571 /* XXX : not implemented */
3572 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3573 SPR_NOACCESS, SPR_NOACCESS,
3574 &spr_read_generic, &spr_write_generic,
3575 0x00000000);
3576 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3577 SPR_NOACCESS, SPR_NOACCESS,
3578 &spr_read_generic, &spr_write_generic,
3579 0x00000000);
3580 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3581 SPR_NOACCESS, SPR_NOACCESS,
3582 &spr_read_generic, &spr_write_generic,
3583 0x00000000);
3584 /* XXX : not implemented */
3585 spr_register(env, SPR_440_CCR1, "CCR1",
3586 SPR_NOACCESS, SPR_NOACCESS,
3587 &spr_read_generic, &spr_write_generic,
3588 0x00000000);
3589 /* Memory management */
3590 #if !defined(CONFIG_USER_ONLY)
3591 env->nb_tlb = 64;
3592 env->nb_ways = 1;
3593 env->id_tlbs = 0;
3594 env->tlb_type = TLB_EMB;
3595 #endif
3596 init_excp_BookE(env);
3597 env->dcache_line_size = 32;
3598 env->icache_line_size = 32;
3599 ppc40x_irq_init(env);
3600
3601 SET_FIT_PERIOD(12, 16, 20, 24);
3602 SET_WDT_PERIOD(20, 24, 28, 32);
3603 }
3604
3605 /* PowerPC 440 GP */
3606 #define POWERPC_INSNS_440GP (PPC_INSNS_BASE | PPC_STRING | \
3607 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | \
3608 PPC_CACHE | PPC_CACHE_ICBI | \
3609 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3610 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | \
3611 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3612 PPC_440_SPEC)
3613 #define POWERPC_INSNS2_440GP (PPC_NONE)
3614 #define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
3615 #define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
3616 #define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
3617 #define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
3618 #define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
3619 #define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3620 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3621 #define check_pow_440GP check_pow_nocheck
3622
3623 __attribute__ (( unused ))
3624 static void init_proc_440GP (CPUPPCState *env)
3625 {
3626 /* Time base */
3627 gen_tbl(env);
3628 gen_spr_BookE(env, 0x000000000000FFFFULL);
3629 gen_spr_440(env);
3630 gen_spr_usprgh(env);
3631 /* Processor identification */
3632 spr_register(env, SPR_BOOKE_PIR, "PIR",
3633 SPR_NOACCESS, SPR_NOACCESS,
3634 &spr_read_generic, &spr_write_pir,
3635 0x00000000);
3636 /* XXX : not implemented */
3637 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3638 SPR_NOACCESS, SPR_NOACCESS,
3639 &spr_read_generic, &spr_write_generic,
3640 0x00000000);
3641 /* XXX : not implemented */
3642 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3643 SPR_NOACCESS, SPR_NOACCESS,
3644 &spr_read_generic, &spr_write_generic,
3645 0x00000000);
3646 /* XXX : not implemented */
3647 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3648 SPR_NOACCESS, SPR_NOACCESS,
3649 &spr_read_generic, &spr_write_generic,
3650 0x00000000);
3651 /* XXX : not implemented */
3652 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3653 SPR_NOACCESS, SPR_NOACCESS,
3654 &spr_read_generic, &spr_write_generic,
3655 0x00000000);
3656 /* Memory management */
3657 #if !defined(CONFIG_USER_ONLY)
3658 env->nb_tlb = 64;
3659 env->nb_ways = 1;
3660 env->id_tlbs = 0;
3661 env->tlb_type = TLB_EMB;
3662 #endif
3663 init_excp_BookE(env);
3664 env->dcache_line_size = 32;
3665 env->icache_line_size = 32;
3666 /* XXX: TODO: allocate internal IRQ controller */
3667
3668 SET_FIT_PERIOD(12, 16, 20, 24);
3669 SET_WDT_PERIOD(20, 24, 28, 32);
3670 }
3671
3672 /* PowerPC 440x4 */
3673 #define POWERPC_INSNS_440x4 (PPC_INSNS_BASE | PPC_STRING | \
3674 PPC_DCR | PPC_WRTEE | \
3675 PPC_CACHE | PPC_CACHE_ICBI | \
3676 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3677 PPC_MEM_TLBSYNC | PPC_MFTB | \
3678 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3679 PPC_440_SPEC)
3680 #define POWERPC_INSNS2_440x4 (PPC_NONE)
3681 #define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
3682 #define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
3683 #define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
3684 #define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
3685 #define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
3686 #define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3687 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3688 #define check_pow_440x4 check_pow_nocheck
3689
3690 __attribute__ (( unused ))
3691 static void init_proc_440x4 (CPUPPCState *env)
3692 {
3693 /* Time base */
3694 gen_tbl(env);
3695 gen_spr_BookE(env, 0x000000000000FFFFULL);
3696 gen_spr_440(env);
3697 gen_spr_usprgh(env);
3698 /* Processor identification */
3699 spr_register(env, SPR_BOOKE_PIR, "PIR",
3700 SPR_NOACCESS, SPR_NOACCESS,
3701 &spr_read_generic, &spr_write_pir,
3702 0x00000000);
3703 /* XXX : not implemented */
3704 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3705 SPR_NOACCESS, SPR_NOACCESS,
3706 &spr_read_generic, &spr_write_generic,
3707 0x00000000);
3708 /* XXX : not implemented */
3709 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3710 SPR_NOACCESS, SPR_NOACCESS,
3711 &spr_read_generic, &spr_write_generic,
3712 0x00000000);
3713 /* XXX : not implemented */
3714 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3715 SPR_NOACCESS, SPR_NOACCESS,
3716 &spr_read_generic, &spr_write_generic,
3717 0x00000000);
3718 /* XXX : not implemented */
3719 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3720 SPR_NOACCESS, SPR_NOACCESS,
3721 &spr_read_generic, &spr_write_generic,
3722 0x00000000);
3723 /* Memory management */
3724 #if !defined(CONFIG_USER_ONLY)
3725 env->nb_tlb = 64;
3726 env->nb_ways = 1;
3727 env->id_tlbs = 0;
3728 env->tlb_type = TLB_EMB;
3729 #endif
3730 init_excp_BookE(env);
3731 env->dcache_line_size = 32;
3732 env->icache_line_size = 32;
3733 /* XXX: TODO: allocate internal IRQ controller */
3734
3735 SET_FIT_PERIOD(12, 16, 20, 24);
3736 SET_WDT_PERIOD(20, 24, 28, 32);
3737 }
3738
3739 /* PowerPC 440x5 */
3740 #define POWERPC_INSNS_440x5 (PPC_INSNS_BASE | PPC_STRING | \
3741 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3742 PPC_CACHE | PPC_CACHE_ICBI | \
3743 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3744 PPC_MEM_TLBSYNC | PPC_MFTB | \
3745 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3746 PPC_440_SPEC)
3747 #define POWERPC_INSNS2_440x5 (PPC_NONE)
3748 #define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
3749 #define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
3750 #define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
3751 #define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
3752 #define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
3753 #define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3754 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3755 #define check_pow_440x5 check_pow_nocheck
3756
3757 static void init_proc_440x5 (CPUPPCState *env)
3758 {
3759 /* Time base */
3760 gen_tbl(env);
3761 gen_spr_BookE(env, 0x000000000000FFFFULL);
3762 gen_spr_440(env);
3763 gen_spr_usprgh(env);
3764 /* Processor identification */
3765 spr_register(env, SPR_BOOKE_PIR, "PIR",
3766 SPR_NOACCESS, SPR_NOACCESS,
3767 &spr_read_generic, &spr_write_pir,
3768 0x00000000);
3769 /* XXX : not implemented */
3770 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3771 SPR_NOACCESS, SPR_NOACCESS,
3772 &spr_read_generic, &spr_write_generic,
3773 0x00000000);
3774 /* XXX : not implemented */
3775 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3776 SPR_NOACCESS, SPR_NOACCESS,
3777 &spr_read_generic, &spr_write_generic,
3778 0x00000000);
3779 /* XXX : not implemented */
3780 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3781 SPR_NOACCESS, SPR_NOACCESS,
3782 &spr_read_generic, &spr_write_generic,
3783 0x00000000);
3784 /* XXX : not implemented */
3785 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3786 SPR_NOACCESS, SPR_NOACCESS,
3787 &spr_read_generic, &spr_write_generic,
3788 0x00000000);
3789 /* XXX : not implemented */
3790 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3791 SPR_NOACCESS, SPR_NOACCESS,
3792 &spr_read_generic, &spr_write_generic,
3793 0x00000000);
3794 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3795 SPR_NOACCESS, SPR_NOACCESS,
3796 &spr_read_generic, &spr_write_generic,
3797 0x00000000);
3798 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3799 SPR_NOACCESS, SPR_NOACCESS,
3800 &spr_read_generic, &spr_write_generic,
3801 0x00000000);
3802 /* XXX : not implemented */
3803 spr_register(env, SPR_440_CCR1, "CCR1",
3804 SPR_NOACCESS, SPR_NOACCESS,
3805 &spr_read_generic, &spr_write_generic,
3806 0x00000000);
3807 /* Memory management */
3808 #if !defined(CONFIG_USER_ONLY)
3809 env->nb_tlb = 64;
3810 env->nb_ways = 1;
3811 env->id_tlbs = 0;
3812 env->tlb_type = TLB_EMB;
3813 #endif
3814 init_excp_BookE(env);
3815 env->dcache_line_size = 32;
3816 env->icache_line_size = 32;
3817 ppc40x_irq_init(env);
3818
3819 SET_FIT_PERIOD(12, 16, 20, 24);
3820 SET_WDT_PERIOD(20, 24, 28, 32);
3821 }
3822
3823 /* PowerPC 460 (guessed) */
3824 #define POWERPC_INSNS_460 (PPC_INSNS_BASE | PPC_STRING | \
3825 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3826 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB | \
3827 PPC_CACHE | PPC_CACHE_ICBI | \
3828 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3829 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3830 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3831 PPC_440_SPEC)
3832 #define POWERPC_INSNS2_460 (PPC_NONE)
3833 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3834 #define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3835 #define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
3836 #define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
3837 #define POWERPC_BFDM_460 (bfd_mach_ppc_403)
3838 #define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3839 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3840 #define check_pow_460 check_pow_nocheck
3841
3842 __attribute__ (( unused ))
3843 static void init_proc_460 (CPUPPCState *env)
3844 {
3845 /* Time base */
3846 gen_tbl(env);
3847 gen_spr_BookE(env, 0x000000000000FFFFULL);
3848 gen_spr_440(env);
3849 gen_spr_usprgh(env);
3850 /* Processor identification */
3851 spr_register(env, SPR_BOOKE_PIR, "PIR",
3852 SPR_NOACCESS, SPR_NOACCESS,
3853 &spr_read_generic, &spr_write_pir,
3854 0x00000000);
3855 /* XXX : not implemented */
3856 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3857 SPR_NOACCESS, SPR_NOACCESS,
3858 &spr_read_generic, &spr_write_generic,
3859 0x00000000);
3860 /* XXX : not implemented */
3861 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3862 SPR_NOACCESS, SPR_NOACCESS,
3863 &spr_read_generic, &spr_write_generic,
3864 0x00000000);
3865 /* XXX : not implemented */
3866 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3867 SPR_NOACCESS, SPR_NOACCESS,
3868 &spr_read_generic, &spr_write_generic,
3869 0x00000000);
3870 /* XXX : not implemented */
3871 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3872 SPR_NOACCESS, SPR_NOACCESS,
3873 &spr_read_generic, &spr_write_generic,
3874 0x00000000);
3875 /* XXX : not implemented */
3876 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3877 SPR_NOACCESS, SPR_NOACCESS,
3878 &spr_read_generic, &spr_write_generic,
3879 0x00000000);
3880 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3881 SPR_NOACCESS, SPR_NOACCESS,
3882 &spr_read_generic, &spr_write_generic,
3883 0x00000000);
3884 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3885 SPR_NOACCESS, SPR_NOACCESS,
3886 &spr_read_generic, &spr_write_generic,
3887 0x00000000);
3888 /* XXX : not implemented */
3889 spr_register(env, SPR_440_CCR1, "CCR1",
3890 SPR_NOACCESS, SPR_NOACCESS,
3891 &spr_read_generic, &spr_write_generic,
3892 0x00000000);
3893 /* XXX : not implemented */
3894 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3895 &spr_read_generic, &spr_write_generic,
3896 &spr_read_generic, &spr_write_generic,
3897 0x00000000);
3898 /* Memory management */
3899 #if !defined(CONFIG_USER_ONLY)
3900 env->nb_tlb = 64;
3901 env->nb_ways = 1;
3902 env->id_tlbs = 0;
3903 env->tlb_type = TLB_EMB;
3904 #endif
3905 init_excp_BookE(env);
3906 env->dcache_line_size = 32;
3907 env->icache_line_size = 32;
3908 /* XXX: TODO: allocate internal IRQ controller */
3909
3910 SET_FIT_PERIOD(12, 16, 20, 24);
3911 SET_WDT_PERIOD(20, 24, 28, 32);
3912 }
3913
3914 /* PowerPC 460F (guessed) */
3915 #define POWERPC_INSNS_460F (PPC_INSNS_BASE | PPC_STRING | \
3916 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
3917 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
3918 PPC_FLOAT_STFIWX | PPC_MFTB | \
3919 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3920 PPC_WRTEE | PPC_MFAPIDI | \
3921 PPC_CACHE | PPC_CACHE_ICBI | \
3922 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3923 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3924 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3925 PPC_440_SPEC)
3926 #define POWERPC_INSNS2_460F (PPC_NONE)
3927 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3928 #define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3929 #define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3930 #define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
3931 #define POWERPC_BFDM_460F (bfd_mach_ppc_403)
3932 #define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3933 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3934 #define check_pow_460F check_pow_nocheck
3935
3936 __attribute__ (( unused ))
3937 static void init_proc_460F (CPUPPCState *env)
3938 {
3939 /* Time base */
3940 gen_tbl(env);
3941 gen_spr_BookE(env, 0x000000000000FFFFULL);
3942 gen_spr_440(env);
3943 gen_spr_usprgh(env);
3944 /* Processor identification */
3945 spr_register(env, SPR_BOOKE_PIR, "PIR",
3946 SPR_NOACCESS, SPR_NOACCESS,
3947 &spr_read_generic, &spr_write_pir,
3948 0x00000000);
3949 /* XXX : not implemented */
3950 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3951 SPR_NOACCESS, SPR_NOACCESS,
3952 &spr_read_generic, &spr_write_generic,
3953 0x00000000);
3954 /* XXX : not implemented */
3955 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3956 SPR_NOACCESS, SPR_NOACCESS,
3957 &spr_read_generic, &spr_write_generic,
3958 0x00000000);
3959 /* XXX : not implemented */
3960 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3961 SPR_NOACCESS, SPR_NOACCESS,
3962 &spr_read_generic, &spr_write_generic,
3963 0x00000000);
3964 /* XXX : not implemented */
3965 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3966 SPR_NOACCESS, SPR_NOACCESS,
3967 &spr_read_generic, &spr_write_generic,
3968 0x00000000);
3969 /* XXX : not implemented */
3970 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3971 SPR_NOACCESS, SPR_NOACCESS,
3972 &spr_read_generic, &spr_write_generic,
3973 0x00000000);
3974 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3975 SPR_NOACCESS, SPR_NOACCESS,
3976 &spr_read_generic, &spr_write_generic,
3977 0x00000000);
3978 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3979 SPR_NOACCESS, SPR_NOACCESS,
3980 &spr_read_generic, &spr_write_generic,
3981 0x00000000);
3982 /* XXX : not implemented */
3983 spr_register(env, SPR_440_CCR1, "CCR1",
3984 SPR_NOACCESS, SPR_NOACCESS,
3985 &spr_read_generic, &spr_write_generic,
3986 0x00000000);
3987 /* XXX : not implemented */
3988 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3989 &spr_read_generic, &spr_write_generic,
3990 &spr_read_generic, &spr_write_generic,
3991 0x00000000);
3992 /* Memory management */
3993 #if !defined(CONFIG_USER_ONLY)
3994 env->nb_tlb = 64;
3995 env->nb_ways = 1;
3996 env->id_tlbs = 0;
3997 env->tlb_type = TLB_EMB;
3998 #endif
3999 init_excp_BookE(env);
4000 env->dcache_line_size = 32;
4001 env->icache_line_size = 32;
4002 /* XXX: TODO: allocate internal IRQ controller */
4003
4004 SET_FIT_PERIOD(12, 16, 20, 24);
4005 SET_WDT_PERIOD(20, 24, 28, 32);
4006 }
4007
4008 /* Freescale 5xx cores (aka RCPU) */
4009 #define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING | \
4010 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
4011 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
4012 PPC_MFTB)
4013 #define POWERPC_INSNS2_MPC5xx (PPC_NONE)
4014 #define POWERPC_MSRM_MPC5xx (0x000000000001FF43ULL)
4015 #define POWERPC_MMU_MPC5xx (POWERPC_MMU_REAL)
4016 #define POWERPC_EXCP_MPC5xx (POWERPC_EXCP_603)
4017 #define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
4018 #define POWERPC_BFDM_MPC5xx (bfd_mach_ppc_505)
4019 #define POWERPC_FLAG_MPC5xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4020 POWERPC_FLAG_BUS_CLK)
4021 #define check_pow_MPC5xx check_pow_none
4022
4023 __attribute__ (( unused ))
4024 static void init_proc_MPC5xx (CPUPPCState *env)
4025 {
4026 /* Time base */
4027 gen_tbl(env);
4028 gen_spr_5xx_8xx(env);
4029 gen_spr_5xx(env);
4030 init_excp_MPC5xx(env);
4031 env->dcache_line_size = 32;
4032 env->icache_line_size = 32;
4033 /* XXX: TODO: allocate internal IRQ controller */
4034 }
4035
4036 /* Freescale 8xx cores (aka PowerQUICC) */
4037 #define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING | \
4038 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
4039 PPC_CACHE_ICBI | PPC_MFTB)
4040 #define POWERPC_INSNS2_MPC8xx (PPC_NONE)
4041 #define POWERPC_MSRM_MPC8xx (0x000000000001F673ULL)
4042 #define POWERPC_MMU_MPC8xx (POWERPC_MMU_MPC8xx)
4043 #define POWERPC_EXCP_MPC8xx (POWERPC_EXCP_603)
4044 #define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
4045 #define POWERPC_BFDM_MPC8xx (bfd_mach_ppc_860)
4046 #define POWERPC_FLAG_MPC8xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4047 POWERPC_FLAG_BUS_CLK)
4048 #define check_pow_MPC8xx check_pow_none
4049
4050 __attribute__ (( unused ))
4051 static void init_proc_MPC8xx (CPUPPCState *env)
4052 {
4053 /* Time base */
4054 gen_tbl(env);
4055 gen_spr_5xx_8xx(env);
4056 gen_spr_8xx(env);
4057 init_excp_MPC8xx(env);
4058 env->dcache_line_size = 32;
4059 env->icache_line_size = 32;
4060 /* XXX: TODO: allocate internal IRQ controller */
4061 }
4062
4063 /* Freescale 82xx cores (aka PowerQUICC-II) */
4064 /* PowerPC G2 */
4065 #define POWERPC_INSNS_G2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4066 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4067 PPC_FLOAT_STFIWX | \
4068 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4069 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4070 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4071 PPC_SEGMENT | PPC_EXTERN)
4072 #define POWERPC_INSNS2_G2 (PPC_NONE)
4073 #define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
4074 #define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
4075 //#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
4076 #define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
4077 #define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
4078 #define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4079 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4080 #define check_pow_G2 check_pow_hid0
4081
4082 static void init_proc_G2 (CPUPPCState *env)
4083 {
4084 gen_spr_ne_601(env);
4085 gen_spr_G2_755(env);
4086 gen_spr_G2(env);
4087 /* Time base */
4088 gen_tbl(env);
4089 /* External access control */
4090 /* XXX : not implemented */
4091 spr_register(env, SPR_EAR, "EAR",
4092 SPR_NOACCESS, SPR_NOACCESS,
4093 &spr_read_generic, &spr_write_generic,
4094 0x00000000);
4095 /* Hardware implementation register */
4096 /* XXX : not implemented */
4097 spr_register(env, SPR_HID0, "HID0",
4098 SPR_NOACCESS, SPR_NOACCESS,
4099 &spr_read_generic, &spr_write_generic,
4100 0x00000000);
4101 /* XXX : not implemented */
4102 spr_register(env, SPR_HID1, "HID1",
4103 SPR_NOACCESS, SPR_NOACCESS,
4104 &spr_read_generic, &spr_write_generic,
4105 0x00000000);
4106 /* XXX : not implemented */
4107 spr_register(env, SPR_HID2, "HID2",
4108 SPR_NOACCESS, SPR_NOACCESS,
4109 &spr_read_generic, &spr_write_generic,
4110 0x00000000);
4111 /* Memory management */
4112 gen_low_BATs(env);
4113 gen_high_BATs(env);
4114 gen_6xx_7xx_soft_tlb(env, 64, 2);
4115 init_excp_G2(env);
4116 env->dcache_line_size = 32;
4117 env->icache_line_size = 32;
4118 /* Allocate hardware IRQ controller */
4119 ppc6xx_irq_init(env);
4120 }
4121
4122 /* PowerPC G2LE */
4123 #define POWERPC_INSNS_G2LE (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4124 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4125 PPC_FLOAT_STFIWX | \
4126 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4127 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4128 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4129 PPC_SEGMENT | PPC_EXTERN)
4130 #define POWERPC_INSNS2_G2LE (PPC_NONE)
4131 #define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
4132 #define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
4133 #define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
4134 #define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
4135 #define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
4136 #define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4137 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4138 #define check_pow_G2LE check_pow_hid0
4139
4140 static void init_proc_G2LE (CPUPPCState *env)
4141 {
4142 gen_spr_ne_601(env);
4143 gen_spr_G2_755(env);
4144 gen_spr_G2(env);
4145 /* Time base */
4146 gen_tbl(env);
4147 /* External access control */
4148 /* XXX : not implemented */
4149 spr_register(env, SPR_EAR, "EAR",
4150 SPR_NOACCESS, SPR_NOACCESS,
4151 &spr_read_generic, &spr_write_generic,
4152 0x00000000);
4153 /* Hardware implementation register */
4154 /* XXX : not implemented */
4155 spr_register(env, SPR_HID0, "HID0",
4156 SPR_NOACCESS, SPR_NOACCESS,
4157 &spr_read_generic, &spr_write_generic,
4158 0x00000000);
4159 /* XXX : not implemented */
4160 spr_register(env, SPR_HID1, "HID1",
4161 SPR_NOACCESS, SPR_NOACCESS,
4162 &spr_read_generic, &spr_write_generic,
4163 0x00000000);
4164 /* XXX : not implemented */
4165 spr_register(env, SPR_HID2, "HID2",
4166 SPR_NOACCESS, SPR_NOACCESS,
4167 &spr_read_generic, &spr_write_generic,
4168 0x00000000);
4169 /* Memory management */
4170 gen_low_BATs(env);
4171 gen_high_BATs(env);
4172 gen_6xx_7xx_soft_tlb(env, 64, 2);
4173 init_excp_G2(env);
4174 env->dcache_line_size = 32;
4175 env->icache_line_size = 32;
4176 /* Allocate hardware IRQ controller */
4177 ppc6xx_irq_init(env);
4178 }
4179
4180 /* e200 core */
4181 /* XXX: unimplemented instructions:
4182 * dcblc
4183 * dcbtlst
4184 * dcbtstls
4185 * icblc
4186 * icbtls
4187 * tlbivax
4188 * all SPE multiply-accumulate instructions
4189 */
4190 #define POWERPC_INSNS_e200 (PPC_INSNS_BASE | PPC_ISEL | \
4191 PPC_SPE | PPC_SPE_SINGLE | \
4192 PPC_WRTEE | PPC_RFDI | \
4193 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4194 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4195 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
4196 PPC_BOOKE)
4197 #define POWERPC_INSNS2_e200 (PPC_NONE)
4198 #define POWERPC_MSRM_e200 (0x000000000606FF30ULL)
4199 #define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE206)
4200 #define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE)
4201 #define POWERPC_INPUT_e200 (PPC_FLAGS_INPUT_BookE)
4202 #define POWERPC_BFDM_e200 (bfd_mach_ppc_860)
4203 #define POWERPC_FLAG_e200 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4204 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4205 POWERPC_FLAG_BUS_CLK)
4206 #define check_pow_e200 check_pow_hid0
4207
4208 __attribute__ (( unused ))
4209 static void init_proc_e200 (CPUPPCState *env)
4210 {
4211 /* Time base */
4212 gen_tbl(env);
4213 gen_spr_BookE(env, 0x000000070000FFFFULL);
4214 /* XXX : not implemented */
4215 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4216 &spr_read_spefscr, &spr_write_spefscr,
4217 &spr_read_spefscr, &spr_write_spefscr,
4218 0x00000000);
4219 /* Memory management */
4220 gen_spr_BookE206(env, 0x0000005D, NULL);
4221 /* XXX : not implemented */
4222 spr_register(env, SPR_HID0, "HID0",
4223 SPR_NOACCESS, SPR_NOACCESS,
4224 &spr_read_generic, &spr_write_generic,
4225 0x00000000);
4226 /* XXX : not implemented */
4227 spr_register(env, SPR_HID1, "HID1",
4228 SPR_NOACCESS, SPR_NOACCESS,
4229 &spr_read_generic, &spr_write_generic,
4230 0x00000000);
4231 /* XXX : not implemented */
4232 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4233 SPR_NOACCESS, SPR_NOACCESS,
4234 &spr_read_generic, &spr_write_generic,
4235 0x00000000);
4236 /* XXX : not implemented */
4237 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4238 SPR_NOACCESS, SPR_NOACCESS,
4239 &spr_read_generic, &spr_write_generic,
4240 0x00000000);
4241 /* XXX : not implemented */
4242 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4243 SPR_NOACCESS, SPR_NOACCESS,
4244 &spr_read_generic, &spr_write_generic,
4245 0x00000000);
4246 /* XXX : not implemented */
4247 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4248 SPR_NOACCESS, SPR_NOACCESS,
4249 &spr_read_generic, &spr_write_generic,
4250 0x00000000);
4251 /* XXX : not implemented */
4252 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4253 SPR_NOACCESS, SPR_NOACCESS,
4254 &spr_read_generic, &spr_write_generic,
4255 0x00000000);
4256 /* XXX : not implemented */
4257 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4258 SPR_NOACCESS, SPR_NOACCESS,
4259 &spr_read_generic, &spr_write_generic,
4260 0x00000000);
4261 /* XXX : not implemented */
4262 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4263 SPR_NOACCESS, SPR_NOACCESS,
4264 &spr_read_generic, &spr_write_generic,
4265 0x00000000);
4266 /* XXX : not implemented */
4267 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4268 SPR_NOACCESS, SPR_NOACCESS,
4269 &spr_read_generic, &spr_write_generic,
4270 0x00000000);
4271 /* XXX : not implemented */
4272 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4273 SPR_NOACCESS, SPR_NOACCESS,
4274 &spr_read_generic, &spr_write_generic,
4275 0x00000000);
4276 /* XXX : not implemented */
4277 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4278 SPR_NOACCESS, SPR_NOACCESS,
4279 &spr_read_generic, &spr_write_generic,
4280 0x00000000);
4281 /* XXX : not implemented */
4282 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4283 SPR_NOACCESS, SPR_NOACCESS,
4284 &spr_read_generic, &spr_write_generic,
4285 0x00000000);
4286 /* XXX : not implemented */
4287 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4288 SPR_NOACCESS, SPR_NOACCESS,
4289 &spr_read_generic, &spr_write_generic,
4290 0x00000000);
4291 /* XXX : not implemented */
4292 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4293 SPR_NOACCESS, SPR_NOACCESS,
4294 &spr_read_generic, &spr_write_generic,
4295 0x00000000); /* TOFIX */
4296 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4297 SPR_NOACCESS, SPR_NOACCESS,
4298 &spr_read_generic, &spr_write_generic,
4299 0x00000000);
4300 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4301 SPR_NOACCESS, SPR_NOACCESS,
4302 &spr_read_generic, &spr_write_generic,
4303 0x00000000);
4304 #if !defined(CONFIG_USER_ONLY)
4305 env->nb_tlb = 64;
4306 env->nb_ways = 1;
4307 env->id_tlbs = 0;
4308 env->tlb_type = TLB_EMB;
4309 #endif
4310 init_excp_e200(env);
4311 env->dcache_line_size = 32;
4312 env->icache_line_size = 32;
4313 /* XXX: TODO: allocate internal IRQ controller */
4314 }
4315
4316 /* e300 core */
4317 #define POWERPC_INSNS_e300 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4318 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4319 PPC_FLOAT_STFIWX | \
4320 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4321 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4322 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4323 PPC_SEGMENT | PPC_EXTERN)
4324 #define POWERPC_INSNS2_e300 (PPC_NONE)
4325 #define POWERPC_MSRM_e300 (0x000000000007FFF3ULL)
4326 #define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx)
4327 #define POWERPC_EXCP_e300 (POWERPC_EXCP_603)
4328 #define POWERPC_INPUT_e300 (PPC_FLAGS_INPUT_6xx)
4329 #define POWERPC_BFDM_e300 (bfd_mach_ppc_603)
4330 #define POWERPC_FLAG_e300 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4331 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4332 #define check_pow_e300 check_pow_hid0
4333
4334 __attribute__ (( unused ))
4335 static void init_proc_e300 (CPUPPCState *env)
4336 {
4337 gen_spr_ne_601(env);
4338 gen_spr_603(env);
4339 /* Time base */
4340 gen_tbl(env);
4341 /* hardware implementation registers */
4342 /* XXX : not implemented */
4343 spr_register(env, SPR_HID0, "HID0",
4344 SPR_NOACCESS, SPR_NOACCESS,
4345 &spr_read_generic, &spr_write_generic,
4346 0x00000000);
4347 /* XXX : not implemented */
4348 spr_register(env, SPR_HID1, "HID1",
4349 SPR_NOACCESS, SPR_NOACCESS,
4350 &spr_read_generic, &spr_write_generic,
4351 0x00000000);
4352 /* XXX : not implemented */
4353 spr_register(env, SPR_HID2, "HID2",
4354 SPR_NOACCESS, SPR_NOACCESS,
4355 &spr_read_generic, &spr_write_generic,
4356 0x00000000);
4357 /* Memory management */
4358 gen_low_BATs(env);
4359 gen_high_BATs(env);
4360 gen_6xx_7xx_soft_tlb(env, 64, 2);
4361 init_excp_603(env);
4362 env->dcache_line_size = 32;
4363 env->icache_line_size = 32;
4364 /* Allocate hardware IRQ controller */
4365 ppc6xx_irq_init(env);
4366 }
4367
4368 /* e500v1 core */
4369 #define POWERPC_INSNS_e500v1 (PPC_INSNS_BASE | PPC_ISEL | \
4370 PPC_SPE | PPC_SPE_SINGLE | \
4371 PPC_WRTEE | PPC_RFDI | \
4372 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4373 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4374 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC)
4375 #define POWERPC_INSNS2_e500v1 (PPC2_BOOKE206)
4376 #define POWERPC_MSRM_e500v1 (0x000000000606FF30ULL)
4377 #define POWERPC_MMU_e500v1 (POWERPC_MMU_BOOKE206)
4378 #define POWERPC_EXCP_e500v1 (POWERPC_EXCP_BOOKE)
4379 #define POWERPC_INPUT_e500v1 (PPC_FLAGS_INPUT_BookE)
4380 #define POWERPC_BFDM_e500v1 (bfd_mach_ppc_860)
4381 #define POWERPC_FLAG_e500v1 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4382 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4383 POWERPC_FLAG_BUS_CLK)
4384 #define check_pow_e500v1 check_pow_hid0
4385 #define init_proc_e500v1 init_proc_e500v1
4386
4387 /* e500v2 core */
4388 #define POWERPC_INSNS_e500v2 (PPC_INSNS_BASE | PPC_ISEL | \
4389 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | \
4390 PPC_WRTEE | PPC_RFDI | \
4391 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4392 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4393 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC)
4394 #define POWERPC_INSNS2_e500v2 (PPC2_BOOKE206)
4395 #define POWERPC_MSRM_e500v2 (0x000000000606FF30ULL)
4396 #define POWERPC_MMU_e500v2 (POWERPC_MMU_BOOKE206)
4397 #define POWERPC_EXCP_e500v2 (POWERPC_EXCP_BOOKE)
4398 #define POWERPC_INPUT_e500v2 (PPC_FLAGS_INPUT_BookE)
4399 #define POWERPC_BFDM_e500v2 (bfd_mach_ppc_860)
4400 #define POWERPC_FLAG_e500v2 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4401 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4402 POWERPC_FLAG_BUS_CLK)
4403 #define check_pow_e500v2 check_pow_hid0
4404 #define init_proc_e500v2 init_proc_e500v2
4405
4406 /* e500mc core */
4407 #define POWERPC_INSNS_e500mc (PPC_INSNS_BASE | PPC_ISEL | \
4408 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | \
4409 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4410 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4411 PPC_FLOAT | PPC_FLOAT_FRES | \
4412 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \
4413 PPC_FLOAT_STFIWX | PPC_WAIT | \
4414 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC)
4415 #define POWERPC_INSNS2_e500mc (PPC2_BOOKE206 | PPC2_PRCNTL)
4416 #define POWERPC_MSRM_e500mc (0x000000001402FB36ULL)
4417 #define POWERPC_MMU_e500mc (POWERPC_MMU_BOOKE206)
4418 #define POWERPC_EXCP_e500mc (POWERPC_EXCP_BOOKE)
4419 #define POWERPC_INPUT_e500mc (PPC_FLAGS_INPUT_BookE)
4420 /* Fixme: figure out the correct flag for e500mc */
4421 #define POWERPC_BFDM_e500mc (bfd_mach_ppc_e500)
4422 #define POWERPC_FLAG_e500mc (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
4423 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4424 #define check_pow_e500mc check_pow_none
4425 #define init_proc_e500mc init_proc_e500mc
4426
4427 enum fsl_e500_version {
4428 fsl_e500v1,
4429 fsl_e500v2,
4430 fsl_e500mc,
4431 };
4432
4433 static void init_proc_e500 (CPUPPCState *env, int version)
4434 {
4435 uint32_t tlbncfg[2];
4436 uint64_t ivor_mask = 0x0000000F0000FFFFULL;
4437 uint32_t l1cfg0 = 0x3800 /* 8 ways */
4438 | 0x0020; /* 32 kb */
4439 #if !defined(CONFIG_USER_ONLY)
4440 int i;
4441 #endif
4442
4443 /* Time base */
4444 gen_tbl(env);
4445 /*
4446 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4447 * complain when accessing them.
4448 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4449 */
4450 if (version == fsl_e500mc) {
4451 ivor_mask = 0x000003FE0000FFFFULL;
4452 }
4453 gen_spr_BookE(env, ivor_mask);
4454 /* Processor identification */
4455 spr_register(env, SPR_BOOKE_PIR, "PIR",
4456 SPR_NOACCESS, SPR_NOACCESS,
4457 &spr_read_generic, &spr_write_pir,
4458 0x00000000);
4459 /* XXX : not implemented */
4460 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4461 &spr_read_spefscr, &spr_write_spefscr,
4462 &spr_read_spefscr, &spr_write_spefscr,
4463 0x00000000);
4464 #if !defined(CONFIG_USER_ONLY)
4465 /* Memory management */
4466 env->nb_pids = 3;
4467 env->nb_ways = 2;
4468 env->id_tlbs = 0;
4469 switch (version) {
4470 case fsl_e500v1:
4471 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4472 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4473 break;
4474 case fsl_e500v2:
4475 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4476 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4477 break;
4478 case fsl_e500mc:
4479 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4480 tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4481 break;
4482 default:
4483 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4484 }
4485 #endif
4486 /* Cache sizes */
4487 switch (version) {
4488 case fsl_e500v1:
4489 case fsl_e500v2:
4490 env->dcache_line_size = 32;
4491 env->icache_line_size = 32;
4492 break;
4493 case fsl_e500mc:
4494 env->dcache_line_size = 64;
4495 env->icache_line_size = 64;
4496 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
4497 break;
4498 default:
4499 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4500 }
4501 gen_spr_BookE206(env, 0x000000DF, tlbncfg);
4502 /* XXX : not implemented */
4503 spr_register(env, SPR_HID0, "HID0",
4504 SPR_NOACCESS, SPR_NOACCESS,
4505 &spr_read_generic, &spr_write_generic,
4506 0x00000000);
4507 /* XXX : not implemented */
4508 spr_register(env, SPR_HID1, "HID1",
4509 SPR_NOACCESS, SPR_NOACCESS,
4510 &spr_read_generic, &spr_write_generic,
4511 0x00000000);
4512 /* XXX : not implemented */
4513 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4514 SPR_NOACCESS, SPR_NOACCESS,
4515 &spr_read_generic, &spr_write_generic,
4516 0x00000000);
4517 /* XXX : not implemented */
4518 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4519 SPR_NOACCESS, SPR_NOACCESS,
4520 &spr_read_generic, &spr_write_generic,
4521 0x00000000);
4522 /* XXX : not implemented */
4523 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4524 SPR_NOACCESS, SPR_NOACCESS,
4525 &spr_read_generic, &spr_write_generic,
4526 0x00000000);
4527 /* XXX : not implemented */
4528 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4529 SPR_NOACCESS, SPR_NOACCESS,
4530 &spr_read_generic, &spr_write_generic,
4531 0x00000000);
4532 /* XXX : not implemented */
4533 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4534 SPR_NOACCESS, SPR_NOACCESS,
4535 &spr_read_generic, &spr_write_generic,
4536 0x00000000);
4537 /* XXX : not implemented */
4538 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4539 SPR_NOACCESS, SPR_NOACCESS,
4540 &spr_read_generic, &spr_write_generic,
4541 0x00000000);
4542 /* XXX : not implemented */
4543 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4544 SPR_NOACCESS, SPR_NOACCESS,
4545 &spr_read_generic, &spr_write_generic,
4546 l1cfg0);
4547 /* XXX : not implemented */
4548 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4549 SPR_NOACCESS, SPR_NOACCESS,
4550 &spr_read_generic, &spr_write_e500_l1csr0,
4551 0x00000000);
4552 /* XXX : not implemented */
4553 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4554 SPR_NOACCESS, SPR_NOACCESS,
4555 &spr_read_generic, &spr_write_generic,
4556 0x00000000);
4557 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4558 SPR_NOACCESS, SPR_NOACCESS,
4559 &spr_read_generic, &spr_write_generic,
4560 0x00000000);
4561 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4562 SPR_NOACCESS, SPR_NOACCESS,
4563 &spr_read_generic, &spr_write_generic,
4564 0x00000000);
4565 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4566 SPR_NOACCESS, SPR_NOACCESS,
4567 &spr_read_generic, &spr_write_booke206_mmucsr0,
4568 0x00000000);
4569
4570 #if !defined(CONFIG_USER_ONLY)
4571 env->nb_tlb = 0;
4572 env->tlb_type = TLB_MAS;
4573 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4574 env->nb_tlb += booke206_tlb_size(env, i);
4575 }
4576 #endif
4577
4578 init_excp_e200(env);
4579 /* Allocate hardware IRQ controller */
4580 ppce500_irq_init(env);
4581 }
4582
4583 static void init_proc_e500v1(CPUPPCState *env)
4584 {
4585 init_proc_e500(env, fsl_e500v1);
4586 }
4587
4588 static void init_proc_e500v2(CPUPPCState *env)
4589 {
4590 init_proc_e500(env, fsl_e500v2);
4591 }
4592
4593 static void init_proc_e500mc(CPUPPCState *env)
4594 {
4595 init_proc_e500(env, fsl_e500mc);
4596 }
4597
4598 /* Non-embedded PowerPC */
4599
4600 /* POWER : same as 601, without mfmsr, mfsr */
4601 #if defined(TODO)
4602 #define POWERPC_INSNS_POWER (XXX_TODO)
4603 /* POWER RSC (from RAD6000) */
4604 #define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
4605 #endif /* TODO */
4606
4607 /* PowerPC 601 */
4608 #define POWERPC_INSNS_601 (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4609 PPC_FLOAT | \
4610 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4611 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4612 PPC_SEGMENT | PPC_EXTERN)
4613 #define POWERPC_INSNS2_601 (PPC_NONE)
4614 #define POWERPC_MSRM_601 (0x000000000000FD70ULL)
4615 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
4616 //#define POWERPC_MMU_601 (POWERPC_MMU_601)
4617 //#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
4618 #define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
4619 #define POWERPC_BFDM_601 (bfd_mach_ppc_601)
4620 #define POWERPC_FLAG_601 (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4621 #define check_pow_601 check_pow_none
4622
4623 static void init_proc_601 (CPUPPCState *env)
4624 {
4625 gen_spr_ne_601(env);
4626 gen_spr_601(env);
4627 /* Hardware implementation registers */
4628 /* XXX : not implemented */
4629 spr_register(env, SPR_HID0, "HID0",
4630 SPR_NOACCESS, SPR_NOACCESS,
4631 &spr_read_generic, &spr_write_hid0_601,
4632 0x80010080);
4633 /* XXX : not implemented */
4634 spr_register(env, SPR_HID1, "HID1",
4635 SPR_NOACCESS, SPR_NOACCESS,
4636 &spr_read_generic, &spr_write_generic,
4637 0x00000000);
4638 /* XXX : not implemented */
4639 spr_register(env, SPR_601_HID2, "HID2",
4640 SPR_NOACCESS, SPR_NOACCESS,
4641 &spr_read_generic, &spr_write_generic,
4642 0x00000000);
4643 /* XXX : not implemented */
4644 spr_register(env, SPR_601_HID5, "HID5",
4645 SPR_NOACCESS, SPR_NOACCESS,
4646 &spr_read_generic, &spr_write_generic,
4647 0x00000000);
4648 /* Memory management */
4649 init_excp_601(env);
4650 /* XXX: beware that dcache line size is 64
4651 * but dcbz uses 32 bytes "sectors"
4652 * XXX: this breaks clcs instruction !
4653 */
4654 env->dcache_line_size = 32;
4655 env->icache_line_size = 64;
4656 /* Allocate hardware IRQ controller */
4657 ppc6xx_irq_init(env);
4658 }
4659
4660 /* PowerPC 601v */
4661 #define POWERPC_INSNS_601v (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4662 PPC_FLOAT | \
4663 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4664 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4665 PPC_SEGMENT | PPC_EXTERN)
4666 #define POWERPC_INSNS2_601v (PPC_NONE)
4667 #define POWERPC_MSRM_601v (0x000000000000FD70ULL)
4668 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
4669 #define POWERPC_MMU_601v (POWERPC_MMU_601)
4670 #define POWERPC_EXCP_601v (POWERPC_EXCP_601)
4671 #define POWERPC_INPUT_601v (PPC_FLAGS_INPUT_6xx)
4672 #define POWERPC_BFDM_601v (bfd_mach_ppc_601)
4673 #define POWERPC_FLAG_601v (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4674 #define check_pow_601v check_pow_none
4675
4676 static void init_proc_601v (CPUPPCState *env)
4677 {
4678 init_proc_601(env);
4679 /* XXX : not implemented */
4680 spr_register(env, SPR_601_HID15, "HID15",
4681 SPR_NOACCESS, SPR_NOACCESS,
4682 &spr_read_generic, &spr_write_generic,
4683 0x00000000);
4684 }
4685
4686 /* PowerPC 602 */
4687 #define POWERPC_INSNS_602 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4688 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4689 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4690 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4691 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4692 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
4693 PPC_SEGMENT | PPC_602_SPEC)
4694 #define POWERPC_INSNS2_602 (PPC_NONE)
4695 #define POWERPC_MSRM_602 (0x0000000000C7FF73ULL)
4696 /* XXX: 602 MMU is quite specific. Should add a special case */
4697 #define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
4698 //#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
4699 #define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
4700 #define POWERPC_BFDM_602 (bfd_mach_ppc_602)
4701 #define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4702 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4703 #define check_pow_602 check_pow_hid0
4704
4705 static void init_proc_602 (CPUPPCState *env)
4706 {
4707 gen_spr_ne_601(env);
4708 gen_spr_602(env);
4709 /* Time base */
4710 gen_tbl(env);
4711 /* hardware implementation registers */
4712 /* XXX : not implemented */
4713 spr_register(env, SPR_HID0, "HID0",
4714 SPR_NOACCESS, SPR_NOACCESS,
4715 &spr_read_generic, &spr_write_generic,
4716 0x00000000);
4717 /* XXX : not implemented */
4718 spr_register(env, SPR_HID1, "HID1",
4719 SPR_NOACCESS, SPR_NOACCESS,
4720 &spr_read_generic, &spr_write_generic,
4721 0x00000000);
4722 /* Memory management */
4723 gen_low_BATs(env);
4724 gen_6xx_7xx_soft_tlb(env, 64, 2);
4725 init_excp_602(env);
4726 env->dcache_line_size = 32;
4727 env->icache_line_size = 32;
4728 /* Allocate hardware IRQ controller */
4729 ppc6xx_irq_init(env);
4730 }
4731
4732 /* PowerPC 603 */
4733 #define POWERPC_INSNS_603 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4734 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4735 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4736 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4737 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4738 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4739 PPC_SEGMENT | PPC_EXTERN)
4740 #define POWERPC_INSNS2_603 (PPC_NONE)
4741 #define POWERPC_MSRM_603 (0x000000000007FF73ULL)
4742 #define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
4743 //#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
4744 #define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
4745 #define POWERPC_BFDM_603 (bfd_mach_ppc_603)
4746 #define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4747 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4748 #define check_pow_603 check_pow_hid0
4749
4750 static void init_proc_603 (CPUPPCState *env)
4751 {
4752 gen_spr_ne_601(env);
4753 gen_spr_603(env);
4754 /* Time base */
4755 gen_tbl(env);
4756 /* hardware implementation registers */
4757 /* XXX : not implemented */
4758 spr_register(env, SPR_HID0, "HID0",
4759 SPR_NOACCESS, SPR_NOACCESS,
4760 &spr_read_generic, &spr_write_generic,
4761 0x00000000);
4762 /* XXX : not implemented */
4763 spr_register(env, SPR_HID1, "HID1",
4764 SPR_NOACCESS, SPR_NOACCESS,
4765 &spr_read_generic, &spr_write_generic,
4766 0x00000000);
4767 /* Memory management */
4768 gen_low_BATs(env);
4769 gen_6xx_7xx_soft_tlb(env, 64, 2);
4770 init_excp_603(env);
4771 env->dcache_line_size = 32;
4772 env->icache_line_size = 32;
4773 /* Allocate hardware IRQ controller */
4774 ppc6xx_irq_init(env);
4775 }
4776
4777 /* PowerPC 603e */
4778 #define POWERPC_INSNS_603E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4779 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4780 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4781 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4782 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4783 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4784 PPC_SEGMENT | PPC_EXTERN)
4785 #define POWERPC_INSNS2_603E (PPC_NONE)
4786 #define POWERPC_MSRM_603E (0x000000000007FF73ULL)
4787 #define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
4788 //#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
4789 #define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
4790 #define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
4791 #define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4792 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4793 #define check_pow_603E check_pow_hid0
4794
4795 static void init_proc_603E (CPUPPCState *env)
4796 {
4797 gen_spr_ne_601(env);
4798 gen_spr_603(env);
4799 /* Time base */
4800 gen_tbl(env);
4801 /* hardware implementation registers */
4802 /* XXX : not implemented */
4803 spr_register(env, SPR_HID0, "HID0",
4804 SPR_NOACCESS, SPR_NOACCESS,
4805 &spr_read_generic, &spr_write_generic,
4806 0x00000000);
4807 /* XXX : not implemented */
4808 spr_register(env, SPR_HID1, "HID1",
4809 SPR_NOACCESS, SPR_NOACCESS,
4810 &spr_read_generic, &spr_write_generic,
4811 0x00000000);
4812 /* XXX : not implemented */
4813 spr_register(env, SPR_IABR, "IABR",
4814 SPR_NOACCESS, SPR_NOACCESS,
4815 &spr_read_generic, &spr_write_generic,
4816 0x00000000);
4817 /* Memory management */
4818 gen_low_BATs(env);
4819 gen_6xx_7xx_soft_tlb(env, 64, 2);
4820 init_excp_603(env);
4821 env->dcache_line_size = 32;
4822 env->icache_line_size = 32;
4823 /* Allocate hardware IRQ controller */
4824 ppc6xx_irq_init(env);
4825 }
4826
4827 /* PowerPC 604 */
4828 #define POWERPC_INSNS_604 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4829 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4830 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4831 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4832 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4833 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4834 PPC_SEGMENT | PPC_EXTERN)
4835 #define POWERPC_INSNS2_604 (PPC_NONE)
4836 #define POWERPC_MSRM_604 (0x000000000005FF77ULL)
4837 #define POWERPC_MMU_604 (POWERPC_MMU_32B)
4838 //#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
4839 #define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
4840 #define POWERPC_BFDM_604 (bfd_mach_ppc_604)
4841 #define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4842 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4843 #define check_pow_604 check_pow_nocheck
4844
4845 static void init_proc_604 (CPUPPCState *env)
4846 {
4847 gen_spr_ne_601(env);
4848 gen_spr_604(env);
4849 /* Time base */
4850 gen_tbl(env);
4851 /* Hardware implementation registers */
4852 /* XXX : not implemented */
4853 spr_register(env, SPR_HID0, "HID0",
4854 SPR_NOACCESS, SPR_NOACCESS,
4855 &spr_read_generic, &spr_write_generic,
4856 0x00000000);
4857 /* Memory management */
4858 gen_low_BATs(env);
4859 init_excp_604(env);
4860 env->dcache_line_size = 32;
4861 env->icache_line_size = 32;
4862 /* Allocate hardware IRQ controller */
4863 ppc6xx_irq_init(env);
4864 }
4865
4866 /* PowerPC 604E */
4867 #define POWERPC_INSNS_604E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4868 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4869 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4870 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4871 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4872 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4873 PPC_SEGMENT | PPC_EXTERN)
4874 #define POWERPC_INSNS2_604E (PPC_NONE)
4875 #define POWERPC_MSRM_604E (0x000000000005FF77ULL)
4876 #define POWERPC_MMU_604E (POWERPC_MMU_32B)
4877 #define POWERPC_EXCP_604E (POWERPC_EXCP_604)
4878 #define POWERPC_INPUT_604E (PPC_FLAGS_INPUT_6xx)
4879 #define POWERPC_BFDM_604E (bfd_mach_ppc_604)
4880 #define POWERPC_FLAG_604E (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4881 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4882 #define check_pow_604E check_pow_nocheck
4883
4884 static void init_proc_604E (CPUPPCState *env)
4885 {
4886 gen_spr_ne_601(env);
4887 gen_spr_604(env);
4888 /* XXX : not implemented */
4889 spr_register(env, SPR_MMCR1, "MMCR1",
4890 SPR_NOACCESS, SPR_NOACCESS,
4891 &spr_read_generic, &spr_write_generic,
4892 0x00000000);
4893 /* XXX : not implemented */
4894 spr_register(env, SPR_PMC3, "PMC3",
4895 SPR_NOACCESS, SPR_NOACCESS,
4896 &spr_read_generic, &spr_write_generic,
4897 0x00000000);
4898 /* XXX : not implemented */
4899 spr_register(env, SPR_PMC4, "PMC4",
4900 SPR_NOACCESS, SPR_NOACCESS,
4901 &spr_read_generic, &spr_write_generic,
4902 0x00000000);
4903 /* Time base */
4904 gen_tbl(env);
4905 /* Hardware implementation registers */
4906 /* XXX : not implemented */
4907 spr_register(env, SPR_HID0, "HID0",
4908 SPR_NOACCESS, SPR_NOACCESS,
4909 &spr_read_generic, &spr_write_generic,
4910 0x00000000);
4911 /* XXX : not implemented */
4912 spr_register(env, SPR_HID1, "HID1",
4913 SPR_NOACCESS, SPR_NOACCESS,
4914 &spr_read_generic, &spr_write_generic,
4915 0x00000000);
4916 /* Memory management */
4917 gen_low_BATs(env);
4918 init_excp_604(env);
4919 env->dcache_line_size = 32;
4920 env->icache_line_size = 32;
4921 /* Allocate hardware IRQ controller */
4922 ppc6xx_irq_init(env);
4923 }
4924
4925 /* PowerPC 740 */
4926 #define POWERPC_INSNS_740 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4927 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4928 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4929 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4930 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4931 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4932 PPC_SEGMENT | PPC_EXTERN)
4933 #define POWERPC_INSNS2_740 (PPC_NONE)
4934 #define POWERPC_MSRM_740 (0x000000000005FF77ULL)
4935 #define POWERPC_MMU_740 (POWERPC_MMU_32B)
4936 #define POWERPC_EXCP_740 (POWERPC_EXCP_7x0)
4937 #define POWERPC_INPUT_740 (PPC_FLAGS_INPUT_6xx)
4938 #define POWERPC_BFDM_740 (bfd_mach_ppc_750)
4939 #define POWERPC_FLAG_740 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4940 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4941 #define check_pow_740 check_pow_hid0
4942
4943 static void init_proc_740 (CPUPPCState *env)
4944 {
4945 gen_spr_ne_601(env);
4946 gen_spr_7xx(env);
4947 /* Time base */
4948 gen_tbl(env);
4949 /* Thermal management */
4950 gen_spr_thrm(env);
4951 /* Hardware implementation registers */
4952 /* XXX : not implemented */
4953 spr_register(env, SPR_HID0, "HID0",
4954 SPR_NOACCESS, SPR_NOACCESS,
4955 &spr_read_generic, &spr_write_generic,
4956 0x00000000);
4957 /* XXX : not implemented */
4958 spr_register(env, SPR_HID1, "HID1",
4959 SPR_NOACCESS, SPR_NOACCESS,
4960 &spr_read_generic, &spr_write_generic,
4961 0x00000000);
4962 /* Memory management */
4963 gen_low_BATs(env);
4964 init_excp_7x0(env);
4965 env->dcache_line_size = 32;
4966 env->icache_line_size = 32;
4967 /* Allocate hardware IRQ controller */
4968 ppc6xx_irq_init(env);
4969 }
4970
4971 /* PowerPC 750 */
4972 #define POWERPC_INSNS_750 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4973 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4974 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4975 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4976 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4977 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4978 PPC_SEGMENT | PPC_EXTERN)
4979 #define POWERPC_INSNS2_750 (PPC_NONE)
4980 #define POWERPC_MSRM_750 (0x000000000005FF77ULL)
4981 #define POWERPC_MMU_750 (POWERPC_MMU_32B)
4982 #define POWERPC_EXCP_750 (POWERPC_EXCP_7x0)
4983 #define POWERPC_INPUT_750 (PPC_FLAGS_INPUT_6xx)
4984 #define POWERPC_BFDM_750 (bfd_mach_ppc_750)
4985 #define POWERPC_FLAG_750 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4986 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4987 #define check_pow_750 check_pow_hid0
4988
4989 static void init_proc_750 (CPUPPCState *env)
4990 {
4991 gen_spr_ne_601(env);
4992 gen_spr_7xx(env);
4993 /* XXX : not implemented */
4994 spr_register(env, SPR_L2CR, "L2CR",
4995 SPR_NOACCESS, SPR_NOACCESS,
4996 &spr_read_generic, &spr_write_generic,
4997 0x00000000);
4998 /* Time base */
4999 gen_tbl(env);
5000 /* Thermal management */
5001 gen_spr_thrm(env);
5002 /* Hardware implementation registers */
5003 /* XXX : not implemented */
5004 spr_register(env, SPR_HID0, "HID0",
5005 SPR_NOACCESS, SPR_NOACCESS,
5006 &spr_read_generic, &spr_write_generic,
5007 0x00000000);
5008 /* XXX : not implemented */
5009 spr_register(env, SPR_HID1, "HID1",
5010 SPR_NOACCESS, SPR_NOACCESS,
5011 &spr_read_generic, &spr_write_generic,
5012 0x00000000);
5013 /* Memory management */
5014 gen_low_BATs(env);
5015 /* XXX: high BATs are also present but are known to be bugged on
5016 * die version 1.x
5017 */
5018 init_excp_7x0(env);
5019 env->dcache_line_size = 32;
5020 env->icache_line_size = 32;
5021 /* Allocate hardware IRQ controller */
5022 ppc6xx_irq_init(env);
5023 }
5024
5025 /* PowerPC 750 CL */
5026 /* XXX: not implemented:
5027 * cache lock instructions:
5028 * dcbz_l
5029 * floating point paired instructions
5030 * psq_lux
5031 * psq_lx
5032 * psq_stux
5033 * psq_stx
5034 * ps_abs
5035 * ps_add
5036 * ps_cmpo0
5037 * ps_cmpo1
5038 * ps_cmpu0
5039 * ps_cmpu1
5040 * ps_div
5041 * ps_madd
5042 * ps_madds0
5043 * ps_madds1
5044 * ps_merge00
5045 * ps_merge01
5046 * ps_merge10
5047 * ps_merge11
5048 * ps_mr
5049 * ps_msub
5050 * ps_mul
5051 * ps_muls0
5052 * ps_muls1
5053 * ps_nabs
5054 * ps_neg
5055 * ps_nmadd
5056 * ps_nmsub
5057 * ps_res
5058 * ps_rsqrte
5059 * ps_sel
5060 * ps_sub
5061 * ps_sum0
5062 * ps_sum1
5063 */
5064 #define POWERPC_INSNS_750cl (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5065 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5066 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5067 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5068 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5069 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5070 PPC_SEGMENT | PPC_EXTERN)
5071 #define POWERPC_INSNS2_750cl (PPC_NONE)
5072 #define POWERPC_MSRM_750cl (0x000000000005FF77ULL)
5073 #define POWERPC_MMU_750cl (POWERPC_MMU_32B)
5074 #define POWERPC_EXCP_750cl (POWERPC_EXCP_7x0)
5075 #define POWERPC_INPUT_750cl (PPC_FLAGS_INPUT_6xx)
5076 #define POWERPC_BFDM_750cl (bfd_mach_ppc_750)
5077 #define POWERPC_FLAG_750cl (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5078 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5079 #define check_pow_750cl check_pow_hid0
5080
5081 static void init_proc_750cl (CPUPPCState *env)
5082 {
5083 gen_spr_ne_601(env);
5084 gen_spr_7xx(env);
5085 /* XXX : not implemented */
5086 spr_register(env, SPR_L2CR, "L2CR",
5087 SPR_NOACCESS, SPR_NOACCESS,
5088 &spr_read_generic, &spr_write_generic,
5089 0x00000000);
5090 /* Time base */
5091 gen_tbl(env);
5092 /* Thermal management */
5093 /* Those registers are fake on 750CL */
5094 spr_register(env, SPR_THRM1, "THRM1",
5095 SPR_NOACCESS, SPR_NOACCESS,
5096 &spr_read_generic, &spr_write_generic,
5097 0x00000000);
5098 spr_register(env, SPR_THRM2, "THRM2",
5099 SPR_NOACCESS, SPR_NOACCESS,
5100 &spr_read_generic, &spr_write_generic,
5101 0x00000000);
5102 spr_register(env, SPR_THRM3, "THRM3",
5103 SPR_NOACCESS, SPR_NOACCESS,
5104 &spr_read_generic, &spr_write_generic,
5105 0x00000000);
5106 /* XXX: not implemented */
5107 spr_register(env, SPR_750_TDCL, "TDCL",
5108 SPR_NOACCESS, SPR_NOACCESS,
5109 &spr_read_generic, &spr_write_generic,
5110 0x00000000);
5111 spr_register(env, SPR_750_TDCH, "TDCH",
5112 SPR_NOACCESS, SPR_NOACCESS,
5113 &spr_read_generic, &spr_write_generic,
5114 0x00000000);
5115 /* DMA */
5116 /* XXX : not implemented */
5117 spr_register(env, SPR_750_WPAR, "WPAR",
5118 SPR_NOACCESS, SPR_NOACCESS,
5119 &spr_read_generic, &spr_write_generic,
5120 0x00000000);
5121 spr_register(env, SPR_750_DMAL, "DMAL",
5122 SPR_NOACCESS, SPR_NOACCESS,
5123 &spr_read_generic, &spr_write_generic,
5124 0x00000000);
5125 spr_register(env, SPR_750_DMAU, "DMAU",
5126 SPR_NOACCESS, SPR_NOACCESS,
5127 &spr_read_generic, &spr_write_generic,
5128 0x00000000);
5129 /* Hardware implementation registers */
5130 /* XXX : not implemented */
5131 spr_register(env, SPR_HID0, "HID0",
5132 SPR_NOACCESS, SPR_NOACCESS,
5133 &spr_read_generic, &spr_write_generic,
5134 0x00000000);
5135 /* XXX : not implemented */
5136 spr_register(env, SPR_HID1, "HID1",
5137 SPR_NOACCESS, SPR_NOACCESS,
5138 &spr_read_generic, &spr_write_generic,
5139 0x00000000);
5140 /* XXX : not implemented */
5141 spr_register(env, SPR_750CL_HID2, "HID2",
5142 SPR_NOACCESS, SPR_NOACCESS,
5143 &spr_read_generic, &spr_write_generic,
5144 0x00000000);
5145 /* XXX : not implemented */
5146 spr_register(env, SPR_750CL_HID4, "HID4",
5147 SPR_NOACCESS, SPR_NOACCESS,
5148 &spr_read_generic, &spr_write_generic,
5149 0x00000000);
5150 /* Quantization registers */
5151 /* XXX : not implemented */
5152 spr_register(env, SPR_750_GQR0, "GQR0",
5153 SPR_NOACCESS, SPR_NOACCESS,
5154 &spr_read_generic, &spr_write_generic,
5155 0x00000000);
5156 /* XXX : not implemented */
5157 spr_register(env, SPR_750_GQR1, "GQR1",
5158 SPR_NOACCESS, SPR_NOACCESS,
5159 &spr_read_generic, &spr_write_generic,
5160 0x00000000);
5161 /* XXX : not implemented */
5162 spr_register(env, SPR_750_GQR2, "GQR2",
5163 SPR_NOACCESS, SPR_NOACCESS,
5164 &spr_read_generic, &spr_write_generic,
5165 0x00000000);
5166 /* XXX : not implemented */
5167 spr_register(env, SPR_750_GQR3, "GQR3",
5168 SPR_NOACCESS, SPR_NOACCESS,
5169 &spr_read_generic, &spr_write_generic,
5170 0x00000000);
5171 /* XXX : not implemented */
5172 spr_register(env, SPR_750_GQR4, "GQR4",
5173 SPR_NOACCESS, SPR_NOACCESS,
5174 &spr_read_generic, &spr_write_generic,
5175 0x00000000);
5176 /* XXX : not implemented */
5177 spr_register(env, SPR_750_GQR5, "GQR5",
5178 SPR_NOACCESS, SPR_NOACCESS,
5179 &spr_read_generic, &spr_write_generic,
5180 0x00000000);
5181 /* XXX : not implemented */
5182 spr_register(env, SPR_750_GQR6, "GQR6",
5183 SPR_NOACCESS, SPR_NOACCESS,
5184 &spr_read_generic, &spr_write_generic,
5185 0x00000000);
5186 /* XXX : not implemented */
5187 spr_register(env, SPR_750_GQR7, "GQR7",
5188 SPR_NOACCESS, SPR_NOACCESS,
5189 &spr_read_generic, &spr_write_generic,
5190 0x00000000);
5191 /* Memory management */
5192 gen_low_BATs(env);
5193 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5194 gen_high_BATs(env);
5195 init_excp_750cl(env);
5196 env->dcache_line_size = 32;
5197 env->icache_line_size = 32;
5198 /* Allocate hardware IRQ controller */
5199 ppc6xx_irq_init(env);
5200 }
5201
5202 /* PowerPC 750CX */
5203 #define POWERPC_INSNS_750cx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5204 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5205 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5206 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5207 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5208 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5209 PPC_SEGMENT | PPC_EXTERN)
5210 #define POWERPC_INSNS2_750cx (PPC_NONE)
5211 #define POWERPC_MSRM_750cx (0x000000000005FF77ULL)
5212 #define POWERPC_MMU_750cx (POWERPC_MMU_32B)
5213 #define POWERPC_EXCP_750cx (POWERPC_EXCP_7x0)
5214 #define POWERPC_INPUT_750cx (PPC_FLAGS_INPUT_6xx)
5215 #define POWERPC_BFDM_750cx (bfd_mach_ppc_750)
5216 #define POWERPC_FLAG_750cx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5217 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5218 #define check_pow_750cx check_pow_hid0
5219
5220 static void init_proc_750cx (CPUPPCState *env)
5221 {
5222 gen_spr_ne_601(env);
5223 gen_spr_7xx(env);
5224 /* XXX : not implemented */
5225 spr_register(env, SPR_L2CR, "L2CR",
5226 SPR_NOACCESS, SPR_NOACCESS,
5227 &spr_read_generic, &spr_write_generic,
5228 0x00000000);
5229 /* Time base */
5230 gen_tbl(env);
5231 /* Thermal management */
5232 gen_spr_thrm(env);
5233 /* This register is not implemented but is present for compatibility */
5234 spr_register(env, SPR_SDA, "SDA",
5235 SPR_NOACCESS, SPR_NOACCESS,
5236 &spr_read_generic, &spr_write_generic,
5237 0x00000000);
5238 /* Hardware implementation registers */
5239 /* XXX : not implemented */
5240 spr_register(env, SPR_HID0, "HID0",
5241 SPR_NOACCESS, SPR_NOACCESS,
5242 &spr_read_generic, &spr_write_generic,
5243 0x00000000);
5244 /* XXX : not implemented */
5245 spr_register(env, SPR_HID1, "HID1",
5246 SPR_NOACCESS, SPR_NOACCESS,
5247 &spr_read_generic, &spr_write_generic,
5248 0x00000000);
5249 /* Memory management */
5250 gen_low_BATs(env);
5251 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5252 gen_high_BATs(env);
5253 init_excp_750cx(env);
5254 env->dcache_line_size = 32;
5255 env->icache_line_size = 32;
5256 /* Allocate hardware IRQ controller */
5257 ppc6xx_irq_init(env);
5258 }
5259
5260 /* PowerPC 750FX */
5261 #define POWERPC_INSNS_750fx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5262 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5263 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5264 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5265 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5266 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5267 PPC_SEGMENT | PPC_EXTERN)
5268 #define POWERPC_INSNS2_750fx (PPC_NONE)
5269 #define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
5270 #define POWERPC_MMU_750fx (POWERPC_MMU_32B)
5271 #define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
5272 #define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
5273 #define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
5274 #define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5275 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5276 #define check_pow_750fx check_pow_hid0
5277
5278 static void init_proc_750fx (CPUPPCState *env)
5279 {
5280 gen_spr_ne_601(env);
5281 gen_spr_7xx(env);
5282 /* XXX : not implemented */
5283 spr_register(env, SPR_L2CR, "L2CR",
5284 SPR_NOACCESS, SPR_NOACCESS,
5285 &spr_read_generic, &spr_write_generic,
5286 0x00000000);
5287 /* Time base */
5288 gen_tbl(env);
5289 /* Thermal management */
5290 gen_spr_thrm(env);
5291 /* XXX : not implemented */
5292 spr_register(env, SPR_750_THRM4, "THRM4",
5293 SPR_NOACCESS, SPR_NOACCESS,
5294 &spr_read_generic, &spr_write_generic,
5295 0x00000000);
5296 /* Hardware implementation registers */
5297 /* XXX : not implemented */
5298 spr_register(env, SPR_HID0, "HID0",
5299 SPR_NOACCESS, SPR_NOACCESS,
5300 &spr_read_generic, &spr_write_generic,
5301 0x00000000);
5302 /* XXX : not implemented */
5303 spr_register(env, SPR_HID1, "HID1",
5304 SPR_NOACCESS, SPR_NOACCESS,
5305 &spr_read_generic, &spr_write_generic,
5306 0x00000000);
5307 /* XXX : not implemented */
5308 spr_register(env, SPR_750FX_HID2, "HID2",
5309 SPR_NOACCESS, SPR_NOACCESS,
5310 &spr_read_generic, &spr_write_generic,
5311 0x00000000);
5312 /* Memory management */
5313 gen_low_BATs(env);
5314 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5315 gen_high_BATs(env);
5316 init_excp_7x0(env);
5317 env->dcache_line_size = 32;
5318 env->icache_line_size = 32;
5319 /* Allocate hardware IRQ controller */
5320 ppc6xx_irq_init(env);
5321 }
5322
5323 /* PowerPC 750GX */
5324 #define POWERPC_INSNS_750gx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5325 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5326 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5327 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5328 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5329 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5330 PPC_SEGMENT | PPC_EXTERN)
5331 #define POWERPC_INSNS2_750gx (PPC_NONE)
5332 #define POWERPC_MSRM_750gx (0x000000000005FF77ULL)
5333 #define POWERPC_MMU_750gx (POWERPC_MMU_32B)
5334 #define POWERPC_EXCP_750gx (POWERPC_EXCP_7x0)
5335 #define POWERPC_INPUT_750gx (PPC_FLAGS_INPUT_6xx)
5336 #define POWERPC_BFDM_750gx (bfd_mach_ppc_750)
5337 #define POWERPC_FLAG_750gx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5338 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5339 #define check_pow_750gx check_pow_hid0
5340
5341 static void init_proc_750gx (CPUPPCState *env)
5342 {
5343 gen_spr_ne_601(env);
5344 gen_spr_7xx(env);
5345 /* XXX : not implemented (XXX: different from 750fx) */
5346 spr_register(env, SPR_L2CR, "L2CR",
5347 SPR_NOACCESS, SPR_NOACCESS,
5348 &spr_read_generic, &spr_write_generic,
5349 0x00000000);
5350 /* Time base */
5351 gen_tbl(env);
5352 /* Thermal management */
5353 gen_spr_thrm(env);
5354 /* XXX : not implemented */
5355 spr_register(env, SPR_750_THRM4, "THRM4",
5356 SPR_NOACCESS, SPR_NOACCESS,
5357 &spr_read_generic, &spr_write_generic,
5358 0x00000000);
5359 /* Hardware implementation registers */
5360 /* XXX : not implemented (XXX: different from 750fx) */
5361 spr_register(env, SPR_HID0, "HID0",
5362 SPR_NOACCESS, SPR_NOACCESS,
5363 &spr_read_generic, &spr_write_generic,
5364 0x00000000);
5365 /* XXX : not implemented */
5366 spr_register(env, SPR_HID1, "HID1",
5367 SPR_NOACCESS, SPR_NOACCESS,
5368 &spr_read_generic, &spr_write_generic,
5369 0x00000000);
5370 /* XXX : not implemented (XXX: different from 750fx) */
5371 spr_register(env, SPR_750FX_HID2, "HID2",
5372 SPR_NOACCESS, SPR_NOACCESS,
5373 &spr_read_generic, &spr_write_generic,
5374 0x00000000);
5375 /* Memory management */
5376 gen_low_BATs(env);
5377 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5378 gen_high_BATs(env);
5379 init_excp_7x0(env);
5380 env->dcache_line_size = 32;
5381 env->icache_line_size = 32;
5382 /* Allocate hardware IRQ controller */
5383 ppc6xx_irq_init(env);
5384 }
5385
5386 /* PowerPC 745 */
5387 #define POWERPC_INSNS_745 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5388 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5389 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5390 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5391 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5392 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5393 PPC_SEGMENT | PPC_EXTERN)
5394 #define POWERPC_INSNS2_745 (PPC_NONE)
5395 #define POWERPC_MSRM_745 (0x000000000005FF77ULL)
5396 #define POWERPC_MMU_745 (POWERPC_MMU_SOFT_6xx)
5397 #define POWERPC_EXCP_745 (POWERPC_EXCP_7x5)
5398 #define POWERPC_INPUT_745 (PPC_FLAGS_INPUT_6xx)
5399 #define POWERPC_BFDM_745 (bfd_mach_ppc_750)
5400 #define POWERPC_FLAG_745 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5401 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5402 #define check_pow_745 check_pow_hid0
5403
5404 static void init_proc_745 (CPUPPCState *env)
5405 {
5406 gen_spr_ne_601(env);
5407 gen_spr_7xx(env);
5408 gen_spr_G2_755(env);
5409 /* Time base */
5410 gen_tbl(env);
5411 /* Thermal management */
5412 gen_spr_thrm(env);
5413 /* Hardware implementation registers */
5414 /* XXX : not implemented */
5415 spr_register(env, SPR_HID0, "HID0",
5416 SPR_NOACCESS, SPR_NOACCESS,
5417 &spr_read_generic, &spr_write_generic,
5418 0x00000000);
5419 /* XXX : not implemented */
5420 spr_register(env, SPR_HID1, "HID1",
5421 SPR_NOACCESS, SPR_NOACCESS,
5422 &spr_read_generic, &spr_write_generic,
5423 0x00000000);
5424 /* XXX : not implemented */
5425 spr_register(env, SPR_HID2, "HID2",
5426 SPR_NOACCESS, SPR_NOACCESS,
5427 &spr_read_generic, &spr_write_generic,
5428 0x00000000);
5429 /* Memory management */
5430 gen_low_BATs(env);
5431 gen_high_BATs(env);
5432 gen_6xx_7xx_soft_tlb(env, 64, 2);
5433 init_excp_7x5(env);
5434 env->dcache_line_size = 32;
5435 env->icache_line_size = 32;
5436 /* Allocate hardware IRQ controller */
5437 ppc6xx_irq_init(env);
5438 }
5439
5440 /* PowerPC 755 */
5441 #define POWERPC_INSNS_755 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5442 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5443 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5444 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5445 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5446 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5447 PPC_SEGMENT | PPC_EXTERN)
5448 #define POWERPC_INSNS2_755 (PPC_NONE)
5449 #define POWERPC_MSRM_755 (0x000000000005FF77ULL)
5450 #define POWERPC_MMU_755 (POWERPC_MMU_SOFT_6xx)
5451 #define POWERPC_EXCP_755 (POWERPC_EXCP_7x5)
5452 #define POWERPC_INPUT_755 (PPC_FLAGS_INPUT_6xx)
5453 #define POWERPC_BFDM_755 (bfd_mach_ppc_750)
5454 #define POWERPC_FLAG_755 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5455 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5456 #define check_pow_755 check_pow_hid0
5457
5458 static void init_proc_755 (CPUPPCState *env)
5459 {
5460 gen_spr_ne_601(env);
5461 gen_spr_7xx(env);
5462 gen_spr_G2_755(env);
5463 /* Time base */
5464 gen_tbl(env);
5465 /* L2 cache control */
5466 /* XXX : not implemented */
5467 spr_register(env, SPR_L2CR, "L2CR",
5468 SPR_NOACCESS, SPR_NOACCESS,
5469 &spr_read_generic, &spr_write_generic,
5470 0x00000000);
5471 /* XXX : not implemented */
5472 spr_register(env, SPR_L2PMCR, "L2PMCR",
5473 SPR_NOACCESS, SPR_NOACCESS,
5474 &spr_read_generic, &spr_write_generic,
5475 0x00000000);
5476 /* Thermal management */
5477 gen_spr_thrm(env);
5478 /* Hardware implementation registers */
5479 /* XXX : not implemented */
5480 spr_register(env, SPR_HID0, "HID0",
5481 SPR_NOACCESS, SPR_NOACCESS,
5482 &spr_read_generic, &spr_write_generic,
5483 0x00000000);
5484 /* XXX : not implemented */
5485 spr_register(env, SPR_HID1, "HID1",
5486 SPR_NOACCESS, SPR_NOACCESS,
5487 &spr_read_generic, &spr_write_generic,
5488 0x00000000);
5489 /* XXX : not implemented */
5490 spr_register(env, SPR_HID2, "HID2",
5491 SPR_NOACCESS, SPR_NOACCESS,
5492 &spr_read_generic, &spr_write_generic,
5493 0x00000000);
5494 /* Memory management */
5495 gen_low_BATs(env);
5496 gen_high_BATs(env);
5497 gen_6xx_7xx_soft_tlb(env, 64, 2);
5498 init_excp_7x5(env);
5499 env->dcache_line_size = 32;
5500 env->icache_line_size = 32;
5501 /* Allocate hardware IRQ controller */
5502 ppc6xx_irq_init(env);
5503 }
5504
5505 /* PowerPC 7400 (aka G4) */
5506 #define POWERPC_INSNS_7400 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5507 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5508 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5509 PPC_FLOAT_STFIWX | \
5510 PPC_CACHE | PPC_CACHE_ICBI | \
5511 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5512 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5513 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5514 PPC_MEM_TLBIA | \
5515 PPC_SEGMENT | PPC_EXTERN | \
5516 PPC_ALTIVEC)
5517 #define POWERPC_INSNS2_7400 (PPC_NONE)
5518 #define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
5519 #define POWERPC_MMU_7400 (POWERPC_MMU_32B)
5520 #define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
5521 #define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
5522 #define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
5523 #define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5524 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5525 POWERPC_FLAG_BUS_CLK)
5526 #define check_pow_7400 check_pow_hid0
5527
5528 static void init_proc_7400 (CPUPPCState *env)
5529 {
5530 gen_spr_ne_601(env);
5531 gen_spr_7xx(env);
5532 /* Time base */
5533 gen_tbl(env);
5534 /* 74xx specific SPR */
5535 gen_spr_74xx(env);
5536 /* XXX : not implemented */
5537 spr_register(env, SPR_UBAMR, "UBAMR",
5538 &spr_read_ureg, SPR_NOACCESS,
5539 &spr_read_ureg, SPR_NOACCESS,
5540 0x00000000);
5541 /* XXX: this seems not implemented on all revisions. */
5542 /* XXX : not implemented */
5543 spr_register(env, SPR_MSSCR1, "MSSCR1",
5544 SPR_NOACCESS, SPR_NOACCESS,
5545 &spr_read_generic, &spr_write_generic,
5546 0x00000000);
5547 /* Thermal management */
5548 gen_spr_thrm(env);
5549 /* Memory management */
5550 gen_low_BATs(env);
5551 init_excp_7400(env);
5552 env->dcache_line_size = 32;
5553 env->icache_line_size = 32;
5554 /* Allocate hardware IRQ controller */
5555 ppc6xx_irq_init(env);
5556 }
5557
5558 /* PowerPC 7410 (aka G4) */
5559 #define POWERPC_INSNS_7410 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5560 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5561 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5562 PPC_FLOAT_STFIWX | \
5563 PPC_CACHE | PPC_CACHE_ICBI | \
5564 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5565 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5566 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5567 PPC_MEM_TLBIA | \
5568 PPC_SEGMENT | PPC_EXTERN | \
5569 PPC_ALTIVEC)
5570 #define POWERPC_INSNS2_7410 (PPC_NONE)
5571 #define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
5572 #define POWERPC_MMU_7410 (POWERPC_MMU_32B)
5573 #define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
5574 #define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
5575 #define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
5576 #define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5577 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5578 POWERPC_FLAG_BUS_CLK)
5579 #define check_pow_7410 check_pow_hid0
5580
5581 static void init_proc_7410 (CPUPPCState *env)
5582 {
5583 gen_spr_ne_601(env);
5584 gen_spr_7xx(env);
5585 /* Time base */
5586 gen_tbl(env);
5587 /* 74xx specific SPR */
5588 gen_spr_74xx(env);
5589 /* XXX : not implemented */
5590 spr_register(env, SPR_UBAMR, "UBAMR",
5591 &spr_read_ureg, SPR_NOACCESS,
5592 &spr_read_ureg, SPR_NOACCESS,
5593 0x00000000);
5594 /* Thermal management */
5595 gen_spr_thrm(env);
5596 /* L2PMCR */
5597 /* XXX : not implemented */
5598 spr_register(env, SPR_L2PMCR, "L2PMCR",
5599 SPR_NOACCESS, SPR_NOACCESS,
5600 &spr_read_generic, &spr_write_generic,
5601 0x00000000);
5602 /* LDSTDB */
5603 /* XXX : not implemented */
5604 spr_register(env, SPR_LDSTDB, "LDSTDB",
5605 SPR_NOACCESS, SPR_NOACCESS,
5606 &spr_read_generic, &spr_write_generic,
5607 0x00000000);
5608 /* Memory management */
5609 gen_low_BATs(env);
5610 init_excp_7400(env);
5611 env->dcache_line_size = 32;
5612 env->icache_line_size = 32;
5613 /* Allocate hardware IRQ controller */
5614 ppc6xx_irq_init(env);
5615 }
5616
5617 /* PowerPC 7440 (aka G4) */
5618 #define POWERPC_INSNS_7440 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5619 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5620 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5621 PPC_FLOAT_STFIWX | \
5622 PPC_CACHE | PPC_CACHE_ICBI | \
5623 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5624 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5625 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5626 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5627 PPC_SEGMENT | PPC_EXTERN | \
5628 PPC_ALTIVEC)
5629 #define POWERPC_INSNS2_7440 (PPC_NONE)
5630 #define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
5631 #define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
5632 #define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
5633 #define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
5634 #define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
5635 #define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5636 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5637 POWERPC_FLAG_BUS_CLK)
5638 #define check_pow_7440 check_pow_hid0_74xx
5639
5640 __attribute__ (( unused ))
5641 static void init_proc_7440 (CPUPPCState *env)
5642 {
5643 gen_spr_ne_601(env);
5644 gen_spr_7xx(env);
5645 /* Time base */
5646 gen_tbl(env);
5647 /* 74xx specific SPR */
5648 gen_spr_74xx(env);
5649 /* XXX : not implemented */
5650 spr_register(env, SPR_UBAMR, "UBAMR",
5651 &spr_read_ureg, SPR_NOACCESS,
5652 &spr_read_ureg, SPR_NOACCESS,
5653 0x00000000);
5654 /* LDSTCR */
5655 /* XXX : not implemented */
5656 spr_register(env, SPR_LDSTCR, "LDSTCR",
5657 SPR_NOACCESS, SPR_NOACCESS,
5658 &spr_read_generic, &spr_write_generic,
5659 0x00000000);
5660 /* ICTRL */
5661 /* XXX : not implemented */
5662 spr_register(env, SPR_ICTRL, "ICTRL",
5663 SPR_NOACCESS, SPR_NOACCESS,
5664 &spr_read_generic, &spr_write_generic,
5665 0x00000000);
5666 /* MSSSR0 */
5667 /* XXX : not implemented */
5668 spr_register(env, SPR_MSSSR0, "MSSSR0",
5669 SPR_NOACCESS, SPR_NOACCESS,
5670 &spr_read_generic, &spr_write_generic,
5671 0x00000000);
5672 /* PMC */
5673 /* XXX : not implemented */
5674 spr_register(env, SPR_PMC5, "PMC5",
5675 SPR_NOACCESS, SPR_NOACCESS,
5676 &spr_read_generic, &spr_write_generic,
5677 0x00000000);
5678 /* XXX : not implemented */
5679 spr_register(env, SPR_UPMC5, "UPMC5",
5680 &spr_read_ureg, SPR_NOACCESS,
5681 &spr_read_ureg, SPR_NOACCESS,
5682 0x00000000);
5683 /* XXX : not implemented */
5684 spr_register(env, SPR_PMC6, "PMC6",
5685 SPR_NOACCESS, SPR_NOACCESS,
5686 &spr_read_generic, &spr_write_generic,
5687 0x00000000);
5688 /* XXX : not implemented */
5689 spr_register(env, SPR_UPMC6, "UPMC6",
5690 &spr_read_ureg, SPR_NOACCESS,
5691 &spr_read_ureg, SPR_NOACCESS,
5692 0x00000000);
5693 /* Memory management */
5694 gen_low_BATs(env);
5695 gen_74xx_soft_tlb(env, 128, 2);
5696 init_excp_7450(env);
5697 env->dcache_line_size = 32;
5698 env->icache_line_size = 32;
5699 /* Allocate hardware IRQ controller */
5700 ppc6xx_irq_init(env);
5701 }
5702
5703 /* PowerPC 7450 (aka G4) */
5704 #define POWERPC_INSNS_7450 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5705 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5706 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5707 PPC_FLOAT_STFIWX | \
5708 PPC_CACHE | PPC_CACHE_ICBI | \
5709 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5710 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5711 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5712 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5713 PPC_SEGMENT | PPC_EXTERN | \
5714 PPC_ALTIVEC)
5715 #define POWERPC_INSNS2_7450 (PPC_NONE)
5716 #define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
5717 #define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
5718 #define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
5719 #define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
5720 #define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
5721 #define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5722 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5723 POWERPC_FLAG_BUS_CLK)
5724 #define check_pow_7450 check_pow_hid0_74xx
5725
5726 __attribute__ (( unused ))
5727 static void init_proc_7450 (CPUPPCState *env)
5728 {
5729 gen_spr_ne_601(env);
5730 gen_spr_7xx(env);
5731 /* Time base */
5732 gen_tbl(env);
5733 /* 74xx specific SPR */
5734 gen_spr_74xx(env);
5735 /* Level 3 cache control */
5736 gen_l3_ctrl(env);
5737 /* L3ITCR1 */
5738 /* XXX : not implemented */
5739 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5740 SPR_NOACCESS, SPR_NOACCESS,
5741 &spr_read_generic, &spr_write_generic,
5742 0x00000000);
5743 /* L3ITCR2 */
5744 /* XXX : not implemented */
5745 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5746 SPR_NOACCESS, SPR_NOACCESS,
5747 &spr_read_generic, &spr_write_generic,
5748 0x00000000);
5749 /* L3ITCR3 */
5750 /* XXX : not implemented */
5751 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5752 SPR_NOACCESS, SPR_NOACCESS,
5753 &spr_read_generic, &spr_write_generic,
5754 0x00000000);
5755 /* L3OHCR */
5756 /* XXX : not implemented */
5757 spr_register(env, SPR_L3OHCR, "L3OHCR",
5758 SPR_NOACCESS, SPR_NOACCESS,
5759 &spr_read_generic, &spr_write_generic,
5760 0x00000000);
5761 /* XXX : not implemented */
5762 spr_register(env, SPR_UBAMR, "UBAMR",
5763 &spr_read_ureg, SPR_NOACCESS,
5764 &spr_read_ureg, SPR_NOACCESS,
5765 0x00000000);
5766 /* LDSTCR */
5767 /* XXX : not implemented */
5768 spr_register(env, SPR_LDSTCR, "LDSTCR",
5769 SPR_NOACCESS, SPR_NOACCESS,
5770 &spr_read_generic, &spr_write_generic,
5771 0x00000000);
5772 /* ICTRL */
5773 /* XXX : not implemented */
5774 spr_register(env, SPR_ICTRL, "ICTRL",
5775 SPR_NOACCESS, SPR_NOACCESS,
5776 &spr_read_generic, &spr_write_generic,
5777 0x00000000);
5778 /* MSSSR0 */
5779 /* XXX : not implemented */
5780 spr_register(env, SPR_MSSSR0, "MSSSR0",
5781 SPR_NOACCESS, SPR_NOACCESS,
5782 &spr_read_generic, &spr_write_generic,
5783 0x00000000);
5784 /* PMC */
5785 /* XXX : not implemented */
5786 spr_register(env, SPR_PMC5, "PMC5",
5787 SPR_NOACCESS, SPR_NOACCESS,
5788 &spr_read_generic, &spr_write_generic,
5789 0x00000000);
5790 /* XXX : not implemented */
5791 spr_register(env, SPR_UPMC5, "UPMC5",
5792 &spr_read_ureg, SPR_NOACCESS,
5793 &spr_read_ureg, SPR_NOACCESS,
5794 0x00000000);
5795 /* XXX : not implemented */
5796 spr_register(env, SPR_PMC6, "PMC6",
5797 SPR_NOACCESS, SPR_NOACCESS,
5798 &spr_read_generic, &spr_write_generic,
5799 0x00000000);
5800 /* XXX : not implemented */
5801 spr_register(env, SPR_UPMC6, "UPMC6",
5802 &spr_read_ureg, SPR_NOACCESS,
5803 &spr_read_ureg, SPR_NOACCESS,
5804 0x00000000);
5805 /* Memory management */
5806 gen_low_BATs(env);
5807 gen_74xx_soft_tlb(env, 128, 2);
5808 init_excp_7450(env);
5809 env->dcache_line_size = 32;
5810 env->icache_line_size = 32;
5811 /* Allocate hardware IRQ controller */
5812 ppc6xx_irq_init(env);
5813 }
5814
5815 /* PowerPC 7445 (aka G4) */
5816 #define POWERPC_INSNS_7445 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5817 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5818 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5819 PPC_FLOAT_STFIWX | \
5820 PPC_CACHE | PPC_CACHE_ICBI | \
5821 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5822 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5823 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5824 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5825 PPC_SEGMENT | PPC_EXTERN | \
5826 PPC_ALTIVEC)
5827 #define POWERPC_INSNS2_7445 (PPC_NONE)
5828 #define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
5829 #define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
5830 #define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
5831 #define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
5832 #define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
5833 #define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5834 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5835 POWERPC_FLAG_BUS_CLK)
5836 #define check_pow_7445 check_pow_hid0_74xx
5837
5838 __attribute__ (( unused ))
5839 static void init_proc_7445 (CPUPPCState *env)
5840 {
5841 gen_spr_ne_601(env);
5842 gen_spr_7xx(env);
5843 /* Time base */
5844 gen_tbl(env);
5845 /* 74xx specific SPR */
5846 gen_spr_74xx(env);
5847 /* LDSTCR */
5848 /* XXX : not implemented */
5849 spr_register(env, SPR_LDSTCR, "LDSTCR",
5850 SPR_NOACCESS, SPR_NOACCESS,
5851 &spr_read_generic, &spr_write_generic,
5852 0x00000000);
5853 /* ICTRL */
5854 /* XXX : not implemented */
5855 spr_register(env, SPR_ICTRL, "ICTRL",
5856 SPR_NOACCESS, SPR_NOACCESS,
5857 &spr_read_generic, &spr_write_generic,
5858 0x00000000);
5859 /* MSSSR0 */
5860 /* XXX : not implemented */
5861 spr_register(env, SPR_MSSSR0, "MSSSR0",
5862 SPR_NOACCESS, SPR_NOACCESS,
5863 &spr_read_generic, &spr_write_generic,
5864 0x00000000);
5865 /* PMC */
5866 /* XXX : not implemented */
5867 spr_register(env, SPR_PMC5, "PMC5",
5868 SPR_NOACCESS, SPR_NOACCESS,
5869 &spr_read_generic, &spr_write_generic,
5870 0x00000000);
5871 /* XXX : not implemented */
5872 spr_register(env, SPR_UPMC5, "UPMC5",
5873 &spr_read_ureg, SPR_NOACCESS,
5874 &spr_read_ureg, SPR_NOACCESS,
5875 0x00000000);
5876 /* XXX : not implemented */
5877 spr_register(env, SPR_PMC6, "PMC6",
5878 SPR_NOACCESS, SPR_NOACCESS,
5879 &spr_read_generic, &spr_write_generic,
5880 0x00000000);
5881 /* XXX : not implemented */
5882 spr_register(env, SPR_UPMC6, "UPMC6",
5883 &spr_read_ureg, SPR_NOACCESS,
5884 &spr_read_ureg, SPR_NOACCESS,
5885 0x00000000);
5886 /* SPRGs */
5887 spr_register(env, SPR_SPRG4, "SPRG4",
5888 SPR_NOACCESS, SPR_NOACCESS,
5889 &spr_read_generic, &spr_write_generic,
5890 0x00000000);
5891 spr_register(env, SPR_USPRG4, "USPRG4",
5892 &spr_read_ureg, SPR_NOACCESS,
5893 &spr_read_ureg, SPR_NOACCESS,
5894 0x00000000);
5895 spr_register(env, SPR_SPRG5, "SPRG5",
5896 SPR_NOACCESS, SPR_NOACCESS,
5897 &spr_read_generic, &spr_write_generic,
5898 0x00000000);
5899 spr_register(env, SPR_USPRG5, "USPRG5",
5900 &spr_read_ureg, SPR_NOACCESS,
5901 &spr_read_ureg, SPR_NOACCESS,
5902 0x00000000);
5903 spr_register(env, SPR_SPRG6, "SPRG6",
5904 SPR_NOACCESS, SPR_NOACCESS,
5905 &spr_read_generic, &spr_write_generic,
5906 0x00000000);
5907 spr_register(env, SPR_USPRG6, "USPRG6",
5908 &spr_read_ureg, SPR_NOACCESS,
5909 &spr_read_ureg, SPR_NOACCESS,
5910 0x00000000);
5911 spr_register(env, SPR_SPRG7, "SPRG7",
5912 SPR_NOACCESS, SPR_NOACCESS,
5913 &spr_read_generic, &spr_write_generic,
5914 0x00000000);
5915 spr_register(env, SPR_USPRG7, "USPRG7",
5916 &spr_read_ureg, SPR_NOACCESS,
5917 &spr_read_ureg, SPR_NOACCESS,
5918 0x00000000);
5919 /* Memory management */
5920 gen_low_BATs(env);
5921 gen_high_BATs(env);
5922 gen_74xx_soft_tlb(env, 128, 2);
5923 init_excp_7450(env);
5924 env->dcache_line_size = 32;
5925 env->icache_line_size = 32;
5926 /* Allocate hardware IRQ controller */
5927 ppc6xx_irq_init(env);
5928 }
5929
5930 /* PowerPC 7455 (aka G4) */
5931 #define POWERPC_INSNS_7455 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5932 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5933 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5934 PPC_FLOAT_STFIWX | \
5935 PPC_CACHE | PPC_CACHE_ICBI | \
5936 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5937 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5938 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5939 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5940 PPC_SEGMENT | PPC_EXTERN | \
5941 PPC_ALTIVEC)
5942 #define POWERPC_INSNS2_7455 (PPC_NONE)
5943 #define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
5944 #define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
5945 #define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
5946 #define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
5947 #define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
5948 #define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5949 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5950 POWERPC_FLAG_BUS_CLK)
5951 #define check_pow_7455 check_pow_hid0_74xx
5952
5953 __attribute__ (( unused ))
5954 static void init_proc_7455 (CPUPPCState *env)
5955 {
5956 gen_spr_ne_601(env);
5957 gen_spr_7xx(env);
5958 /* Time base */
5959 gen_tbl(env);
5960 /* 74xx specific SPR */
5961 gen_spr_74xx(env);
5962 /* Level 3 cache control */
5963 gen_l3_ctrl(env);
5964 /* LDSTCR */
5965 /* XXX : not implemented */
5966 spr_register(env, SPR_LDSTCR, "LDSTCR",
5967 SPR_NOACCESS, SPR_NOACCESS,
5968 &spr_read_generic, &spr_write_generic,
5969 0x00000000);
5970 /* ICTRL */
5971 /* XXX : not implemented */
5972 spr_register(env, SPR_ICTRL, "ICTRL",
5973 SPR_NOACCESS, SPR_NOACCESS,
5974 &spr_read_generic, &spr_write_generic,
5975 0x00000000);
5976 /* MSSSR0 */
5977 /* XXX : not implemented */
5978 spr_register(env, SPR_MSSSR0, "MSSSR0",
5979 SPR_NOACCESS, SPR_NOACCESS,
5980 &spr_read_generic, &spr_write_generic,
5981 0x00000000);
5982 /* PMC */
5983 /* XXX : not implemented */
5984 spr_register(env, SPR_PMC5, "PMC5",
5985 SPR_NOACCESS, SPR_NOACCESS,
5986 &spr_read_generic, &spr_write_generic,
5987 0x00000000);
5988 /* XXX : not implemented */
5989 spr_register(env, SPR_UPMC5, "UPMC5",
5990 &spr_read_ureg, SPR_NOACCESS,
5991 &spr_read_ureg, SPR_NOACCESS,
5992 0x00000000);
5993 /* XXX : not implemented */
5994 spr_register(env, SPR_PMC6, "PMC6",
5995 SPR_NOACCESS, SPR_NOACCESS,
5996 &spr_read_generic, &spr_write_generic,
5997 0x00000000);
5998 /* XXX : not implemented */
5999 spr_register(env, SPR_UPMC6, "UPMC6",
6000 &spr_read_ureg, SPR_NOACCESS,
6001 &spr_read_ureg, SPR_NOACCESS,
6002 0x00000000);
6003 /* SPRGs */
6004 spr_register(env, SPR_SPRG4, "SPRG4",
6005 SPR_NOACCESS, SPR_NOACCESS,
6006 &spr_read_generic, &spr_write_generic,
6007 0x00000000);
6008 spr_register(env, SPR_USPRG4, "USPRG4",
6009 &spr_read_ureg, SPR_NOACCESS,
6010 &spr_read_ureg, SPR_NOACCESS,
6011 0x00000000);
6012 spr_register(env, SPR_SPRG5, "SPRG5",
6013 SPR_NOACCESS, SPR_NOACCESS,
6014 &spr_read_generic, &spr_write_generic,
6015 0x00000000);
6016 spr_register(env, SPR_USPRG5, "USPRG5",
6017 &spr_read_ureg, SPR_NOACCESS,
6018 &spr_read_ureg, SPR_NOACCESS,
6019 0x00000000);
6020 spr_register(env, SPR_SPRG6, "SPRG6",
6021 SPR_NOACCESS, SPR_NOACCESS,
6022 &spr_read_generic, &spr_write_generic,
6023 0x00000000);
6024 spr_register(env, SPR_USPRG6, "USPRG6",
6025 &spr_read_ureg, SPR_NOACCESS,
6026 &spr_read_ureg, SPR_NOACCESS,
6027 0x00000000);
6028 spr_register(env, SPR_SPRG7, "SPRG7",
6029 SPR_NOACCESS, SPR_NOACCESS,
6030 &spr_read_generic, &spr_write_generic,
6031 0x00000000);
6032 spr_register(env, SPR_USPRG7, "USPRG7",
6033 &spr_read_ureg, SPR_NOACCESS,
6034 &spr_read_ureg, SPR_NOACCESS,
6035 0x00000000);
6036 /* Memory management */
6037 gen_low_BATs(env);
6038 gen_high_BATs(env);
6039 gen_74xx_soft_tlb(env, 128, 2);
6040 init_excp_7450(env);
6041 env->dcache_line_size = 32;
6042 env->icache_line_size = 32;
6043 /* Allocate hardware IRQ controller */
6044 ppc6xx_irq_init(env);
6045 }
6046
6047 /* PowerPC 7457 (aka G4) */
6048 #define POWERPC_INSNS_7457 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6049 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6050 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6051 PPC_FLOAT_STFIWX | \
6052 PPC_CACHE | PPC_CACHE_ICBI | \
6053 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
6054 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6055 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6056 PPC_MEM_TLBIA | PPC_74xx_TLB | \
6057 PPC_SEGMENT | PPC_EXTERN | \
6058 PPC_ALTIVEC)
6059 #define POWERPC_INSNS2_7457 (PPC_NONE)
6060 #define POWERPC_MSRM_7457 (0x000000000205FF77ULL)
6061 #define POWERPC_MMU_7457 (POWERPC_MMU_SOFT_74xx)
6062 #define POWERPC_EXCP_7457 (POWERPC_EXCP_74xx)
6063 #define POWERPC_INPUT_7457 (PPC_FLAGS_INPUT_6xx)
6064 #define POWERPC_BFDM_7457 (bfd_mach_ppc_7400)
6065 #define POWERPC_FLAG_7457 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6066 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6067 POWERPC_FLAG_BUS_CLK)
6068 #define check_pow_7457 check_pow_hid0_74xx
6069
6070 __attribute__ (( unused ))
6071 static void init_proc_7457 (CPUPPCState *env)
6072 {
6073 gen_spr_ne_601(env);
6074 gen_spr_7xx(env);
6075 /* Time base */
6076 gen_tbl(env);
6077 /* 74xx specific SPR */
6078 gen_spr_74xx(env);
6079 /* Level 3 cache control */
6080 gen_l3_ctrl(env);
6081 /* L3ITCR1 */
6082 /* XXX : not implemented */
6083 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6084 SPR_NOACCESS, SPR_NOACCESS,
6085 &spr_read_generic, &spr_write_generic,
6086 0x00000000);
6087 /* L3ITCR2 */
6088 /* XXX : not implemented */
6089 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6090 SPR_NOACCESS, SPR_NOACCESS,
6091 &spr_read_generic, &spr_write_generic,
6092 0x00000000);
6093 /* L3ITCR3 */
6094 /* XXX : not implemented */
6095 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6096 SPR_NOACCESS, SPR_NOACCESS,
6097 &spr_read_generic, &spr_write_generic,
6098 0x00000000);
6099 /* L3OHCR */
6100 /* XXX : not implemented */
6101 spr_register(env, SPR_L3OHCR, "L3OHCR",
6102 SPR_NOACCESS, SPR_NOACCESS,
6103 &spr_read_generic, &spr_write_generic,
6104 0x00000000);
6105 /* LDSTCR */
6106 /* XXX : not implemented */
6107 spr_register(env, SPR_LDSTCR, "LDSTCR",
6108 SPR_NOACCESS, SPR_NOACCESS,
6109 &spr_read_generic, &spr_write_generic,
6110 0x00000000);
6111 /* ICTRL */
6112 /* XXX : not implemented */
6113 spr_register(env, SPR_ICTRL, "ICTRL",
6114 SPR_NOACCESS, SPR_NOACCESS,
6115 &spr_read_generic, &spr_write_generic,
6116 0x00000000);
6117 /* MSSSR0 */
6118 /* XXX : not implemented */
6119 spr_register(env, SPR_MSSSR0, "MSSSR0",
6120 SPR_NOACCESS, SPR_NOACCESS,
6121 &spr_read_generic, &spr_write_generic,
6122 0x00000000);
6123 /* PMC */
6124 /* XXX : not implemented */
6125 spr_register(env, SPR_PMC5, "PMC5",
6126 SPR_NOACCESS, SPR_NOACCESS,
6127 &spr_read_generic, &spr_write_generic,
6128 0x00000000);
6129 /* XXX : not implemented */
6130 spr_register(env, SPR_UPMC5, "UPMC5",
6131 &spr_read_ureg, SPR_NOACCESS,
6132 &spr_read_ureg, SPR_NOACCESS,
6133 0x00000000);
6134 /* XXX : not implemented */
6135 spr_register(env, SPR_PMC6, "PMC6",
6136 SPR_NOACCESS, SPR_NOACCESS,
6137 &spr_read_generic, &spr_write_generic,
6138 0x00000000);
6139 /* XXX : not implemented */
6140 spr_register(env, SPR_UPMC6, "UPMC6",
6141 &spr_read_ureg, SPR_NOACCESS,
6142 &spr_read_ureg, SPR_NOACCESS,
6143 0x00000000);
6144 /* SPRGs */
6145 spr_register(env, SPR_SPRG4, "SPRG4",
6146 SPR_NOACCESS, SPR_NOACCESS,
6147 &spr_read_generic, &spr_write_generic,
6148 0x00000000);
6149 spr_register(env, SPR_USPRG4, "USPRG4",
6150 &spr_read_ureg, SPR_NOACCESS,
6151 &spr_read_ureg, SPR_NOACCESS,
6152 0x00000000);
6153 spr_register(env, SPR_SPRG5, "SPRG5",
6154 SPR_NOACCESS, SPR_NOACCESS,
6155 &spr_read_generic, &spr_write_generic,
6156 0x00000000);
6157 spr_register(env, SPR_USPRG5, "USPRG5",
6158 &spr_read_ureg, SPR_NOACCESS,
6159 &spr_read_ureg, SPR_NOACCESS,
6160 0x00000000);
6161 spr_register(env, SPR_SPRG6, "SPRG6",
6162 SPR_NOACCESS, SPR_NOACCESS,
6163 &spr_read_generic, &spr_write_generic,
6164 0x00000000);
6165 spr_register(env, SPR_USPRG6, "USPRG6",
6166 &spr_read_ureg, SPR_NOACCESS,
6167 &spr_read_ureg, SPR_NOACCESS,
6168 0x00000000);
6169 spr_register(env, SPR_SPRG7, "SPRG7",
6170 SPR_NOACCESS, SPR_NOACCESS,
6171 &spr_read_generic, &spr_write_generic,
6172 0x00000000);
6173 spr_register(env, SPR_USPRG7, "USPRG7",
6174 &spr_read_ureg, SPR_NOACCESS,
6175 &spr_read_ureg, SPR_NOACCESS,
6176 0x00000000);
6177 /* Memory management */
6178 gen_low_BATs(env);
6179 gen_high_BATs(env);
6180 gen_74xx_soft_tlb(env, 128, 2);
6181 init_excp_7450(env);
6182 env->dcache_line_size = 32;
6183 env->icache_line_size = 32;
6184 /* Allocate hardware IRQ controller */
6185 ppc6xx_irq_init(env);
6186 }
6187
6188 #if defined (TARGET_PPC64)
6189 /* PowerPC 970 */
6190 #define POWERPC_INSNS_970 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6191 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6192 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6193 PPC_FLOAT_STFIWX | \
6194 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6195 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6196 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6197 PPC_64B | PPC_ALTIVEC | \
6198 PPC_SEGMENT_64B | PPC_SLBI)
6199 #define POWERPC_INSNS2_970 (PPC_NONE)
6200 #define POWERPC_MSRM_970 (0x900000000204FF36ULL)
6201 #define POWERPC_MMU_970 (POWERPC_MMU_64B)
6202 //#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
6203 #define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
6204 #define POWERPC_BFDM_970 (bfd_mach_ppc64)
6205 #define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6206 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6207 POWERPC_FLAG_BUS_CLK)
6208
6209 #if defined(CONFIG_USER_ONLY)
6210 #define POWERPC970_HID5_INIT 0x00000080
6211 #else
6212 #define POWERPC970_HID5_INIT 0x00000000
6213 #endif
6214
6215 static int check_pow_970 (CPUPPCState *env)
6216 {
6217 if (env->spr[SPR_HID0] & 0x00600000)
6218 return 1;
6219
6220 return 0;
6221 }
6222
6223 static void init_proc_970 (CPUPPCState *env)
6224 {
6225 gen_spr_ne_601(env);
6226 gen_spr_7xx(env);
6227 /* Time base */
6228 gen_tbl(env);
6229 /* Hardware implementation registers */
6230 /* XXX : not implemented */
6231 spr_register(env, SPR_HID0, "HID0",
6232 SPR_NOACCESS, SPR_NOACCESS,
6233 &spr_read_generic, &spr_write_clear,
6234 0x60000000);
6235 /* XXX : not implemented */
6236 spr_register(env, SPR_HID1, "HID1",
6237 SPR_NOACCESS, SPR_NOACCESS,
6238 &spr_read_generic, &spr_write_generic,
6239 0x00000000);
6240 /* XXX : not implemented */
6241 spr_register(env, SPR_750FX_HID2, "HID2",
6242 SPR_NOACCESS, SPR_NOACCESS,
6243 &spr_read_generic, &spr_write_generic,
6244 0x00000000);
6245 /* XXX : not implemented */
6246 spr_register(env, SPR_970_HID5, "HID5",
6247 SPR_NOACCESS, SPR_NOACCESS,
6248 &spr_read_generic, &spr_write_generic,
6249 POWERPC970_HID5_INIT);
6250 /* XXX : not implemented */
6251 spr_register(env, SPR_L2CR, "L2CR",
6252 SPR_NOACCESS, SPR_NOACCESS,
6253 &spr_read_generic, &spr_write_generic,
6254 0x00000000);
6255 /* Memory management */
6256 /* XXX: not correct */
6257 gen_low_BATs(env);
6258 /* XXX : not implemented */
6259 spr_register(env, SPR_MMUCFG, "MMUCFG",
6260 SPR_NOACCESS, SPR_NOACCESS,
6261 &spr_read_generic, SPR_NOACCESS,
6262 0x00000000); /* TOFIX */
6263 /* XXX : not implemented */
6264 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6265 SPR_NOACCESS, SPR_NOACCESS,
6266 &spr_read_generic, &spr_write_generic,
6267 0x00000000); /* TOFIX */
6268 spr_register(env, SPR_HIOR, "SPR_HIOR",
6269 SPR_NOACCESS, SPR_NOACCESS,
6270 &spr_read_hior, &spr_write_hior,
6271 0x00000000);
6272 #if !defined(CONFIG_USER_ONLY)
6273 env->slb_nr = 32;
6274 #endif
6275 init_excp_970(env);
6276 env->dcache_line_size = 128;
6277 env->icache_line_size = 128;
6278 /* Allocate hardware IRQ controller */
6279 ppc970_irq_init(env);
6280 /* Can't find information on what this should be on reset. This
6281 * value is the one used by 74xx processors. */
6282 vscr_init(env, 0x00010000);
6283 }
6284
6285 /* PowerPC 970FX (aka G5) */
6286 #define POWERPC_INSNS_970FX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6287 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6288 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6289 PPC_FLOAT_STFIWX | \
6290 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6291 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6292 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6293 PPC_64B | PPC_ALTIVEC | \
6294 PPC_SEGMENT_64B | PPC_SLBI)
6295 #define POWERPC_INSNS2_970FX (PPC_NONE)
6296 #define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
6297 #define POWERPC_MMU_970FX (POWERPC_MMU_64B)
6298 #define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
6299 #define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
6300 #define POWERPC_BFDM_970FX (bfd_mach_ppc64)
6301 #define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6302 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6303 POWERPC_FLAG_BUS_CLK)
6304
6305 static int check_pow_970FX (CPUPPCState *env)
6306 {
6307 if (env->spr[SPR_HID0] & 0x00600000)
6308 return 1;
6309
6310 return 0;
6311 }
6312
6313 static void init_proc_970FX (CPUPPCState *env)
6314 {
6315 gen_spr_ne_601(env);
6316 gen_spr_7xx(env);
6317 /* Time base */
6318 gen_tbl(env);
6319 /* Hardware implementation registers */
6320 /* XXX : not implemented */
6321 spr_register(env, SPR_HID0, "HID0",
6322 SPR_NOACCESS, SPR_NOACCESS,
6323 &spr_read_generic, &spr_write_clear,
6324 0x60000000);
6325 /* XXX : not implemented */
6326 spr_register(env, SPR_HID1, "HID1",
6327 SPR_NOACCESS, SPR_NOACCESS,
6328 &spr_read_generic, &spr_write_generic,
6329 0x00000000);
6330 /* XXX : not implemented */
6331 spr_register(env, SPR_750FX_HID2, "HID2",
6332 SPR_NOACCESS, SPR_NOACCESS,
6333 &spr_read_generic, &spr_write_generic,
6334 0x00000000);
6335 /* XXX : not implemented */
6336 spr_register(env, SPR_970_HID5, "HID5",
6337 SPR_NOACCESS, SPR_NOACCESS,
6338 &spr_read_generic, &spr_write_generic,
6339 POWERPC970_HID5_INIT);
6340 /* XXX : not implemented */
6341 spr_register(env, SPR_L2CR, "L2CR",
6342 SPR_NOACCESS, SPR_NOACCESS,
6343 &spr_read_generic, &spr_write_generic,
6344 0x00000000);
6345 /* Memory management */
6346 /* XXX: not correct */
6347 gen_low_BATs(env);
6348 /* XXX : not implemented */
6349 spr_register(env, SPR_MMUCFG, "MMUCFG",
6350 SPR_NOACCESS, SPR_NOACCESS,
6351 &spr_read_generic, SPR_NOACCESS,
6352 0x00000000); /* TOFIX */
6353 /* XXX : not implemented */
6354 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6355 SPR_NOACCESS, SPR_NOACCESS,
6356 &spr_read_generic, &spr_write_generic,
6357 0x00000000); /* TOFIX */
6358 spr_register(env, SPR_HIOR, "SPR_HIOR",
6359 SPR_NOACCESS, SPR_NOACCESS,
6360 &spr_read_hior, &spr_write_hior,
6361 0x00000000);
6362 spr_register(env, SPR_CTRL, "SPR_CTRL",
6363 SPR_NOACCESS, SPR_NOACCESS,
6364 &spr_read_generic, &spr_write_generic,
6365 0x00000000);
6366 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6367 SPR_NOACCESS, SPR_NOACCESS,
6368 &spr_read_generic, &spr_write_generic,
6369 0x00000000);
6370 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6371 &spr_read_generic, &spr_write_generic,
6372 &spr_read_generic, &spr_write_generic,
6373 0x00000000);
6374 #if !defined(CONFIG_USER_ONLY)
6375 env->slb_nr = 64;
6376 #endif
6377 init_excp_970(env);
6378 env->dcache_line_size = 128;
6379 env->icache_line_size = 128;
6380 /* Allocate hardware IRQ controller */
6381 ppc970_irq_init(env);
6382 /* Can't find information on what this should be on reset. This
6383 * value is the one used by 74xx processors. */
6384 vscr_init(env, 0x00010000);
6385 }
6386
6387 /* PowerPC 970 GX */
6388 #define POWERPC_INSNS_970GX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6389 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6390 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6391 PPC_FLOAT_STFIWX | \
6392 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6393 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6394 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6395 PPC_64B | PPC_ALTIVEC | \
6396 PPC_SEGMENT_64B | PPC_SLBI)
6397 #define POWERPC_INSNS2_970GX (PPC_NONE)
6398 #define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
6399 #define POWERPC_MMU_970GX (POWERPC_MMU_64B)
6400 #define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
6401 #define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
6402 #define POWERPC_BFDM_970GX (bfd_mach_ppc64)
6403 #define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6404 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6405 POWERPC_FLAG_BUS_CLK)
6406
6407 static int check_pow_970GX (CPUPPCState *env)
6408 {
6409 if (env->spr[SPR_HID0] & 0x00600000)
6410 return 1;
6411
6412 return 0;
6413 }
6414
6415 static void init_proc_970GX (CPUPPCState *env)
6416 {
6417 gen_spr_ne_601(env);
6418 gen_spr_7xx(env);
6419 /* Time base */
6420 gen_tbl(env);
6421 /* Hardware implementation registers */
6422 /* XXX : not implemented */
6423 spr_register(env, SPR_HID0, "HID0",
6424 SPR_NOACCESS, SPR_NOACCESS,
6425 &spr_read_generic, &spr_write_clear,
6426 0x60000000);
6427 /* XXX : not implemented */
6428 spr_register(env, SPR_HID1, "HID1",
6429 SPR_NOACCESS, SPR_NOACCESS,
6430 &spr_read_generic, &spr_write_generic,
6431 0x00000000);
6432 /* XXX : not implemented */
6433 spr_register(env, SPR_750FX_HID2, "HID2",
6434 SPR_NOACCESS, SPR_NOACCESS,
6435 &spr_read_generic, &spr_write_generic,
6436 0x00000000);
6437 /* XXX : not implemented */
6438 spr_register(env, SPR_970_HID5, "HID5",
6439 SPR_NOACCESS, SPR_NOACCESS,
6440 &spr_read_generic, &spr_write_generic,
6441 POWERPC970_HID5_INIT);
6442 /* XXX : not implemented */
6443 spr_register(env, SPR_L2CR, "L2CR",
6444 SPR_NOACCESS, SPR_NOACCESS,
6445 &spr_read_generic, &spr_write_generic,
6446 0x00000000);
6447 /* Memory management */
6448 /* XXX: not correct */
6449 gen_low_BATs(env);
6450 /* XXX : not implemented */
6451 spr_register(env, SPR_MMUCFG, "MMUCFG",
6452 SPR_NOACCESS, SPR_NOACCESS,
6453 &spr_read_generic, SPR_NOACCESS,
6454 0x00000000); /* TOFIX */
6455 /* XXX : not implemented */
6456 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6457 SPR_NOACCESS, SPR_NOACCESS,
6458 &spr_read_generic, &spr_write_generic,
6459 0x00000000); /* TOFIX */
6460 spr_register(env, SPR_HIOR, "SPR_HIOR",
6461 SPR_NOACCESS, SPR_NOACCESS,
6462 &spr_read_hior, &spr_write_hior,
6463 0x00000000);
6464 #if !defined(CONFIG_USER_ONLY)
6465 env->slb_nr = 32;
6466 #endif
6467 init_excp_970(env);
6468 env->dcache_line_size = 128;
6469 env->icache_line_size = 128;
6470 /* Allocate hardware IRQ controller */
6471 ppc970_irq_init(env);
6472 /* Can't find information on what this should be on reset. This
6473 * value is the one used by 74xx processors. */
6474 vscr_init(env, 0x00010000);
6475 }
6476
6477 /* PowerPC 970 MP */
6478 #define POWERPC_INSNS_970MP (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6479 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6480 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6481 PPC_FLOAT_STFIWX | \
6482 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6483 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6484 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6485 PPC_64B | PPC_ALTIVEC | \
6486 PPC_SEGMENT_64B | PPC_SLBI)
6487 #define POWERPC_INSNS2_970MP (PPC_NONE)
6488 #define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
6489 #define POWERPC_MMU_970MP (POWERPC_MMU_64B)
6490 #define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
6491 #define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970)
6492 #define POWERPC_BFDM_970MP (bfd_mach_ppc64)
6493 #define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6494 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6495 POWERPC_FLAG_BUS_CLK)
6496
6497 static int check_pow_970MP (CPUPPCState *env)
6498 {
6499 if (env->spr[SPR_HID0] & 0x01C00000)
6500 return 1;
6501
6502 return 0;
6503 }
6504
6505 static void init_proc_970MP (CPUPPCState *env)
6506 {
6507 gen_spr_ne_601(env);
6508 gen_spr_7xx(env);
6509 /* Time base */
6510 gen_tbl(env);
6511 /* Hardware implementation registers */
6512 /* XXX : not implemented */
6513 spr_register(env, SPR_HID0, "HID0",
6514 SPR_NOACCESS, SPR_NOACCESS,
6515 &spr_read_generic, &spr_write_clear,
6516 0x60000000);
6517 /* XXX : not implemented */
6518 spr_register(env, SPR_HID1, "HID1",
6519 SPR_NOACCESS, SPR_NOACCESS,
6520 &spr_read_generic, &spr_write_generic,
6521 0x00000000);
6522 /* XXX : not implemented */
6523 spr_register(env, SPR_750FX_HID2, "HID2",
6524 SPR_NOACCESS, SPR_NOACCESS,
6525 &spr_read_generic, &spr_write_generic,
6526 0x00000000);
6527 /* XXX : not implemented */
6528 spr_register(env, SPR_970_HID5, "HID5",
6529 SPR_NOACCESS, SPR_NOACCESS,
6530 &spr_read_generic, &spr_write_generic,
6531 POWERPC970_HID5_INIT);
6532 /* XXX : not implemented */
6533 spr_register(env, SPR_L2CR, "L2CR",
6534 SPR_NOACCESS, SPR_NOACCESS,
6535 &spr_read_generic, &spr_write_generic,
6536 0x00000000);
6537 /* Memory management */
6538 /* XXX: not correct */
6539 gen_low_BATs(env);
6540 /* XXX : not implemented */
6541 spr_register(env, SPR_MMUCFG, "MMUCFG",
6542 SPR_NOACCESS, SPR_NOACCESS,
6543 &spr_read_generic, SPR_NOACCESS,
6544 0x00000000); /* TOFIX */
6545 /* XXX : not implemented */
6546 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6547 SPR_NOACCESS, SPR_NOACCESS,
6548 &spr_read_generic, &spr_write_generic,
6549 0x00000000); /* TOFIX */
6550 spr_register(env, SPR_HIOR, "SPR_HIOR",
6551 SPR_NOACCESS, SPR_NOACCESS,
6552 &spr_read_hior, &spr_write_hior,
6553 0x00000000);
6554 #if !defined(CONFIG_USER_ONLY)
6555 env->slb_nr = 32;
6556 #endif
6557 init_excp_970(env);
6558 env->dcache_line_size = 128;
6559 env->icache_line_size = 128;
6560 /* Allocate hardware IRQ controller */
6561 ppc970_irq_init(env);
6562 /* Can't find information on what this should be on reset. This
6563 * value is the one used by 74xx processors. */
6564 vscr_init(env, 0x00010000);
6565 }
6566
6567 #if defined(TARGET_PPC64)
6568 /* POWER7 */
6569 #define POWERPC_INSNS_POWER7 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6570 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6571 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6572 PPC_FLOAT_STFIWX | \
6573 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6574 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6575 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6576 PPC_64B | PPC_ALTIVEC | \
6577 PPC_SEGMENT_64B | PPC_SLBI | \
6578 PPC_POPCNTB | PPC_POPCNTWD)
6579 #define POWERPC_INSNS2_POWER7 (PPC2_VSX | PPC2_DFP | PPC2_DBRX)
6580 #define POWERPC_MSRM_POWER7 (0x800000000204FF36ULL)
6581 #define POWERPC_MMU_POWER7 (POWERPC_MMU_2_06)
6582 #define POWERPC_EXCP_POWER7 (POWERPC_EXCP_POWER7)
6583 #define POWERPC_INPUT_POWER7 (PPC_FLAGS_INPUT_POWER7)
6584 #define POWERPC_BFDM_POWER7 (bfd_mach_ppc64)
6585 #define POWERPC_FLAG_POWER7 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6586 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6587 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR)
6588 #define check_pow_POWER7 check_pow_nocheck
6589
6590 static void init_proc_POWER7 (CPUPPCState *env)
6591 {
6592 gen_spr_ne_601(env);
6593 gen_spr_7xx(env);
6594 /* Time base */
6595 gen_tbl(env);
6596 /* Processor identification */
6597 spr_register(env, SPR_PIR, "PIR",
6598 SPR_NOACCESS, SPR_NOACCESS,
6599 &spr_read_generic, &spr_write_pir,
6600 0x00000000);
6601 #if !defined(CONFIG_USER_ONLY)
6602 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
6603 spr_register(env, SPR_PURR, "PURR",
6604 &spr_read_purr, SPR_NOACCESS,
6605 &spr_read_purr, SPR_NOACCESS,
6606 0x00000000);
6607 spr_register(env, SPR_SPURR, "SPURR",
6608 &spr_read_purr, SPR_NOACCESS,
6609 &spr_read_purr, SPR_NOACCESS,
6610 0x00000000);
6611 spr_register(env, SPR_CFAR, "SPR_CFAR",
6612 SPR_NOACCESS, SPR_NOACCESS,
6613 &spr_read_cfar, &spr_write_cfar,
6614 0x00000000);
6615 spr_register(env, SPR_DSCR, "SPR_DSCR",
6616 SPR_NOACCESS, SPR_NOACCESS,
6617 &spr_read_generic, &spr_write_generic,
6618 0x00000000);
6619 #endif /* !CONFIG_USER_ONLY */
6620 /* Memory management */
6621 /* XXX : not implemented */
6622 spr_register(env, SPR_MMUCFG, "MMUCFG",
6623 SPR_NOACCESS, SPR_NOACCESS,
6624 &spr_read_generic, SPR_NOACCESS,
6625 0x00000000); /* TOFIX */
6626 /* XXX : not implemented */
6627 spr_register(env, SPR_CTRL, "SPR_CTRLT",
6628 SPR_NOACCESS, SPR_NOACCESS,
6629 &spr_read_generic, &spr_write_generic,
6630 0x80800000);
6631 spr_register(env, SPR_UCTRL, "SPR_CTRLF",
6632 SPR_NOACCESS, SPR_NOACCESS,
6633 &spr_read_generic, &spr_write_generic,
6634 0x80800000);
6635 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6636 &spr_read_generic, &spr_write_generic,
6637 &spr_read_generic, &spr_write_generic,
6638 0x00000000);
6639 #if !defined(CONFIG_USER_ONLY)
6640 env->slb_nr = 32;
6641 #endif
6642 init_excp_POWER7(env);
6643 env->dcache_line_size = 128;
6644 env->icache_line_size = 128;
6645 /* Allocate hardware IRQ controller */
6646 ppcPOWER7_irq_init(env);
6647 /* Can't find information on what this should be on reset. This
6648 * value is the one used by 74xx processors. */
6649 vscr_init(env, 0x00010000);
6650 }
6651 #endif /* TARGET_PPC64 */
6652
6653 /* PowerPC 620 */
6654 #define POWERPC_INSNS_620 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6655 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6656 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6657 PPC_FLOAT_STFIWX | \
6658 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
6659 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6660 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6661 PPC_SEGMENT | PPC_EXTERN | \
6662 PPC_64B | PPC_SLBI)
6663 #define POWERPC_INSNS2_620 (PPC_NONE)
6664 #define POWERPC_MSRM_620 (0x800000000005FF77ULL)
6665 //#define POWERPC_MMU_620 (POWERPC_MMU_620)
6666 #define POWERPC_EXCP_620 (POWERPC_EXCP_970)
6667 #define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx)
6668 #define POWERPC_BFDM_620 (bfd_mach_ppc64)
6669 #define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
6670 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
6671 #define check_pow_620 check_pow_nocheck /* Check this */
6672
6673 __attribute__ (( unused ))
6674 static void init_proc_620 (CPUPPCState *env)
6675 {
6676 gen_spr_ne_601(env);
6677 gen_spr_620(env);
6678 /* Time base */
6679 gen_tbl(env);
6680 /* Hardware implementation registers */
6681 /* XXX : not implemented */
6682 spr_register(env, SPR_HID0, "HID0",
6683 SPR_NOACCESS, SPR_NOACCESS,
6684 &spr_read_generic, &spr_write_generic,
6685 0x00000000);
6686 /* Memory management */
6687 gen_low_BATs(env);
6688 init_excp_620(env);
6689 env->dcache_line_size = 64;
6690 env->icache_line_size = 64;
6691 /* Allocate hardware IRQ controller */
6692 ppc6xx_irq_init(env);
6693 }
6694 #endif /* defined (TARGET_PPC64) */
6695
6696 /* Default 32 bits PowerPC target will be 604 */
6697 #define CPU_POWERPC_PPC32 CPU_POWERPC_604
6698 #define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
6699 #define POWERPC_INSNS2_PPC32 POWERPC_INSNS2_604
6700 #define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
6701 #define POWERPC_MMU_PPC32 POWERPC_MMU_604
6702 #define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
6703 #define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
6704 #define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
6705 #define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
6706 #define check_pow_PPC32 check_pow_604
6707 #define init_proc_PPC32 init_proc_604
6708
6709 /* Default 64 bits PowerPC target will be 970 FX */
6710 #define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
6711 #define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
6712 #define POWERPC_INSNS2_PPC64 POWERPC_INSNS2_970FX
6713 #define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
6714 #define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
6715 #define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
6716 #define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
6717 #define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
6718 #define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
6719 #define check_pow_PPC64 check_pow_970FX
6720 #define init_proc_PPC64 init_proc_970FX
6721
6722 /* Default PowerPC target will be PowerPC 32 */
6723 #if defined (TARGET_PPC64) && 0 // XXX: TODO
6724 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
6725 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
6726 #define POWERPC_INSNS2_DEFAULT POWERPC_INSNS2_PPC64
6727 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
6728 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
6729 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
6730 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
6731 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
6732 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
6733 #define check_pow_DEFAULT check_pow_PPC64
6734 #define init_proc_DEFAULT init_proc_PPC64
6735 #else
6736 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
6737 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
6738 #define POWERPC_INSNS2_DEFAULT POWERPC_INSNS2_PPC32
6739 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
6740 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
6741 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
6742 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
6743 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
6744 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
6745 #define check_pow_DEFAULT check_pow_PPC32
6746 #define init_proc_DEFAULT init_proc_PPC32
6747 #endif
6748
6749 /*****************************************************************************/
6750 /* PVR definitions for most known PowerPC */
6751 enum {
6752 /* PowerPC 401 family */
6753 /* Generic PowerPC 401 */
6754 #define CPU_POWERPC_401 CPU_POWERPC_401G2
6755 /* PowerPC 401 cores */
6756 CPU_POWERPC_401A1 = 0x00210000,
6757 CPU_POWERPC_401B2 = 0x00220000,
6758 #if 0
6759 CPU_POWERPC_401B3 = xxx,
6760 #endif
6761 CPU_POWERPC_401C2 = 0x00230000,
6762 CPU_POWERPC_401D2 = 0x00240000,
6763 CPU_POWERPC_401E2 = 0x00250000,
6764 CPU_POWERPC_401F2 = 0x00260000,
6765 CPU_POWERPC_401G2 = 0x00270000,
6766 /* PowerPC 401 microcontrolers */
6767 #if 0
6768 CPU_POWERPC_401GF = xxx,
6769 #endif
6770 #define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
6771 /* IBM Processor for Network Resources */
6772 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
6773 #if 0
6774 CPU_POWERPC_XIPCHIP = xxx,
6775 #endif
6776 /* PowerPC 403 family */
6777 /* Generic PowerPC 403 */
6778 #define CPU_POWERPC_403 CPU_POWERPC_403GC
6779 /* PowerPC 403 microcontrollers */
6780 CPU_POWERPC_403GA = 0x00200011,
6781 CPU_POWERPC_403GB = 0x00200100,
6782 CPU_POWERPC_403GC = 0x00200200,
6783 CPU_POWERPC_403GCX = 0x00201400,
6784 #if 0
6785 CPU_POWERPC_403GP = xxx,
6786 #endif
6787 /* PowerPC 405 family */
6788 /* Generic PowerPC 405 */
6789 #define CPU_POWERPC_405 CPU_POWERPC_405D4
6790 /* PowerPC 405 cores */
6791 #if 0
6792 CPU_POWERPC_405A3 = xxx,
6793 #endif
6794 #if 0
6795 CPU_POWERPC_405A4 = xxx,
6796 #endif
6797 #if 0
6798 CPU_POWERPC_405B3 = xxx,
6799 #endif
6800 #if 0
6801 CPU_POWERPC_405B4 = xxx,
6802 #endif
6803 #if 0
6804 CPU_POWERPC_405C3 = xxx,
6805 #endif
6806 #if 0
6807 CPU_POWERPC_405C4 = xxx,
6808 #endif
6809 CPU_POWERPC_405D2 = 0x20010000,
6810 #if 0
6811 CPU_POWERPC_405D3 = xxx,
6812 #endif
6813 CPU_POWERPC_405D4 = 0x41810000,
6814 #if 0
6815 CPU_POWERPC_405D5 = xxx,
6816 #endif
6817 #if 0
6818 CPU_POWERPC_405E4 = xxx,
6819 #endif
6820 #if 0
6821 CPU_POWERPC_405F4 = xxx,
6822 #endif
6823 #if 0
6824 CPU_POWERPC_405F5 = xxx,
6825 #endif
6826 #if 0
6827 CPU_POWERPC_405F6 = xxx,
6828 #endif
6829 /* PowerPC 405 microcontrolers */
6830 /* XXX: missing 0x200108a0 */
6831 #define CPU_POWERPC_405CR CPU_POWERPC_405CRc
6832 CPU_POWERPC_405CRa = 0x40110041,
6833 CPU_POWERPC_405CRb = 0x401100C5,
6834 CPU_POWERPC_405CRc = 0x40110145,
6835 CPU_POWERPC_405EP = 0x51210950,
6836 #if 0
6837 CPU_POWERPC_405EXr = xxx,
6838 #endif
6839 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
6840 #if 0
6841 CPU_POWERPC_405FX = xxx,
6842 #endif
6843 #define CPU_POWERPC_405GP CPU_POWERPC_405GPd
6844 CPU_POWERPC_405GPa = 0x40110000,
6845 CPU_POWERPC_405GPb = 0x40110040,
6846 CPU_POWERPC_405GPc = 0x40110082,
6847 CPU_POWERPC_405GPd = 0x401100C4,
6848 #define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
6849 CPU_POWERPC_405GPR = 0x50910951,
6850 #if 0
6851 CPU_POWERPC_405H = xxx,
6852 #endif
6853 #if 0
6854 CPU_POWERPC_405L = xxx,
6855 #endif
6856 CPU_POWERPC_405LP = 0x41F10000,
6857 #if 0
6858 CPU_POWERPC_405PM = xxx,
6859 #endif
6860 #if 0
6861 CPU_POWERPC_405PS = xxx,
6862 #endif
6863 #if 0
6864 CPU_POWERPC_405S = xxx,
6865 #endif
6866 /* IBM network processors */
6867 CPU_POWERPC_NPE405H = 0x414100C0,
6868 CPU_POWERPC_NPE405H2 = 0x41410140,
6869 CPU_POWERPC_NPE405L = 0x416100C0,
6870 CPU_POWERPC_NPE4GS3 = 0x40B10000,
6871 #if 0
6872 CPU_POWERPC_NPCxx1 = xxx,
6873 #endif
6874 #if 0
6875 CPU_POWERPC_NPR161 = xxx,
6876 #endif
6877 #if 0
6878 CPU_POWERPC_LC77700 = xxx,
6879 #endif
6880 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
6881 #if 0
6882 CPU_POWERPC_STB01000 = xxx,
6883 #endif
6884 #if 0
6885 CPU_POWERPC_STB01010 = xxx,
6886 #endif
6887 #if 0
6888 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
6889 #endif
6890 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
6891 #if 0
6892 CPU_POWERPC_STB043 = xxx,
6893 #endif
6894 #if 0
6895 CPU_POWERPC_STB045 = xxx,
6896 #endif
6897 CPU_POWERPC_STB04 = 0x41810000,
6898 CPU_POWERPC_STB25 = 0x51510950,
6899 #if 0
6900 CPU_POWERPC_STB130 = xxx,
6901 #endif
6902 /* Xilinx cores */
6903 CPU_POWERPC_X2VP4 = 0x20010820,
6904 #define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
6905 CPU_POWERPC_X2VP20 = 0x20010860,
6906 #define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
6907 #if 0
6908 CPU_POWERPC_ZL10310 = xxx,
6909 #endif
6910 #if 0
6911 CPU_POWERPC_ZL10311 = xxx,
6912 #endif
6913 #if 0
6914 CPU_POWERPC_ZL10320 = xxx,
6915 #endif
6916 #if 0
6917 CPU_POWERPC_ZL10321 = xxx,
6918 #endif
6919 /* PowerPC 440 family */
6920 /* Generic PowerPC 440 */
6921 #define CPU_POWERPC_440 CPU_POWERPC_440GXf
6922 /* PowerPC 440 cores */
6923 #if 0
6924 CPU_POWERPC_440A4 = xxx,
6925 #endif
6926 CPU_POWERPC_440_XILINX = 0x7ff21910,
6927 #if 0
6928 CPU_POWERPC_440A5 = xxx,
6929 #endif
6930 #if 0
6931 CPU_POWERPC_440B4 = xxx,
6932 #endif
6933 #if 0
6934 CPU_POWERPC_440F5 = xxx,
6935 #endif
6936 #if 0
6937 CPU_POWERPC_440G5 = xxx,
6938 #endif
6939 #if 0
6940 CPU_POWERPC_440H4 = xxx,
6941 #endif
6942 #if 0
6943 CPU_POWERPC_440H6 = xxx,
6944 #endif
6945 /* PowerPC 440 microcontrolers */
6946 #define CPU_POWERPC_440EP CPU_POWERPC_440EPb
6947 CPU_POWERPC_440EPa = 0x42221850,
6948 CPU_POWERPC_440EPb = 0x422218D3,
6949 #define CPU_POWERPC_440GP CPU_POWERPC_440GPc
6950 CPU_POWERPC_440GPb = 0x40120440,
6951 CPU_POWERPC_440GPc = 0x40120481,
6952 #define CPU_POWERPC_440GR CPU_POWERPC_440GRa
6953 #define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
6954 CPU_POWERPC_440GRX = 0x200008D0,
6955 #define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
6956 #define CPU_POWERPC_440GX CPU_POWERPC_440GXf
6957 CPU_POWERPC_440GXa = 0x51B21850,
6958 CPU_POWERPC_440GXb = 0x51B21851,
6959 CPU_POWERPC_440GXc = 0x51B21892,
6960 CPU_POWERPC_440GXf = 0x51B21894,
6961 #if 0
6962 CPU_POWERPC_440S = xxx,
6963 #endif
6964 CPU_POWERPC_440SP = 0x53221850,
6965 CPU_POWERPC_440SP2 = 0x53221891,
6966 CPU_POWERPC_440SPE = 0x53421890,
6967 /* PowerPC 460 family */
6968 #if 0
6969 /* Generic PowerPC 464 */
6970 #define CPU_POWERPC_464 CPU_POWERPC_464H90
6971 #endif
6972 /* PowerPC 464 microcontrolers */
6973 #if 0
6974 CPU_POWERPC_464H90 = xxx,
6975 #endif
6976 #if 0
6977 CPU_POWERPC_464H90FP = xxx,
6978 #endif
6979 /* Freescale embedded PowerPC cores */
6980 /* PowerPC MPC 5xx cores (aka RCPU) */
6981 CPU_POWERPC_MPC5xx = 0x00020020,
6982 #define CPU_POWERPC_MGT560 CPU_POWERPC_MPC5xx
6983 #define CPU_POWERPC_MPC509 CPU_POWERPC_MPC5xx
6984 #define CPU_POWERPC_MPC533 CPU_POWERPC_MPC5xx
6985 #define CPU_POWERPC_MPC534 CPU_POWERPC_MPC5xx
6986 #define CPU_POWERPC_MPC555 CPU_POWERPC_MPC5xx
6987 #define CPU_POWERPC_MPC556 CPU_POWERPC_MPC5xx
6988 #define CPU_POWERPC_MPC560 CPU_POWERPC_MPC5xx
6989 #define CPU_POWERPC_MPC561 CPU_POWERPC_MPC5xx
6990 #define CPU_POWERPC_MPC562 CPU_POWERPC_MPC5xx
6991 #define CPU_POWERPC_MPC563 CPU_POWERPC_MPC5xx
6992 #define CPU_POWERPC_MPC564 CPU_POWERPC_MPC5xx
6993 #define CPU_POWERPC_MPC565 CPU_POWERPC_MPC5xx
6994 #define CPU_POWERPC_MPC566 CPU_POWERPC_MPC5xx
6995 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
6996 CPU_POWERPC_MPC8xx = 0x00500000,
6997 #define CPU_POWERPC_MGT823 CPU_POWERPC_MPC8xx
6998 #define CPU_POWERPC_MPC821 CPU_POWERPC_MPC8xx
6999 #define CPU_POWERPC_MPC823 CPU_POWERPC_MPC8xx
7000 #define CPU_POWERPC_MPC850 CPU_POWERPC_MPC8xx
7001 #define CPU_POWERPC_MPC852T CPU_POWERPC_MPC8xx
7002 #define CPU_POWERPC_MPC855T CPU_POWERPC_MPC8xx
7003 #define CPU_POWERPC_MPC857 CPU_POWERPC_MPC8xx
7004 #define CPU_POWERPC_MPC859 CPU_POWERPC_MPC8xx
7005 #define CPU_POWERPC_MPC860 CPU_POWERPC_MPC8xx
7006 #define CPU_POWERPC_MPC862 CPU_POWERPC_MPC8xx
7007 #define CPU_POWERPC_MPC866 CPU_POWERPC_MPC8xx
7008 #define CPU_POWERPC_MPC870 CPU_POWERPC_MPC8xx
7009 #define CPU_POWERPC_MPC875 CPU_POWERPC_MPC8xx
7010 #define CPU_POWERPC_MPC880 CPU_POWERPC_MPC8xx
7011 #define CPU_POWERPC_MPC885 CPU_POWERPC_MPC8xx
7012 /* G2 cores (aka PowerQUICC-II) */
7013 CPU_POWERPC_G2 = 0x00810011,
7014 CPU_POWERPC_G2H4 = 0x80811010,
7015 CPU_POWERPC_G2gp = 0x80821010,
7016 CPU_POWERPC_G2ls = 0x90810010,
7017 CPU_POWERPC_MPC603 = 0x00810100,
7018 CPU_POWERPC_G2_HIP3 = 0x00810101,
7019 CPU_POWERPC_G2_HIP4 = 0x80811014,
7020 /* G2_LE core (aka PowerQUICC-II) */
7021 CPU_POWERPC_G2LE = 0x80820010,
7022 CPU_POWERPC_G2LEgp = 0x80822010,
7023 CPU_POWERPC_G2LEls = 0xA0822010,
7024 CPU_POWERPC_G2LEgp1 = 0x80822011,
7025 CPU_POWERPC_G2LEgp3 = 0x80822013,
7026 /* MPC52xx microcontrollers */
7027 /* XXX: MPC 5121 ? */
7028 #define CPU_POWERPC_MPC52xx CPU_POWERPC_MPC5200
7029 #define CPU_POWERPC_MPC5200 CPU_POWERPC_MPC5200_v12
7030 #define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1
7031 #define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1
7032 #define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
7033 #define CPU_POWERPC_MPC5200B CPU_POWERPC_MPC5200B_v21
7034 #define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
7035 #define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
7036 /* MPC82xx microcontrollers */
7037 #define CPU_POWERPC_MPC82xx CPU_POWERPC_MPC8280
7038 #define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
7039 #define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
7040 #define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
7041 #define CPU_POWERPC_MPC8247 CPU_POWERPC_G2LEgp3
7042 #define CPU_POWERPC_MPC8248 CPU_POWERPC_G2LEgp3
7043 #define CPU_POWERPC_MPC8250 CPU_POWERPC_MPC8250_HiP4
7044 #define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
7045 #define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
7046 #define CPU_POWERPC_MPC8255 CPU_POWERPC_MPC8255_HiP4
7047 #define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3
7048 #define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4
7049 #define CPU_POWERPC_MPC8260 CPU_POWERPC_MPC8260_HiP4
7050 #define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3
7051 #define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4
7052 #define CPU_POWERPC_MPC8264 CPU_POWERPC_MPC8264_HiP4
7053 #define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3
7054 #define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4
7055 #define CPU_POWERPC_MPC8265 CPU_POWERPC_MPC8265_HiP4
7056 #define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3
7057 #define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4
7058 #define CPU_POWERPC_MPC8266 CPU_POWERPC_MPC8266_HiP4
7059 #define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
7060 #define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
7061 #define CPU_POWERPC_MPC8270 CPU_POWERPC_G2LEgp3
7062 #define CPU_POWERPC_MPC8271 CPU_POWERPC_G2LEgp3
7063 #define CPU_POWERPC_MPC8272 CPU_POWERPC_G2LEgp3
7064 #define CPU_POWERPC_MPC8275 CPU_POWERPC_G2LEgp3
7065 #define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3
7066 /* e200 family */
7067 /* e200 cores */
7068 #define CPU_POWERPC_e200 CPU_POWERPC_e200z6
7069 #if 0
7070 CPU_POWERPC_e200z0 = xxx,
7071 #endif
7072 #if 0
7073 CPU_POWERPC_e200z1 = xxx,
7074 #endif
7075 #if 0 /* ? */
7076 CPU_POWERPC_e200z3 = 0x81120000,
7077 #endif
7078 CPU_POWERPC_e200z5 = 0x81000000,
7079 CPU_POWERPC_e200z6 = 0x81120000,
7080 /* MPC55xx microcontrollers */
7081 #define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567
7082 #if 0
7083 #define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1
7084 #define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
7085 #define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
7086 #define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1
7087 #define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
7088 #define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
7089 #define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
7090 #define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1
7091 #define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
7092 #define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
7093 #define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1
7094 #define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
7095 #define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
7096 #define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
7097 #endif
7098 #if 0
7099 #define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
7100 #define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
7101 #endif
7102 #define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
7103 #define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
7104 #define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
7105 #define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
7106 #define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
7107 #define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
7108 /* e300 family */
7109 /* e300 cores */
7110 #define CPU_POWERPC_e300 CPU_POWERPC_e300c3
7111 CPU_POWERPC_e300c1 = 0x00830010,
7112 CPU_POWERPC_e300c2 = 0x00840010,
7113 CPU_POWERPC_e300c3 = 0x00850010,
7114 CPU_POWERPC_e300c4 = 0x00860010,
7115 /* MPC83xx microcontrollers */
7116 #define CPU_POWERPC_MPC831x CPU_POWERPC_e300c3
7117 #define CPU_POWERPC_MPC832x CPU_POWERPC_e300c2
7118 #define CPU_POWERPC_MPC834x CPU_POWERPC_e300c1
7119 #define CPU_POWERPC_MPC835x CPU_POWERPC_e300c1
7120 #define CPU_POWERPC_MPC836x CPU_POWERPC_e300c1
7121 #define CPU_POWERPC_MPC837x CPU_POWERPC_e300c4
7122 /* e500 family */
7123 /* e500 cores */
7124 #define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22
7125 #define CPU_POWERPC_e500v1 CPU_POWERPC_e500v1_v20
7126 #define CPU_POWERPC_e500v2 CPU_POWERPC_e500v2_v22
7127 CPU_POWERPC_e500v1_v10 = 0x80200010,
7128 CPU_POWERPC_e500v1_v20 = 0x80200020,
7129 CPU_POWERPC_e500v2_v10 = 0x80210010,
7130 CPU_POWERPC_e500v2_v11 = 0x80210011,
7131 CPU_POWERPC_e500v2_v20 = 0x80210020,
7132 CPU_POWERPC_e500v2_v21 = 0x80210021,
7133 CPU_POWERPC_e500v2_v22 = 0x80210022,
7134 CPU_POWERPC_e500v2_v30 = 0x80210030,
7135 CPU_POWERPC_e500mc = 0x80230020,
7136 /* MPC85xx microcontrollers */
7137 #define CPU_POWERPC_MPC8533 CPU_POWERPC_MPC8533_v11
7138 #define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
7139 #define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
7140 #define CPU_POWERPC_MPC8533E CPU_POWERPC_MPC8533E_v11
7141 #define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
7142 #define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
7143 #define CPU_POWERPC_MPC8540 CPU_POWERPC_MPC8540_v21
7144 #define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500v1_v10
7145 #define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500v1_v20
7146 #define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500v1_v20
7147 #define CPU_POWERPC_MPC8541 CPU_POWERPC_MPC8541_v11
7148 #define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500v1_v20
7149 #define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500v1_v20
7150 #define CPU_POWERPC_MPC8541E CPU_POWERPC_MPC8541E_v11
7151 #define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500v1_v20
7152 #define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500v1_v20
7153 #define CPU_POWERPC_MPC8543 CPU_POWERPC_MPC8543_v21
7154 #define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10
7155 #define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11
7156 #define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20
7157 #define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21
7158 #define CPU_POWERPC_MPC8543E CPU_POWERPC_MPC8543E_v21
7159 #define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10
7160 #define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11
7161 #define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20
7162 #define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21
7163 #define CPU_POWERPC_MPC8544 CPU_POWERPC_MPC8544_v11
7164 #define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
7165 #define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
7166 #define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
7167 #define CPU_POWERPC_MPC8544E CPU_POWERPC_MPC8544E_v11
7168 #define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
7169 #define CPU_POWERPC_MPC8545 CPU_POWERPC_MPC8545_v21
7170 #define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10
7171 #define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20
7172 #define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21
7173 #define CPU_POWERPC_MPC8545E CPU_POWERPC_MPC8545E_v21
7174 #define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10
7175 #define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20
7176 #define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21
7177 #define CPU_POWERPC_MPC8547E CPU_POWERPC_MPC8545E_v21
7178 #define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10
7179 #define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20
7180 #define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21
7181 #define CPU_POWERPC_MPC8548 CPU_POWERPC_MPC8548_v21
7182 #define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10
7183 #define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11
7184 #define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20
7185 #define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21
7186 #define CPU_POWERPC_MPC8548E CPU_POWERPC_MPC8548E_v21
7187 #define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10
7188 #define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11
7189 #define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20
7190 #define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21
7191 #define CPU_POWERPC_MPC8555 CPU_POWERPC_MPC8555_v11
7192 #define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10
7193 #define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11
7194 #define CPU_POWERPC_MPC8555E CPU_POWERPC_MPC8555E_v11
7195 #define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10
7196 #define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11
7197 #define CPU_POWERPC_MPC8560 CPU_POWERPC_MPC8560_v21
7198 #define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10
7199 #define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20
7200 #define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21
7201 #define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
7202 #define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22
7203 #define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
7204 #define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22
7205 #define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
7206 #define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30
7207 /* e600 family */
7208 /* e600 cores */
7209 CPU_POWERPC_e600 = 0x80040010,
7210 /* MPC86xx microcontrollers */
7211 #define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
7212 #define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
7213 #define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
7214 /* PowerPC 6xx cores */
7215 #define CPU_POWERPC_601 CPU_POWERPC_601_v2
7216 CPU_POWERPC_601_v0 = 0x00010001,
7217 CPU_POWERPC_601_v1 = 0x00010001,
7218 #define CPU_POWERPC_601v CPU_POWERPC_601_v2
7219 CPU_POWERPC_601_v2 = 0x00010002,
7220 CPU_POWERPC_602 = 0x00050100,
7221 CPU_POWERPC_603 = 0x00030100,
7222 #define CPU_POWERPC_603E CPU_POWERPC_603E_v41
7223 CPU_POWERPC_603E_v11 = 0x00060101,
7224 CPU_POWERPC_603E_v12 = 0x00060102,
7225 CPU_POWERPC_603E_v13 = 0x00060103,
7226 CPU_POWERPC_603E_v14 = 0x00060104,
7227 CPU_POWERPC_603E_v22 = 0x00060202,
7228 CPU_POWERPC_603E_v3 = 0x00060300,
7229 CPU_POWERPC_603E_v4 = 0x00060400,
7230 CPU_POWERPC_603E_v41 = 0x00060401,
7231 CPU_POWERPC_603E7t = 0x00071201,
7232 CPU_POWERPC_603E7v = 0x00070100,
7233 CPU_POWERPC_603E7v1 = 0x00070101,
7234 CPU_POWERPC_603E7v2 = 0x00070201,
7235 CPU_POWERPC_603E7 = 0x00070200,
7236 CPU_POWERPC_603P = 0x00070000,
7237 #define CPU_POWERPC_603R CPU_POWERPC_603E7t
7238 /* XXX: missing 0x00040303 (604) */
7239 CPU_POWERPC_604 = 0x00040103,
7240 #define CPU_POWERPC_604E CPU_POWERPC_604E_v24
7241 /* XXX: missing 0x00091203 */
7242 /* XXX: missing 0x00092110 */
7243 /* XXX: missing 0x00092120 */
7244 CPU_POWERPC_604E_v10 = 0x00090100,
7245 CPU_POWERPC_604E_v22 = 0x00090202,
7246 CPU_POWERPC_604E_v24 = 0x00090204,
7247 /* XXX: missing 0x000a0100 */
7248 /* XXX: missing 0x00093102 */
7249 CPU_POWERPC_604R = 0x000a0101,
7250 #if 0
7251 CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */
7252 #endif
7253 /* PowerPC 740/750 cores (aka G3) */
7254 /* XXX: missing 0x00084202 */
7255 #define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
7256 CPU_POWERPC_7x0_v10 = 0x00080100,
7257 CPU_POWERPC_7x0_v20 = 0x00080200,
7258 CPU_POWERPC_7x0_v21 = 0x00080201,
7259 CPU_POWERPC_7x0_v22 = 0x00080202,
7260 CPU_POWERPC_7x0_v30 = 0x00080300,
7261 CPU_POWERPC_7x0_v31 = 0x00080301,
7262 CPU_POWERPC_740E = 0x00080100,
7263 CPU_POWERPC_750E = 0x00080200,
7264 CPU_POWERPC_7x0P = 0x10080000,
7265 /* XXX: missing 0x00087010 (CL ?) */
7266 #define CPU_POWERPC_750CL CPU_POWERPC_750CL_v20
7267 CPU_POWERPC_750CL_v10 = 0x00087200,
7268 CPU_POWERPC_750CL_v20 = 0x00087210, /* aka rev E */
7269 #define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
7270 CPU_POWERPC_750CX_v10 = 0x00082100,
7271 CPU_POWERPC_750CX_v20 = 0x00082200,
7272 CPU_POWERPC_750CX_v21 = 0x00082201,
7273 CPU_POWERPC_750CX_v22 = 0x00082202,
7274 #define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
7275 CPU_POWERPC_750CXE_v21 = 0x00082211,
7276 CPU_POWERPC_750CXE_v22 = 0x00082212,
7277 CPU_POWERPC_750CXE_v23 = 0x00082213,
7278 CPU_POWERPC_750CXE_v24 = 0x00082214,
7279 CPU_POWERPC_750CXE_v24b = 0x00083214,
7280 CPU_POWERPC_750CXE_v30 = 0x00082310,
7281 CPU_POWERPC_750CXE_v31 = 0x00082311,
7282 CPU_POWERPC_750CXE_v31b = 0x00083311,
7283 CPU_POWERPC_750CXR = 0x00083410,
7284 CPU_POWERPC_750FL = 0x70000203,
7285 #define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
7286 CPU_POWERPC_750FX_v10 = 0x70000100,
7287 CPU_POWERPC_750FX_v20 = 0x70000200,
7288 CPU_POWERPC_750FX_v21 = 0x70000201,
7289 CPU_POWERPC_750FX_v22 = 0x70000202,
7290 CPU_POWERPC_750FX_v23 = 0x70000203,
7291 CPU_POWERPC_750GL = 0x70020102,
7292 #define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
7293 CPU_POWERPC_750GX_v10 = 0x70020100,
7294 CPU_POWERPC_750GX_v11 = 0x70020101,
7295 CPU_POWERPC_750GX_v12 = 0x70020102,
7296 #define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
7297 CPU_POWERPC_750L_v20 = 0x00088200,
7298 CPU_POWERPC_750L_v21 = 0x00088201,
7299 CPU_POWERPC_750L_v22 = 0x00088202,
7300 CPU_POWERPC_750L_v30 = 0x00088300,
7301 CPU_POWERPC_750L_v32 = 0x00088302,
7302 /* PowerPC 745/755 cores */
7303 #define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
7304 CPU_POWERPC_7x5_v10 = 0x00083100,
7305 CPU_POWERPC_7x5_v11 = 0x00083101,
7306 CPU_POWERPC_7x5_v20 = 0x00083200,
7307 CPU_POWERPC_7x5_v21 = 0x00083201,
7308 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
7309 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
7310 CPU_POWERPC_7x5_v24 = 0x00083204,
7311 CPU_POWERPC_7x5_v25 = 0x00083205,
7312 CPU_POWERPC_7x5_v26 = 0x00083206,
7313 CPU_POWERPC_7x5_v27 = 0x00083207,
7314 CPU_POWERPC_7x5_v28 = 0x00083208,
7315 #if 0
7316 CPU_POWERPC_7x5P = xxx,
7317 #endif
7318 /* PowerPC 74xx cores (aka G4) */
7319 /* XXX: missing 0x000C1101 */
7320 #define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
7321 CPU_POWERPC_7400_v10 = 0x000C0100,
7322 CPU_POWERPC_7400_v11 = 0x000C0101,
7323 CPU_POWERPC_7400_v20 = 0x000C0200,
7324 CPU_POWERPC_7400_v21 = 0x000C0201,
7325 CPU_POWERPC_7400_v22 = 0x000C0202,
7326 CPU_POWERPC_7400_v26 = 0x000C0206,
7327 CPU_POWERPC_7400_v27 = 0x000C0207,
7328 CPU_POWERPC_7400_v28 = 0x000C0208,
7329 CPU_POWERPC_7400_v29 = 0x000C0209,
7330 #define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
7331 CPU_POWERPC_7410_v10 = 0x800C1100,
7332 CPU_POWERPC_7410_v11 = 0x800C1101,
7333 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
7334 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
7335 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
7336 #define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
7337 CPU_POWERPC_7448_v10 = 0x80040100,
7338 CPU_POWERPC_7448_v11 = 0x80040101,
7339 CPU_POWERPC_7448_v20 = 0x80040200,
7340 CPU_POWERPC_7448_v21 = 0x80040201,
7341 #define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
7342 CPU_POWERPC_7450_v10 = 0x80000100,
7343 CPU_POWERPC_7450_v11 = 0x80000101,
7344 CPU_POWERPC_7450_v12 = 0x80000102,
7345 CPU_POWERPC_7450_v20 = 0x80000200, /* aka A, B, C, D: 2.04 */
7346 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
7347 #define CPU_POWERPC_74x1 CPU_POWERPC_74x1_v23
7348 CPU_POWERPC_74x1_v23 = 0x80000203, /* aka G: 2.3 */
7349 /* XXX: this entry might be a bug in some documentation */
7350 CPU_POWERPC_74x1_v210 = 0x80000210, /* aka G: 2.3 ? */
7351 #define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
7352 CPU_POWERPC_74x5_v10 = 0x80010100,
7353 /* XXX: missing 0x80010200 */
7354 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
7355 CPU_POWERPC_74x5_v32 = 0x80010302,
7356 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
7357 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
7358 #define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
7359 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
7360 CPU_POWERPC_74x7_v11 = 0x80020101, /* aka B: 1.1 */
7361 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
7362 #define CPU_POWERPC_74x7A CPU_POWERPC_74x7A_v12
7363 CPU_POWERPC_74x7A_v10 = 0x80030100, /* aka A: 1.0 */
7364 CPU_POWERPC_74x7A_v11 = 0x80030101, /* aka B: 1.1 */
7365 CPU_POWERPC_74x7A_v12 = 0x80030102, /* aka C: 1.2 */
7366 /* 64 bits PowerPC */
7367 #if defined(TARGET_PPC64)
7368 CPU_POWERPC_620 = 0x00140000,
7369 CPU_POWERPC_630 = 0x00400000,
7370 CPU_POWERPC_631 = 0x00410104,
7371 CPU_POWERPC_POWER4 = 0x00350000,
7372 CPU_POWERPC_POWER4P = 0x00380000,
7373 /* XXX: missing 0x003A0201 */
7374 CPU_POWERPC_POWER5 = 0x003A0203,
7375 #define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
7376 CPU_POWERPC_POWER5P = 0x003B0000,
7377 #define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
7378 CPU_POWERPC_POWER6 = 0x003E0000,
7379 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */
7380 CPU_POWERPC_POWER6A = 0x0F000002,
7381 #define CPU_POWERPC_POWER7 CPU_POWERPC_POWER7_v20
7382 CPU_POWERPC_POWER7_v20 = 0x003F0200,
7383 CPU_POWERPC_POWER7_v21 = 0x003F0201,
7384 CPU_POWERPC_POWER7_v23 = 0x003F0203,
7385 CPU_POWERPC_970 = 0x00390202,
7386 #define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
7387 CPU_POWERPC_970FX_v10 = 0x00391100,
7388 CPU_POWERPC_970FX_v20 = 0x003C0200,
7389 CPU_POWERPC_970FX_v21 = 0x003C0201,
7390 CPU_POWERPC_970FX_v30 = 0x003C0300,
7391 CPU_POWERPC_970FX_v31 = 0x003C0301,
7392 CPU_POWERPC_970GX = 0x00450000,
7393 #define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
7394 CPU_POWERPC_970MP_v10 = 0x00440100,
7395 CPU_POWERPC_970MP_v11 = 0x00440101,
7396 #define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
7397 CPU_POWERPC_CELL_v10 = 0x00700100,
7398 CPU_POWERPC_CELL_v20 = 0x00700400,
7399 CPU_POWERPC_CELL_v30 = 0x00700500,
7400 CPU_POWERPC_CELL_v31 = 0x00700501,
7401 #define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
7402 CPU_POWERPC_RS64 = 0x00330000,
7403 CPU_POWERPC_RS64II = 0x00340000,
7404 CPU_POWERPC_RS64III = 0x00360000,
7405 CPU_POWERPC_RS64IV = 0x00370000,
7406 #endif /* defined(TARGET_PPC64) */
7407 /* Original POWER */
7408 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
7409 * POWER2 (RIOS2) & RSC2 (P2SC) here
7410 */
7411 #if 0
7412 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
7413 #endif
7414 #if 0
7415 CPU_POWER2 = xxx, /* 0x40000 ? */
7416 #endif
7417 /* PA Semi core */
7418 CPU_POWERPC_PA6T = 0x00900000,
7419 };
7420
7421 /* System version register (used on MPC 8xxx) */
7422 enum {
7423 POWERPC_SVR_NONE = 0x00000000,
7424 #define POWERPC_SVR_52xx POWERPC_SVR_5200
7425 #define POWERPC_SVR_5200 POWERPC_SVR_5200_v12
7426 POWERPC_SVR_5200_v10 = 0x80110010,
7427 POWERPC_SVR_5200_v11 = 0x80110011,
7428 POWERPC_SVR_5200_v12 = 0x80110012,
7429 #define POWERPC_SVR_5200B POWERPC_SVR_5200B_v21
7430 POWERPC_SVR_5200B_v20 = 0x80110020,
7431 POWERPC_SVR_5200B_v21 = 0x80110021,
7432 #define POWERPC_SVR_55xx POWERPC_SVR_5567
7433 #if 0
7434 POWERPC_SVR_5533 = xxx,
7435 #endif
7436 #if 0
7437 POWERPC_SVR_5534 = xxx,
7438 #endif
7439 #if 0
7440 POWERPC_SVR_5553 = xxx,
7441 #endif
7442 #if 0
7443 POWERPC_SVR_5554 = xxx,
7444 #endif
7445 #if 0
7446 POWERPC_SVR_5561 = xxx,
7447 #endif
7448 #if 0
7449 POWERPC_SVR_5565 = xxx,
7450 #endif
7451 #if 0
7452 POWERPC_SVR_5566 = xxx,
7453 #endif
7454 #if 0
7455 POWERPC_SVR_5567 = xxx,
7456 #endif
7457 #if 0
7458 POWERPC_SVR_8313 = xxx,
7459 #endif
7460 #if 0
7461 POWERPC_SVR_8313E = xxx,
7462 #endif
7463 #if 0
7464 POWERPC_SVR_8314 = xxx,
7465 #endif
7466 #if 0
7467 POWERPC_SVR_8314E = xxx,
7468 #endif
7469 #if 0
7470 POWERPC_SVR_8315 = xxx,
7471 #endif
7472 #if 0
7473 POWERPC_SVR_8315E = xxx,
7474 #endif
7475 #if 0
7476 POWERPC_SVR_8321 = xxx,
7477 #endif
7478 #if 0
7479 POWERPC_SVR_8321E = xxx,
7480 #endif
7481 #if 0
7482 POWERPC_SVR_8323 = xxx,
7483 #endif
7484 #if 0
7485 POWERPC_SVR_8323E = xxx,
7486 #endif
7487 POWERPC_SVR_8343 = 0x80570010,
7488 POWERPC_SVR_8343A = 0x80570030,
7489 POWERPC_SVR_8343E = 0x80560010,
7490 POWERPC_SVR_8343EA = 0x80560030,
7491 #define POWERPC_SVR_8347 POWERPC_SVR_8347T
7492 POWERPC_SVR_8347P = 0x80550010, /* PBGA package */
7493 POWERPC_SVR_8347T = 0x80530010, /* TBGA package */
7494 #define POWERPC_SVR_8347A POWERPC_SVR_8347AT
7495 POWERPC_SVR_8347AP = 0x80550030, /* PBGA package */
7496 POWERPC_SVR_8347AT = 0x80530030, /* TBGA package */
7497 #define POWERPC_SVR_8347E POWERPC_SVR_8347ET
7498 POWERPC_SVR_8347EP = 0x80540010, /* PBGA package */
7499 POWERPC_SVR_8347ET = 0x80520010, /* TBGA package */
7500 #define POWERPC_SVR_8347EA POWERPC_SVR_8347EAT
7501 POWERPC_SVR_8347EAP = 0x80540030, /* PBGA package */
7502 POWERPC_SVR_8347EAT = 0x80520030, /* TBGA package */
7503 POWERPC_SVR_8349 = 0x80510010,
7504 POWERPC_SVR_8349A = 0x80510030,
7505 POWERPC_SVR_8349E = 0x80500010,
7506 POWERPC_SVR_8349EA = 0x80500030,
7507 #if 0
7508 POWERPC_SVR_8358E = xxx,
7509 #endif
7510 #if 0
7511 POWERPC_SVR_8360E = xxx,
7512 #endif
7513 #define POWERPC_SVR_E500 0x40000000
7514 POWERPC_SVR_8377 = 0x80C70010 | POWERPC_SVR_E500,
7515 POWERPC_SVR_8377E = 0x80C60010 | POWERPC_SVR_E500,
7516 POWERPC_SVR_8378 = 0x80C50010 | POWERPC_SVR_E500,
7517 POWERPC_SVR_8378E = 0x80C40010 | POWERPC_SVR_E500,
7518 POWERPC_SVR_8379 = 0x80C30010 | POWERPC_SVR_E500,
7519 POWERPC_SVR_8379E = 0x80C00010 | POWERPC_SVR_E500,
7520 #define POWERPC_SVR_8533 POWERPC_SVR_8533_v11
7521 POWERPC_SVR_8533_v10 = 0x80340010 | POWERPC_SVR_E500,
7522 POWERPC_SVR_8533_v11 = 0x80340011 | POWERPC_SVR_E500,
7523 #define POWERPC_SVR_8533E POWERPC_SVR_8533E_v11
7524 POWERPC_SVR_8533E_v10 = 0x803C0010 | POWERPC_SVR_E500,
7525 POWERPC_SVR_8533E_v11 = 0x803C0011 | POWERPC_SVR_E500,
7526 #define POWERPC_SVR_8540 POWERPC_SVR_8540_v21
7527 POWERPC_SVR_8540_v10 = 0x80300010 | POWERPC_SVR_E500,
7528 POWERPC_SVR_8540_v20 = 0x80300020 | POWERPC_SVR_E500,
7529 POWERPC_SVR_8540_v21 = 0x80300021 | POWERPC_SVR_E500,
7530 #define POWERPC_SVR_8541 POWERPC_SVR_8541_v11
7531 POWERPC_SVR_8541_v10 = 0x80720010 | POWERPC_SVR_E500,
7532 POWERPC_SVR_8541_v11 = 0x80720011 | POWERPC_SVR_E500,
7533 #define POWERPC_SVR_8541E POWERPC_SVR_8541E_v11
7534 POWERPC_SVR_8541E_v10 = 0x807A0010 | POWERPC_SVR_E500,
7535 POWERPC_SVR_8541E_v11 = 0x807A0011 | POWERPC_SVR_E500,
7536 #define POWERPC_SVR_8543 POWERPC_SVR_8543_v21
7537 POWERPC_SVR_8543_v10 = 0x80320010 | POWERPC_SVR_E500,
7538 POWERPC_SVR_8543_v11 = 0x80320011 | POWERPC_SVR_E500,
7539 POWERPC_SVR_8543_v20 = 0x80320020 | POWERPC_SVR_E500,
7540 POWERPC_SVR_8543_v21 = 0x80320021 | POWERPC_SVR_E500,
7541 #define POWERPC_SVR_8543E POWERPC_SVR_8543E_v21
7542 POWERPC_SVR_8543E_v10 = 0x803A0010 | POWERPC_SVR_E500,
7543 POWERPC_SVR_8543E_v11 = 0x803A0011 | POWERPC_SVR_E500,
7544 POWERPC_SVR_8543E_v20 = 0x803A0020 | POWERPC_SVR_E500,
7545 POWERPC_SVR_8543E_v21 = 0x803A0021 | POWERPC_SVR_E500,
7546 #define POWERPC_SVR_8544 POWERPC_SVR_8544_v11
7547 POWERPC_SVR_8544_v10 = 0x80340110 | POWERPC_SVR_E500,
7548 POWERPC_SVR_8544_v11 = 0x80340111 | POWERPC_SVR_E500,
7549 #define POWERPC_SVR_8544E POWERPC_SVR_8544E_v11
7550 POWERPC_SVR_8544E_v10 = 0x803C0110 | POWERPC_SVR_E500,
7551 POWERPC_SVR_8544E_v11 = 0x803C0111 | POWERPC_SVR_E500,
7552 #define POWERPC_SVR_8545 POWERPC_SVR_8545_v21
7553 POWERPC_SVR_8545_v20 = 0x80310220 | POWERPC_SVR_E500,
7554 POWERPC_SVR_8545_v21 = 0x80310221 | POWERPC_SVR_E500,
7555 #define POWERPC_SVR_8545E POWERPC_SVR_8545E_v21
7556 POWERPC_SVR_8545E_v20 = 0x80390220 | POWERPC_SVR_E500,
7557 POWERPC_SVR_8545E_v21 = 0x80390221 | POWERPC_SVR_E500,
7558 #define POWERPC_SVR_8547E POWERPC_SVR_8547E_v21
7559 POWERPC_SVR_8547E_v20 = 0x80390120 | POWERPC_SVR_E500,
7560 POWERPC_SVR_8547E_v21 = 0x80390121 | POWERPC_SVR_E500,
7561 #define POWERPC_SVR_8548 POWERPC_SVR_8548_v21
7562 POWERPC_SVR_8548_v10 = 0x80310010 | POWERPC_SVR_E500,
7563 POWERPC_SVR_8548_v11 = 0x80310011 | POWERPC_SVR_E500,
7564 POWERPC_SVR_8548_v20 = 0x80310020 | POWERPC_SVR_E500,
7565 POWERPC_SVR_8548_v21 = 0x80310021 | POWERPC_SVR_E500,
7566 #define POWERPC_SVR_8548E POWERPC_SVR_8548E_v21
7567 POWERPC_SVR_8548E_v10 = 0x80390010 | POWERPC_SVR_E500,
7568 POWERPC_SVR_8548E_v11 = 0x80390011 | POWERPC_SVR_E500,
7569 POWERPC_SVR_8548E_v20 = 0x80390020 | POWERPC_SVR_E500,
7570 POWERPC_SVR_8548E_v21 = 0x80390021 | POWERPC_SVR_E500,
7571 #define POWERPC_SVR_8555 POWERPC_SVR_8555_v11
7572 POWERPC_SVR_8555_v10 = 0x80710010 | POWERPC_SVR_E500,
7573 POWERPC_SVR_8555_v11 = 0x80710011 | POWERPC_SVR_E500,
7574 #define POWERPC_SVR_8555E POWERPC_SVR_8555_v11
7575 POWERPC_SVR_8555E_v10 = 0x80790010 | POWERPC_SVR_E500,
7576 POWERPC_SVR_8555E_v11 = 0x80790011 | POWERPC_SVR_E500,
7577 #define POWERPC_SVR_8560 POWERPC_SVR_8560_v21
7578 POWERPC_SVR_8560_v10 = 0x80700010 | POWERPC_SVR_E500,
7579 POWERPC_SVR_8560_v20 = 0x80700020 | POWERPC_SVR_E500,
7580 POWERPC_SVR_8560_v21 = 0x80700021 | POWERPC_SVR_E500,
7581 POWERPC_SVR_8567 = 0x80750111 | POWERPC_SVR_E500,
7582 POWERPC_SVR_8567E = 0x807D0111 | POWERPC_SVR_E500,
7583 POWERPC_SVR_8568 = 0x80750011 | POWERPC_SVR_E500,
7584 POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500,
7585 POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500,
7586 POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500,
7587 #if 0
7588 POWERPC_SVR_8610 = xxx,
7589 #endif
7590 POWERPC_SVR_8641 = 0x80900021,
7591 POWERPC_SVR_8641D = 0x80900121,
7592 };
7593
7594 /*****************************************************************************/
7595 /* PowerPC CPU definitions */
7596 #define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
7597 { \
7598 .name = _name, \
7599 .pvr = _pvr, \
7600 .svr = _svr, \
7601 .insns_flags = glue(POWERPC_INSNS_,_type), \
7602 .insns_flags2 = glue(POWERPC_INSNS2_,_type), \
7603 .msr_mask = glue(POWERPC_MSRM_,_type), \
7604 .mmu_model = glue(POWERPC_MMU_,_type), \
7605 .excp_model = glue(POWERPC_EXCP_,_type), \
7606 .bus_model = glue(POWERPC_INPUT_,_type), \
7607 .bfd_mach = glue(POWERPC_BFDM_,_type), \
7608 .flags = glue(POWERPC_FLAG_,_type), \
7609 .init_proc = &glue(init_proc_,_type), \
7610 .check_pow = &glue(check_pow_,_type), \
7611 }
7612 #define POWERPC_DEF(_name, _pvr, _type) \
7613 POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
7614
7615 static const ppc_def_t ppc_defs[] = {
7616 /* Embedded PowerPC */
7617 /* PowerPC 401 family */
7618 /* Generic PowerPC 401 */
7619 POWERPC_DEF("401", CPU_POWERPC_401, 401),
7620 /* PowerPC 401 cores */
7621 /* PowerPC 401A1 */
7622 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401),
7623 /* PowerPC 401B2 */
7624 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2),
7625 #if defined (TODO)
7626 /* PowerPC 401B3 */
7627 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3),
7628 #endif
7629 /* PowerPC 401C2 */
7630 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2),
7631 /* PowerPC 401D2 */
7632 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2),
7633 /* PowerPC 401E2 */
7634 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2),
7635 /* PowerPC 401F2 */
7636 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2),
7637 /* PowerPC 401G2 */
7638 /* XXX: to be checked */
7639 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2),
7640 /* PowerPC 401 microcontrolers */
7641 #if defined (TODO)
7642 /* PowerPC 401GF */
7643 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401),
7644 #endif
7645 /* IOP480 (401 microcontroler) */
7646 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480),
7647 /* IBM Processor for Network Resources */
7648 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401),
7649 #if defined (TODO)
7650 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401),
7651 #endif
7652 /* PowerPC 403 family */
7653 /* Generic PowerPC 403 */
7654 POWERPC_DEF("403", CPU_POWERPC_403, 403),
7655 /* PowerPC 403 microcontrolers */
7656 /* PowerPC 403 GA */
7657 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403),
7658 /* PowerPC 403 GB */
7659 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403),
7660 /* PowerPC 403 GC */
7661 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403),
7662 /* PowerPC 403 GCX */
7663 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX),
7664 #if defined (TODO)
7665 /* PowerPC 403 GP */
7666 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403),
7667 #endif
7668 /* PowerPC 405 family */
7669 /* Generic PowerPC 405 */
7670 POWERPC_DEF("405", CPU_POWERPC_405, 405),
7671 /* PowerPC 405 cores */
7672 #if defined (TODO)
7673 /* PowerPC 405 A3 */
7674 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405),
7675 #endif
7676 #if defined (TODO)
7677 /* PowerPC 405 A4 */
7678 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405),
7679 #endif
7680 #if defined (TODO)
7681 /* PowerPC 405 B3 */
7682 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405),
7683 #endif
7684 #if defined (TODO)
7685 /* PowerPC 405 B4 */
7686 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405),
7687 #endif
7688 #if defined (TODO)
7689 /* PowerPC 405 C3 */
7690 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405),
7691 #endif
7692 #if defined (TODO)
7693 /* PowerPC 405 C4 */
7694 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405),
7695 #endif
7696 /* PowerPC 405 D2 */
7697 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405),
7698 #if defined (TODO)
7699 /* PowerPC 405 D3 */
7700 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405),
7701 #endif
7702 /* PowerPC 405 D4 */
7703 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405),
7704 #if defined (TODO)
7705 /* PowerPC 405 D5 */
7706 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405),
7707 #endif
7708 #if defined (TODO)
7709 /* PowerPC 405 E4 */
7710 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405),
7711 #endif
7712 #if defined (TODO)
7713 /* PowerPC 405 F4 */
7714 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405),
7715 #endif
7716 #if defined (TODO)
7717 /* PowerPC 405 F5 */
7718 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405),
7719 #endif
7720 #if defined (TODO)
7721 /* PowerPC 405 F6 */
7722 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405),
7723 #endif
7724 /* PowerPC 405 microcontrolers */
7725 /* PowerPC 405 CR */
7726 POWERPC_DEF("405CR", CPU_POWERPC_405CR, 405),
7727 /* PowerPC 405 CRa */
7728 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405),
7729 /* PowerPC 405 CRb */
7730 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405),
7731 /* PowerPC 405 CRc */
7732 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405),
7733 /* PowerPC 405 EP */
7734 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405),
7735 #if defined(TODO)
7736 /* PowerPC 405 EXr */
7737 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405),
7738 #endif
7739 /* PowerPC 405 EZ */
7740 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405),
7741 #if defined(TODO)
7742 /* PowerPC 405 FX */
7743 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405),
7744 #endif
7745 /* PowerPC 405 GP */
7746 POWERPC_DEF("405GP", CPU_POWERPC_405GP, 405),
7747 /* PowerPC 405 GPa */
7748 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405),
7749 /* PowerPC 405 GPb */
7750 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405),
7751 /* PowerPC 405 GPc */
7752 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405),
7753 /* PowerPC 405 GPd */
7754 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405),
7755 /* PowerPC 405 GPe */
7756 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 405),
7757 /* PowerPC 405 GPR */
7758 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405),
7759 #if defined(TODO)
7760 /* PowerPC 405 H */
7761 POWERPC_DEF("405H", CPU_POWERPC_405H, 405),
7762 #endif
7763 #if defined(TODO)
7764 /* PowerPC 405 L */
7765 POWERPC_DEF("405L", CPU_POWERPC_405L, 405),
7766 #endif
7767 /* PowerPC 405 LP */
7768 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405),
7769 #if defined(TODO)
7770 /* PowerPC 405 PM */
7771 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405),
7772 #endif
7773 #if defined(TODO)
7774 /* PowerPC 405 PS */
7775 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405),
7776 #endif
7777 #if defined(TODO)
7778 /* PowerPC 405 S */
7779 POWERPC_DEF("405S", CPU_POWERPC_405S, 405),
7780 #endif
7781 /* Npe405 H */
7782 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405),
7783 /* Npe405 H2 */
7784 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405),
7785 /* Npe405 L */
7786 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405),
7787 /* Npe4GS3 */
7788 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405),
7789 #if defined (TODO)
7790 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405),
7791 #endif
7792 #if defined (TODO)
7793 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405),
7794 #endif
7795 #if defined (TODO)
7796 /* PowerPC LC77700 (Sanyo) */
7797 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405),
7798 #endif
7799 /* PowerPC 401/403/405 based set-top-box microcontrolers */
7800 #if defined (TODO)
7801 /* STB010000 */
7802 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2),
7803 #endif
7804 #if defined (TODO)
7805 /* STB01010 */
7806 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2),
7807 #endif
7808 #if defined (TODO)
7809 /* STB0210 */
7810 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3),
7811 #endif
7812 /* STB03xx */
7813 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405),
7814 #if defined (TODO)
7815 /* STB043x */
7816 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405),
7817 #endif
7818 #if defined (TODO)
7819 /* STB045x */
7820 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405),
7821 #endif
7822 /* STB04xx */
7823 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405),
7824 /* STB25xx */
7825 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405),
7826 #if defined (TODO)
7827 /* STB130 */
7828 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405),
7829 #endif
7830 /* Xilinx PowerPC 405 cores */
7831 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405),
7832 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 405),
7833 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405),
7834 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 405),
7835 #if defined (TODO)
7836 /* Zarlink ZL10310 */
7837 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405),
7838 #endif
7839 #if defined (TODO)
7840 /* Zarlink ZL10311 */
7841 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405),
7842 #endif
7843 #if defined (TODO)
7844 /* Zarlink ZL10320 */
7845 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405),
7846 #endif
7847 #if defined (TODO)
7848 /* Zarlink ZL10321 */
7849 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405),
7850 #endif
7851 /* PowerPC 440 family */
7852 #if defined(TODO_USER_ONLY)
7853 /* Generic PowerPC 440 */
7854 POWERPC_DEF("440", CPU_POWERPC_440, 440GP),
7855 #endif
7856 /* PowerPC 440 cores */
7857 #if defined (TODO)
7858 /* PowerPC 440 A4 */
7859 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4),
7860 #endif
7861 /* PowerPC 440 Xilinx 5 */
7862 POWERPC_DEF("440-Xilinx", CPU_POWERPC_440_XILINX, 440x5),
7863 #if defined (TODO)
7864 /* PowerPC 440 A5 */
7865 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5),
7866 #endif
7867 #if defined (TODO)
7868 /* PowerPC 440 B4 */
7869 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4),
7870 #endif
7871 #if defined (TODO)
7872 /* PowerPC 440 G4 */
7873 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4),
7874 #endif
7875 #if defined (TODO)
7876 /* PowerPC 440 F5 */
7877 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5),
7878 #endif
7879 #if defined (TODO)
7880 /* PowerPC 440 G5 */
7881 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5),
7882 #endif
7883 #if defined (TODO)
7884 /* PowerPC 440H4 */
7885 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4),
7886 #endif
7887 #if defined (TODO)
7888 /* PowerPC 440H6 */
7889 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5),
7890 #endif
7891 /* PowerPC 440 microcontrolers */
7892 /* PowerPC 440 EP */
7893 POWERPC_DEF("440EP", CPU_POWERPC_440EP, 440EP),
7894 /* PowerPC 440 EPa */
7895 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP),
7896 /* PowerPC 440 EPb */
7897 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP),
7898 /* PowerPC 440 EPX */
7899 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP),
7900 #if defined(TODO_USER_ONLY)
7901 /* PowerPC 440 GP */
7902 POWERPC_DEF("440GP", CPU_POWERPC_440GP, 440GP),
7903 #endif
7904 #if defined(TODO_USER_ONLY)
7905 /* PowerPC 440 GPb */
7906 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP),
7907 #endif
7908 #if defined(TODO_USER_ONLY)
7909 /* PowerPC 440 GPc */
7910 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP),
7911 #endif
7912 #if defined(TODO_USER_ONLY)
7913 /* PowerPC 440 GR */
7914 POWERPC_DEF("440GR", CPU_POWERPC_440GR, 440x5),
7915 #endif
7916 #if defined(TODO_USER_ONLY)
7917 /* PowerPC 440 GRa */
7918 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5),
7919 #endif
7920 #if defined(TODO_USER_ONLY)
7921 /* PowerPC 440 GRX */
7922 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5),
7923 #endif
7924 #if defined(TODO_USER_ONLY)
7925 /* PowerPC 440 GX */
7926 POWERPC_DEF("440GX", CPU_POWERPC_440GX, 440EP),
7927 #endif
7928 #if defined(TODO_USER_ONLY)
7929 /* PowerPC 440 GXa */
7930 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP),
7931 #endif
7932 #if defined(TODO_USER_ONLY)
7933 /* PowerPC 440 GXb */
7934 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP),
7935 #endif
7936 #if defined(TODO_USER_ONLY)
7937 /* PowerPC 440 GXc */
7938 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP),
7939 #endif
7940 #if defined(TODO_USER_ONLY)
7941 /* PowerPC 440 GXf */
7942 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP),
7943 #endif
7944 #if defined(TODO)
7945 /* PowerPC 440 S */
7946 POWERPC_DEF("440S", CPU_POWERPC_440S, 440),
7947 #endif
7948 #if defined(TODO_USER_ONLY)
7949 /* PowerPC 440 SP */
7950 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP),
7951 #endif
7952 #if defined(TODO_USER_ONLY)
7953 /* PowerPC 440 SP2 */
7954 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP),
7955 #endif
7956 #if defined(TODO_USER_ONLY)
7957 /* PowerPC 440 SPE */
7958 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP),
7959 #endif
7960 /* PowerPC 460 family */
7961 #if defined (TODO)
7962 /* Generic PowerPC 464 */
7963 POWERPC_DEF("464", CPU_POWERPC_464, 460),
7964 #endif
7965 /* PowerPC 464 microcontrolers */
7966 #if defined (TODO)
7967 /* PowerPC 464H90 */
7968 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460),
7969 #endif
7970 #if defined (TODO)
7971 /* PowerPC 464H90F */
7972 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F),
7973 #endif
7974 /* Freescale embedded PowerPC cores */
7975 /* MPC5xx family (aka RCPU) */
7976 #if defined(TODO_USER_ONLY)
7977 /* Generic MPC5xx core */
7978 POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx),
7979 #endif
7980 #if defined(TODO_USER_ONLY)
7981 /* Codename for MPC5xx core */
7982 POWERPC_DEF("RCPU", CPU_POWERPC_MPC5xx, MPC5xx),
7983 #endif
7984 /* MPC5xx microcontrollers */
7985 #if defined(TODO_USER_ONLY)
7986 /* MGT560 */
7987 POWERPC_DEF("MGT560", CPU_POWERPC_MGT560, MPC5xx),
7988 #endif
7989 #if defined(TODO_USER_ONLY)
7990 /* MPC509 */
7991 POWERPC_DEF("MPC509", CPU_POWERPC_MPC509, MPC5xx),
7992 #endif
7993 #if defined(TODO_USER_ONLY)
7994 /* MPC533 */
7995 POWERPC_DEF("MPC533", CPU_POWERPC_MPC533, MPC5xx),
7996 #endif
7997 #if defined(TODO_USER_ONLY)
7998 /* MPC534 */
7999 POWERPC_DEF("MPC534", CPU_POWERPC_MPC534, MPC5xx),
8000 #endif
8001 #if defined(TODO_USER_ONLY)
8002 /* MPC555 */
8003 POWERPC_DEF("MPC555", CPU_POWERPC_MPC555, MPC5xx),
8004 #endif
8005 #if defined(TODO_USER_ONLY)
8006 /* MPC556 */
8007 POWERPC_DEF("MPC556", CPU_POWERPC_MPC556, MPC5xx),
8008 #endif
8009 #if defined(TODO_USER_ONLY)
8010 /* MPC560 */
8011 POWERPC_DEF("MPC560", CPU_POWERPC_MPC560, MPC5xx),
8012 #endif
8013 #if defined(TODO_USER_ONLY)
8014 /* MPC561 */
8015 POWERPC_DEF("MPC561", CPU_POWERPC_MPC561, MPC5xx),
8016 #endif
8017 #if defined(TODO_USER_ONLY)
8018 /* MPC562 */
8019 POWERPC_DEF("MPC562", CPU_POWERPC_MPC562, MPC5xx),
8020 #endif
8021 #if defined(TODO_USER_ONLY)
8022 /* MPC563 */
8023 POWERPC_DEF("MPC563", CPU_POWERPC_MPC563, MPC5xx),
8024 #endif
8025 #if defined(TODO_USER_ONLY)
8026 /* MPC564 */
8027 POWERPC_DEF("MPC564", CPU_POWERPC_MPC564, MPC5xx),
8028 #endif
8029 #if defined(TODO_USER_ONLY)
8030 /* MPC565 */
8031 POWERPC_DEF("MPC565", CPU_POWERPC_MPC565, MPC5xx),
8032 #endif
8033 #if defined(TODO_USER_ONLY)
8034 /* MPC566 */
8035 POWERPC_DEF("MPC566", CPU_POWERPC_MPC566, MPC5xx),
8036 #endif
8037 /* MPC8xx family (aka PowerQUICC) */
8038 #if defined(TODO_USER_ONLY)
8039 /* Generic MPC8xx core */
8040 POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx),
8041 #endif
8042 #if defined(TODO_USER_ONLY)
8043 /* Codename for MPC8xx core */
8044 POWERPC_DEF("PowerQUICC", CPU_POWERPC_MPC8xx, MPC8xx),
8045 #endif
8046 /* MPC8xx microcontrollers */
8047 #if defined(TODO_USER_ONLY)
8048 /* MGT823 */
8049 POWERPC_DEF("MGT823", CPU_POWERPC_MGT823, MPC8xx),
8050 #endif
8051 #if defined(TODO_USER_ONLY)
8052 /* MPC821 */
8053 POWERPC_DEF("MPC821", CPU_POWERPC_MPC821, MPC8xx),
8054 #endif
8055 #if defined(TODO_USER_ONLY)
8056 /* MPC823 */
8057 POWERPC_DEF("MPC823", CPU_POWERPC_MPC823, MPC8xx),
8058 #endif
8059 #if defined(TODO_USER_ONLY)
8060 /* MPC850 */
8061 POWERPC_DEF("MPC850", CPU_POWERPC_MPC850, MPC8xx),
8062 #endif
8063 #if defined(TODO_USER_ONLY)
8064 /* MPC852T */
8065 POWERPC_DEF("MPC852T", CPU_POWERPC_MPC852T, MPC8xx),
8066 #endif
8067 #if defined(TODO_USER_ONLY)
8068 /* MPC855T */
8069 POWERPC_DEF("MPC855T", CPU_POWERPC_MPC855T, MPC8xx),
8070 #endif
8071 #if defined(TODO_USER_ONLY)
8072 /* MPC857 */
8073 POWERPC_DEF("MPC857", CPU_POWERPC_MPC857, MPC8xx),
8074 #endif
8075 #if defined(TODO_USER_ONLY)
8076 /* MPC859 */
8077 POWERPC_DEF("MPC859", CPU_POWERPC_MPC859, MPC8xx),
8078 #endif
8079 #if defined(TODO_USER_ONLY)
8080 /* MPC860 */
8081 POWERPC_DEF("MPC860", CPU_POWERPC_MPC860, MPC8xx),
8082 #endif
8083 #if defined(TODO_USER_ONLY)
8084 /* MPC862 */
8085 POWERPC_DEF("MPC862", CPU_POWERPC_MPC862, MPC8xx),
8086 #endif
8087 #if defined(TODO_USER_ONLY)
8088 /* MPC866 */
8089 POWERPC_DEF("MPC866", CPU_POWERPC_MPC866, MPC8xx),
8090 #endif
8091 #if defined(TODO_USER_ONLY)
8092 /* MPC870 */
8093 POWERPC_DEF("MPC870", CPU_POWERPC_MPC870, MPC8xx),
8094 #endif
8095 #if defined(TODO_USER_ONLY)
8096 /* MPC875 */
8097 POWERPC_DEF("MPC875", CPU_POWERPC_MPC875, MPC8xx),
8098 #endif
8099 #if defined(TODO_USER_ONLY)
8100 /* MPC880 */
8101 POWERPC_DEF("MPC880", CPU_POWERPC_MPC880, MPC8xx),
8102 #endif
8103 #if defined(TODO_USER_ONLY)
8104 /* MPC885 */
8105 POWERPC_DEF("MPC885", CPU_POWERPC_MPC885, MPC8xx),
8106 #endif
8107 /* MPC82xx family (aka PowerQUICC-II) */
8108 /* Generic MPC52xx core */
8109 POWERPC_DEF_SVR("MPC52xx",
8110 CPU_POWERPC_MPC52xx, POWERPC_SVR_52xx, G2LE),
8111 /* Generic MPC82xx core */
8112 POWERPC_DEF("MPC82xx", CPU_POWERPC_MPC82xx, G2),
8113 /* Codename for MPC82xx */
8114 POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx, G2),
8115 /* PowerPC G2 core */
8116 POWERPC_DEF("G2", CPU_POWERPC_G2, G2),
8117 /* PowerPC G2 H4 core */
8118 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2),
8119 /* PowerPC G2 GP core */
8120 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2),
8121 /* PowerPC G2 LS core */
8122 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2),
8123 /* PowerPC G2 HiP3 core */
8124 POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2),
8125 /* PowerPC G2 HiP4 core */
8126 POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2),
8127 /* PowerPC MPC603 core */
8128 POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E),
8129 /* PowerPC G2le core (same as G2 plus little-endian mode support) */
8130 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE),
8131 /* PowerPC G2LE GP core */
8132 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE),
8133 /* PowerPC G2LE LS core */
8134 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE),
8135 /* PowerPC G2LE GP1 core */
8136 POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE),
8137 /* PowerPC G2LE GP3 core */
8138 POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp1, G2LE),
8139 /* PowerPC MPC603 microcontrollers */
8140 /* MPC8240 */
8141 POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240, 603E),
8142 /* PowerPC G2 microcontrollers */
8143 #if defined(TODO)
8144 /* MPC5121 */
8145 POWERPC_DEF_SVR("MPC5121",
8146 CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE),
8147 #endif
8148 /* MPC5200 */
8149 POWERPC_DEF_SVR("MPC5200",
8150 CPU_POWERPC_MPC5200, POWERPC_SVR_5200, G2LE),
8151 /* MPC5200 v1.0 */
8152 POWERPC_DEF_SVR("MPC5200_v10",
8153 CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE),
8154 /* MPC5200 v1.1 */
8155 POWERPC_DEF_SVR("MPC5200_v11",
8156 CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE),
8157 /* MPC5200 v1.2 */
8158 POWERPC_DEF_SVR("MPC5200_v12",
8159 CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE),
8160 /* MPC5200B */
8161 POWERPC_DEF_SVR("MPC5200B",
8162 CPU_POWERPC_MPC5200B, POWERPC_SVR_5200B, G2LE),
8163 /* MPC5200B v2.0 */
8164 POWERPC_DEF_SVR("MPC5200B_v20",
8165 CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE),
8166 /* MPC5200B v2.1 */
8167 POWERPC_DEF_SVR("MPC5200B_v21",
8168 CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE),
8169 /* MPC8241 */
8170 POWERPC_DEF("MPC8241", CPU_POWERPC_MPC8241, G2),
8171 /* MPC8245 */
8172 POWERPC_DEF("MPC8245", CPU_POWERPC_MPC8245, G2),
8173 /* MPC8247 */
8174 POWERPC_DEF("MPC8247", CPU_POWERPC_MPC8247, G2LE),
8175 /* MPC8248 */
8176 POWERPC_DEF("MPC8248", CPU_POWERPC_MPC8248, G2LE),
8177 /* MPC8250 */
8178 POWERPC_DEF("MPC8250", CPU_POWERPC_MPC8250, G2),
8179 /* MPC8250 HiP3 */
8180 POWERPC_DEF("MPC8250_HiP3", CPU_POWERPC_MPC8250_HiP3, G2),
8181 /* MPC8250 HiP4 */
8182 POWERPC_DEF("MPC8250_HiP4", CPU_POWERPC_MPC8250_HiP4, G2),
8183 /* MPC8255 */
8184 POWERPC_DEF("MPC8255", CPU_POWERPC_MPC8255, G2),
8185 /* MPC8255 HiP3 */
8186 POWERPC_DEF("MPC8255_HiP3", CPU_POWERPC_MPC8255_HiP3, G2),
8187 /* MPC8255 HiP4 */
8188 POWERPC_DEF("MPC8255_HiP4", CPU_POWERPC_MPC8255_HiP4, G2),
8189 /* MPC8260 */
8190 POWERPC_DEF("MPC8260", CPU_POWERPC_MPC8260, G2),
8191 /* MPC8260 HiP3 */
8192 POWERPC_DEF("MPC8260_HiP3", CPU_POWERPC_MPC8260_HiP3, G2),
8193 /* MPC8260 HiP4 */
8194 POWERPC_DEF("MPC8260_HiP4", CPU_POWERPC_MPC8260_HiP4, G2),
8195 /* MPC8264 */
8196 POWERPC_DEF("MPC8264", CPU_POWERPC_MPC8264, G2),
8197 /* MPC8264 HiP3 */
8198 POWERPC_DEF("MPC8264_HiP3", CPU_POWERPC_MPC8264_HiP3, G2),
8199 /* MPC8264 HiP4 */
8200 POWERPC_DEF("MPC8264_HiP4", CPU_POWERPC_MPC8264_HiP4, G2),
8201 /* MPC8265 */
8202 POWERPC_DEF("MPC8265", CPU_POWERPC_MPC8265, G2),
8203 /* MPC8265 HiP3 */
8204 POWERPC_DEF("MPC8265_HiP3", CPU_POWERPC_MPC8265_HiP3, G2),
8205 /* MPC8265 HiP4 */
8206 POWERPC_DEF("MPC8265_HiP4", CPU_POWERPC_MPC8265_HiP4, G2),
8207 /* MPC8266 */
8208 POWERPC_DEF("MPC8266", CPU_POWERPC_MPC8266, G2),
8209 /* MPC8266 HiP3 */
8210 POWERPC_DEF("MPC8266_HiP3", CPU_POWERPC_MPC8266_HiP3, G2),
8211 /* MPC8266 HiP4 */
8212 POWERPC_DEF("MPC8266_HiP4", CPU_POWERPC_MPC8266_HiP4, G2),
8213 /* MPC8270 */
8214 POWERPC_DEF("MPC8270", CPU_POWERPC_MPC8270, G2LE),
8215 /* MPC8271 */
8216 POWERPC_DEF("MPC8271", CPU_POWERPC_MPC8271, G2LE),
8217 /* MPC8272 */
8218 POWERPC_DEF("MPC8272", CPU_POWERPC_MPC8272, G2LE),
8219 /* MPC8275 */
8220 POWERPC_DEF("MPC8275", CPU_POWERPC_MPC8275, G2LE),
8221 /* MPC8280 */
8222 POWERPC_DEF("MPC8280", CPU_POWERPC_MPC8280, G2LE),
8223 /* e200 family */
8224 /* Generic PowerPC e200 core */
8225 POWERPC_DEF("e200", CPU_POWERPC_e200, e200),
8226 /* Generic MPC55xx core */
8227 #if defined (TODO)
8228 POWERPC_DEF_SVR("MPC55xx",
8229 CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200),
8230 #endif
8231 #if defined (TODO)
8232 /* PowerPC e200z0 core */
8233 POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200),
8234 #endif
8235 #if defined (TODO)
8236 /* PowerPC e200z1 core */
8237 POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200),
8238 #endif
8239 #if defined (TODO)
8240 /* PowerPC e200z3 core */
8241 POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200),
8242 #endif
8243 /* PowerPC e200z5 core */
8244 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200),
8245 /* PowerPC e200z6 core */
8246 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200),
8247 /* PowerPC e200 microcontrollers */
8248 #if defined (TODO)
8249 /* MPC5514E */
8250 POWERPC_DEF_SVR("MPC5514E",
8251 CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200),
8252 #endif
8253 #if defined (TODO)
8254 /* MPC5514E v0 */
8255 POWERPC_DEF_SVR("MPC5514E_v0",
8256 CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200),
8257 #endif
8258 #if defined (TODO)
8259 /* MPC5514E v1 */
8260 POWERPC_DEF_SVR("MPC5514E_v1",
8261 CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200),
8262 #endif
8263 #if defined (TODO)
8264 /* MPC5514G */
8265 POWERPC_DEF_SVR("MPC5514G",
8266 CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200),
8267 #endif
8268 #if defined (TODO)
8269 /* MPC5514G v0 */
8270 POWERPC_DEF_SVR("MPC5514G_v0",
8271 CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200),
8272 #endif
8273 #if defined (TODO)
8274 /* MPC5514G v1 */
8275 POWERPC_DEF_SVR("MPC5514G_v1",
8276 CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200),
8277 #endif
8278 #if defined (TODO)
8279 /* MPC5515S */
8280 POWERPC_DEF_SVR("MPC5515S",
8281 CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200),
8282 #endif
8283 #if defined (TODO)
8284 /* MPC5516E */
8285 POWERPC_DEF_SVR("MPC5516E",
8286 CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200),
8287 #endif
8288 #if defined (TODO)
8289 /* MPC5516E v0 */
8290 POWERPC_DEF_SVR("MPC5516E_v0",
8291 CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200),
8292 #endif
8293 #if defined (TODO)
8294 /* MPC5516E v1 */
8295 POWERPC_DEF_SVR("MPC5516E_v1",
8296 CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200),
8297 #endif
8298 #if defined (TODO)
8299 /* MPC5516G */
8300 POWERPC_DEF_SVR("MPC5516G",
8301 CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200),
8302 #endif
8303 #if defined (TODO)
8304 /* MPC5516G v0 */
8305 POWERPC_DEF_SVR("MPC5516G_v0",
8306 CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200),
8307 #endif
8308 #if defined (TODO)
8309 /* MPC5516G v1 */
8310 POWERPC_DEF_SVR("MPC5516G_v1",
8311 CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200),
8312 #endif
8313 #if defined (TODO)
8314 /* MPC5516S */
8315 POWERPC_DEF_SVR("MPC5516S",
8316 CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200),
8317 #endif
8318 #if defined (TODO)
8319 /* MPC5533 */
8320 POWERPC_DEF_SVR("MPC5533",
8321 CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200),
8322 #endif
8323 #if defined (TODO)
8324 /* MPC5534 */
8325 POWERPC_DEF_SVR("MPC5534",
8326 CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200),
8327 #endif
8328 #if defined (TODO)
8329 /* MPC5553 */
8330 POWERPC_DEF_SVR("MPC5553",
8331 CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200),
8332 #endif
8333 #if defined (TODO)
8334 /* MPC5554 */
8335 POWERPC_DEF_SVR("MPC5554",
8336 CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200),
8337 #endif
8338 #if defined (TODO)
8339 /* MPC5561 */
8340 POWERPC_DEF_SVR("MPC5561",
8341 CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200),
8342 #endif
8343 #if defined (TODO)
8344 /* MPC5565 */
8345 POWERPC_DEF_SVR("MPC5565",
8346 CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200),
8347 #endif
8348 #if defined (TODO)
8349 /* MPC5566 */
8350 POWERPC_DEF_SVR("MPC5566",
8351 CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200),
8352 #endif
8353 #if defined (TODO)
8354 /* MPC5567 */
8355 POWERPC_DEF_SVR("MPC5567",
8356 CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200),
8357 #endif
8358 /* e300 family */
8359 /* Generic PowerPC e300 core */
8360 POWERPC_DEF("e300", CPU_POWERPC_e300, e300),
8361 /* PowerPC e300c1 core */
8362 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300),
8363 /* PowerPC e300c2 core */
8364 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300),
8365 /* PowerPC e300c3 core */
8366 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300),
8367 /* PowerPC e300c4 core */
8368 POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300),
8369 /* PowerPC e300 microcontrollers */
8370 #if defined (TODO)
8371 /* MPC8313 */
8372 POWERPC_DEF_SVR("MPC8313",
8373 CPU_POWERPC_MPC831x, POWERPC_SVR_8313, e300),
8374 #endif
8375 #if defined (TODO)
8376 /* MPC8313E */
8377 POWERPC_DEF_SVR("MPC8313E",
8378 CPU_POWERPC_MPC831x, POWERPC_SVR_8313E, e300),
8379 #endif
8380 #if defined (TODO)
8381 /* MPC8314 */
8382 POWERPC_DEF_SVR("MPC8314",
8383 CPU_POWERPC_MPC831x, POWERPC_SVR_8314, e300),
8384 #endif
8385 #if defined (TODO)
8386 /* MPC8314E */
8387 POWERPC_DEF_SVR("MPC8314E",
8388 CPU_POWERPC_MPC831x, POWERPC_SVR_8314E, e300),
8389 #endif
8390 #if defined (TODO)
8391 /* MPC8315 */
8392 POWERPC_DEF_SVR("MPC8315",
8393 CPU_POWERPC_MPC831x, POWERPC_SVR_8315, e300),
8394 #endif
8395 #if defined (TODO)
8396 /* MPC8315E */
8397 POWERPC_DEF_SVR("MPC8315E",
8398 CPU_POWERPC_MPC831x, POWERPC_SVR_8315E, e300),
8399 #endif
8400 #if defined (TODO)
8401 /* MPC8321 */
8402 POWERPC_DEF_SVR("MPC8321",
8403 CPU_POWERPC_MPC832x, POWERPC_SVR_8321, e300),
8404 #endif
8405 #if defined (TODO)
8406 /* MPC8321E */
8407 POWERPC_DEF_SVR("MPC8321E",
8408 CPU_POWERPC_MPC832x, POWERPC_SVR_8321E, e300),
8409 #endif
8410 #if defined (TODO)
8411 /* MPC8323 */
8412 POWERPC_DEF_SVR("MPC8323",
8413 CPU_POWERPC_MPC832x, POWERPC_SVR_8323, e300),
8414 #endif
8415 #if defined (TODO)
8416 /* MPC8323E */
8417 POWERPC_DEF_SVR("MPC8323E",
8418 CPU_POWERPC_MPC832x, POWERPC_SVR_8323E, e300),
8419 #endif
8420 /* MPC8343 */
8421 POWERPC_DEF_SVR("MPC8343",
8422 CPU_POWERPC_MPC834x, POWERPC_SVR_8343, e300),
8423 /* MPC8343A */
8424 POWERPC_DEF_SVR("MPC8343A",
8425 CPU_POWERPC_MPC834x, POWERPC_SVR_8343A, e300),
8426 /* MPC8343E */
8427 POWERPC_DEF_SVR("MPC8343E",
8428 CPU_POWERPC_MPC834x, POWERPC_SVR_8343E, e300),
8429 /* MPC8343EA */
8430 POWERPC_DEF_SVR("MPC8343EA",
8431 CPU_POWERPC_MPC834x, POWERPC_SVR_8343EA, e300),
8432 /* MPC8347 */
8433 POWERPC_DEF_SVR("MPC8347",
8434 CPU_POWERPC_MPC834x, POWERPC_SVR_8347, e300),
8435 /* MPC8347T */
8436 POWERPC_DEF_SVR("MPC8347T",
8437 CPU_POWERPC_MPC834x, POWERPC_SVR_8347T, e300),
8438 /* MPC8347P */
8439 POWERPC_DEF_SVR("MPC8347P",
8440 CPU_POWERPC_MPC834x, POWERPC_SVR_8347P, e300),
8441 /* MPC8347A */
8442 POWERPC_DEF_SVR("MPC8347A",
8443 CPU_POWERPC_MPC834x, POWERPC_SVR_8347A, e300),
8444 /* MPC8347AT */
8445 POWERPC_DEF_SVR("MPC8347AT",
8446 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AT, e300),
8447 /* MPC8347AP */
8448 POWERPC_DEF_SVR("MPC8347AP",
8449 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AP, e300),
8450 /* MPC8347E */
8451 POWERPC_DEF_SVR("MPC8347E",
8452 CPU_POWERPC_MPC834x, POWERPC_SVR_8347E, e300),
8453 /* MPC8347ET */
8454 POWERPC_DEF_SVR("MPC8347ET",
8455 CPU_POWERPC_MPC834x, POWERPC_SVR_8347ET, e300),
8456 /* MPC8343EP */
8457 POWERPC_DEF_SVR("MPC8347EP",
8458 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EP, e300),
8459 /* MPC8347EA */
8460 POWERPC_DEF_SVR("MPC8347EA",
8461 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EA, e300),
8462 /* MPC8347EAT */
8463 POWERPC_DEF_SVR("MPC8347EAT",
8464 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAT, e300),
8465 /* MPC8343EAP */
8466 POWERPC_DEF_SVR("MPC8347EAP",
8467 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAP, e300),
8468 /* MPC8349 */
8469 POWERPC_DEF_SVR("MPC8349",
8470 CPU_POWERPC_MPC834x, POWERPC_SVR_8349, e300),
8471 /* MPC8349A */
8472 POWERPC_DEF_SVR("MPC8349A",
8473 CPU_POWERPC_MPC834x, POWERPC_SVR_8349A, e300),
8474 /* MPC8349E */
8475 POWERPC_DEF_SVR("MPC8349E",
8476 CPU_POWERPC_MPC834x, POWERPC_SVR_8349E, e300),
8477 /* MPC8349EA */
8478 POWERPC_DEF_SVR("MPC8349EA",
8479 CPU_POWERPC_MPC834x, POWERPC_SVR_8349EA, e300),
8480 #if defined (TODO)
8481 /* MPC8358E */
8482 POWERPC_DEF_SVR("MPC8358E",
8483 CPU_POWERPC_MPC835x, POWERPC_SVR_8358E, e300),
8484 #endif
8485 #if defined (TODO)
8486 /* MPC8360E */
8487 POWERPC_DEF_SVR("MPC8360E",
8488 CPU_POWERPC_MPC836x, POWERPC_SVR_8360E, e300),
8489 #endif
8490 /* MPC8377 */
8491 POWERPC_DEF_SVR("MPC8377",
8492 CPU_POWERPC_MPC837x, POWERPC_SVR_8377, e300),
8493 /* MPC8377E */
8494 POWERPC_DEF_SVR("MPC8377E",
8495 CPU_POWERPC_MPC837x, POWERPC_SVR_8377E, e300),
8496 /* MPC8378 */
8497 POWERPC_DEF_SVR("MPC8378",
8498 CPU_POWERPC_MPC837x, POWERPC_SVR_8378, e300),
8499 /* MPC8378E */
8500 POWERPC_DEF_SVR("MPC8378E",
8501 CPU_POWERPC_MPC837x, POWERPC_SVR_8378E, e300),
8502 /* MPC8379 */
8503 POWERPC_DEF_SVR("MPC8379",
8504 CPU_POWERPC_MPC837x, POWERPC_SVR_8379, e300),
8505 /* MPC8379E */
8506 POWERPC_DEF_SVR("MPC8379E",
8507 CPU_POWERPC_MPC837x, POWERPC_SVR_8379E, e300),
8508 /* e500 family */
8509 /* PowerPC e500 core */
8510 POWERPC_DEF("e500", CPU_POWERPC_e500v2_v22, e500v2),
8511 /* PowerPC e500v1 core */
8512 POWERPC_DEF("e500v1", CPU_POWERPC_e500v1, e500v1),
8513 /* PowerPC e500 v1.0 core */
8514 POWERPC_DEF("e500_v10", CPU_POWERPC_e500v1_v10, e500v1),
8515 /* PowerPC e500 v2.0 core */
8516 POWERPC_DEF("e500_v20", CPU_POWERPC_e500v1_v20, e500v1),
8517 /* PowerPC e500v2 core */
8518 POWERPC_DEF("e500v2", CPU_POWERPC_e500v2, e500v2),
8519 /* PowerPC e500v2 v1.0 core */
8520 POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500v2),
8521 /* PowerPC e500v2 v2.0 core */
8522 POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500v2),
8523 /* PowerPC e500v2 v2.1 core */
8524 POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500v2),
8525 /* PowerPC e500v2 v2.2 core */
8526 POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500v2),
8527 /* PowerPC e500v2 v3.0 core */
8528 POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500v2),
8529 POWERPC_DEF("e500mc", CPU_POWERPC_e500mc, e500mc),
8530 /* PowerPC e500 microcontrollers */
8531 /* MPC8533 */
8532 POWERPC_DEF_SVR("MPC8533",
8533 CPU_POWERPC_MPC8533, POWERPC_SVR_8533, e500v2),
8534 /* MPC8533 v1.0 */
8535 POWERPC_DEF_SVR("MPC8533_v10",
8536 CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500v2),
8537 /* MPC8533 v1.1 */
8538 POWERPC_DEF_SVR("MPC8533_v11",
8539 CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500v2),
8540 /* MPC8533E */
8541 POWERPC_DEF_SVR("MPC8533E",
8542 CPU_POWERPC_MPC8533E, POWERPC_SVR_8533E, e500v2),
8543 /* MPC8533E v1.0 */
8544 POWERPC_DEF_SVR("MPC8533E_v10",
8545 CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2),
8546 POWERPC_DEF_SVR("MPC8533E_v11",
8547 CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2),
8548 /* MPC8540 */
8549 POWERPC_DEF_SVR("MPC8540",
8550 CPU_POWERPC_MPC8540, POWERPC_SVR_8540, e500v1),
8551 /* MPC8540 v1.0 */
8552 POWERPC_DEF_SVR("MPC8540_v10",
8553 CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500v1),
8554 /* MPC8540 v2.0 */
8555 POWERPC_DEF_SVR("MPC8540_v20",
8556 CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500v1),
8557 /* MPC8540 v2.1 */
8558 POWERPC_DEF_SVR("MPC8540_v21",
8559 CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500v1),
8560 /* MPC8541 */
8561 POWERPC_DEF_SVR("MPC8541",
8562 CPU_POWERPC_MPC8541, POWERPC_SVR_8541, e500v1),
8563 /* MPC8541 v1.0 */
8564 POWERPC_DEF_SVR("MPC8541_v10",
8565 CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500v1),
8566 /* MPC8541 v1.1 */
8567 POWERPC_DEF_SVR("MPC8541_v11",
8568 CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500v1),
8569 /* MPC8541E */
8570 POWERPC_DEF_SVR("MPC8541E",
8571 CPU_POWERPC_MPC8541E, POWERPC_SVR_8541E, e500v1),
8572 /* MPC8541E v1.0 */
8573 POWERPC_DEF_SVR("MPC8541E_v10",
8574 CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1),
8575 /* MPC8541E v1.1 */
8576 POWERPC_DEF_SVR("MPC8541E_v11",
8577 CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1),
8578 /* MPC8543 */
8579 POWERPC_DEF_SVR("MPC8543",
8580 CPU_POWERPC_MPC8543, POWERPC_SVR_8543, e500v2),
8581 /* MPC8543 v1.0 */
8582 POWERPC_DEF_SVR("MPC8543_v10",
8583 CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500v2),
8584 /* MPC8543 v1.1 */
8585 POWERPC_DEF_SVR("MPC8543_v11",
8586 CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500v2),
8587 /* MPC8543 v2.0 */
8588 POWERPC_DEF_SVR("MPC8543_v20",
8589 CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500v2),
8590 /* MPC8543 v2.1 */
8591 POWERPC_DEF_SVR("MPC8543_v21",
8592 CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500v2),
8593 /* MPC8543E */
8594 POWERPC_DEF_SVR("MPC8543E",
8595 CPU_POWERPC_MPC8543E, POWERPC_SVR_8543E, e500v2),
8596 /* MPC8543E v1.0 */
8597 POWERPC_DEF_SVR("MPC8543E_v10",
8598 CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2),
8599 /* MPC8543E v1.1 */
8600 POWERPC_DEF_SVR("MPC8543E_v11",
8601 CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500v2),
8602 /* MPC8543E v2.0 */
8603 POWERPC_DEF_SVR("MPC8543E_v20",
8604 CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500v2),
8605 /* MPC8543E v2.1 */
8606 POWERPC_DEF_SVR("MPC8543E_v21",
8607 CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2),
8608 /* MPC8544 */
8609 POWERPC_DEF_SVR("MPC8544",
8610 CPU_POWERPC_MPC8544, POWERPC_SVR_8544, e500v2),
8611 /* MPC8544 v1.0 */
8612 POWERPC_DEF_SVR("MPC8544_v10",
8613 CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500v2),
8614 /* MPC8544 v1.1 */
8615 POWERPC_DEF_SVR("MPC8544_v11",
8616 CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500v2),
8617 /* MPC8544E */
8618 POWERPC_DEF_SVR("MPC8544E",
8619 CPU_POWERPC_MPC8544E, POWERPC_SVR_8544E, e500v2),
8620 /* MPC8544E v1.0 */
8621 POWERPC_DEF_SVR("MPC8544E_v10",
8622 CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2),
8623 /* MPC8544E v1.1 */
8624 POWERPC_DEF_SVR("MPC8544E_v11",
8625 CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2),
8626 /* MPC8545 */
8627 POWERPC_DEF_SVR("MPC8545",
8628 CPU_POWERPC_MPC8545, POWERPC_SVR_8545, e500v2),
8629 /* MPC8545 v2.0 */
8630 POWERPC_DEF_SVR("MPC8545_v20",
8631 CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500v2),
8632 /* MPC8545 v2.1 */
8633 POWERPC_DEF_SVR("MPC8545_v21",
8634 CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500v2),
8635 /* MPC8545E */
8636 POWERPC_DEF_SVR("MPC8545E",
8637 CPU_POWERPC_MPC8545E, POWERPC_SVR_8545E, e500v2),
8638 /* MPC8545E v2.0 */
8639 POWERPC_DEF_SVR("MPC8545E_v20",
8640 CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2),
8641 /* MPC8545E v2.1 */
8642 POWERPC_DEF_SVR("MPC8545E_v21",
8643 CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2),
8644 /* MPC8547E */
8645 POWERPC_DEF_SVR("MPC8547E",
8646 CPU_POWERPC_MPC8547E, POWERPC_SVR_8547E, e500v2),
8647 /* MPC8547E v2.0 */
8648 POWERPC_DEF_SVR("MPC8547E_v20",
8649 CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2),
8650 /* MPC8547E v2.1 */
8651 POWERPC_DEF_SVR("MPC8547E_v21",
8652 CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2),
8653 /* MPC8548 */
8654 POWERPC_DEF_SVR("MPC8548",
8655 CPU_POWERPC_MPC8548, POWERPC_SVR_8548, e500v2),
8656 /* MPC8548 v1.0 */
8657 POWERPC_DEF_SVR("MPC8548_v10",
8658 CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500v2),
8659 /* MPC8548 v1.1 */
8660 POWERPC_DEF_SVR("MPC8548_v11",
8661 CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500v2),
8662 /* MPC8548 v2.0 */
8663 POWERPC_DEF_SVR("MPC8548_v20",
8664 CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500v2),
8665 /* MPC8548 v2.1 */
8666 POWERPC_DEF_SVR("MPC8548_v21",
8667 CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500v2),
8668 /* MPC8548E */
8669 POWERPC_DEF_SVR("MPC8548E",
8670 CPU_POWERPC_MPC8548E, POWERPC_SVR_8548E, e500v2),
8671 /* MPC8548E v1.0 */
8672 POWERPC_DEF_SVR("MPC8548E_v10",
8673 CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2),
8674 /* MPC8548E v1.1 */
8675 POWERPC_DEF_SVR("MPC8548E_v11",
8676 CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500v2),
8677 /* MPC8548E v2.0 */
8678 POWERPC_DEF_SVR("MPC8548E_v20",
8679 CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500v2),
8680 /* MPC8548E v2.1 */
8681 POWERPC_DEF_SVR("MPC8548E_v21",
8682 CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2),
8683 /* MPC8555 */
8684 POWERPC_DEF_SVR("MPC8555",
8685 CPU_POWERPC_MPC8555, POWERPC_SVR_8555, e500v2),
8686 /* MPC8555 v1.0 */
8687 POWERPC_DEF_SVR("MPC8555_v10",
8688 CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500v2),
8689 /* MPC8555 v1.1 */
8690 POWERPC_DEF_SVR("MPC8555_v11",
8691 CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500v2),
8692 /* MPC8555E */
8693 POWERPC_DEF_SVR("MPC8555E",
8694 CPU_POWERPC_MPC8555E, POWERPC_SVR_8555E, e500v2),
8695 /* MPC8555E v1.0 */
8696 POWERPC_DEF_SVR("MPC8555E_v10",
8697 CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2),
8698 /* MPC8555E v1.1 */
8699 POWERPC_DEF_SVR("MPC8555E_v11",
8700 CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2),
8701 /* MPC8560 */
8702 POWERPC_DEF_SVR("MPC8560",
8703 CPU_POWERPC_MPC8560, POWERPC_SVR_8560, e500v2),
8704 /* MPC8560 v1.0 */
8705 POWERPC_DEF_SVR("MPC8560_v10",
8706 CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500v2),
8707 /* MPC8560 v2.0 */
8708 POWERPC_DEF_SVR("MPC8560_v20",
8709 CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500v2),
8710 /* MPC8560 v2.1 */
8711 POWERPC_DEF_SVR("MPC8560_v21",
8712 CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500v2),
8713 /* MPC8567 */
8714 POWERPC_DEF_SVR("MPC8567",
8715 CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500v2),
8716 /* MPC8567E */
8717 POWERPC_DEF_SVR("MPC8567E",
8718 CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500v2),
8719 /* MPC8568 */
8720 POWERPC_DEF_SVR("MPC8568",
8721 CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500v2),
8722 /* MPC8568E */
8723 POWERPC_DEF_SVR("MPC8568E",
8724 CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500v2),
8725 /* MPC8572 */
8726 POWERPC_DEF_SVR("MPC8572",
8727 CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500v2),
8728 /* MPC8572E */
8729 POWERPC_DEF_SVR("MPC8572E",
8730 CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500v2),
8731 /* e600 family */
8732 /* PowerPC e600 core */
8733 POWERPC_DEF("e600", CPU_POWERPC_e600, 7400),
8734 /* PowerPC e600 microcontrollers */
8735 #if defined (TODO)
8736 /* MPC8610 */
8737 POWERPC_DEF_SVR("MPC8610",
8738 CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400),
8739 #endif
8740 /* MPC8641 */
8741 POWERPC_DEF_SVR("MPC8641",
8742 CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400),
8743 /* MPC8641D */
8744 POWERPC_DEF_SVR("MPC8641D",
8745 CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400),
8746 /* 32 bits "classic" PowerPC */
8747 /* PowerPC 6xx family */
8748 /* PowerPC 601 */
8749 POWERPC_DEF("601", CPU_POWERPC_601, 601v),
8750 /* PowerPC 601v0 */
8751 POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601),
8752 /* PowerPC 601v1 */
8753 POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601),
8754 /* PowerPC 601v */
8755 POWERPC_DEF("601v", CPU_POWERPC_601v, 601v),
8756 /* PowerPC 601v2 */
8757 POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v),
8758 /* PowerPC 602 */
8759 POWERPC_DEF("602", CPU_POWERPC_602, 602),
8760 /* PowerPC 603 */
8761 POWERPC_DEF("603", CPU_POWERPC_603, 603),
8762 /* Code name for PowerPC 603 */
8763 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603),
8764 /* PowerPC 603e (aka PID6) */
8765 POWERPC_DEF("603e", CPU_POWERPC_603E, 603E),
8766 /* Code name for PowerPC 603e */
8767 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E),
8768 /* PowerPC 603e v1.1 */
8769 POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E),
8770 /* PowerPC 603e v1.2 */
8771 POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E),
8772 /* PowerPC 603e v1.3 */
8773 POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E),
8774 /* PowerPC 603e v1.4 */
8775 POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E),
8776 /* PowerPC 603e v2.2 */
8777 POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E),
8778 /* PowerPC 603e v3 */
8779 POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E),
8780 /* PowerPC 603e v4 */
8781 POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E),
8782 /* PowerPC 603e v4.1 */
8783 POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E),
8784 /* PowerPC 603e (aka PID7) */
8785 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E),
8786 /* PowerPC 603e7t */
8787 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E),
8788 /* PowerPC 603e7v */
8789 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E),
8790 /* Code name for PowerPC 603ev */
8791 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 603E),
8792 /* PowerPC 603e7v1 */
8793 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E),
8794 /* PowerPC 603e7v2 */
8795 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E),
8796 /* PowerPC 603p (aka PID7v) */
8797 POWERPC_DEF("603p", CPU_POWERPC_603P, 603E),
8798 /* PowerPC 603r (aka PID7t) */
8799 POWERPC_DEF("603r", CPU_POWERPC_603R, 603E),
8800 /* Code name for PowerPC 603r */
8801 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E),
8802 /* PowerPC 604 */
8803 POWERPC_DEF("604", CPU_POWERPC_604, 604),
8804 /* PowerPC 604e (aka PID9) */
8805 POWERPC_DEF("604e", CPU_POWERPC_604E, 604E),
8806 /* Code name for PowerPC 604e */
8807 POWERPC_DEF("Sirocco", CPU_POWERPC_604E, 604E),
8808 /* PowerPC 604e v1.0 */
8809 POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E),
8810 /* PowerPC 604e v2.2 */
8811 POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604E),
8812 /* PowerPC 604e v2.4 */
8813 POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E),
8814 /* PowerPC 604r (aka PIDA) */
8815 POWERPC_DEF("604r", CPU_POWERPC_604R, 604E),
8816 /* Code name for PowerPC 604r */
8817 POWERPC_DEF("Mach5", CPU_POWERPC_604R, 604E),
8818 #if defined(TODO)
8819 /* PowerPC 604ev */
8820 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E),
8821 #endif
8822 /* PowerPC 7xx family */
8823 /* Generic PowerPC 740 (G3) */
8824 POWERPC_DEF("740", CPU_POWERPC_7x0, 740),
8825 /* Code name for PowerPC 740 */
8826 POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 740),
8827 /* Generic PowerPC 750 (G3) */
8828 POWERPC_DEF("750", CPU_POWERPC_7x0, 750),
8829 /* Code name for PowerPC 750 */
8830 POWERPC_DEF("Typhoon", CPU_POWERPC_7x0, 750),
8831 /* PowerPC 740/750 is also known as G3 */
8832 POWERPC_DEF("G3", CPU_POWERPC_7x0, 750),
8833 /* PowerPC 740 v1.0 (G3) */
8834 POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740),
8835 /* PowerPC 750 v1.0 (G3) */
8836 POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10, 750),
8837 /* PowerPC 740 v2.0 (G3) */
8838 POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 740),
8839 /* PowerPC 750 v2.0 (G3) */
8840 POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 750),
8841 /* PowerPC 740 v2.1 (G3) */
8842 POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 740),
8843 /* PowerPC 750 v2.1 (G3) */
8844 POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 750),
8845 /* PowerPC 740 v2.2 (G3) */
8846 POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 740),
8847 /* PowerPC 750 v2.2 (G3) */
8848 POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 750),
8849 /* PowerPC 740 v3.0 (G3) */
8850 POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 740),
8851 /* PowerPC 750 v3.0 (G3) */
8852 POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 750),
8853 /* PowerPC 740 v3.1 (G3) */
8854 POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 740),
8855 /* PowerPC 750 v3.1 (G3) */
8856 POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 750),
8857 /* PowerPC 740E (G3) */
8858 POWERPC_DEF("740e", CPU_POWERPC_740E, 740),
8859 /* PowerPC 750E (G3) */
8860 POWERPC_DEF("750e", CPU_POWERPC_750E, 750),
8861 /* PowerPC 740P (G3) */
8862 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740),
8863 /* PowerPC 750P (G3) */
8864 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750),
8865 /* Code name for PowerPC 740P/750P (G3) */
8866 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 750),
8867 /* PowerPC 750CL (G3 embedded) */
8868 POWERPC_DEF("750cl", CPU_POWERPC_750CL, 750cl),
8869 /* PowerPC 750CL v1.0 */
8870 POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750cl),
8871 /* PowerPC 750CL v2.0 */
8872 POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750cl),
8873 /* PowerPC 750CX (G3 embedded) */
8874 POWERPC_DEF("750cx", CPU_POWERPC_750CX, 750cx),
8875 /* PowerPC 750CX v1.0 (G3 embedded) */
8876 POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750cx),
8877 /* PowerPC 750CX v2.1 (G3 embedded) */
8878 POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20, 750cx),
8879 /* PowerPC 750CX v2.1 (G3 embedded) */
8880 POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750cx),
8881 /* PowerPC 750CX v2.2 (G3 embedded) */
8882 POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750cx),
8883 /* PowerPC 750CXe (G3 embedded) */
8884 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 750cx),
8885 /* PowerPC 750CXe v2.1 (G3 embedded) */
8886 POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750cx),
8887 /* PowerPC 750CXe v2.2 (G3 embedded) */
8888 POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 750cx),
8889 /* PowerPC 750CXe v2.3 (G3 embedded) */
8890 POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 750cx),
8891 /* PowerPC 750CXe v2.4 (G3 embedded) */
8892 POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 750cx),
8893 /* PowerPC 750CXe v2.4b (G3 embedded) */
8894 POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 750cx),
8895 /* PowerPC 750CXe v3.0 (G3 embedded) */
8896 POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30, 750cx),
8897 /* PowerPC 750CXe v3.1 (G3 embedded) */
8898 POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 750cx),
8899 /* PowerPC 750CXe v3.1b (G3 embedded) */
8900 POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 750cx),
8901 /* PowerPC 750CXr (G3 embedded) */
8902 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750cx),
8903 /* PowerPC 750FL (G3 embedded) */
8904 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx),
8905 /* PowerPC 750FX (G3 embedded) */
8906 POWERPC_DEF("750fx", CPU_POWERPC_750FX, 750fx),
8907 /* PowerPC 750FX v1.0 (G3 embedded) */
8908 POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx),
8909 /* PowerPC 750FX v2.0 (G3 embedded) */
8910 POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx),
8911 /* PowerPC 750FX v2.1 (G3 embedded) */
8912 POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx),
8913 /* PowerPC 750FX v2.2 (G3 embedded) */
8914 POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx),
8915 /* PowerPC 750FX v2.3 (G3 embedded) */
8916 POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx),
8917 /* PowerPC 750GL (G3 embedded) */
8918 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750gx),
8919 /* PowerPC 750GX (G3 embedded) */
8920 POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750gx),
8921 /* PowerPC 750GX v1.0 (G3 embedded) */
8922 POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750gx),
8923 /* PowerPC 750GX v1.1 (G3 embedded) */
8924 POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750gx),
8925 /* PowerPC 750GX v1.2 (G3 embedded) */
8926 POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750gx),
8927 /* PowerPC 750L (G3 embedded) */
8928 POWERPC_DEF("750l", CPU_POWERPC_750L, 750),
8929 /* Code name for PowerPC 750L (G3 embedded) */
8930 POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 750),
8931 /* PowerPC 750L v2.0 (G3 embedded) */
8932 POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750),
8933 /* PowerPC 750L v2.1 (G3 embedded) */
8934 POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21, 750),
8935 /* PowerPC 750L v2.2 (G3 embedded) */
8936 POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 750),
8937 /* PowerPC 750L v3.0 (G3 embedded) */
8938 POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750),
8939 /* PowerPC 750L v3.2 (G3 embedded) */
8940 POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750),
8941 /* Generic PowerPC 745 */
8942 POWERPC_DEF("745", CPU_POWERPC_7x5, 745),
8943 /* Generic PowerPC 755 */
8944 POWERPC_DEF("755", CPU_POWERPC_7x5, 755),
8945 /* Code name for PowerPC 745/755 */
8946 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 755),
8947 /* PowerPC 745 v1.0 */
8948 POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745),
8949 /* PowerPC 755 v1.0 */
8950 POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 755),
8951 /* PowerPC 745 v1.1 */
8952 POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 745),
8953 /* PowerPC 755 v1.1 */
8954 POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 755),
8955 /* PowerPC 745 v2.0 */
8956 POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 745),
8957 /* PowerPC 755 v2.0 */
8958 POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 755),
8959 /* PowerPC 745 v2.1 */
8960 POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 745),
8961 /* PowerPC 755 v2.1 */
8962 POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 755),
8963 /* PowerPC 745 v2.2 */
8964 POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 745),
8965 /* PowerPC 755 v2.2 */
8966 POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 755),
8967 /* PowerPC 745 v2.3 */
8968 POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 745),
8969 /* PowerPC 755 v2.3 */
8970 POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 755),
8971 /* PowerPC 745 v2.4 */
8972 POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 745),
8973 /* PowerPC 755 v2.4 */
8974 POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 755),
8975 /* PowerPC 745 v2.5 */
8976 POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 745),
8977 /* PowerPC 755 v2.5 */
8978 POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 755),
8979 /* PowerPC 745 v2.6 */
8980 POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 745),
8981 /* PowerPC 755 v2.6 */
8982 POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 755),
8983 /* PowerPC 745 v2.7 */
8984 POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 745),
8985 /* PowerPC 755 v2.7 */
8986 POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 755),
8987 /* PowerPC 745 v2.8 */
8988 POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 745),
8989 /* PowerPC 755 v2.8 */
8990 POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755),
8991 #if defined (TODO)
8992 /* PowerPC 745P (G3) */
8993 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745),
8994 /* PowerPC 755P (G3) */
8995 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755),
8996 #endif
8997 /* PowerPC 74xx family */
8998 /* PowerPC 7400 (G4) */
8999 POWERPC_DEF("7400", CPU_POWERPC_7400, 7400),
9000 /* Code name for PowerPC 7400 */
9001 POWERPC_DEF("Max", CPU_POWERPC_7400, 7400),
9002 /* PowerPC 74xx is also well known as G4 */
9003 POWERPC_DEF("G4", CPU_POWERPC_7400, 7400),
9004 /* PowerPC 7400 v1.0 (G4) */
9005 POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400),
9006 /* PowerPC 7400 v1.1 (G4) */
9007 POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400),
9008 /* PowerPC 7400 v2.0 (G4) */
9009 POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400),
9010 /* PowerPC 7400 v2.1 (G4) */
9011 POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21, 7400),
9012 /* PowerPC 7400 v2.2 (G4) */
9013 POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400),
9014 /* PowerPC 7400 v2.6 (G4) */
9015 POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400),
9016 /* PowerPC 7400 v2.7 (G4) */
9017 POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400),
9018 /* PowerPC 7400 v2.8 (G4) */
9019 POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400),
9020 /* PowerPC 7400 v2.9 (G4) */
9021 POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400),
9022 /* PowerPC 7410 (G4) */
9023 POWERPC_DEF("7410", CPU_POWERPC_7410, 7410),
9024 /* Code name for PowerPC 7410 */
9025 POWERPC_DEF("Nitro", CPU_POWERPC_7410, 7410),
9026 /* PowerPC 7410 v1.0 (G4) */
9027 POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410),
9028 /* PowerPC 7410 v1.1 (G4) */
9029 POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410),
9030 /* PowerPC 7410 v1.2 (G4) */
9031 POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410),
9032 /* PowerPC 7410 v1.3 (G4) */
9033 POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410),
9034 /* PowerPC 7410 v1.4 (G4) */
9035 POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410),
9036 /* PowerPC 7448 (G4) */
9037 POWERPC_DEF("7448", CPU_POWERPC_7448, 7400),
9038 /* PowerPC 7448 v1.0 (G4) */
9039 POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400),
9040 /* PowerPC 7448 v1.1 (G4) */
9041 POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400),
9042 /* PowerPC 7448 v2.0 (G4) */
9043 POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400),
9044 /* PowerPC 7448 v2.1 (G4) */
9045 POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400),
9046 /* PowerPC 7450 (G4) */
9047 POWERPC_DEF("7450", CPU_POWERPC_7450, 7450),
9048 /* Code name for PowerPC 7450 */
9049 POWERPC_DEF("Vger", CPU_POWERPC_7450, 7450),
9050 /* PowerPC 7450 v1.0 (G4) */
9051 POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450),
9052 /* PowerPC 7450 v1.1 (G4) */
9053 POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450),
9054 /* PowerPC 7450 v1.2 (G4) */
9055 POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450),
9056 /* PowerPC 7450 v2.0 (G4) */
9057 POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450),
9058 /* PowerPC 7450 v2.1 (G4) */
9059 POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450),
9060 /* PowerPC 7441 (G4) */
9061 POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440),
9062 /* PowerPC 7451 (G4) */
9063 POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450),
9064 /* PowerPC 7441 v2.1 (G4) */
9065 POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21, 7440),
9066 /* PowerPC 7441 v2.3 (G4) */
9067 POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23, 7440),
9068 /* PowerPC 7451 v2.3 (G4) */
9069 POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23, 7450),
9070 /* PowerPC 7441 v2.10 (G4) */
9071 POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210, 7440),
9072 /* PowerPC 7451 v2.10 (G4) */
9073 POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210, 7450),
9074 /* PowerPC 7445 (G4) */
9075 POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445),
9076 /* PowerPC 7455 (G4) */
9077 POWERPC_DEF("7455", CPU_POWERPC_74x5, 7455),
9078 /* Code name for PowerPC 7445/7455 */
9079 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 7455),
9080 /* PowerPC 7445 v1.0 (G4) */
9081 POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445),
9082 /* PowerPC 7455 v1.0 (G4) */
9083 POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455),
9084 /* PowerPC 7445 v2.1 (G4) */
9085 POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445),
9086 /* PowerPC 7455 v2.1 (G4) */
9087 POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455),
9088 /* PowerPC 7445 v3.2 (G4) */
9089 POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445),
9090 /* PowerPC 7455 v3.2 (G4) */
9091 POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455),
9092 /* PowerPC 7445 v3.3 (G4) */
9093 POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445),
9094 /* PowerPC 7455 v3.3 (G4) */
9095 POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455),
9096 /* PowerPC 7445 v3.4 (G4) */
9097 POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445),
9098 /* PowerPC 7455 v3.4 (G4) */
9099 POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455),
9100 /* PowerPC 7447 (G4) */
9101 POWERPC_DEF("7447", CPU_POWERPC_74x7, 7445),
9102 /* PowerPC 7457 (G4) */
9103 POWERPC_DEF("7457", CPU_POWERPC_74x7, 7455),
9104 /* Code name for PowerPC 7447/7457 */
9105 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 7455),
9106 /* PowerPC 7447 v1.0 (G4) */
9107 POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445),
9108 /* PowerPC 7457 v1.0 (G4) */
9109 POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455),
9110 /* PowerPC 7447 v1.1 (G4) */
9111 POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445),
9112 /* PowerPC 7457 v1.1 (G4) */
9113 POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455),
9114 /* PowerPC 7457 v1.2 (G4) */
9115 POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455),
9116 /* PowerPC 7447A (G4) */
9117 POWERPC_DEF("7447A", CPU_POWERPC_74x7A, 7445),
9118 /* PowerPC 7457A (G4) */
9119 POWERPC_DEF("7457A", CPU_POWERPC_74x7A, 7455),
9120 /* PowerPC 7447A v1.0 (G4) */
9121 POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445),
9122 /* PowerPC 7457A v1.0 (G4) */
9123 POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455),
9124 /* Code name for PowerPC 7447A/7457A */
9125 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7A_v10, 7455),
9126 /* PowerPC 7447A v1.1 (G4) */
9127 POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445),
9128 /* PowerPC 7457A v1.1 (G4) */
9129 POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455),
9130 /* PowerPC 7447A v1.2 (G4) */
9131 POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445),
9132 /* PowerPC 7457A v1.2 (G4) */
9133 POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455),
9134 /* 64 bits PowerPC */
9135 #if defined (TARGET_PPC64)
9136 /* PowerPC 620 */
9137 POWERPC_DEF("620", CPU_POWERPC_620, 620),
9138 /* Code name for PowerPC 620 */
9139 POWERPC_DEF("Trident", CPU_POWERPC_620, 620),
9140 #if defined (TODO)
9141 /* PowerPC 630 (POWER3) */
9142 POWERPC_DEF("630", CPU_POWERPC_630, 630),
9143 POWERPC_DEF("POWER3", CPU_POWERPC_630, 630),
9144 /* Code names for POWER3 */
9145 POWERPC_DEF("Boxer", CPU_POWERPC_630, 630),
9146 POWERPC_DEF("Dino", CPU_POWERPC_630, 630),
9147 #endif
9148 #if defined (TODO)
9149 /* PowerPC 631 (Power 3+) */
9150 POWERPC_DEF("631", CPU_POWERPC_631, 631),
9151 POWERPC_DEF("POWER3+", CPU_POWERPC_631, 631),
9152 #endif
9153 #if defined (TODO)
9154 /* POWER4 */
9155 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4),
9156 #endif
9157 #if defined (TODO)
9158 /* POWER4p */
9159 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P),
9160 #endif
9161 #if defined (TODO)
9162 /* POWER5 */
9163 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5),
9164 /* POWER5GR */
9165 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5),
9166 #endif
9167 #if defined (TODO)
9168 /* POWER5+ */
9169 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P),
9170 /* POWER5GS */
9171 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P),
9172 #endif
9173 #if defined (TODO)
9174 /* POWER6 */
9175 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6),
9176 /* POWER6 running in POWER5 mode */
9177 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5),
9178 /* POWER6A */
9179 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6),
9180 #endif
9181 /* POWER7 */
9182 POWERPC_DEF("POWER7", CPU_POWERPC_POWER7, POWER7),
9183 POWERPC_DEF("POWER7_v2.0", CPU_POWERPC_POWER7_v20, POWER7),
9184 POWERPC_DEF("POWER7_v2.1", CPU_POWERPC_POWER7_v21, POWER7),
9185 POWERPC_DEF("POWER7_v2.3", CPU_POWERPC_POWER7_v23, POWER7),
9186 /* PowerPC 970 */
9187 POWERPC_DEF("970", CPU_POWERPC_970, 970),
9188 /* PowerPC 970FX (G5) */
9189 POWERPC_DEF("970fx", CPU_POWERPC_970FX, 970FX),
9190 /* PowerPC 970FX v1.0 (G5) */
9191 POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX),
9192 /* PowerPC 970FX v2.0 (G5) */
9193 POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX),
9194 /* PowerPC 970FX v2.1 (G5) */
9195 POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX),
9196 /* PowerPC 970FX v3.0 (G5) */
9197 POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX),
9198 /* PowerPC 970FX v3.1 (G5) */
9199 POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX),
9200 /* PowerPC 970GX (G5) */
9201 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX),
9202 /* PowerPC 970MP */
9203 POWERPC_DEF("970mp", CPU_POWERPC_970MP, 970MP),
9204 /* PowerPC 970MP v1.0 */
9205 POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP),
9206 /* PowerPC 970MP v1.1 */
9207 POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP),
9208 #if defined (TODO)
9209 /* PowerPC Cell */
9210 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970),
9211 #endif
9212 #if defined (TODO)
9213 /* PowerPC Cell v1.0 */
9214 POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970),
9215 #endif
9216 #if defined (TODO)
9217 /* PowerPC Cell v2.0 */
9218 POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970),
9219 #endif
9220 #if defined (TODO)
9221 /* PowerPC Cell v3.0 */
9222 POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970),
9223 #endif
9224 #if defined (TODO)
9225 /* PowerPC Cell v3.1 */
9226 POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970),
9227 #endif
9228 #if defined (TODO)
9229 /* PowerPC Cell v3.2 */
9230 POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970),
9231 #endif
9232 #if defined (TODO)
9233 /* RS64 (Apache/A35) */
9234 /* This one seems to support the whole POWER2 instruction set
9235 * and the PowerPC 64 one.
9236 */
9237 /* What about A10 & A30 ? */
9238 POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64),
9239 POWERPC_DEF("Apache", CPU_POWERPC_RS64, RS64),
9240 POWERPC_DEF("A35", CPU_POWERPC_RS64, RS64),
9241 #endif
9242 #if defined (TODO)
9243 /* RS64-II (NorthStar/A50) */
9244 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64),
9245 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, RS64),
9246 POWERPC_DEF("A50", CPU_POWERPC_RS64II, RS64),
9247 #endif
9248 #if defined (TODO)
9249 /* RS64-III (Pulsar) */
9250 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64),
9251 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, RS64),
9252 #endif
9253 #if defined (TODO)
9254 /* RS64-IV (IceStar/IStar/SStar) */
9255 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64),
9256 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, RS64),
9257 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, RS64),
9258 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, RS64),
9259 #endif
9260 #endif /* defined (TARGET_PPC64) */
9261 /* POWER */
9262 #if defined (TODO)
9263 /* Original POWER */
9264 POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER),
9265 POWERPC_DEF("RIOS", CPU_POWERPC_POWER, POWER),
9266 POWERPC_DEF("RSC", CPU_POWERPC_POWER, POWER),
9267 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, POWER),
9268 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, POWER),
9269 #endif
9270 #if defined (TODO)
9271 /* POWER2 */
9272 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER),
9273 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, POWER),
9274 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, POWER),
9275 #endif
9276 /* PA semi cores */
9277 #if defined (TODO)
9278 /* PA PA6T */
9279 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T),
9280 #endif
9281 /* Generic PowerPCs */
9282 #if defined (TARGET_PPC64)
9283 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, PPC64),
9284 #endif
9285 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32),
9286 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, DEFAULT),
9287 /* Fallback */
9288 POWERPC_DEF("default", CPU_POWERPC_DEFAULT, DEFAULT),
9289 };
9290
9291 /*****************************************************************************/
9292 /* Generic CPU instantiation routine */
9293 static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
9294 {
9295 #if !defined(CONFIG_USER_ONLY)
9296 int i;
9297
9298 env->irq_inputs = NULL;
9299 /* Set all exception vectors to an invalid address */
9300 for (i = 0; i < POWERPC_EXCP_NB; i++)
9301 env->excp_vectors[i] = (target_ulong)(-1ULL);
9302 env->hreset_excp_prefix = 0x00000000;
9303 env->ivor_mask = 0x00000000;
9304 env->ivpr_mask = 0x00000000;
9305 /* Default MMU definitions */
9306 env->nb_BATs = 0;
9307 env->nb_tlb = 0;
9308 env->nb_ways = 0;
9309 env->tlb_type = TLB_NONE;
9310 #endif
9311 /* Register SPR common to all PowerPC implementations */
9312 gen_spr_generic(env);
9313 spr_register(env, SPR_PVR, "PVR",
9314 /* Linux permits userspace to read PVR */
9315 #if defined(CONFIG_LINUX_USER)
9316 &spr_read_generic,
9317 #else
9318 SPR_NOACCESS,
9319 #endif
9320 SPR_NOACCESS,
9321 &spr_read_generic, SPR_NOACCESS,
9322 def->pvr);
9323 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
9324 if (def->svr != POWERPC_SVR_NONE) {
9325 if (def->svr & POWERPC_SVR_E500) {
9326 spr_register(env, SPR_E500_SVR, "SVR",
9327 SPR_NOACCESS, SPR_NOACCESS,
9328 &spr_read_generic, SPR_NOACCESS,
9329 def->svr & ~POWERPC_SVR_E500);
9330 } else {
9331 spr_register(env, SPR_SVR, "SVR",
9332 SPR_NOACCESS, SPR_NOACCESS,
9333 &spr_read_generic, SPR_NOACCESS,
9334 def->svr);
9335 }
9336 }
9337 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
9338 (*def->init_proc)(env);
9339 #if !defined(CONFIG_USER_ONLY)
9340 env->excp_prefix = env->hreset_excp_prefix;
9341 #endif
9342 /* MSR bits & flags consistency checks */
9343 if (env->msr_mask & (1 << 25)) {
9344 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9345 case POWERPC_FLAG_SPE:
9346 case POWERPC_FLAG_VRE:
9347 break;
9348 default:
9349 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9350 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
9351 exit(1);
9352 }
9353 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9354 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9355 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
9356 exit(1);
9357 }
9358 if (env->msr_mask & (1 << 17)) {
9359 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9360 case POWERPC_FLAG_TGPR:
9361 case POWERPC_FLAG_CE:
9362 break;
9363 default:
9364 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9365 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
9366 exit(1);
9367 }
9368 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9369 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9370 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
9371 exit(1);
9372 }
9373 if (env->msr_mask & (1 << 10)) {
9374 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9375 POWERPC_FLAG_UBLE)) {
9376 case POWERPC_FLAG_SE:
9377 case POWERPC_FLAG_DWE:
9378 case POWERPC_FLAG_UBLE:
9379 break;
9380 default:
9381 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9382 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
9383 "POWERPC_FLAG_UBLE\n");
9384 exit(1);
9385 }
9386 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9387 POWERPC_FLAG_UBLE)) {
9388 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9389 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
9390 "POWERPC_FLAG_UBLE\n");
9391 exit(1);
9392 }
9393 if (env->msr_mask & (1 << 9)) {
9394 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9395 case POWERPC_FLAG_BE:
9396 case POWERPC_FLAG_DE:
9397 break;
9398 default:
9399 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9400 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
9401 exit(1);
9402 }
9403 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9404 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9405 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
9406 exit(1);
9407 }
9408 if (env->msr_mask & (1 << 2)) {
9409 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9410 case POWERPC_FLAG_PX:
9411 case POWERPC_FLAG_PMM:
9412 break;
9413 default:
9414 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9415 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
9416 exit(1);
9417 }
9418 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9419 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9420 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
9421 exit(1);
9422 }
9423 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
9424 fprintf(stderr, "PowerPC flags inconsistency\n"
9425 "Should define the time-base and decrementer clock source\n");
9426 exit(1);
9427 }
9428 /* Allocate TLBs buffer when needed */
9429 #if !defined(CONFIG_USER_ONLY)
9430 if (env->nb_tlb != 0) {
9431 int nb_tlb = env->nb_tlb;
9432 if (env->id_tlbs != 0)
9433 nb_tlb *= 2;
9434 switch (env->tlb_type) {
9435 case TLB_6XX:
9436 env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
9437 break;
9438 case TLB_EMB:
9439 env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
9440 break;
9441 case TLB_MAS:
9442 env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
9443 break;
9444 }
9445 /* Pre-compute some useful values */
9446 env->tlb_per_way = env->nb_tlb / env->nb_ways;
9447 }
9448 if (env->irq_inputs == NULL) {
9449 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
9450 " Attempt QEMU to crash very soon !\n");
9451 }
9452 #endif
9453 if (env->check_pow == NULL) {
9454 fprintf(stderr, "WARNING: no power management check handler "
9455 "registered.\n"
9456 " Attempt QEMU to crash very soon !\n");
9457 }
9458 }
9459
9460 #if defined(PPC_DUMP_CPU)
9461 static void dump_ppc_sprs (CPUPPCState *env)
9462 {
9463 ppc_spr_t *spr;
9464 #if !defined(CONFIG_USER_ONLY)
9465 uint32_t sr, sw;
9466 #endif
9467 uint32_t ur, uw;
9468 int i, j, n;
9469
9470 printf("Special purpose registers:\n");
9471 for (i = 0; i < 32; i++) {
9472 for (j = 0; j < 32; j++) {
9473 n = (i << 5) | j;
9474 spr = &env->spr_cb[n];
9475 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
9476 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
9477 #if !defined(CONFIG_USER_ONLY)
9478 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
9479 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
9480 if (sw || sr || uw || ur) {
9481 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
9482 (i << 5) | j, (i << 5) | j, spr->name,
9483 sw ? 'w' : '-', sr ? 'r' : '-',
9484 uw ? 'w' : '-', ur ? 'r' : '-');
9485 }
9486 #else
9487 if (uw || ur) {
9488 printf("SPR: %4d (%03x) %-8s u%c%c\n",
9489 (i << 5) | j, (i << 5) | j, spr->name,
9490 uw ? 'w' : '-', ur ? 'r' : '-');
9491 }
9492 #endif
9493 }
9494 }
9495 fflush(stdout);
9496 fflush(stderr);
9497 }
9498 #endif
9499
9500 /*****************************************************************************/
9501 #include <stdlib.h>
9502 #include <string.h>
9503
9504 /* Opcode types */
9505 enum {
9506 PPC_DIRECT = 0, /* Opcode routine */
9507 PPC_INDIRECT = 1, /* Indirect opcode table */
9508 };
9509
9510 static inline int is_indirect_opcode (void *handler)
9511 {
9512 return ((uintptr_t)handler & 0x03) == PPC_INDIRECT;
9513 }
9514
9515 static inline opc_handler_t **ind_table(void *handler)
9516 {
9517 return (opc_handler_t **)((uintptr_t)handler & ~3);
9518 }
9519
9520 /* Instruction table creation */
9521 /* Opcodes tables creation */
9522 static void fill_new_table (opc_handler_t **table, int len)
9523 {
9524 int i;
9525
9526 for (i = 0; i < len; i++)
9527 table[i] = &invalid_handler;
9528 }
9529
9530 static int create_new_table (opc_handler_t **table, unsigned char idx)
9531 {
9532 opc_handler_t **tmp;
9533
9534 tmp = malloc(0x20 * sizeof(opc_handler_t));
9535 fill_new_table(tmp, 0x20);
9536 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
9537
9538 return 0;
9539 }
9540
9541 static int insert_in_table (opc_handler_t **table, unsigned char idx,
9542 opc_handler_t *handler)
9543 {
9544 if (table[idx] != &invalid_handler)
9545 return -1;
9546 table[idx] = handler;
9547
9548 return 0;
9549 }
9550
9551 static int register_direct_insn (opc_handler_t **ppc_opcodes,
9552 unsigned char idx, opc_handler_t *handler)
9553 {
9554 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9555 printf("*** ERROR: opcode %02x already assigned in main "
9556 "opcode table\n", idx);
9557 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9558 printf(" Registered handler '%s' - new handler '%s'\n",
9559 ppc_opcodes[idx]->oname, handler->oname);
9560 #endif
9561 return -1;
9562 }
9563
9564 return 0;
9565 }
9566
9567 static int register_ind_in_table (opc_handler_t **table,
9568 unsigned char idx1, unsigned char idx2,
9569 opc_handler_t *handler)
9570 {
9571 if (table[idx1] == &invalid_handler) {
9572 if (create_new_table(table, idx1) < 0) {
9573 printf("*** ERROR: unable to create indirect table "
9574 "idx=%02x\n", idx1);
9575 return -1;
9576 }
9577 } else {
9578 if (!is_indirect_opcode(table[idx1])) {
9579 printf("*** ERROR: idx %02x already assigned to a direct "
9580 "opcode\n", idx1);
9581 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9582 printf(" Registered handler '%s' - new handler '%s'\n",
9583 ind_table(table[idx1])[idx2]->oname, handler->oname);
9584 #endif
9585 return -1;
9586 }
9587 }
9588 if (handler != NULL &&
9589 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9590 printf("*** ERROR: opcode %02x already assigned in "
9591 "opcode table %02x\n", idx2, idx1);
9592 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9593 printf(" Registered handler '%s' - new handler '%s'\n",
9594 ind_table(table[idx1])[idx2]->oname, handler->oname);
9595 #endif
9596 return -1;
9597 }
9598
9599 return 0;
9600 }
9601
9602 static int register_ind_insn (opc_handler_t **ppc_opcodes,
9603 unsigned char idx1, unsigned char idx2,
9604 opc_handler_t *handler)
9605 {
9606 int ret;
9607
9608 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
9609
9610 return ret;
9611 }
9612
9613 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
9614 unsigned char idx1, unsigned char idx2,
9615 unsigned char idx3, opc_handler_t *handler)
9616 {
9617 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9618 printf("*** ERROR: unable to join indirect table idx "
9619 "[%02x-%02x]\n", idx1, idx2);
9620 return -1;
9621 }
9622 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
9623 handler) < 0) {
9624 printf("*** ERROR: unable to insert opcode "
9625 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9626 return -1;
9627 }
9628
9629 return 0;
9630 }
9631
9632 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
9633 {
9634 if (insn->opc2 != 0xFF) {
9635 if (insn->opc3 != 0xFF) {
9636 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9637 insn->opc3, &insn->handler) < 0)
9638 return -1;
9639 } else {
9640 if (register_ind_insn(ppc_opcodes, insn->opc1,
9641 insn->opc2, &insn->handler) < 0)
9642 return -1;
9643 }
9644 } else {
9645 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
9646 return -1;
9647 }
9648
9649 return 0;
9650 }
9651
9652 static int test_opcode_table (opc_handler_t **table, int len)
9653 {
9654 int i, count, tmp;
9655
9656 for (i = 0, count = 0; i < len; i++) {
9657 /* Consistency fixup */
9658 if (table[i] == NULL)
9659 table[i] = &invalid_handler;
9660 if (table[i] != &invalid_handler) {
9661 if (is_indirect_opcode(table[i])) {
9662 tmp = test_opcode_table(ind_table(table[i]), 0x20);
9663 if (tmp == 0) {
9664 free(table[i]);
9665 table[i] = &invalid_handler;
9666 } else {
9667 count++;
9668 }
9669 } else {
9670 count++;
9671 }
9672 }
9673 }
9674
9675 return count;
9676 }
9677
9678 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
9679 {
9680 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
9681 printf("*** WARNING: no opcode defined !\n");
9682 }
9683
9684 /*****************************************************************************/
9685 static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def)
9686 {
9687 opcode_t *opc;
9688
9689 fill_new_table(env->opcodes, 0x40);
9690 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
9691 if (((opc->handler.type & def->insns_flags) != 0) ||
9692 ((opc->handler.type2 & def->insns_flags2) != 0)) {
9693 if (register_insn(env->opcodes, opc) < 0) {
9694 printf("*** ERROR initializing PowerPC instruction "
9695 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
9696 opc->opc3);
9697 return -1;
9698 }
9699 }
9700 }
9701 fix_opcode_tables(env->opcodes);
9702 fflush(stdout);
9703 fflush(stderr);
9704
9705 return 0;
9706 }
9707
9708 #if defined(PPC_DUMP_CPU)
9709 static void dump_ppc_insns (CPUPPCState *env)
9710 {
9711 opc_handler_t **table, *handler;
9712 const char *p, *q;
9713 uint8_t opc1, opc2, opc3;
9714
9715 printf("Instructions set:\n");
9716 /* opc1 is 6 bits long */
9717 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
9718 table = env->opcodes;
9719 handler = table[opc1];
9720 if (is_indirect_opcode(handler)) {
9721 /* opc2 is 5 bits long */
9722 for (opc2 = 0; opc2 < 0x20; opc2++) {
9723 table = env->opcodes;
9724 handler = env->opcodes[opc1];
9725 table = ind_table(handler);
9726 handler = table[opc2];
9727 if (is_indirect_opcode(handler)) {
9728 table = ind_table(handler);
9729 /* opc3 is 5 bits long */
9730 for (opc3 = 0; opc3 < 0x20; opc3++) {
9731 handler = table[opc3];
9732 if (handler->handler != &gen_invalid) {
9733 /* Special hack to properly dump SPE insns */
9734 p = strchr(handler->oname, '_');
9735 if (p == NULL) {
9736 printf("INSN: %02x %02x %02x (%02d %04d) : "
9737 "%s\n",
9738 opc1, opc2, opc3, opc1,
9739 (opc3 << 5) | opc2,
9740 handler->oname);
9741 } else {
9742 q = "speundef";
9743 if ((p - handler->oname) != strlen(q) ||
9744 memcmp(handler->oname, q, strlen(q)) != 0) {
9745 /* First instruction */
9746 printf("INSN: %02x %02x %02x (%02d %04d) : "
9747 "%.*s\n",
9748 opc1, opc2 << 1, opc3, opc1,
9749 (opc3 << 6) | (opc2 << 1),
9750 (int)(p - handler->oname),
9751 handler->oname);
9752 }
9753 if (strcmp(p + 1, q) != 0) {
9754 /* Second instruction */
9755 printf("INSN: %02x %02x %02x (%02d %04d) : "
9756 "%s\n",
9757 opc1, (opc2 << 1) | 1, opc3, opc1,
9758 (opc3 << 6) | (opc2 << 1) | 1,
9759 p + 1);
9760 }
9761 }
9762 }
9763 }
9764 } else {
9765 if (handler->handler != &gen_invalid) {
9766 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9767 opc1, opc2, opc1, opc2, handler->oname);
9768 }
9769 }
9770 }
9771 } else {
9772 if (handler->handler != &gen_invalid) {
9773 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9774 opc1, opc1, handler->oname);
9775 }
9776 }
9777 }
9778 }
9779 #endif
9780
9781 static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9782 {
9783 if (n < 32) {
9784 stfq_p(mem_buf, env->fpr[n]);
9785 return 8;
9786 }
9787 if (n == 32) {
9788 stl_p(mem_buf, env->fpscr);
9789 return 4;
9790 }
9791 return 0;
9792 }
9793
9794 static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9795 {
9796 if (n < 32) {
9797 env->fpr[n] = ldfq_p(mem_buf);
9798 return 8;
9799 }
9800 if (n == 32) {
9801 /* FPSCR not implemented */
9802 return 4;
9803 }
9804 return 0;
9805 }
9806
9807 static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9808 {
9809 if (n < 32) {
9810 #ifdef HOST_WORDS_BIGENDIAN
9811 stq_p(mem_buf, env->avr[n].u64[0]);
9812 stq_p(mem_buf+8, env->avr[n].u64[1]);
9813 #else
9814 stq_p(mem_buf, env->avr[n].u64[1]);
9815 stq_p(mem_buf+8, env->avr[n].u64[0]);
9816 #endif
9817 return 16;
9818 }
9819 if (n == 32) {
9820 stl_p(mem_buf, env->vscr);
9821 return 4;
9822 }
9823 if (n == 33) {
9824 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9825 return 4;
9826 }
9827 return 0;
9828 }
9829
9830 static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9831 {
9832 if (n < 32) {
9833 #ifdef HOST_WORDS_BIGENDIAN
9834 env->avr[n].u64[0] = ldq_p(mem_buf);
9835 env->avr[n].u64[1] = ldq_p(mem_buf+8);
9836 #else
9837 env->avr[n].u64[1] = ldq_p(mem_buf);
9838 env->avr[n].u64[0] = ldq_p(mem_buf+8);
9839 #endif
9840 return 16;
9841 }
9842 if (n == 32) {
9843 env->vscr = ldl_p(mem_buf);
9844 return 4;
9845 }
9846 if (n == 33) {
9847 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9848 return 4;
9849 }
9850 return 0;
9851 }
9852
9853 static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9854 {
9855 if (n < 32) {
9856 #if defined(TARGET_PPC64)
9857 stl_p(mem_buf, env->gpr[n] >> 32);
9858 #else
9859 stl_p(mem_buf, env->gprh[n]);
9860 #endif
9861 return 4;
9862 }
9863 if (n == 32) {
9864 stq_p(mem_buf, env->spe_acc);
9865 return 8;
9866 }
9867 if (n == 33) {
9868 stl_p(mem_buf, env->spe_fscr);
9869 return 4;
9870 }
9871 return 0;
9872 }
9873
9874 static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9875 {
9876 if (n < 32) {
9877 #if defined(TARGET_PPC64)
9878 target_ulong lo = (uint32_t)env->gpr[n];
9879 target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
9880 env->gpr[n] = lo | hi;
9881 #else
9882 env->gprh[n] = ldl_p(mem_buf);
9883 #endif
9884 return 4;
9885 }
9886 if (n == 32) {
9887 env->spe_acc = ldq_p(mem_buf);
9888 return 8;
9889 }
9890 if (n == 33) {
9891 env->spe_fscr = ldl_p(mem_buf);
9892 return 4;
9893 }
9894 return 0;
9895 }
9896
9897 static int ppc_fixup_cpu(CPUPPCState *env)
9898 {
9899 /* TCG doesn't (yet) emulate some groups of instructions that
9900 * are implemented on some otherwise supported CPUs (e.g. VSX
9901 * and decimal floating point instructions on POWER7). We
9902 * remove unsupported instruction groups from the cpu state's
9903 * instruction masks and hope the guest can cope. For at
9904 * least the pseries machine, the unavailability of these
9905 * instructions can be advertised to the guest via the device
9906 * tree. */
9907 if ((env->insns_flags & ~PPC_TCG_INSNS)
9908 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
9909 fprintf(stderr, "Warning: Disabling some instructions which are not "
9910 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")\n",
9911 env->insns_flags & ~PPC_TCG_INSNS,
9912 env->insns_flags2 & ~PPC_TCG_INSNS2);
9913 }
9914 env->insns_flags &= PPC_TCG_INSNS;
9915 env->insns_flags2 &= PPC_TCG_INSNS2;
9916 return 0;
9917 }
9918
9919 int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
9920 {
9921 env->msr_mask = def->msr_mask;
9922 env->mmu_model = def->mmu_model;
9923 env->excp_model = def->excp_model;
9924 env->bus_model = def->bus_model;
9925 env->insns_flags = def->insns_flags;
9926 env->insns_flags2 = def->insns_flags2;
9927 env->flags = def->flags;
9928 env->bfd_mach = def->bfd_mach;
9929 env->check_pow = def->check_pow;
9930
9931 if (kvm_enabled()) {
9932 if (kvmppc_fixup_cpu(env) != 0) {
9933 fprintf(stderr, "Unable to virtualize selected CPU with KVM\n");
9934 exit(1);
9935 }
9936 } else {
9937 if (ppc_fixup_cpu(env) != 0) {
9938 fprintf(stderr, "Unable to emulate selected CPU with TCG\n");
9939 exit(1);
9940 }
9941 }
9942
9943 if (create_ppc_opcodes(env, def) < 0)
9944 return -1;
9945 init_ppc_proc(env, def);
9946
9947 if (def->insns_flags & PPC_FLOAT) {
9948 gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
9949 33, "power-fpu.xml", 0);
9950 }
9951 if (def->insns_flags & PPC_ALTIVEC) {
9952 gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
9953 34, "power-altivec.xml", 0);
9954 }
9955 if (def->insns_flags & PPC_SPE) {
9956 gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
9957 34, "power-spe.xml", 0);
9958 }
9959
9960 #if defined(PPC_DUMP_CPU)
9961 {
9962 const char *mmu_model, *excp_model, *bus_model;
9963 switch (env->mmu_model) {
9964 case POWERPC_MMU_32B:
9965 mmu_model = "PowerPC 32";
9966 break;
9967 case POWERPC_MMU_SOFT_6xx:
9968 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
9969 break;
9970 case POWERPC_MMU_SOFT_74xx:
9971 mmu_model = "PowerPC 74xx with software driven TLBs";
9972 break;
9973 case POWERPC_MMU_SOFT_4xx:
9974 mmu_model = "PowerPC 4xx with software driven TLBs";
9975 break;
9976 case POWERPC_MMU_SOFT_4xx_Z:
9977 mmu_model = "PowerPC 4xx with software driven TLBs "
9978 "and zones protections";
9979 break;
9980 case POWERPC_MMU_REAL:
9981 mmu_model = "PowerPC real mode only";
9982 break;
9983 case POWERPC_MMU_MPC8xx:
9984 mmu_model = "PowerPC MPC8xx";
9985 break;
9986 case POWERPC_MMU_BOOKE:
9987 mmu_model = "PowerPC BookE";
9988 break;
9989 case POWERPC_MMU_BOOKE206:
9990 mmu_model = "PowerPC BookE 2.06";
9991 break;
9992 case POWERPC_MMU_601:
9993 mmu_model = "PowerPC 601";
9994 break;
9995 #if defined (TARGET_PPC64)
9996 case POWERPC_MMU_64B:
9997 mmu_model = "PowerPC 64";
9998 break;
9999 case POWERPC_MMU_620:
10000 mmu_model = "PowerPC 620";
10001 break;
10002 #endif
10003 default:
10004 mmu_model = "Unknown or invalid";
10005 break;
10006 }
10007 switch (env->excp_model) {
10008 case POWERPC_EXCP_STD:
10009 excp_model = "PowerPC";
10010 break;
10011 case POWERPC_EXCP_40x:
10012 excp_model = "PowerPC 40x";
10013 break;
10014 case POWERPC_EXCP_601:
10015 excp_model = "PowerPC 601";
10016 break;
10017 case POWERPC_EXCP_602:
10018 excp_model = "PowerPC 602";
10019 break;
10020 case POWERPC_EXCP_603:
10021 excp_model = "PowerPC 603";
10022 break;
10023 case POWERPC_EXCP_603E:
10024 excp_model = "PowerPC 603e";
10025 break;
10026 case POWERPC_EXCP_604:
10027 excp_model = "PowerPC 604";
10028 break;
10029 case POWERPC_EXCP_7x0:
10030 excp_model = "PowerPC 740/750";
10031 break;
10032 case POWERPC_EXCP_7x5:
10033 excp_model = "PowerPC 745/755";
10034 break;
10035 case POWERPC_EXCP_74xx:
10036 excp_model = "PowerPC 74xx";
10037 break;
10038 case POWERPC_EXCP_BOOKE:
10039 excp_model = "PowerPC BookE";
10040 break;
10041 #if defined (TARGET_PPC64)
10042 case POWERPC_EXCP_970:
10043 excp_model = "PowerPC 970";
10044 break;
10045 #endif
10046 default:
10047 excp_model = "Unknown or invalid";
10048 break;
10049 }
10050 switch (env->bus_model) {
10051 case PPC_FLAGS_INPUT_6xx:
10052 bus_model = "PowerPC 6xx";
10053 break;
10054 case PPC_FLAGS_INPUT_BookE:
10055 bus_model = "PowerPC BookE";
10056 break;
10057 case PPC_FLAGS_INPUT_405:
10058 bus_model = "PowerPC 405";
10059 break;
10060 case PPC_FLAGS_INPUT_401:
10061 bus_model = "PowerPC 401/403";
10062 break;
10063 case PPC_FLAGS_INPUT_RCPU:
10064 bus_model = "RCPU / MPC8xx";
10065 break;
10066 #if defined (TARGET_PPC64)
10067 case PPC_FLAGS_INPUT_970:
10068 bus_model = "PowerPC 970";
10069 break;
10070 #endif
10071 default:
10072 bus_model = "Unknown or invalid";
10073 break;
10074 }
10075 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
10076 " MMU model : %s\n",
10077 def->name, def->pvr, def->msr_mask, mmu_model);
10078 #if !defined(CONFIG_USER_ONLY)
10079 if (env->tlb != NULL) {
10080 printf(" %d %s TLB in %d ways\n",
10081 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
10082 env->nb_ways);
10083 }
10084 #endif
10085 printf(" Exceptions model : %s\n"
10086 " Bus model : %s\n",
10087 excp_model, bus_model);
10088 printf(" MSR features :\n");
10089 if (env->flags & POWERPC_FLAG_SPE)
10090 printf(" signal processing engine enable"
10091 "\n");
10092 else if (env->flags & POWERPC_FLAG_VRE)
10093 printf(" vector processor enable\n");
10094 if (env->flags & POWERPC_FLAG_TGPR)
10095 printf(" temporary GPRs\n");
10096 else if (env->flags & POWERPC_FLAG_CE)
10097 printf(" critical input enable\n");
10098 if (env->flags & POWERPC_FLAG_SE)
10099 printf(" single-step trace mode\n");
10100 else if (env->flags & POWERPC_FLAG_DWE)
10101 printf(" debug wait enable\n");
10102 else if (env->flags & POWERPC_FLAG_UBLE)
10103 printf(" user BTB lock enable\n");
10104 if (env->flags & POWERPC_FLAG_BE)
10105 printf(" branch-step trace mode\n");
10106 else if (env->flags & POWERPC_FLAG_DE)
10107 printf(" debug interrupt enable\n");
10108 if (env->flags & POWERPC_FLAG_PX)
10109 printf(" inclusive protection\n");
10110 else if (env->flags & POWERPC_FLAG_PMM)
10111 printf(" performance monitor mark\n");
10112 if (env->flags == POWERPC_FLAG_NONE)
10113 printf(" none\n");
10114 printf(" Time-base/decrementer clock source: %s\n",
10115 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
10116 }
10117 dump_ppc_insns(env);
10118 dump_ppc_sprs(env);
10119 fflush(stdout);
10120 #endif
10121
10122 return 0;
10123 }
10124
10125 static bool ppc_cpu_usable(const ppc_def_t *def)
10126 {
10127 #if defined(TARGET_PPCEMB)
10128 /* When using the ppcemb target, we only support 440 style cores */
10129 if (def->mmu_model != POWERPC_MMU_BOOKE) {
10130 return false;
10131 }
10132 #endif
10133
10134 return true;
10135 }
10136
10137 const ppc_def_t *ppc_find_by_pvr(uint32_t pvr)
10138 {
10139 int i;
10140
10141 for (i = 0; i < ARRAY_SIZE(ppc_defs); i++) {
10142 if (!ppc_cpu_usable(&ppc_defs[i])) {
10143 continue;
10144 }
10145
10146 /* If we have an exact match, we're done */
10147 if (pvr == ppc_defs[i].pvr) {
10148 return &ppc_defs[i];
10149 }
10150 }
10151
10152 return NULL;
10153 }
10154
10155 #include <ctype.h>
10156
10157 const ppc_def_t *cpu_ppc_find_by_name (const char *name)
10158 {
10159 const ppc_def_t *ret;
10160 const char *p;
10161 int i, max, len;
10162
10163 if (kvm_enabled() && (strcasecmp(name, "host") == 0)) {
10164 return kvmppc_host_cpu_def();
10165 }
10166
10167 /* Check if the given name is a PVR */
10168 len = strlen(name);
10169 if (len == 10 && name[0] == '0' && name[1] == 'x') {
10170 p = name + 2;
10171 goto check_pvr;
10172 } else if (len == 8) {
10173 p = name;
10174 check_pvr:
10175 for (i = 0; i < 8; i++) {
10176 if (!qemu_isxdigit(*p++))
10177 break;
10178 }
10179 if (i == 8)
10180 return ppc_find_by_pvr(strtoul(name, NULL, 16));
10181 }
10182 ret = NULL;
10183 max = ARRAY_SIZE(ppc_defs);
10184 for (i = 0; i < max; i++) {
10185 if (!ppc_cpu_usable(&ppc_defs[i])) {
10186 continue;
10187 }
10188
10189 if (strcasecmp(name, ppc_defs[i].name) == 0) {
10190 ret = &ppc_defs[i];
10191 break;
10192 }
10193 }
10194
10195 return ret;
10196 }
10197
10198 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf)
10199 {
10200 int i, max;
10201
10202 max = ARRAY_SIZE(ppc_defs);
10203 for (i = 0; i < max; i++) {
10204 if (!ppc_cpu_usable(&ppc_defs[i])) {
10205 continue;
10206 }
10207
10208 (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
10209 ppc_defs[i].name, ppc_defs[i].pvr);
10210 }
10211 }
10212
10213 /* CPUClass::reset() */
10214 static void ppc_cpu_reset(CPUState *s)
10215 {
10216 PowerPCCPU *cpu = POWERPC_CPU(s);
10217 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
10218 CPUPPCState *env = &cpu->env;
10219 target_ulong msr;
10220
10221 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
10222 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
10223 log_cpu_state(env, 0);
10224 }
10225
10226 pcc->parent_reset(s);
10227
10228 msr = (target_ulong)0;
10229 if (0) {
10230 /* XXX: find a suitable condition to enable the hypervisor mode */
10231 msr |= (target_ulong)MSR_HVB;
10232 }
10233 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
10234 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
10235 msr |= (target_ulong)1 << MSR_EP;
10236 #if defined(DO_SINGLE_STEP) && 0
10237 /* Single step trace mode */
10238 msr |= (target_ulong)1 << MSR_SE;
10239 msr |= (target_ulong)1 << MSR_BE;
10240 #endif
10241 #if defined(CONFIG_USER_ONLY)
10242 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
10243 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
10244 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
10245 msr |= (target_ulong)1 << MSR_PR;
10246 #else
10247 env->excp_prefix = env->hreset_excp_prefix;
10248 env->nip = env->hreset_vector | env->excp_prefix;
10249 if (env->mmu_model != POWERPC_MMU_REAL) {
10250 ppc_tlb_invalidate_all(env);
10251 }
10252 #endif
10253 env->msr = msr & env->msr_mask;
10254 #if defined(TARGET_PPC64)
10255 if (env->mmu_model & POWERPC_MMU_64) {
10256 env->msr |= (1ULL << MSR_SF);
10257 }
10258 #endif
10259 hreg_compute_hflags(env);
10260 env->reserve_addr = (target_ulong)-1ULL;
10261 /* Be sure no exception or interrupt is pending */
10262 env->pending_interrupts = 0;
10263 env->exception_index = POWERPC_EXCP_NONE;
10264 env->error_code = 0;
10265 /* Flush all TLBs */
10266 tlb_flush(env, 1);
10267 }
10268
10269 static void ppc_cpu_initfn(Object *obj)
10270 {
10271 PowerPCCPU *cpu = POWERPC_CPU(obj);
10272 CPUPPCState *env = &cpu->env;
10273
10274 cpu_exec_init(env);
10275 }
10276
10277 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
10278 {
10279 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10280 CPUClass *cc = CPU_CLASS(oc);
10281
10282 pcc->parent_reset = cc->reset;
10283 cc->reset = ppc_cpu_reset;
10284 }
10285
10286 static const TypeInfo ppc_cpu_type_info = {
10287 .name = TYPE_POWERPC_CPU,
10288 .parent = TYPE_CPU,
10289 .instance_size = sizeof(PowerPCCPU),
10290 .instance_init = ppc_cpu_initfn,
10291 .abstract = false,
10292 .class_size = sizeof(PowerPCCPUClass),
10293 .class_init = ppc_cpu_class_init,
10294 };
10295
10296 static void ppc_cpu_register_types(void)
10297 {
10298 type_register_static(&ppc_cpu_type_info);
10299 }
10300
10301 type_init(ppc_cpu_register_types)
Qemu copy for testing