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Merge remote-tracking branch 'sweil/tci' into staging
[qemu.git] / target-s390x / cpu.h
1 /*
2 * S/390 virtual CPU header
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * Contributions after 2012-10-29 are licensed under the terms of the
17 * GNU GPL, version 2 or (at your option) any later version.
18 *
19 * You should have received a copy of the GNU (Lesser) General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 */
22 #ifndef CPU_S390X_H
23 #define CPU_S390X_H
24
25 #include "config.h"
26 #include "qemu-common.h"
27
28 #define TARGET_LONG_BITS 64
29
30 #define ELF_MACHINE EM_S390
31
32 #define CPUArchState struct CPUS390XState
33
34 #include "exec/cpu-defs.h"
35 #define TARGET_PAGE_BITS 12
36
37 #define TARGET_PHYS_ADDR_SPACE_BITS 64
38 #define TARGET_VIRT_ADDR_SPACE_BITS 64
39
40 #include "exec/cpu-all.h"
41
42 #include "fpu/softfloat.h"
43
44 #define NB_MMU_MODES 3
45
46 #define MMU_MODE0_SUFFIX _primary
47 #define MMU_MODE1_SUFFIX _secondary
48 #define MMU_MODE2_SUFFIX _home
49
50 #define MMU_USER_IDX 1
51
52 #define MAX_EXT_QUEUE 16
53 #define MAX_IO_QUEUE 16
54 #define MAX_MCHK_QUEUE 16
55
56 #define PSW_MCHK_MASK 0x0004000000000000
57 #define PSW_IO_MASK 0x0200000000000000
58
59 typedef struct PSW {
60 uint64_t mask;
61 uint64_t addr;
62 } PSW;
63
64 typedef struct ExtQueue {
65 uint32_t code;
66 uint32_t param;
67 uint32_t param64;
68 } ExtQueue;
69
70 typedef struct IOIntQueue {
71 uint16_t id;
72 uint16_t nr;
73 uint32_t parm;
74 uint32_t word;
75 } IOIntQueue;
76
77 typedef struct MchkQueue {
78 uint16_t type;
79 } MchkQueue;
80
81 /* Defined values for CPUS390XState.runtime_reg_dirty_mask */
82 #define KVM_S390_RUNTIME_DIRTY_NONE 0
83 #define KVM_S390_RUNTIME_DIRTY_PARTIAL 1
84 #define KVM_S390_RUNTIME_DIRTY_FULL 2
85
86 typedef struct CPUS390XState {
87 uint64_t regs[16]; /* GP registers */
88 CPU_DoubleU fregs[16]; /* FP registers */
89 uint32_t aregs[16]; /* access registers */
90
91 uint32_t fpc; /* floating-point control register */
92 uint32_t cc_op;
93
94 float_status fpu_status; /* passed to softfloat lib */
95
96 /* The low part of a 128-bit return, or remainder of a divide. */
97 uint64_t retxl;
98
99 PSW psw;
100
101 uint64_t cc_src;
102 uint64_t cc_dst;
103 uint64_t cc_vr;
104
105 uint64_t __excp_addr;
106 uint64_t psa;
107
108 uint32_t int_pgm_code;
109 uint32_t int_pgm_ilen;
110
111 uint32_t int_svc_code;
112 uint32_t int_svc_ilen;
113
114 uint64_t cregs[16]; /* control registers */
115
116 ExtQueue ext_queue[MAX_EXT_QUEUE];
117 IOIntQueue io_queue[MAX_IO_QUEUE][8];
118 MchkQueue mchk_queue[MAX_MCHK_QUEUE];
119
120 int pending_int;
121 int ext_index;
122 int io_index[8];
123 int mchk_index;
124
125 uint64_t ckc;
126 uint64_t cputm;
127 uint32_t todpr;
128
129 /* on S390 the runtime register set has two dirty states:
130 * a partial dirty state in which only the registers that
131 * are needed all the time are fetched. And a fully dirty
132 * state in which all runtime registers are fetched.
133 */
134 uint32_t runtime_reg_dirty_mask;
135
136 CPU_COMMON
137
138 /* reset does memset(0) up to here */
139
140 int cpu_num;
141 uint8_t *storage_keys;
142
143 uint64_t tod_offset;
144 uint64_t tod_basetime;
145 QEMUTimer *tod_timer;
146
147 QEMUTimer *cpu_timer;
148 } CPUS390XState;
149
150 #include "cpu-qom.h"
151 #include <sysemu/kvm.h>
152
153 /* distinguish between 24 bit and 31 bit addressing */
154 #define HIGH_ORDER_BIT 0x80000000
155
156 /* Interrupt Codes */
157 /* Program Interrupts */
158 #define PGM_OPERATION 0x0001
159 #define PGM_PRIVILEGED 0x0002
160 #define PGM_EXECUTE 0x0003
161 #define PGM_PROTECTION 0x0004
162 #define PGM_ADDRESSING 0x0005
163 #define PGM_SPECIFICATION 0x0006
164 #define PGM_DATA 0x0007
165 #define PGM_FIXPT_OVERFLOW 0x0008
166 #define PGM_FIXPT_DIVIDE 0x0009
167 #define PGM_DEC_OVERFLOW 0x000a
168 #define PGM_DEC_DIVIDE 0x000b
169 #define PGM_HFP_EXP_OVERFLOW 0x000c
170 #define PGM_HFP_EXP_UNDERFLOW 0x000d
171 #define PGM_HFP_SIGNIFICANCE 0x000e
172 #define PGM_HFP_DIVIDE 0x000f
173 #define PGM_SEGMENT_TRANS 0x0010
174 #define PGM_PAGE_TRANS 0x0011
175 #define PGM_TRANS_SPEC 0x0012
176 #define PGM_SPECIAL_OP 0x0013
177 #define PGM_OPERAND 0x0015
178 #define PGM_TRACE_TABLE 0x0016
179 #define PGM_SPACE_SWITCH 0x001c
180 #define PGM_HFP_SQRT 0x001d
181 #define PGM_PC_TRANS_SPEC 0x001f
182 #define PGM_AFX_TRANS 0x0020
183 #define PGM_ASX_TRANS 0x0021
184 #define PGM_LX_TRANS 0x0022
185 #define PGM_EX_TRANS 0x0023
186 #define PGM_PRIM_AUTH 0x0024
187 #define PGM_SEC_AUTH 0x0025
188 #define PGM_ALET_SPEC 0x0028
189 #define PGM_ALEN_SPEC 0x0029
190 #define PGM_ALE_SEQ 0x002a
191 #define PGM_ASTE_VALID 0x002b
192 #define PGM_ASTE_SEQ 0x002c
193 #define PGM_EXT_AUTH 0x002d
194 #define PGM_STACK_FULL 0x0030
195 #define PGM_STACK_EMPTY 0x0031
196 #define PGM_STACK_SPEC 0x0032
197 #define PGM_STACK_TYPE 0x0033
198 #define PGM_STACK_OP 0x0034
199 #define PGM_ASCE_TYPE 0x0038
200 #define PGM_REG_FIRST_TRANS 0x0039
201 #define PGM_REG_SEC_TRANS 0x003a
202 #define PGM_REG_THIRD_TRANS 0x003b
203 #define PGM_MONITOR 0x0040
204 #define PGM_PER 0x0080
205 #define PGM_CRYPTO 0x0119
206
207 /* External Interrupts */
208 #define EXT_INTERRUPT_KEY 0x0040
209 #define EXT_CLOCK_COMP 0x1004
210 #define EXT_CPU_TIMER 0x1005
211 #define EXT_MALFUNCTION 0x1200
212 #define EXT_EMERGENCY 0x1201
213 #define EXT_EXTERNAL_CALL 0x1202
214 #define EXT_ETR 0x1406
215 #define EXT_SERVICE 0x2401
216 #define EXT_VIRTIO 0x2603
217
218 /* PSW defines */
219 #undef PSW_MASK_PER
220 #undef PSW_MASK_DAT
221 #undef PSW_MASK_IO
222 #undef PSW_MASK_EXT
223 #undef PSW_MASK_KEY
224 #undef PSW_SHIFT_KEY
225 #undef PSW_MASK_MCHECK
226 #undef PSW_MASK_WAIT
227 #undef PSW_MASK_PSTATE
228 #undef PSW_MASK_ASC
229 #undef PSW_MASK_CC
230 #undef PSW_MASK_PM
231 #undef PSW_MASK_64
232 #undef PSW_MASK_32
233 #undef PSW_MASK_ESA_ADDR
234
235 #define PSW_MASK_PER 0x4000000000000000ULL
236 #define PSW_MASK_DAT 0x0400000000000000ULL
237 #define PSW_MASK_IO 0x0200000000000000ULL
238 #define PSW_MASK_EXT 0x0100000000000000ULL
239 #define PSW_MASK_KEY 0x00F0000000000000ULL
240 #define PSW_SHIFT_KEY 56
241 #define PSW_MASK_MCHECK 0x0004000000000000ULL
242 #define PSW_MASK_WAIT 0x0002000000000000ULL
243 #define PSW_MASK_PSTATE 0x0001000000000000ULL
244 #define PSW_MASK_ASC 0x0000C00000000000ULL
245 #define PSW_MASK_CC 0x0000300000000000ULL
246 #define PSW_MASK_PM 0x00000F0000000000ULL
247 #define PSW_MASK_64 0x0000000100000000ULL
248 #define PSW_MASK_32 0x0000000080000000ULL
249 #define PSW_MASK_ESA_ADDR 0x000000007fffffffULL
250
251 #undef PSW_ASC_PRIMARY
252 #undef PSW_ASC_ACCREG
253 #undef PSW_ASC_SECONDARY
254 #undef PSW_ASC_HOME
255
256 #define PSW_ASC_PRIMARY 0x0000000000000000ULL
257 #define PSW_ASC_ACCREG 0x0000400000000000ULL
258 #define PSW_ASC_SECONDARY 0x0000800000000000ULL
259 #define PSW_ASC_HOME 0x0000C00000000000ULL
260
261 /* tb flags */
262
263 #define FLAG_MASK_PER (PSW_MASK_PER >> 32)
264 #define FLAG_MASK_DAT (PSW_MASK_DAT >> 32)
265 #define FLAG_MASK_IO (PSW_MASK_IO >> 32)
266 #define FLAG_MASK_EXT (PSW_MASK_EXT >> 32)
267 #define FLAG_MASK_KEY (PSW_MASK_KEY >> 32)
268 #define FLAG_MASK_MCHECK (PSW_MASK_MCHECK >> 32)
269 #define FLAG_MASK_WAIT (PSW_MASK_WAIT >> 32)
270 #define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> 32)
271 #define FLAG_MASK_ASC (PSW_MASK_ASC >> 32)
272 #define FLAG_MASK_CC (PSW_MASK_CC >> 32)
273 #define FLAG_MASK_PM (PSW_MASK_PM >> 32)
274 #define FLAG_MASK_64 (PSW_MASK_64 >> 32)
275 #define FLAG_MASK_32 0x00001000
276
277 static inline int cpu_mmu_index (CPUS390XState *env)
278 {
279 if (env->psw.mask & PSW_MASK_PSTATE) {
280 return 1;
281 }
282
283 return 0;
284 }
285
286 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
287 target_ulong *cs_base, int *flags)
288 {
289 *pc = env->psw.addr;
290 *cs_base = 0;
291 *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
292 ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
293 }
294
295 /* While the PoO talks about ILC (a number between 1-3) what is actually
296 stored in LowCore is shifted left one bit (an even between 2-6). As
297 this is the actual length of the insn and therefore more useful, that
298 is what we want to pass around and manipulate. To make sure that we
299 have applied this distinction universally, rename the "ILC" to "ILEN". */
300 static inline int get_ilen(uint8_t opc)
301 {
302 switch (opc >> 6) {
303 case 0:
304 return 2;
305 case 1:
306 case 2:
307 return 4;
308 default:
309 return 6;
310 }
311 }
312
313 #ifndef CONFIG_USER_ONLY
314 /* In several cases of runtime exceptions, we havn't recorded the true
315 instruction length. Use these codes when raising exceptions in order
316 to re-compute the length by examining the insn in memory. */
317 #define ILEN_LATER 0x20
318 #define ILEN_LATER_INC 0x21
319 #endif
320
321 S390CPU *cpu_s390x_init(const char *cpu_model);
322 void s390x_translate_init(void);
323 int cpu_s390x_exec(CPUS390XState *s);
324
325 /* you can call this signal handler from your SIGBUS and SIGSEGV
326 signal handlers to inform the virtual CPU of exceptions. non zero
327 is returned if the signal was handled by the virtual CPU. */
328 int cpu_s390x_signal_handler(int host_signum, void *pinfo,
329 void *puc);
330 int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw,
331 int mmu_idx);
332 #define cpu_handle_mmu_fault cpu_s390x_handle_mmu_fault
333
334 #include "ioinst.h"
335
336 #ifndef CONFIG_USER_ONLY
337 void *s390_cpu_physical_memory_map(CPUS390XState *env, hwaddr addr, hwaddr *len,
338 int is_write);
339 void s390_cpu_physical_memory_unmap(CPUS390XState *env, void *addr, hwaddr len,
340 int is_write);
341 static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb)
342 {
343 hwaddr addr = 0;
344 uint8_t reg;
345
346 reg = ipb >> 28;
347 if (reg > 0) {
348 addr = env->regs[reg];
349 }
350 addr += (ipb >> 16) & 0xfff;
351
352 return addr;
353 }
354
355 void s390x_tod_timer(void *opaque);
356 void s390x_cpu_timer(void *opaque);
357
358 int s390_virtio_hypercall(CPUS390XState *env);
359
360 #ifdef CONFIG_KVM
361 void kvm_s390_interrupt(S390CPU *cpu, int type, uint32_t code);
362 void kvm_s390_virtio_irq(S390CPU *cpu, int config_change, uint64_t token);
363 void kvm_s390_interrupt_internal(S390CPU *cpu, int type, uint32_t parm,
364 uint64_t parm64, int vm);
365 #else
366 static inline void kvm_s390_interrupt(S390CPU *cpu, int type, uint32_t code)
367 {
368 }
369
370 static inline void kvm_s390_virtio_irq(S390CPU *cpu, int config_change,
371 uint64_t token)
372 {
373 }
374
375 static inline void kvm_s390_interrupt_internal(S390CPU *cpu, int type,
376 uint32_t parm, uint64_t parm64,
377 int vm)
378 {
379 }
380 #endif
381 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
382 void s390_add_running_cpu(S390CPU *cpu);
383 unsigned s390_del_running_cpu(S390CPU *cpu);
384
385 /* service interrupts are floating therefore we must not pass an cpustate */
386 void s390_sclp_extint(uint32_t parm);
387
388 /* from s390-virtio-bus */
389 extern const hwaddr virtio_size;
390
391 #else
392 static inline void s390_add_running_cpu(S390CPU *cpu)
393 {
394 }
395
396 static inline unsigned s390_del_running_cpu(S390CPU *cpu)
397 {
398 return 0;
399 }
400 #endif
401 void cpu_lock(void);
402 void cpu_unlock(void);
403
404 typedef struct SubchDev SubchDev;
405
406 #ifndef CONFIG_USER_ONLY
407 extern void io_subsystem_reset(void);
408 SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
409 uint16_t schid);
410 bool css_subch_visible(SubchDev *sch);
411 void css_conditional_io_interrupt(SubchDev *sch);
412 int css_do_stsch(SubchDev *sch, SCHIB *schib);
413 bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
414 int css_do_msch(SubchDev *sch, SCHIB *schib);
415 int css_do_xsch(SubchDev *sch);
416 int css_do_csch(SubchDev *sch);
417 int css_do_hsch(SubchDev *sch);
418 int css_do_ssch(SubchDev *sch, ORB *orb);
419 int css_do_tsch(SubchDev *sch, IRB *irb);
420 int css_do_stcrw(CRW *crw);
421 int css_do_tpi(IOIntCode *int_code, int lowcore);
422 int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
423 int rfmt, void *buf);
424 void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
425 int css_enable_mcsse(void);
426 int css_enable_mss(void);
427 int css_do_rsch(SubchDev *sch);
428 int css_do_rchp(uint8_t cssid, uint8_t chpid);
429 bool css_present(uint8_t cssid);
430 #else
431 static inline SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
432 uint16_t schid)
433 {
434 return NULL;
435 }
436 static inline bool css_subch_visible(SubchDev *sch)
437 {
438 return false;
439 }
440 static inline void css_conditional_io_interrupt(SubchDev *sch)
441 {
442 }
443 static inline int css_do_stsch(SubchDev *sch, SCHIB *schib)
444 {
445 return -ENODEV;
446 }
447 static inline bool css_schid_final(uint8_t cssid, uint8_t ssid, uint16_t schid)
448 {
449 return true;
450 }
451 static inline int css_do_msch(SubchDev *sch, SCHIB *schib)
452 {
453 return -ENODEV;
454 }
455 static inline int css_do_xsch(SubchDev *sch)
456 {
457 return -ENODEV;
458 }
459 static inline int css_do_csch(SubchDev *sch)
460 {
461 return -ENODEV;
462 }
463 static inline int css_do_hsch(SubchDev *sch)
464 {
465 return -ENODEV;
466 }
467 static inline int css_do_ssch(SubchDev *sch, ORB *orb)
468 {
469 return -ENODEV;
470 }
471 static inline int css_do_tsch(SubchDev *sch, IRB *irb)
472 {
473 return -ENODEV;
474 }
475 static inline int css_do_stcrw(CRW *crw)
476 {
477 return 1;
478 }
479 static inline int css_do_tpi(IOIntCode *int_code, int lowcore)
480 {
481 return 0;
482 }
483 static inline int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid,
484 int rfmt, uint8_t l_chpid, void *buf)
485 {
486 return 0;
487 }
488 static inline void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo)
489 {
490 }
491 static inline int css_enable_mss(void)
492 {
493 return -EINVAL;
494 }
495 static inline int css_enable_mcsse(void)
496 {
497 return -EINVAL;
498 }
499 static inline int css_do_rsch(SubchDev *sch)
500 {
501 return -ENODEV;
502 }
503 static inline int css_do_rchp(uint8_t cssid, uint8_t chpid)
504 {
505 return -ENODEV;
506 }
507 static inline bool css_present(uint8_t cssid)
508 {
509 return false;
510 }
511 #endif
512
513 #define cpu_init(model) (&cpu_s390x_init(model)->env)
514 #define cpu_exec cpu_s390x_exec
515 #define cpu_gen_code cpu_s390x_gen_code
516 #define cpu_signal_handler cpu_s390x_signal_handler
517
518 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
519 #define cpu_list s390_cpu_list
520
521 #include "exec/exec-all.h"
522
523 #define EXCP_EXT 1 /* external interrupt */
524 #define EXCP_SVC 2 /* supervisor call (syscall) */
525 #define EXCP_PGM 3 /* program interruption */
526 #define EXCP_IO 7 /* I/O interrupt */
527 #define EXCP_MCHK 8 /* machine check */
528
529 #define INTERRUPT_EXT (1 << 0)
530 #define INTERRUPT_TOD (1 << 1)
531 #define INTERRUPT_CPUTIMER (1 << 2)
532 #define INTERRUPT_IO (1 << 3)
533 #define INTERRUPT_MCHK (1 << 4)
534
535 /* Program Status Word. */
536 #define S390_PSWM_REGNUM 0
537 #define S390_PSWA_REGNUM 1
538 /* General Purpose Registers. */
539 #define S390_R0_REGNUM 2
540 #define S390_R1_REGNUM 3
541 #define S390_R2_REGNUM 4
542 #define S390_R3_REGNUM 5
543 #define S390_R4_REGNUM 6
544 #define S390_R5_REGNUM 7
545 #define S390_R6_REGNUM 8
546 #define S390_R7_REGNUM 9
547 #define S390_R8_REGNUM 10
548 #define S390_R9_REGNUM 11
549 #define S390_R10_REGNUM 12
550 #define S390_R11_REGNUM 13
551 #define S390_R12_REGNUM 14
552 #define S390_R13_REGNUM 15
553 #define S390_R14_REGNUM 16
554 #define S390_R15_REGNUM 17
555 /* Access Registers. */
556 #define S390_A0_REGNUM 18
557 #define S390_A1_REGNUM 19
558 #define S390_A2_REGNUM 20
559 #define S390_A3_REGNUM 21
560 #define S390_A4_REGNUM 22
561 #define S390_A5_REGNUM 23
562 #define S390_A6_REGNUM 24
563 #define S390_A7_REGNUM 25
564 #define S390_A8_REGNUM 26
565 #define S390_A9_REGNUM 27
566 #define S390_A10_REGNUM 28
567 #define S390_A11_REGNUM 29
568 #define S390_A12_REGNUM 30
569 #define S390_A13_REGNUM 31
570 #define S390_A14_REGNUM 32
571 #define S390_A15_REGNUM 33
572 /* Floating Point Control Word. */
573 #define S390_FPC_REGNUM 34
574 /* Floating Point Registers. */
575 #define S390_F0_REGNUM 35
576 #define S390_F1_REGNUM 36
577 #define S390_F2_REGNUM 37
578 #define S390_F3_REGNUM 38
579 #define S390_F4_REGNUM 39
580 #define S390_F5_REGNUM 40
581 #define S390_F6_REGNUM 41
582 #define S390_F7_REGNUM 42
583 #define S390_F8_REGNUM 43
584 #define S390_F9_REGNUM 44
585 #define S390_F10_REGNUM 45
586 #define S390_F11_REGNUM 46
587 #define S390_F12_REGNUM 47
588 #define S390_F13_REGNUM 48
589 #define S390_F14_REGNUM 49
590 #define S390_F15_REGNUM 50
591 /* Total. */
592 #define S390_NUM_REGS 51
593
594 /* CC optimization */
595
596 enum cc_op {
597 CC_OP_CONST0 = 0, /* CC is 0 */
598 CC_OP_CONST1, /* CC is 1 */
599 CC_OP_CONST2, /* CC is 2 */
600 CC_OP_CONST3, /* CC is 3 */
601
602 CC_OP_DYNAMIC, /* CC calculation defined by env->cc_op */
603 CC_OP_STATIC, /* CC value is env->cc_op */
604
605 CC_OP_NZ, /* env->cc_dst != 0 */
606 CC_OP_LTGT_32, /* signed less/greater than (32bit) */
607 CC_OP_LTGT_64, /* signed less/greater than (64bit) */
608 CC_OP_LTUGTU_32, /* unsigned less/greater than (32bit) */
609 CC_OP_LTUGTU_64, /* unsigned less/greater than (64bit) */
610 CC_OP_LTGT0_32, /* signed less/greater than 0 (32bit) */
611 CC_OP_LTGT0_64, /* signed less/greater than 0 (64bit) */
612
613 CC_OP_ADD_64, /* overflow on add (64bit) */
614 CC_OP_ADDU_64, /* overflow on unsigned add (64bit) */
615 CC_OP_ADDC_64, /* overflow on unsigned add-carry (64bit) */
616 CC_OP_SUB_64, /* overflow on subtraction (64bit) */
617 CC_OP_SUBU_64, /* overflow on unsigned subtraction (64bit) */
618 CC_OP_SUBB_64, /* overflow on unsigned sub-borrow (64bit) */
619 CC_OP_ABS_64, /* sign eval on abs (64bit) */
620 CC_OP_NABS_64, /* sign eval on nabs (64bit) */
621
622 CC_OP_ADD_32, /* overflow on add (32bit) */
623 CC_OP_ADDU_32, /* overflow on unsigned add (32bit) */
624 CC_OP_ADDC_32, /* overflow on unsigned add-carry (32bit) */
625 CC_OP_SUB_32, /* overflow on subtraction (32bit) */
626 CC_OP_SUBU_32, /* overflow on unsigned subtraction (32bit) */
627 CC_OP_SUBB_32, /* overflow on unsigned sub-borrow (32bit) */
628 CC_OP_ABS_32, /* sign eval on abs (64bit) */
629 CC_OP_NABS_32, /* sign eval on nabs (64bit) */
630
631 CC_OP_COMP_32, /* complement */
632 CC_OP_COMP_64, /* complement */
633
634 CC_OP_TM_32, /* test under mask (32bit) */
635 CC_OP_TM_64, /* test under mask (64bit) */
636
637 CC_OP_NZ_F32, /* FP dst != 0 (32bit) */
638 CC_OP_NZ_F64, /* FP dst != 0 (64bit) */
639 CC_OP_NZ_F128, /* FP dst != 0 (128bit) */
640
641 CC_OP_ICM, /* insert characters under mask */
642 CC_OP_SLA_32, /* Calculate shift left signed (32bit) */
643 CC_OP_SLA_64, /* Calculate shift left signed (64bit) */
644 CC_OP_FLOGR, /* find leftmost one */
645 CC_OP_MAX
646 };
647
648 static const char *cc_names[] = {
649 [CC_OP_CONST0] = "CC_OP_CONST0",
650 [CC_OP_CONST1] = "CC_OP_CONST1",
651 [CC_OP_CONST2] = "CC_OP_CONST2",
652 [CC_OP_CONST3] = "CC_OP_CONST3",
653 [CC_OP_DYNAMIC] = "CC_OP_DYNAMIC",
654 [CC_OP_STATIC] = "CC_OP_STATIC",
655 [CC_OP_NZ] = "CC_OP_NZ",
656 [CC_OP_LTGT_32] = "CC_OP_LTGT_32",
657 [CC_OP_LTGT_64] = "CC_OP_LTGT_64",
658 [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
659 [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
660 [CC_OP_LTGT0_32] = "CC_OP_LTGT0_32",
661 [CC_OP_LTGT0_64] = "CC_OP_LTGT0_64",
662 [CC_OP_ADD_64] = "CC_OP_ADD_64",
663 [CC_OP_ADDU_64] = "CC_OP_ADDU_64",
664 [CC_OP_ADDC_64] = "CC_OP_ADDC_64",
665 [CC_OP_SUB_64] = "CC_OP_SUB_64",
666 [CC_OP_SUBU_64] = "CC_OP_SUBU_64",
667 [CC_OP_SUBB_64] = "CC_OP_SUBB_64",
668 [CC_OP_ABS_64] = "CC_OP_ABS_64",
669 [CC_OP_NABS_64] = "CC_OP_NABS_64",
670 [CC_OP_ADD_32] = "CC_OP_ADD_32",
671 [CC_OP_ADDU_32] = "CC_OP_ADDU_32",
672 [CC_OP_ADDC_32] = "CC_OP_ADDC_32",
673 [CC_OP_SUB_32] = "CC_OP_SUB_32",
674 [CC_OP_SUBU_32] = "CC_OP_SUBU_32",
675 [CC_OP_SUBB_32] = "CC_OP_SUBB_32",
676 [CC_OP_ABS_32] = "CC_OP_ABS_32",
677 [CC_OP_NABS_32] = "CC_OP_NABS_32",
678 [CC_OP_COMP_32] = "CC_OP_COMP_32",
679 [CC_OP_COMP_64] = "CC_OP_COMP_64",
680 [CC_OP_TM_32] = "CC_OP_TM_32",
681 [CC_OP_TM_64] = "CC_OP_TM_64",
682 [CC_OP_NZ_F32] = "CC_OP_NZ_F32",
683 [CC_OP_NZ_F64] = "CC_OP_NZ_F64",
684 [CC_OP_NZ_F128] = "CC_OP_NZ_F128",
685 [CC_OP_ICM] = "CC_OP_ICM",
686 [CC_OP_SLA_32] = "CC_OP_SLA_32",
687 [CC_OP_SLA_64] = "CC_OP_SLA_64",
688 [CC_OP_FLOGR] = "CC_OP_FLOGR",
689 };
690
691 static inline const char *cc_name(int cc_op)
692 {
693 return cc_names[cc_op];
694 }
695
696 static inline void setcc(S390CPU *cpu, uint64_t cc)
697 {
698 CPUS390XState *env = &cpu->env;
699
700 env->psw.mask &= ~(3ull << 44);
701 env->psw.mask |= (cc & 3) << 44;
702 }
703
704 typedef struct LowCore
705 {
706 /* prefix area: defined by architecture */
707 uint32_t ccw1[2]; /* 0x000 */
708 uint32_t ccw2[4]; /* 0x008 */
709 uint8_t pad1[0x80-0x18]; /* 0x018 */
710 uint32_t ext_params; /* 0x080 */
711 uint16_t cpu_addr; /* 0x084 */
712 uint16_t ext_int_code; /* 0x086 */
713 uint16_t svc_ilen; /* 0x088 */
714 uint16_t svc_code; /* 0x08a */
715 uint16_t pgm_ilen; /* 0x08c */
716 uint16_t pgm_code; /* 0x08e */
717 uint32_t data_exc_code; /* 0x090 */
718 uint16_t mon_class_num; /* 0x094 */
719 uint16_t per_perc_atmid; /* 0x096 */
720 uint64_t per_address; /* 0x098 */
721 uint8_t exc_access_id; /* 0x0a0 */
722 uint8_t per_access_id; /* 0x0a1 */
723 uint8_t op_access_id; /* 0x0a2 */
724 uint8_t ar_access_id; /* 0x0a3 */
725 uint8_t pad2[0xA8-0xA4]; /* 0x0a4 */
726 uint64_t trans_exc_code; /* 0x0a8 */
727 uint64_t monitor_code; /* 0x0b0 */
728 uint16_t subchannel_id; /* 0x0b8 */
729 uint16_t subchannel_nr; /* 0x0ba */
730 uint32_t io_int_parm; /* 0x0bc */
731 uint32_t io_int_word; /* 0x0c0 */
732 uint8_t pad3[0xc8-0xc4]; /* 0x0c4 */
733 uint32_t stfl_fac_list; /* 0x0c8 */
734 uint8_t pad4[0xe8-0xcc]; /* 0x0cc */
735 uint32_t mcck_interruption_code[2]; /* 0x0e8 */
736 uint8_t pad5[0xf4-0xf0]; /* 0x0f0 */
737 uint32_t external_damage_code; /* 0x0f4 */
738 uint64_t failing_storage_address; /* 0x0f8 */
739 uint8_t pad6[0x120-0x100]; /* 0x100 */
740 PSW restart_old_psw; /* 0x120 */
741 PSW external_old_psw; /* 0x130 */
742 PSW svc_old_psw; /* 0x140 */
743 PSW program_old_psw; /* 0x150 */
744 PSW mcck_old_psw; /* 0x160 */
745 PSW io_old_psw; /* 0x170 */
746 uint8_t pad7[0x1a0-0x180]; /* 0x180 */
747 PSW restart_psw; /* 0x1a0 */
748 PSW external_new_psw; /* 0x1b0 */
749 PSW svc_new_psw; /* 0x1c0 */
750 PSW program_new_psw; /* 0x1d0 */
751 PSW mcck_new_psw; /* 0x1e0 */
752 PSW io_new_psw; /* 0x1f0 */
753 PSW return_psw; /* 0x200 */
754 uint8_t irb[64]; /* 0x210 */
755 uint64_t sync_enter_timer; /* 0x250 */
756 uint64_t async_enter_timer; /* 0x258 */
757 uint64_t exit_timer; /* 0x260 */
758 uint64_t last_update_timer; /* 0x268 */
759 uint64_t user_timer; /* 0x270 */
760 uint64_t system_timer; /* 0x278 */
761 uint64_t last_update_clock; /* 0x280 */
762 uint64_t steal_clock; /* 0x288 */
763 PSW return_mcck_psw; /* 0x290 */
764 uint8_t pad8[0xc00-0x2a0]; /* 0x2a0 */
765 /* System info area */
766 uint64_t save_area[16]; /* 0xc00 */
767 uint8_t pad9[0xd40-0xc80]; /* 0xc80 */
768 uint64_t kernel_stack; /* 0xd40 */
769 uint64_t thread_info; /* 0xd48 */
770 uint64_t async_stack; /* 0xd50 */
771 uint64_t kernel_asce; /* 0xd58 */
772 uint64_t user_asce; /* 0xd60 */
773 uint64_t panic_stack; /* 0xd68 */
774 uint64_t user_exec_asce; /* 0xd70 */
775 uint8_t pad10[0xdc0-0xd78]; /* 0xd78 */
776
777 /* SMP info area: defined by DJB */
778 uint64_t clock_comparator; /* 0xdc0 */
779 uint64_t ext_call_fast; /* 0xdc8 */
780 uint64_t percpu_offset; /* 0xdd0 */
781 uint64_t current_task; /* 0xdd8 */
782 uint32_t softirq_pending; /* 0xde0 */
783 uint32_t pad_0x0de4; /* 0xde4 */
784 uint64_t int_clock; /* 0xde8 */
785 uint8_t pad12[0xe00-0xdf0]; /* 0xdf0 */
786
787 /* 0xe00 is used as indicator for dump tools */
788 /* whether the kernel died with panic() or not */
789 uint32_t panic_magic; /* 0xe00 */
790
791 uint8_t pad13[0x11b8-0xe04]; /* 0xe04 */
792
793 /* 64 bit extparam used for pfault, diag 250 etc */
794 uint64_t ext_params2; /* 0x11B8 */
795
796 uint8_t pad14[0x1200-0x11C0]; /* 0x11C0 */
797
798 /* System info area */
799
800 uint64_t floating_pt_save_area[16]; /* 0x1200 */
801 uint64_t gpregs_save_area[16]; /* 0x1280 */
802 uint32_t st_status_fixed_logout[4]; /* 0x1300 */
803 uint8_t pad15[0x1318-0x1310]; /* 0x1310 */
804 uint32_t prefixreg_save_area; /* 0x1318 */
805 uint32_t fpt_creg_save_area; /* 0x131c */
806 uint8_t pad16[0x1324-0x1320]; /* 0x1320 */
807 uint32_t tod_progreg_save_area; /* 0x1324 */
808 uint32_t cpu_timer_save_area[2]; /* 0x1328 */
809 uint32_t clock_comp_save_area[2]; /* 0x1330 */
810 uint8_t pad17[0x1340-0x1338]; /* 0x1338 */
811 uint32_t access_regs_save_area[16]; /* 0x1340 */
812 uint64_t cregs_save_area[16]; /* 0x1380 */
813
814 /* align to the top of the prefix area */
815
816 uint8_t pad18[0x2000-0x1400]; /* 0x1400 */
817 } QEMU_PACKED LowCore;
818
819 /* STSI */
820 #define STSI_LEVEL_MASK 0x00000000f0000000ULL
821 #define STSI_LEVEL_CURRENT 0x0000000000000000ULL
822 #define STSI_LEVEL_1 0x0000000010000000ULL
823 #define STSI_LEVEL_2 0x0000000020000000ULL
824 #define STSI_LEVEL_3 0x0000000030000000ULL
825 #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
826 #define STSI_R0_SEL1_MASK 0x00000000000000ffULL
827 #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
828 #define STSI_R1_SEL2_MASK 0x000000000000ffffULL
829
830 /* Basic Machine Configuration */
831 struct sysib_111 {
832 uint32_t res1[8];
833 uint8_t manuf[16];
834 uint8_t type[4];
835 uint8_t res2[12];
836 uint8_t model[16];
837 uint8_t sequence[16];
838 uint8_t plant[4];
839 uint8_t res3[156];
840 };
841
842 /* Basic Machine CPU */
843 struct sysib_121 {
844 uint32_t res1[80];
845 uint8_t sequence[16];
846 uint8_t plant[4];
847 uint8_t res2[2];
848 uint16_t cpu_addr;
849 uint8_t res3[152];
850 };
851
852 /* Basic Machine CPUs */
853 struct sysib_122 {
854 uint8_t res1[32];
855 uint32_t capability;
856 uint16_t total_cpus;
857 uint16_t active_cpus;
858 uint16_t standby_cpus;
859 uint16_t reserved_cpus;
860 uint16_t adjustments[2026];
861 };
862
863 /* LPAR CPU */
864 struct sysib_221 {
865 uint32_t res1[80];
866 uint8_t sequence[16];
867 uint8_t plant[4];
868 uint16_t cpu_id;
869 uint16_t cpu_addr;
870 uint8_t res3[152];
871 };
872
873 /* LPAR CPUs */
874 struct sysib_222 {
875 uint32_t res1[32];
876 uint16_t lpar_num;
877 uint8_t res2;
878 uint8_t lcpuc;
879 uint16_t total_cpus;
880 uint16_t conf_cpus;
881 uint16_t standby_cpus;
882 uint16_t reserved_cpus;
883 uint8_t name[8];
884 uint32_t caf;
885 uint8_t res3[16];
886 uint16_t dedicated_cpus;
887 uint16_t shared_cpus;
888 uint8_t res4[180];
889 };
890
891 /* VM CPUs */
892 struct sysib_322 {
893 uint8_t res1[31];
894 uint8_t count;
895 struct {
896 uint8_t res2[4];
897 uint16_t total_cpus;
898 uint16_t conf_cpus;
899 uint16_t standby_cpus;
900 uint16_t reserved_cpus;
901 uint8_t name[8];
902 uint32_t caf;
903 uint8_t cpi[16];
904 uint8_t res3[24];
905 } vm[8];
906 uint8_t res4[3552];
907 };
908
909 /* MMU defines */
910 #define _ASCE_ORIGIN ~0xfffULL /* segment table origin */
911 #define _ASCE_SUBSPACE 0x200 /* subspace group control */
912 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
913 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
914 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
915 #define _ASCE_REAL_SPACE 0x20 /* real space control */
916 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
917 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */
918 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */
919 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */
920 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
921 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */
922
923 #define _REGION_ENTRY_ORIGIN ~0xfffULL /* region/segment table origin */
924 #define _REGION_ENTRY_INV 0x20 /* invalid region table entry */
925 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
926 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
927 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
928 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
929 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */
930
931 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL /* segment table origin */
932 #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
933 #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
934
935 #define _PAGE_RO 0x200 /* HW read-only bit */
936 #define _PAGE_INVALID 0x400 /* HW invalid bit */
937
938 #define SK_C (0x1 << 1)
939 #define SK_R (0x1 << 2)
940 #define SK_F (0x1 << 3)
941 #define SK_ACC_MASK (0xf << 4)
942
943 #define SIGP_SENSE 0x01
944 #define SIGP_EXTERNAL_CALL 0x02
945 #define SIGP_EMERGENCY 0x03
946 #define SIGP_START 0x04
947 #define SIGP_STOP 0x05
948 #define SIGP_RESTART 0x06
949 #define SIGP_STOP_STORE_STATUS 0x09
950 #define SIGP_INITIAL_CPU_RESET 0x0b
951 #define SIGP_CPU_RESET 0x0c
952 #define SIGP_SET_PREFIX 0x0d
953 #define SIGP_STORE_STATUS_ADDR 0x0e
954 #define SIGP_SET_ARCH 0x12
955
956 /* cpu status bits */
957 #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
958 #define SIGP_STAT_INCORRECT_STATE 0x00000200UL
959 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
960 #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
961 #define SIGP_STAT_STOPPED 0x00000040UL
962 #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
963 #define SIGP_STAT_CHECK_STOP 0x00000010UL
964 #define SIGP_STAT_INOPERATIVE 0x00000004UL
965 #define SIGP_STAT_INVALID_ORDER 0x00000002UL
966 #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
967
968 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
969 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
970 target_ulong *raddr, int *flags);
971 int sclp_service_call(uint32_t sccb, uint64_t code);
972 uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
973 uint64_t vr);
974
975 #define TARGET_HAS_ICE 1
976
977 /* The value of the TOD clock for 1.1.1970. */
978 #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
979
980 /* Converts ns to s390's clock format */
981 static inline uint64_t time2tod(uint64_t ns) {
982 return (ns << 9) / 125;
983 }
984
985 static inline void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
986 uint64_t param64)
987 {
988 CPUS390XState *env = &cpu->env;
989
990 if (env->ext_index == MAX_EXT_QUEUE - 1) {
991 /* ugh - can't queue anymore. Let's drop. */
992 return;
993 }
994
995 env->ext_index++;
996 assert(env->ext_index < MAX_EXT_QUEUE);
997
998 env->ext_queue[env->ext_index].code = code;
999 env->ext_queue[env->ext_index].param = param;
1000 env->ext_queue[env->ext_index].param64 = param64;
1001
1002 env->pending_int |= INTERRUPT_EXT;
1003 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1004 }
1005
1006 static inline void cpu_inject_io(S390CPU *cpu, uint16_t subchannel_id,
1007 uint16_t subchannel_number,
1008 uint32_t io_int_parm, uint32_t io_int_word)
1009 {
1010 CPUS390XState *env = &cpu->env;
1011 int isc = IO_INT_WORD_ISC(io_int_word);
1012
1013 if (env->io_index[isc] == MAX_IO_QUEUE - 1) {
1014 /* ugh - can't queue anymore. Let's drop. */
1015 return;
1016 }
1017
1018 env->io_index[isc]++;
1019 assert(env->io_index[isc] < MAX_IO_QUEUE);
1020
1021 env->io_queue[env->io_index[isc]][isc].id = subchannel_id;
1022 env->io_queue[env->io_index[isc]][isc].nr = subchannel_number;
1023 env->io_queue[env->io_index[isc]][isc].parm = io_int_parm;
1024 env->io_queue[env->io_index[isc]][isc].word = io_int_word;
1025
1026 env->pending_int |= INTERRUPT_IO;
1027 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1028 }
1029
1030 static inline void cpu_inject_crw_mchk(S390CPU *cpu)
1031 {
1032 CPUS390XState *env = &cpu->env;
1033
1034 if (env->mchk_index == MAX_MCHK_QUEUE - 1) {
1035 /* ugh - can't queue anymore. Let's drop. */
1036 return;
1037 }
1038
1039 env->mchk_index++;
1040 assert(env->mchk_index < MAX_MCHK_QUEUE);
1041
1042 env->mchk_queue[env->mchk_index].type = 1;
1043
1044 env->pending_int |= INTERRUPT_MCHK;
1045 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1046 }
1047
1048 static inline bool cpu_has_work(CPUState *cpu)
1049 {
1050 S390CPU *s390_cpu = S390_CPU(cpu);
1051 CPUS390XState *env = &s390_cpu->env;
1052
1053 return (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
1054 (env->psw.mask & PSW_MASK_EXT);
1055 }
1056
1057 /* fpu_helper.c */
1058 uint32_t set_cc_nz_f32(float32 v);
1059 uint32_t set_cc_nz_f64(float64 v);
1060 uint32_t set_cc_nz_f128(float128 v);
1061
1062 /* misc_helper.c */
1063 #ifndef CONFIG_USER_ONLY
1064 void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3);
1065 #endif
1066 void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
1067 void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
1068 uintptr_t retaddr);
1069
1070 #ifdef CONFIG_KVM
1071 void kvm_s390_io_interrupt(S390CPU *cpu, uint16_t subchannel_id,
1072 uint16_t subchannel_nr, uint32_t io_int_parm,
1073 uint32_t io_int_word);
1074 void kvm_s390_crw_mchk(S390CPU *cpu);
1075 void kvm_s390_enable_css_support(S390CPU *cpu);
1076 int kvm_s390_get_registers_partial(CPUState *cpu);
1077 int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
1078 int vq, bool assign);
1079 int kvm_s390_cpu_restart(S390CPU *cpu);
1080 #else
1081 static inline void kvm_s390_io_interrupt(S390CPU *cpu,
1082 uint16_t subchannel_id,
1083 uint16_t subchannel_nr,
1084 uint32_t io_int_parm,
1085 uint32_t io_int_word)
1086 {
1087 }
1088 static inline void kvm_s390_crw_mchk(S390CPU *cpu)
1089 {
1090 }
1091 static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1092 {
1093 }
1094 static inline int kvm_s390_get_registers_partial(CPUState *cpu)
1095 {
1096 return -ENOSYS;
1097 }
1098 static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier,
1099 uint32_t sch, int vq,
1100 bool assign)
1101 {
1102 return -ENOSYS;
1103 }
1104 static inline int kvm_s390_cpu_restart(S390CPU *cpu)
1105 {
1106 return -ENOSYS;
1107 }
1108 #endif
1109
1110 static inline int s390_cpu_restart(S390CPU *cpu)
1111 {
1112 if (kvm_enabled()) {
1113 return kvm_s390_cpu_restart(cpu);
1114 }
1115 return -ENOSYS;
1116 }
1117
1118 static inline void s390_io_interrupt(S390CPU *cpu,
1119 uint16_t subchannel_id,
1120 uint16_t subchannel_nr,
1121 uint32_t io_int_parm,
1122 uint32_t io_int_word)
1123 {
1124 if (kvm_enabled()) {
1125 kvm_s390_io_interrupt(cpu, subchannel_id, subchannel_nr, io_int_parm,
1126 io_int_word);
1127 } else {
1128 cpu_inject_io(cpu, subchannel_id, subchannel_nr, io_int_parm,
1129 io_int_word);
1130 }
1131 }
1132
1133 static inline void s390_crw_mchk(S390CPU *cpu)
1134 {
1135 if (kvm_enabled()) {
1136 kvm_s390_crw_mchk(cpu);
1137 } else {
1138 cpu_inject_crw_mchk(cpu);
1139 }
1140 }
1141
1142 static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
1143 uint32_t sch_id, int vq,
1144 bool assign)
1145 {
1146 if (kvm_enabled()) {
1147 return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
1148 } else {
1149 return -ENOSYS;
1150 }
1151 }
1152
1153 #endif
Qemu copy for testing