target-unicore32/helper.c

   1 /*
   2  * Copyright (C) 2010-2012 Guan Xuetao
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * Contributions from 2012-04-01 on are considered under GPL version 2,
   9  * or (at your option) any later version.
  10  */
  11
  12 #include "cpu.h"
  13 #include "exec/gdbstub.h"
  14 #include "helper.h"
  15 #include "qemu/host-utils.h"
  16 #ifndef CONFIG_USER_ONLY
  17 #include "ui/console.h"
  18 #endif
  19
  20 #undef DEBUG_UC32
  21
  22 #ifdef DEBUG_UC32
  23 #define DPRINTF(fmt, ...) printf("%s: " fmt , __func__, ## __VA_ARGS__)
  24 #else
  25 #define DPRINTF(fmt, ...) do {} while (0)
  26 #endif
  27
  28 CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
  29 {
  30     UniCore32CPU *cpu;
  31     CPUUniCore32State *env;
  32     ObjectClass *oc;
  33     static int inited = 1;
  34
  35     oc = cpu_class_by_name(TYPE_UNICORE32_CPU, cpu_model);
  36     if (oc == NULL) {
  37         return NULL;
  38     }
  39     cpu = UNICORE32_CPU(object_new(object_class_get_name(oc)));
  40     env = &cpu->env;
  41     env->cpu_model_str = cpu_model;
  42
  43     if (inited) {
  44         inited = 0;
  45         uc32_translate_init();
  46     }
  47
  48     qemu_init_vcpu(env);
  49     return env;
  50 }
  51
  52 uint32_t HELPER(clo)(uint32_t x)
  53 {
  54     return clo32(x);
  55 }
  56
  57 uint32_t HELPER(clz)(uint32_t x)
  58 {
  59     return clz32(x);
  60 }
  61
  62 #ifndef CONFIG_USER_ONLY
  63 void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg,
  64         uint32_t cop)
  65 {
  66     /*
  67      * movc pp.nn, rn, #imm9
  68      *      rn: UCOP_REG_D
  69      *      nn: UCOP_REG_N
  70      *          1: sys control reg.
  71      *          2: page table base reg.
  72      *          3: data fault status reg.
  73      *          4: insn fault status reg.
  74      *          5: cache op. reg.
  75      *          6: tlb op. reg.
  76      *      imm9: split UCOP_IMM10 with bit5 is 0
  77      */
  78     switch (creg) {
  79     case 1:
  80         if (cop != 0) {
  81             goto unrecognized;
  82         }
  83         env->cp0.c1_sys = val;
  84         break;
  85     case 2:
  86         if (cop != 0) {
  87             goto unrecognized;
  88         }
  89         env->cp0.c2_base = val;
  90         break;
  91     case 3:
  92         if (cop != 0) {
  93             goto unrecognized;
  94         }
  95         env->cp0.c3_faultstatus = val;
  96         break;
  97     case 4:
  98         if (cop != 0) {
  99             goto unrecognized;
 100         }
 101         env->cp0.c4_faultaddr = val;
 102         break;
 103     case 5:
 104         switch (cop) {
 105         case 28:
 106             DPRINTF("Invalidate Entire I&D cache\n");
 107             return;
 108         case 20:
 109             DPRINTF("Invalidate Entire Icache\n");
 110             return;
 111         case 12:
 112             DPRINTF("Invalidate Entire Dcache\n");
 113             return;
 114         case 10:
 115             DPRINTF("Clean Entire Dcache\n");
 116             return;
 117         case 14:
 118             DPRINTF("Flush Entire Dcache\n");
 119             return;
 120         case 13:
 121             DPRINTF("Invalidate Dcache line\n");
 122             return;
 123         case 11:
 124             DPRINTF("Clean Dcache line\n");
 125             return;
 126         case 15:
 127             DPRINTF("Flush Dcache line\n");
 128             return;
 129         }
 130         break;
 131     case 6:
 132         if ((cop <= 6) && (cop >= 2)) {
 133             /* invalid all tlb */
 134             tlb_flush(env, 1);
 135             return;
 136         }
 137         break;
 138     default:
 139         goto unrecognized;
 140     }
 141     return;
 142 unrecognized:
 143     DPRINTF("Wrong register (%d) or wrong operation (%d) in cp0_set!\n",
 144             creg, cop);
 145 }
 146
 147 uint32_t helper_cp0_get(CPUUniCore32State *env, uint32_t creg, uint32_t cop)
 148 {
 149     /*
 150      * movc rd, pp.nn, #imm9
 151      *      rd: UCOP_REG_D
 152      *      nn: UCOP_REG_N
 153      *          0: cpuid and cachetype
 154      *          1: sys control reg.
 155      *          2: page table base reg.
 156      *          3: data fault status reg.
 157      *          4: insn fault status reg.
 158      *      imm9: split UCOP_IMM10 with bit5 is 0
 159      */
 160     switch (creg) {
 161     case 0:
 162         switch (cop) {
 163         case 0:
 164             return env->cp0.c0_cpuid;
 165         case 1:
 166             return env->cp0.c0_cachetype;
 167         }
 168         break;
 169     case 1:
 170         if (cop == 0) {
 171             return env->cp0.c1_sys;
 172         }
 173         break;
 174     case 2:
 175         if (cop == 0) {
 176             return env->cp0.c2_base;
 177         }
 178         break;
 179     case 3:
 180         if (cop == 0) {
 181             return env->cp0.c3_faultstatus;
 182         }
 183         break;
 184     case 4:
 185         if (cop == 0) {
 186             return env->cp0.c4_faultaddr;
 187         }
 188         break;
 189     }
 190     DPRINTF("Wrong register (%d) or wrong operation (%d) in cp0_set!\n",
 191             creg, cop);
 192     return 0;
 193 }
 194
 195 #ifdef CONFIG_CURSES
 196 /*
 197  * FIXME:
 198  *     1. curses windows will be blank when switching back
 199  *     2. backspace is not handled yet
 200  */
 201 static void putc_on_screen(unsigned char ch)
 202 {
 203     static WINDOW *localwin;
 204     static int init;
 205
 206     if (!init) {
 207         /* Assume 80 * 30 screen to minimize the implementation */
 208         localwin = newwin(30, 80, 0, 0);
 209         scrollok(localwin, TRUE);
 210         init = TRUE;
 211     }
 212
 213     if (isprint(ch)) {
 214         wprintw(localwin, "%c", ch);
 215     } else {
 216         switch (ch) {
 217         case '\n':
 218             wprintw(localwin, "%c", ch);
 219             break;
 220         case '\r':
 221             /* If '\r' is put before '\n', the curses window will destroy the
 222              * last print line. And meanwhile, '\n' implifies '\r' inside. */
 223             break;
 224         default: /* Not handled, so just print it hex code */
 225             wprintw(localwin, "-- 0x%x --", ch);
 226         }
 227     }
 228
 229     wrefresh(localwin);
 230 }
 231 #else
 232 #define putc_on_screen(c)               do { } while (0)
 233 #endif
 234
 235 void helper_cp1_putc(target_ulong x)
 236 {
 237     putc_on_screen((unsigned char)x);   /* Output to screen */
 238     DPRINTF("%c", x);                   /* Output to stdout */
 239 }
 240 #endif
 241
 242 #ifdef CONFIG_USER_ONLY
 243 void switch_mode(CPUUniCore32State *env, int mode)
 244 {
 245     if (mode != ASR_MODE_USER) {
 246         cpu_abort(env, "Tried to switch out of user mode\n");
 247     }
 248 }
 249
 250 void do_interrupt(CPUUniCore32State *env)
 251 {
 252     cpu_abort(env, "NO interrupt in user mode\n");
 253 }
 254
 255 int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address,
 256                               int access_type, int mmu_idx)
 257 {
 258     cpu_abort(env, "NO mmu fault in user mode\n");
 259     return 1;
 260 }
 261 #endif