2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2009-2010 Aurelien Jarno <aurelien@aurel32.net>
5 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 * Register definitions
31 static const char * const tcg_target_reg_names
[TCG_TARGET_NB_REGS
] = {
32 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
33 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
34 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
35 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
36 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
37 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
38 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
39 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
43 #ifdef CONFIG_USE_GUEST_BASE
44 #define TCG_GUEST_BASE_REG TCG_REG_R55
46 #define TCG_GUEST_BASE_REG TCG_REG_R0
52 /* Branch registers */
64 /* Floating point registers */
84 /* Predicate registers */
104 /* Application registers */
109 static const int tcg_target_reg_alloc_order
[] = {
164 static const int tcg_target_call_iarg_regs
[8] = {
175 static const int tcg_target_call_oarg_regs
[2] = {
180 /* maximum number of register used for input function arguments */
181 static inline int tcg_target_get_call_iarg_regs_count(int flags
)
190 /* bundle templates: stops (double bar in the IA64 manual) are marked with
191 an uppercase letter. */
220 OPC_ADD_A1
= 0x10000000000ull
,
221 OPC_AND_A1
= 0x10060000000ull
,
222 OPC_AND_A3
= 0x10160000000ull
,
223 OPC_ANDCM_A1
= 0x10068000000ull
,
224 OPC_ANDCM_A3
= 0x10168000000ull
,
225 OPC_ADDS_A4
= 0x10800000000ull
,
226 OPC_ADDL_A5
= 0x12000000000ull
,
227 OPC_ALLOC_M34
= 0x02c00000000ull
,
228 OPC_BR_DPTK_FEW_B1
= 0x08400000000ull
,
229 OPC_BR_SPTK_MANY_B1
= 0x08000001000ull
,
230 OPC_BR_SPTK_MANY_B4
= 0x00100001000ull
,
231 OPC_BR_CALL_SPTK_MANY_B5
= 0x02100001000ull
,
232 OPC_BR_RET_SPTK_MANY_B4
= 0x00108001100ull
,
233 OPC_BRL_SPTK_MANY_X3
= 0x18000001000ull
,
234 OPC_CMP_LT_A6
= 0x18000000000ull
,
235 OPC_CMP_LTU_A6
= 0x1a000000000ull
,
236 OPC_CMP_EQ_A6
= 0x1c000000000ull
,
237 OPC_CMP4_LT_A6
= 0x18400000000ull
,
238 OPC_CMP4_LTU_A6
= 0x1a400000000ull
,
239 OPC_CMP4_EQ_A6
= 0x1c400000000ull
,
240 OPC_DEP_Z_I12
= 0x0a600000000ull
,
241 OPC_EXTR_I11
= 0x0a400002000ull
,
242 OPC_EXTR_U_I11
= 0x0a400000000ull
,
243 OPC_FCVT_FX_TRUNC_S1_F10
= 0x004d0000000ull
,
244 OPC_FCVT_FXU_TRUNC_S1_F10
= 0x004d8000000ull
,
245 OPC_FCVT_XF_F11
= 0x000e0000000ull
,
246 OPC_FMA_S1_F1
= 0x10400000000ull
,
247 OPC_FNMA_S1_F1
= 0x18400000000ull
,
248 OPC_FRCPA_S1_F6
= 0x00600000000ull
,
249 OPC_GETF_SIG_M19
= 0x08708000000ull
,
250 OPC_LD1_M1
= 0x08000000000ull
,
251 OPC_LD1_M3
= 0x0a000000000ull
,
252 OPC_LD2_M1
= 0x08040000000ull
,
253 OPC_LD2_M3
= 0x0a040000000ull
,
254 OPC_LD4_M1
= 0x08080000000ull
,
255 OPC_LD4_M3
= 0x0a080000000ull
,
256 OPC_LD8_M1
= 0x080c0000000ull
,
257 OPC_LD8_M3
= 0x0a0c0000000ull
,
258 OPC_MUX1_I3
= 0x0eca0000000ull
,
259 OPC_NOP_B9
= 0x04008000000ull
,
260 OPC_NOP_F16
= 0x00008000000ull
,
261 OPC_NOP_I18
= 0x00008000000ull
,
262 OPC_NOP_M48
= 0x00008000000ull
,
263 OPC_MOV_I21
= 0x00e00100000ull
,
264 OPC_MOV_RET_I21
= 0x00e00500000ull
,
265 OPC_MOV_I22
= 0x00188000000ull
,
266 OPC_MOV_I_I26
= 0x00150000000ull
,
267 OPC_MOVL_X2
= 0x0c000000000ull
,
268 OPC_OR_A1
= 0x10070000000ull
,
269 OPC_SETF_EXP_M18
= 0x0c748000000ull
,
270 OPC_SETF_SIG_M18
= 0x0c708000000ull
,
271 OPC_SHL_I7
= 0x0f240000000ull
,
272 OPC_SHR_I5
= 0x0f220000000ull
,
273 OPC_SHR_U_I5
= 0x0f200000000ull
,
274 OPC_SHRP_I10
= 0x0ac00000000ull
,
275 OPC_SXT1_I29
= 0x000a0000000ull
,
276 OPC_SXT2_I29
= 0x000a8000000ull
,
277 OPC_SXT4_I29
= 0x000b0000000ull
,
278 OPC_ST1_M4
= 0x08c00000000ull
,
279 OPC_ST2_M4
= 0x08c40000000ull
,
280 OPC_ST4_M4
= 0x08c80000000ull
,
281 OPC_ST8_M4
= 0x08cc0000000ull
,
282 OPC_SUB_A1
= 0x10028000000ull
,
283 OPC_SUB_A3
= 0x10128000000ull
,
284 OPC_UNPACK4_L_I2
= 0x0f860000000ull
,
285 OPC_XMA_L_F2
= 0x1d000000000ull
,
286 OPC_XOR_A1
= 0x10078000000ull
,
287 OPC_ZXT1_I29
= 0x00080000000ull
,
288 OPC_ZXT2_I29
= 0x00088000000ull
,
289 OPC_ZXT4_I29
= 0x00090000000ull
,
292 static inline uint64_t tcg_opc_a1(int qp
, uint64_t opc
, int r1
,
296 | ((r3
& 0x7f) << 20)
297 | ((r2
& 0x7f) << 13)
302 static inline uint64_t tcg_opc_a3(int qp
, uint64_t opc
, int r1
,
303 uint64_t imm
, int r3
)
306 | ((imm
& 0x80) << 29) /* s */
307 | ((imm
& 0x7f) << 13) /* imm7b */
308 | ((r3
& 0x7f) << 20)
313 static inline uint64_t tcg_opc_a4(int qp
, uint64_t opc
, int r1
,
314 uint64_t imm
, int r3
)
317 | ((imm
& 0x2000) << 23) /* s */
318 | ((imm
& 0x1f80) << 20) /* imm6d */
319 | ((imm
& 0x007f) << 13) /* imm7b */
320 | ((r3
& 0x7f) << 20)
325 static inline uint64_t tcg_opc_a5(int qp
, uint64_t opc
, int r1
,
326 uint64_t imm
, int r3
)
329 | ((imm
& 0x200000) << 15) /* s */
330 | ((imm
& 0x1f0000) << 6) /* imm5c */
331 | ((imm
& 0x00ff80) << 20) /* imm9d */
332 | ((imm
& 0x00007f) << 13) /* imm7b */
333 | ((r3
& 0x03) << 20)
338 static inline uint64_t tcg_opc_a6(int qp
, uint64_t opc
, int p1
,
339 int p2
, int r2
, int r3
)
342 | ((p2
& 0x3f) << 27)
343 | ((r3
& 0x7f) << 20)
344 | ((r2
& 0x7f) << 13)
349 static inline uint64_t tcg_opc_b1(int qp
, uint64_t opc
, uint64_t imm
)
352 | ((imm
& 0x100000) << 16) /* s */
353 | ((imm
& 0x0fffff) << 13) /* imm20b */
357 static inline uint64_t tcg_opc_b4(int qp
, uint64_t opc
, int b2
)
364 static inline uint64_t tcg_opc_b5(int qp
, uint64_t opc
, int b1
, int b2
)
373 static inline uint64_t tcg_opc_b9(int qp
, uint64_t opc
, uint64_t imm
)
376 | ((imm
& 0x100000) << 16) /* i */
377 | ((imm
& 0x0fffff) << 6) /* imm20a */
381 static inline uint64_t tcg_opc_f1(int qp
, uint64_t opc
, int f1
,
382 int f3
, int f4
, int f2
)
385 | ((f4
& 0x7f) << 27)
386 | ((f3
& 0x7f) << 20)
387 | ((f2
& 0x7f) << 13)
392 static inline uint64_t tcg_opc_f2(int qp
, uint64_t opc
, int f1
,
393 int f3
, int f4
, int f2
)
396 | ((f4
& 0x7f) << 27)
397 | ((f3
& 0x7f) << 20)
398 | ((f2
& 0x7f) << 13)
403 static inline uint64_t tcg_opc_f6(int qp
, uint64_t opc
, int f1
,
404 int p2
, int f2
, int f3
)
407 | ((p2
& 0x3f) << 27)
408 | ((f3
& 0x7f) << 20)
409 | ((f2
& 0x7f) << 13)
414 static inline uint64_t tcg_opc_f10(int qp
, uint64_t opc
, int f1
, int f2
)
417 | ((f2
& 0x7f) << 13)
422 static inline uint64_t tcg_opc_f11(int qp
, uint64_t opc
, int f1
, int f2
)
425 | ((f2
& 0x7f) << 13)
430 static inline uint64_t tcg_opc_f16(int qp
, uint64_t opc
, uint64_t imm
)
433 | ((imm
& 0x100000) << 16) /* i */
434 | ((imm
& 0x0fffff) << 6) /* imm20a */
438 static inline uint64_t tcg_opc_i2(int qp
, uint64_t opc
, int r1
,
442 | ((r3
& 0x7f) << 20)
443 | ((r2
& 0x7f) << 13)
448 static inline uint64_t tcg_opc_i3(int qp
, uint64_t opc
, int r1
,
452 | ((mbtype
& 0x0f) << 20)
453 | ((r2
& 0x7f) << 13)
458 static inline uint64_t tcg_opc_i5(int qp
, uint64_t opc
, int r1
,
462 | ((r3
& 0x7f) << 20)
463 | ((r2
& 0x7f) << 13)
468 static inline uint64_t tcg_opc_i7(int qp
, uint64_t opc
, int r1
,
472 | ((r3
& 0x7f) << 20)
473 | ((r2
& 0x7f) << 13)
478 static inline uint64_t tcg_opc_i10(int qp
, uint64_t opc
, int r1
,
479 int r2
, int r3
, uint64_t count
)
482 | ((count
& 0x3f) << 27)
483 | ((r3
& 0x7f) << 20)
484 | ((r2
& 0x7f) << 13)
489 static inline uint64_t tcg_opc_i11(int qp
, uint64_t opc
, int r1
,
490 int r3
, uint64_t pos
, uint64_t len
)
493 | ((len
& 0x3f) << 27)
494 | ((r3
& 0x7f) << 20)
495 | ((pos
& 0x3f) << 14)
500 static inline uint64_t tcg_opc_i12(int qp
, uint64_t opc
, int r1
,
501 int r2
, uint64_t pos
, uint64_t len
)
504 | ((len
& 0x3f) << 27)
505 | ((pos
& 0x3f) << 20)
506 | ((r2
& 0x7f) << 13)
511 static inline uint64_t tcg_opc_i18(int qp
, uint64_t opc
, uint64_t imm
)
514 | ((imm
& 0x100000) << 16) /* i */
515 | ((imm
& 0x0fffff) << 6) /* imm20a */
519 static inline uint64_t tcg_opc_i21(int qp
, uint64_t opc
, int b1
,
520 int r2
, uint64_t imm
)
523 | ((imm
& 0x1ff) << 24)
524 | ((r2
& 0x7f) << 13)
529 static inline uint64_t tcg_opc_i22(int qp
, uint64_t opc
, int r1
, int b2
)
537 static inline uint64_t tcg_opc_i26(int qp
, uint64_t opc
, int ar3
, int r2
)
540 | ((ar3
& 0x7f) << 20)
541 | ((r2
& 0x7f) << 13)
545 static inline uint64_t tcg_opc_i29(int qp
, uint64_t opc
, int r1
, int r3
)
548 | ((r3
& 0x7f) << 20)
553 static inline uint64_t tcg_opc_l2(uint64_t imm
)
555 return (imm
& 0x7fffffffffc00000ull
) >> 22;
558 static inline uint64_t tcg_opc_l3(uint64_t imm
)
560 return (imm
& 0x07fffffffff00000ull
) >> 18;
563 static inline uint64_t tcg_opc_m1(int qp
, uint64_t opc
, int r1
, int r3
)
566 | ((r3
& 0x7f) << 20)
571 static inline uint64_t tcg_opc_m3(int qp
, uint64_t opc
, int r1
,
572 int r3
, uint64_t imm
)
575 | ((imm
& 0x100) << 28) /* s */
576 | ((imm
& 0x080) << 20) /* i */
577 | ((imm
& 0x07f) << 13) /* imm7b */
578 | ((r3
& 0x7f) << 20)
583 static inline uint64_t tcg_opc_m4(int qp
, uint64_t opc
, int r2
, int r3
)
586 | ((r3
& 0x7f) << 20)
587 | ((r2
& 0x7f) << 13)
591 static inline uint64_t tcg_opc_m18(int qp
, uint64_t opc
, int f1
, int r2
)
594 | ((r2
& 0x7f) << 13)
599 static inline uint64_t tcg_opc_m19(int qp
, uint64_t opc
, int r1
, int f2
)
602 | ((f2
& 0x7f) << 13)
607 static inline uint64_t tcg_opc_m34(int qp
, uint64_t opc
, int r1
,
608 int sof
, int sol
, int sor
)
611 | ((sor
& 0x0f) << 27)
612 | ((sol
& 0x7f) << 20)
613 | ((sof
& 0x7f) << 13)
618 static inline uint64_t tcg_opc_m48(int qp
, uint64_t opc
, uint64_t imm
)
621 | ((imm
& 0x100000) << 16) /* i */
622 | ((imm
& 0x0fffff) << 6) /* imm20a */
626 static inline uint64_t tcg_opc_x2(int qp
, uint64_t opc
,
627 int r1
, uint64_t imm
)
630 | ((imm
& 0x8000000000000000ull
) >> 27) /* i */
631 | (imm
& 0x0000000000200000ull
) /* ic */
632 | ((imm
& 0x00000000001f0000ull
) << 6) /* imm5c */
633 | ((imm
& 0x000000000000ff80ull
) << 20) /* imm9d */
634 | ((imm
& 0x000000000000007full
) << 13) /* imm7b */
639 static inline uint64_t tcg_opc_x3(int qp
, uint64_t opc
, uint64_t imm
)
642 | ((imm
& 0x0800000000000000ull
) >> 23) /* i */
643 | ((imm
& 0x00000000000fffffull
) << 13) /* imm20b */
652 static inline void reloc_pcrel21b (void *pc
, tcg_target_long target
)
658 slot
= (tcg_target_long
) pc
& 3;
659 pc
= (void *)((tcg_target_long
) pc
& ~3);
661 disp
= target
- (tcg_target_long
) pc
;
662 imm
= (uint64_t) disp
>> 4;
666 *(uint64_t *)(pc
+ 0) = (*(uint64_t *)(pc
+ 8) & 0xfffffdc00003ffffull
)
667 | ((imm
& 0x100000) << 21) /* s */
668 | ((imm
& 0x0fffff) << 18); /* imm20b */
671 *(uint64_t *)(pc
+ 8) = (*(uint64_t *)(pc
+ 8) & 0xfffffffffffb8000ull
)
672 | ((imm
& 0x100000) >> 2) /* s */
673 | ((imm
& 0x0fffe0) >> 5); /* imm20b */
674 *(uint64_t *)(pc
+ 0) = (*(uint64_t *)(pc
+ 0) & 0x07ffffffffffffffull
)
675 | ((imm
& 0x00001f) << 59); /* imm20b */
678 *(uint64_t *)(pc
+ 8) = (*(uint64_t *)(pc
+ 8) & 0xf700000fffffffffull
)
679 | ((imm
& 0x100000) << 39) /* s */
680 | ((imm
& 0x0fffff) << 36); /* imm20b */
685 static inline uint64_t get_reloc_pcrel21b (void *pc
)
690 slot
= (tcg_target_long
) pc
& 3;
691 pc
= (void *)((tcg_target_long
) pc
& ~3);
693 low
= (*(uint64_t *)(pc
+ 0));
694 high
= (*(uint64_t *)(pc
+ 8));
698 return ((low
>> 21) & 0x100000) + /* s */
699 ((low
>> 18) & 0x0fffff); /* imm20b */
701 return ((high
<< 2) & 0x100000) + /* s */
702 ((high
<< 5) & 0x0fffe0) + /* imm20b */
703 ((low
>> 59) & 0x00001f); /* imm20b */
705 return ((high
>> 39) & 0x100000) + /* s */
706 ((high
>> 36) & 0x0fffff); /* imm20b */
712 static inline void reloc_pcrel60b (void *pc
, tcg_target_long target
)
717 disp
= target
- (tcg_target_long
) pc
;
718 imm
= (uint64_t) disp
>> 4;
720 *(uint64_t *)(pc
+ 8) = (*(uint64_t *)(pc
+ 8) & 0xf700000fff800000ull
)
721 | (imm
& 0x0800000000000000ull
) /* s */
722 | ((imm
& 0x07fffff000000000ull
) >> 36) /* imm39 */
723 | ((imm
& 0x00000000000fffffull
) << 36); /* imm20b */
724 *(uint64_t *)(pc
+ 0) = (*(uint64_t *)(pc
+ 0) & 0x00003fffffffffffull
)
725 | ((imm
& 0x0000000ffff00000ull
) << 28); /* imm39 */
728 static inline uint64_t get_reloc_pcrel60b (void *pc
)
732 low
= (*(uint64_t *)(pc
+ 0));
733 high
= (*(uint64_t *)(pc
+ 8));
735 return ((high
) & 0x0800000000000000ull
) + /* s */
736 ((high
>> 36) & 0x00000000000fffffull
) + /* imm20b */
737 ((high
<< 36) & 0x07fffff000000000ull
) + /* imm39 */
738 ((low
>> 28) & 0x0000000ffff00000ull
); /* imm39 */
742 static void patch_reloc(uint8_t *code_ptr
, int type
,
743 tcg_target_long value
, tcg_target_long addend
)
747 case R_IA64_PCREL21B
:
748 reloc_pcrel21b(code_ptr
, value
);
750 case R_IA64_PCREL60B
:
751 reloc_pcrel60b(code_ptr
, value
);
761 /* parse target specific constraints */
762 static int target_parse_constraint(TCGArgConstraint
*ct
, const char **pct_str
)
769 ct
->ct
|= TCG_CT_REG
;
770 tcg_regset_set(ct
->u
.regs
, 0xffffffffffffffffull
);
773 ct
->ct
|= TCG_CT_CONST_S22
;
776 ct
->ct
|= TCG_CT_REG
;
777 tcg_regset_set(ct
->u
.regs
, 0xffffffffffffffffull
);
778 #if defined(CONFIG_SOFTMMU)
779 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R56
);
780 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R57
);
784 /* We are cheating a bit here, using the fact that the register
785 r0 is also the register number 0. Hence there is no need
786 to check for const_args in each instruction. */
787 ct
->ct
|= TCG_CT_CONST_ZERO
;
797 /* test if a constant matches the constraint */
798 static inline int tcg_target_const_match(tcg_target_long val
,
799 const TCGArgConstraint
*arg_ct
)
803 if (ct
& TCG_CT_CONST
)
805 else if ((ct
& TCG_CT_CONST_ZERO
) && val
== 0)
807 else if ((ct
& TCG_CT_CONST_S22
) && val
== ((int32_t)val
<< 10) >> 10)
817 static uint8_t *tb_ret_addr
;
819 static inline void tcg_out_bundle(TCGContext
*s
, int template,
820 uint64_t slot0
, uint64_t slot1
,
823 template &= 0x1f; /* 5 bits */
824 slot0
&= 0x1ffffffffffull
; /* 41 bits */
825 slot1
&= 0x1ffffffffffull
; /* 41 bits */
826 slot2
&= 0x1ffffffffffull
; /* 41 bits */
828 *(uint64_t *)(s
->code_ptr
+ 0) = (slot1
<< 46) | (slot0
<< 5) | template;
829 *(uint64_t *)(s
->code_ptr
+ 8) = (slot2
<< 23) | (slot1
>> 18);
833 static inline void tcg_out_mov(TCGContext
*s
, TCGType type
,
834 TCGArg ret
, TCGArg arg
)
836 tcg_out_bundle(s
, mmI
,
837 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
838 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
839 tcg_opc_a4(TCG_REG_P0
, OPC_ADDS_A4
, ret
, 0, arg
));
842 static inline void tcg_out_movi(TCGContext
*s
, TCGType type
,
843 TCGArg reg
, tcg_target_long arg
)
845 tcg_out_bundle(s
, mLX
,
846 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
848 tcg_opc_x2 (TCG_REG_P0
, OPC_MOVL_X2
, reg
, arg
));
851 static inline void tcg_out_addi(TCGContext
*s
, TCGArg reg
, tcg_target_long val
)
853 if (val
== ((int32_t)val
<< 10) >> 10) {
854 tcg_out_bundle(s
, MmI
,
855 tcg_opc_a5(TCG_REG_P0
, OPC_ADDL_A5
,
856 TCG_REG_R2
, val
, TCG_REG_R0
),
857 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
858 tcg_opc_a1 (TCG_REG_P0
, OPC_ADD_A1
, reg
,
861 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_R2
, val
);
862 tcg_out_bundle(s
, mmI
,
863 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
864 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
865 tcg_opc_a1 (TCG_REG_P0
, OPC_ADD_A1
, reg
,
870 static void tcg_out_br(TCGContext
*s
, int label_index
)
872 TCGLabel
*l
= &s
->labels
[label_index
];
874 tcg_out_bundle(s
, mmB
,
875 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
876 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
877 tcg_opc_b1 (TCG_REG_P0
, OPC_BR_SPTK_MANY_B1
,
878 get_reloc_pcrel21b(s
->code_ptr
+ 2)));
881 reloc_pcrel21b((s
->code_ptr
- 16) + 2, l
->u
.value
);
883 tcg_out_reloc(s
, (s
->code_ptr
- 16) + 2,
884 R_IA64_PCREL21B
, label_index
, 0);
888 static inline void tcg_out_call(TCGContext
*s
, TCGArg addr
)
890 tcg_out_bundle(s
, MmI
,
891 tcg_opc_m1 (TCG_REG_P0
, OPC_LD8_M1
, TCG_REG_R2
, addr
),
892 tcg_opc_a4 (TCG_REG_P0
, OPC_ADDS_A4
, TCG_REG_R3
, 8, addr
),
893 tcg_opc_i21(TCG_REG_P0
, OPC_MOV_I21
,
894 TCG_REG_B6
, TCG_REG_R2
, 0));
895 tcg_out_bundle(s
, mmB
,
896 tcg_opc_m1 (TCG_REG_P0
, OPC_LD8_M1
, TCG_REG_R1
, TCG_REG_R3
),
897 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
898 tcg_opc_b5 (TCG_REG_P0
, OPC_BR_CALL_SPTK_MANY_B5
,
899 TCG_REG_B0
, TCG_REG_B6
));
902 static void tcg_out_exit_tb(TCGContext
*s
, tcg_target_long arg
)
907 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_R8
, arg
);
909 disp
= tb_ret_addr
- s
->code_ptr
;
910 imm
= (uint64_t)disp
>> 4;
912 tcg_out_bundle(s
, mLX
,
913 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
915 tcg_opc_x3 (TCG_REG_P0
, OPC_BRL_SPTK_MANY_X3
, imm
));
918 static inline void tcg_out_goto_tb(TCGContext
*s
, TCGArg arg
)
920 if (s
->tb_jmp_offset
) {
921 /* direct jump method */
924 /* indirect jump method */
925 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_R2
,
926 (tcg_target_long
)(s
->tb_next
+ arg
));
927 tcg_out_bundle(s
, MmI
,
928 tcg_opc_m1 (TCG_REG_P0
, OPC_LD8_M1
,
929 TCG_REG_R2
, TCG_REG_R2
),
930 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
931 tcg_opc_i21(TCG_REG_P0
, OPC_MOV_I21
, TCG_REG_B6
,
933 tcg_out_bundle(s
, mmB
,
934 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
935 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
936 tcg_opc_b4 (TCG_REG_P0
, OPC_BR_SPTK_MANY_B4
,
939 s
->tb_next_offset
[arg
] = s
->code_ptr
- s
->code_buf
;
942 static inline void tcg_out_jmp(TCGContext
*s
, TCGArg addr
)
944 tcg_out_bundle(s
, mmI
,
945 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
946 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
947 tcg_opc_i21(TCG_REG_P0
, OPC_MOV_I21
, TCG_REG_B6
, addr
, 0));
948 tcg_out_bundle(s
, mmB
,
949 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
950 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
951 tcg_opc_b4(TCG_REG_P0
, OPC_BR_SPTK_MANY_B4
, TCG_REG_B6
));
954 static inline void tcg_out_ld_rel(TCGContext
*s
, uint64_t opc_m4
, TCGArg arg
,
955 TCGArg arg1
, tcg_target_long arg2
)
957 if (arg2
== ((int16_t)arg2
>> 2) << 2) {
958 tcg_out_bundle(s
, MmI
,
959 tcg_opc_a4(TCG_REG_P0
, OPC_ADDS_A4
,
960 TCG_REG_R2
, arg2
, arg1
),
961 tcg_opc_m1 (TCG_REG_P0
, opc_m4
, arg
, TCG_REG_R2
),
962 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0));
964 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_R2
, arg2
);
965 tcg_out_bundle(s
, MmI
,
966 tcg_opc_a1 (TCG_REG_P0
, OPC_ADD_A1
,
967 TCG_REG_R2
, TCG_REG_R2
, arg1
),
968 tcg_opc_m1 (TCG_REG_P0
, opc_m4
, arg
, TCG_REG_R2
),
969 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0));
973 static inline void tcg_out_st_rel(TCGContext
*s
, uint64_t opc_m4
, TCGArg arg
,
974 TCGArg arg1
, tcg_target_long arg2
)
976 if (arg2
== ((int16_t)arg2
>> 2) << 2) {
977 tcg_out_bundle(s
, MmI
,
978 tcg_opc_a4(TCG_REG_P0
, OPC_ADDS_A4
,
979 TCG_REG_R2
, arg2
, arg1
),
980 tcg_opc_m4 (TCG_REG_P0
, opc_m4
, arg
, TCG_REG_R2
),
981 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0));
983 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_R2
, arg2
);
984 tcg_out_bundle(s
, MmI
,
985 tcg_opc_a1 (TCG_REG_P0
, OPC_ADD_A1
,
986 TCG_REG_R2
, TCG_REG_R2
, arg1
),
987 tcg_opc_m4 (TCG_REG_P0
, opc_m4
, arg
, TCG_REG_R2
),
988 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0));
992 static inline void tcg_out_ld(TCGContext
*s
, TCGType type
, TCGArg arg
,
993 TCGArg arg1
, tcg_target_long arg2
)
995 if (type
== TCG_TYPE_I32
) {
996 tcg_out_ld_rel(s
, OPC_LD4_M1
, arg
, arg1
, arg2
);
998 tcg_out_ld_rel(s
, OPC_LD8_M1
, arg
, arg1
, arg2
);
1002 static inline void tcg_out_st(TCGContext
*s
, TCGType type
, TCGArg arg
,
1003 TCGArg arg1
, tcg_target_long arg2
)
1005 if (type
== TCG_TYPE_I32
) {
1006 tcg_out_st_rel(s
, OPC_ST4_M4
, arg
, arg1
, arg2
);
1008 tcg_out_st_rel(s
, OPC_ST8_M4
, arg
, arg1
, arg2
);
1012 static inline void tcg_out_alu(TCGContext
*s
, uint64_t opc_a1
, TCGArg ret
,
1013 TCGArg arg1
, int const_arg1
,
1014 TCGArg arg2
, int const_arg2
)
1016 uint64_t opc1
, opc2
;
1018 if (const_arg1
&& arg1
!= 0) {
1019 opc1
= tcg_opc_a5(TCG_REG_P0
, OPC_ADDL_A5
,
1020 TCG_REG_R2
, arg1
, TCG_REG_R0
);
1023 opc1
= tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0);
1026 if (const_arg2
&& arg2
!= 0) {
1027 opc2
= tcg_opc_a5(TCG_REG_P0
, OPC_ADDL_A5
,
1028 TCG_REG_R3
, arg2
, TCG_REG_R0
);
1031 opc2
= tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0);
1034 tcg_out_bundle(s
, mII
,
1037 tcg_opc_a1(TCG_REG_P0
, opc_a1
, ret
, arg1
, arg2
));
1040 static inline void tcg_out_eqv(TCGContext
*s
, TCGArg ret
,
1041 TCGArg arg1
, int const_arg1
,
1042 TCGArg arg2
, int const_arg2
)
1044 tcg_out_bundle(s
, mII
,
1045 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1046 tcg_opc_a1 (TCG_REG_P0
, OPC_XOR_A1
, ret
, arg1
, arg2
),
1047 tcg_opc_a3 (TCG_REG_P0
, OPC_ANDCM_A3
, ret
, -1, ret
));
1050 static inline void tcg_out_nand(TCGContext
*s
, TCGArg ret
,
1051 TCGArg arg1
, int const_arg1
,
1052 TCGArg arg2
, int const_arg2
)
1054 tcg_out_bundle(s
, mII
,
1055 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1056 tcg_opc_a1 (TCG_REG_P0
, OPC_AND_A1
, ret
, arg1
, arg2
),
1057 tcg_opc_a3 (TCG_REG_P0
, OPC_ANDCM_A3
, ret
, -1, ret
));
1060 static inline void tcg_out_nor(TCGContext
*s
, TCGArg ret
,
1061 TCGArg arg1
, int const_arg1
,
1062 TCGArg arg2
, int const_arg2
)
1064 tcg_out_bundle(s
, mII
,
1065 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1066 tcg_opc_a1 (TCG_REG_P0
, OPC_OR_A1
, ret
, arg1
, arg2
),
1067 tcg_opc_a3 (TCG_REG_P0
, OPC_ANDCM_A3
, ret
, -1, ret
));
1070 static inline void tcg_out_orc(TCGContext
*s
, TCGArg ret
,
1071 TCGArg arg1
, int const_arg1
,
1072 TCGArg arg2
, int const_arg2
)
1074 tcg_out_bundle(s
, mII
,
1075 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1076 tcg_opc_a3 (TCG_REG_P0
, OPC_ANDCM_A3
, TCG_REG_R2
, -1, arg2
),
1077 tcg_opc_a1 (TCG_REG_P0
, OPC_OR_A1
, ret
, arg1
, TCG_REG_R2
));
1080 static inline void tcg_out_mul(TCGContext
*s
, TCGArg ret
,
1081 TCGArg arg1
, TCGArg arg2
)
1083 tcg_out_bundle(s
, mmI
,
1084 tcg_opc_m18(TCG_REG_P0
, OPC_SETF_SIG_M18
, TCG_REG_F6
, arg1
),
1085 tcg_opc_m18(TCG_REG_P0
, OPC_SETF_SIG_M18
, TCG_REG_F7
, arg2
),
1086 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0));
1087 tcg_out_bundle(s
, mmF
,
1088 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1089 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1090 tcg_opc_f2 (TCG_REG_P0
, OPC_XMA_L_F2
, TCG_REG_F6
, TCG_REG_F6
,
1091 TCG_REG_F7
, TCG_REG_F0
));
1092 tcg_out_bundle(s
, miI
,
1093 tcg_opc_m19(TCG_REG_P0
, OPC_GETF_SIG_M19
, ret
, TCG_REG_F6
),
1094 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1095 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0));
1098 static inline void tcg_out_sar_i32(TCGContext
*s
, TCGArg ret
, TCGArg arg1
,
1099 TCGArg arg2
, int const_arg2
)
1102 tcg_out_bundle(s
, miI
,
1103 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1104 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1105 tcg_opc_i11(TCG_REG_P0
, OPC_EXTR_I11
,
1106 ret
, arg1
, arg2
, 31 - arg2
));
1108 tcg_out_bundle(s
, mII
,
1109 tcg_opc_a3 (TCG_REG_P0
, OPC_AND_A3
,
1110 TCG_REG_R3
, 0x1f, arg2
),
1111 tcg_opc_i29(TCG_REG_P0
, OPC_SXT4_I29
, TCG_REG_R2
, arg1
),
1112 tcg_opc_i5 (TCG_REG_P0
, OPC_SHR_I5
, ret
,
1113 TCG_REG_R2
, TCG_REG_R3
));
1117 static inline void tcg_out_sar_i64(TCGContext
*s
, TCGArg ret
, TCGArg arg1
,
1118 TCGArg arg2
, int const_arg2
)
1121 tcg_out_bundle(s
, miI
,
1122 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1123 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1124 tcg_opc_i11(TCG_REG_P0
, OPC_EXTR_I11
,
1125 ret
, arg1
, arg2
, 63 - arg2
));
1127 tcg_out_bundle(s
, miI
,
1128 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1129 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1130 tcg_opc_i5 (TCG_REG_P0
, OPC_SHR_I5
, ret
, arg1
, arg2
));
1134 static inline void tcg_out_shl_i32(TCGContext
*s
, TCGArg ret
, TCGArg arg1
,
1135 TCGArg arg2
, int const_arg2
)
1138 tcg_out_bundle(s
, miI
,
1139 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1140 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1141 tcg_opc_i12(TCG_REG_P0
, OPC_DEP_Z_I12
, ret
,
1142 arg1
, 63 - arg2
, 31 - arg2
));
1144 tcg_out_bundle(s
, mII
,
1145 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1146 tcg_opc_a3 (TCG_REG_P0
, OPC_AND_A3
, TCG_REG_R2
,
1148 tcg_opc_i7 (TCG_REG_P0
, OPC_SHL_I7
, ret
,
1153 static inline void tcg_out_shl_i64(TCGContext
*s
, TCGArg ret
, TCGArg arg1
,
1154 TCGArg arg2
, int const_arg2
)
1157 tcg_out_bundle(s
, miI
,
1158 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1159 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1160 tcg_opc_i12(TCG_REG_P0
, OPC_DEP_Z_I12
, ret
,
1161 arg1
, 63 - arg2
, 63 - arg2
));
1163 tcg_out_bundle(s
, miI
,
1164 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1165 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1166 tcg_opc_i7 (TCG_REG_P0
, OPC_SHL_I7
, ret
,
1171 static inline void tcg_out_shr_i32(TCGContext
*s
, TCGArg ret
, TCGArg arg1
,
1172 TCGArg arg2
, int const_arg2
)
1175 tcg_out_bundle(s
, miI
,
1176 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1177 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1178 tcg_opc_i11(TCG_REG_P0
, OPC_EXTR_U_I11
, ret
,
1179 arg1
, arg2
, 31 - arg2
));
1181 tcg_out_bundle(s
, mII
,
1182 tcg_opc_a3 (TCG_REG_P0
, OPC_AND_A3
, TCG_REG_R3
,
1184 tcg_opc_i29(TCG_REG_P0
, OPC_ZXT4_I29
, TCG_REG_R2
, arg1
),
1185 tcg_opc_i5 (TCG_REG_P0
, OPC_SHR_U_I5
, ret
,
1186 TCG_REG_R2
, TCG_REG_R3
));
1190 static inline void tcg_out_shr_i64(TCGContext
*s
, TCGArg ret
, TCGArg arg1
,
1191 TCGArg arg2
, int const_arg2
)
1194 tcg_out_bundle(s
, miI
,
1195 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1196 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1197 tcg_opc_i11(TCG_REG_P0
, OPC_EXTR_U_I11
, ret
,
1198 arg1
, arg2
, 63 - arg2
));
1200 tcg_out_bundle(s
, miI
,
1201 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1202 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1203 tcg_opc_i5 (TCG_REG_P0
, OPC_SHR_U_I5
, ret
,
1208 static inline void tcg_out_rotl_i32(TCGContext
*s
, TCGArg ret
, TCGArg arg1
,
1209 TCGArg arg2
, int const_arg2
)
1212 tcg_out_bundle(s
, mII
,
1213 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1214 tcg_opc_i2 (TCG_REG_P0
, OPC_UNPACK4_L_I2
,
1215 TCG_REG_R2
, arg1
, arg1
),
1216 tcg_opc_i11(TCG_REG_P0
, OPC_EXTR_U_I11
, ret
,
1217 TCG_REG_R2
, 32 - arg2
, 31));
1219 tcg_out_bundle(s
, miI
,
1220 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1221 tcg_opc_i2 (TCG_REG_P0
, OPC_UNPACK4_L_I2
,
1222 TCG_REG_R2
, arg1
, arg1
),
1223 tcg_opc_a3 (TCG_REG_P0
, OPC_AND_A3
, TCG_REG_R3
,
1225 tcg_out_bundle(s
, mII
,
1226 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1227 tcg_opc_a3 (TCG_REG_P0
, OPC_SUB_A3
, TCG_REG_R3
,
1229 tcg_opc_i5 (TCG_REG_P0
, OPC_SHR_U_I5
, ret
,
1230 TCG_REG_R2
, TCG_REG_R3
));
1234 static inline void tcg_out_rotl_i64(TCGContext
*s
, TCGArg ret
, TCGArg arg1
,
1235 TCGArg arg2
, int const_arg2
)
1238 tcg_out_bundle(s
, miI
,
1239 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1240 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1241 tcg_opc_i10(TCG_REG_P0
, OPC_SHRP_I10
, ret
, arg1
,
1242 arg1
, 0x40 - arg2
));
1244 tcg_out_bundle(s
, mII
,
1245 tcg_opc_a3 (TCG_REG_P0
, OPC_SUB_A3
, TCG_REG_R2
,
1247 tcg_opc_i7 (TCG_REG_P0
, OPC_SHL_I7
, TCG_REG_R3
,
1249 tcg_opc_i5 (TCG_REG_P0
, OPC_SHR_U_I5
, TCG_REG_R2
,
1251 tcg_out_bundle(s
, miI
,
1252 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1253 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1254 tcg_opc_a1 (TCG_REG_P0
, OPC_OR_A1
, ret
,
1255 TCG_REG_R2
, TCG_REG_R3
));
1259 static inline void tcg_out_rotr_i32(TCGContext
*s
, TCGArg ret
, TCGArg arg1
,
1260 TCGArg arg2
, int const_arg2
)
1263 tcg_out_bundle(s
, mII
,
1264 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1265 tcg_opc_i2 (TCG_REG_P0
, OPC_UNPACK4_L_I2
,
1266 TCG_REG_R2
, arg1
, arg1
),
1267 tcg_opc_i11(TCG_REG_P0
, OPC_EXTR_U_I11
, ret
,
1268 TCG_REG_R2
, arg2
, 31));
1270 tcg_out_bundle(s
, mII
,
1271 tcg_opc_a3 (TCG_REG_P0
, OPC_AND_A3
, TCG_REG_R3
,
1273 tcg_opc_i2 (TCG_REG_P0
, OPC_UNPACK4_L_I2
,
1274 TCG_REG_R2
, arg1
, arg1
),
1275 tcg_opc_i5 (TCG_REG_P0
, OPC_SHR_U_I5
, ret
,
1276 TCG_REG_R2
, TCG_REG_R3
));
1280 static inline void tcg_out_rotr_i64(TCGContext
*s
, TCGArg ret
, TCGArg arg1
,
1281 TCGArg arg2
, int const_arg2
)
1284 tcg_out_bundle(s
, miI
,
1285 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1286 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1287 tcg_opc_i10(TCG_REG_P0
, OPC_SHRP_I10
, ret
, arg1
,
1290 tcg_out_bundle(s
, mII
,
1291 tcg_opc_a3 (TCG_REG_P0
, OPC_SUB_A3
, TCG_REG_R2
,
1293 tcg_opc_i5 (TCG_REG_P0
, OPC_SHR_U_I5
, TCG_REG_R3
,
1295 tcg_opc_i7 (TCG_REG_P0
, OPC_SHL_I7
, TCG_REG_R2
,
1297 tcg_out_bundle(s
, miI
,
1298 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1299 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1300 tcg_opc_a1 (TCG_REG_P0
, OPC_OR_A1
, ret
,
1301 TCG_REG_R2
, TCG_REG_R3
));
1305 static inline void tcg_out_ext(TCGContext
*s
, uint64_t opc_i29
,
1306 TCGArg ret
, TCGArg arg
)
1308 tcg_out_bundle(s
, miI
,
1309 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1310 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1311 tcg_opc_i29(TCG_REG_P0
, opc_i29
, ret
, arg
));
1314 static inline void tcg_out_bswap16(TCGContext
*s
, TCGArg ret
, TCGArg arg
)
1316 tcg_out_bundle(s
, mII
,
1317 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1318 tcg_opc_i12(TCG_REG_P0
, OPC_DEP_Z_I12
, ret
, arg
, 15, 15),
1319 tcg_opc_i3 (TCG_REG_P0
, OPC_MUX1_I3
, ret
, ret
, 0xb));
1322 static inline void tcg_out_bswap32(TCGContext
*s
, TCGArg ret
, TCGArg arg
)
1324 tcg_out_bundle(s
, mII
,
1325 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1326 tcg_opc_i12(TCG_REG_P0
, OPC_DEP_Z_I12
, ret
, arg
, 31, 31),
1327 tcg_opc_i3 (TCG_REG_P0
, OPC_MUX1_I3
, ret
, ret
, 0xb));
1330 static inline void tcg_out_bswap64(TCGContext
*s
, TCGArg ret
, TCGArg arg
)
1332 tcg_out_bundle(s
, mII
,
1333 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1334 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1335 tcg_opc_i3 (TCG_REG_P0
, OPC_MUX1_I3
, ret
, arg
, 0xb));
1338 static inline uint64_t tcg_opc_cmp_a(int qp
, TCGCond cond
, TCGArg arg1
,
1339 TCGArg arg2
, int cmp4
)
1341 uint64_t opc_eq_a6
, opc_lt_a6
, opc_ltu_a6
;
1344 opc_eq_a6
= OPC_CMP4_EQ_A6
;
1345 opc_lt_a6
= OPC_CMP4_LT_A6
;
1346 opc_ltu_a6
= OPC_CMP4_LTU_A6
;
1348 opc_eq_a6
= OPC_CMP_EQ_A6
;
1349 opc_lt_a6
= OPC_CMP_LT_A6
;
1350 opc_ltu_a6
= OPC_CMP_LTU_A6
;
1355 return tcg_opc_a6 (qp
, opc_eq_a6
, TCG_REG_P6
, TCG_REG_P7
, arg1
, arg2
);
1357 return tcg_opc_a6 (qp
, opc_eq_a6
, TCG_REG_P7
, TCG_REG_P6
, arg1
, arg2
);
1359 return tcg_opc_a6 (qp
, opc_lt_a6
, TCG_REG_P6
, TCG_REG_P7
, arg1
, arg2
);
1361 return tcg_opc_a6 (qp
, opc_ltu_a6
, TCG_REG_P6
, TCG_REG_P7
, arg1
, arg2
);
1363 return tcg_opc_a6 (qp
, opc_lt_a6
, TCG_REG_P7
, TCG_REG_P6
, arg1
, arg2
);
1365 return tcg_opc_a6 (qp
, opc_ltu_a6
, TCG_REG_P7
, TCG_REG_P6
, arg1
, arg2
);
1367 return tcg_opc_a6 (qp
, opc_lt_a6
, TCG_REG_P7
, TCG_REG_P6
, arg2
, arg1
);
1369 return tcg_opc_a6 (qp
, opc_ltu_a6
, TCG_REG_P7
, TCG_REG_P6
, arg2
, arg1
);
1371 return tcg_opc_a6 (qp
, opc_lt_a6
, TCG_REG_P6
, TCG_REG_P7
, arg2
, arg1
);
1373 return tcg_opc_a6 (qp
, opc_ltu_a6
, TCG_REG_P6
, TCG_REG_P7
, arg2
, arg1
);
1380 static inline void tcg_out_brcond(TCGContext
*s
, TCGCond cond
, TCGArg arg1
,
1381 int const_arg1
, TCGArg arg2
, int const_arg2
,
1382 int label_index
, int cmp4
)
1384 TCGLabel
*l
= &s
->labels
[label_index
];
1385 uint64_t opc1
, opc2
;
1387 if (const_arg1
&& arg1
!= 0) {
1388 opc1
= tcg_opc_a5(TCG_REG_P0
, OPC_ADDL_A5
, TCG_REG_R2
,
1392 opc1
= tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0);
1395 if (const_arg2
&& arg2
!= 0) {
1396 opc2
= tcg_opc_a5(TCG_REG_P0
, OPC_ADDL_A5
, TCG_REG_R3
,
1400 opc2
= tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0);
1403 tcg_out_bundle(s
, mII
,
1406 tcg_opc_cmp_a(TCG_REG_P0
, cond
, arg1
, arg2
, cmp4
));
1407 tcg_out_bundle(s
, mmB
,
1408 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1409 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1410 tcg_opc_b1 (TCG_REG_P6
, OPC_BR_DPTK_FEW_B1
,
1411 get_reloc_pcrel21b(s
->code_ptr
+ 2)));
1414 reloc_pcrel21b((s
->code_ptr
- 16) + 2, l
->u
.value
);
1416 tcg_out_reloc(s
, (s
->code_ptr
- 16) + 2,
1417 R_IA64_PCREL21B
, label_index
, 0);
1421 static inline void tcg_out_setcond(TCGContext
*s
, TCGCond cond
, TCGArg ret
,
1422 TCGArg arg1
, TCGArg arg2
, int cmp4
)
1424 tcg_out_bundle(s
, MmI
,
1425 tcg_opc_cmp_a(TCG_REG_P0
, cond
, arg1
, arg2
, cmp4
),
1426 tcg_opc_a5(TCG_REG_P6
, OPC_ADDL_A5
, ret
, 1, TCG_REG_R0
),
1427 tcg_opc_a5(TCG_REG_P7
, OPC_ADDL_A5
, ret
, 0, TCG_REG_R0
));
1430 #if defined(CONFIG_SOFTMMU)
1432 #include "../../softmmu_defs.h"
1434 /* Load and compare a TLB entry, and return the result in (p6, p7).
1435 R2 is loaded with the address of the addend TLB entry.
1436 R56 is loaded with the address, zero extented on 32-bit targets. */
1437 static inline void tcg_out_qemu_tlb(TCGContext
*s
, TCGArg addr_reg
,
1438 int s_bits
, uint64_t offset_rw
,
1439 uint64_t offset_addend
)
1441 tcg_out_bundle(s
, mII
,
1442 tcg_opc_a5 (TCG_REG_P0
, OPC_ADDL_A5
, TCG_REG_R3
,
1443 TARGET_PAGE_MASK
| ((1 << s_bits
) - 1),
1445 tcg_opc_i11(TCG_REG_P0
, OPC_EXTR_U_I11
, TCG_REG_R2
,
1446 addr_reg
, TARGET_PAGE_BITS
, CPU_TLB_BITS
- 1),
1447 tcg_opc_i12(TCG_REG_P0
, OPC_DEP_Z_I12
, TCG_REG_R2
,
1448 TCG_REG_R2
, 63 - CPU_TLB_ENTRY_BITS
,
1449 63 - CPU_TLB_ENTRY_BITS
));
1450 tcg_out_bundle(s
, mII
,
1451 tcg_opc_a5 (TCG_REG_P0
, OPC_ADDL_A5
, TCG_REG_R2
,
1452 offset_rw
, TCG_REG_R2
),
1453 #if TARGET_LONG_BITS == 32
1454 tcg_opc_i29(TCG_REG_P0
, OPC_ZXT4_I29
, TCG_REG_R56
, addr_reg
),
1456 tcg_opc_a4(TCG_REG_P0
, OPC_ADDS_A4
, TCG_REG_R56
,
1459 tcg_opc_a1 (TCG_REG_P0
, OPC_ADD_A1
, TCG_REG_R2
,
1460 TCG_REG_R2
, TCG_AREG0
));
1461 tcg_out_bundle(s
, mII
,
1462 tcg_opc_m3 (TCG_REG_P0
,
1463 (TARGET_LONG_BITS
== 32
1464 ? OPC_LD4_M3
: OPC_LD8_M3
), TCG_REG_R57
,
1465 TCG_REG_R2
, offset_addend
- offset_rw
),
1466 tcg_opc_a1 (TCG_REG_P0
, OPC_AND_A1
, TCG_REG_R3
,
1467 TCG_REG_R3
, TCG_REG_R56
),
1468 tcg_opc_a6 (TCG_REG_P0
, OPC_CMP_EQ_A6
, TCG_REG_P6
,
1469 TCG_REG_P7
, TCG_REG_R3
, TCG_REG_R57
));
1472 static void *qemu_ld_helpers
[4] = {
1479 static inline void tcg_out_qemu_ld(TCGContext
*s
, const TCGArg
*args
, int opc
)
1481 int addr_reg
, data_reg
, mem_index
, s_bits
, bswap
;
1482 uint64_t opc_ld_m1
[4] = { OPC_LD1_M1
, OPC_LD2_M1
, OPC_LD4_M1
, OPC_LD8_M1
};
1483 uint64_t opc_ext_i29
[8] = { OPC_ZXT1_I29
, OPC_ZXT2_I29
, OPC_ZXT4_I29
, 0,
1484 OPC_SXT1_I29
, OPC_SXT2_I29
, OPC_SXT4_I29
, 0 };
1491 #ifdef TARGET_WORDS_BIGENDIAN
1497 /* Read the TLB entry */
1498 tcg_out_qemu_tlb(s
, addr_reg
, s_bits
,
1499 offsetof(CPUState
, tlb_table
[mem_index
][0].addr_read
),
1500 offsetof(CPUState
, tlb_table
[mem_index
][0].addend
));
1502 /* P6 is the fast path, and P7 the slow path */
1503 tcg_out_bundle(s
, mLX
,
1504 tcg_opc_a5 (TCG_REG_P7
, OPC_ADDL_A5
, TCG_REG_R57
,
1505 mem_index
, TCG_REG_R0
),
1506 tcg_opc_l2 ((tcg_target_long
) qemu_ld_helpers
[s_bits
]),
1507 tcg_opc_x2 (TCG_REG_P7
, OPC_MOVL_X2
, TCG_REG_R2
,
1508 (tcg_target_long
) qemu_ld_helpers
[s_bits
]));
1509 tcg_out_bundle(s
, MmI
,
1510 tcg_opc_m3 (TCG_REG_P0
, OPC_LD8_M3
, TCG_REG_R3
,
1512 tcg_opc_a1 (TCG_REG_P6
, OPC_ADD_A1
, TCG_REG_R3
,
1513 TCG_REG_R3
, TCG_REG_R56
),
1514 tcg_opc_i21(TCG_REG_P7
, OPC_MOV_I21
, TCG_REG_B6
,
1516 if (bswap
&& s_bits
== 1) {
1517 tcg_out_bundle(s
, MmI
,
1518 tcg_opc_m1 (TCG_REG_P6
, opc_ld_m1
[s_bits
],
1519 TCG_REG_R8
, TCG_REG_R3
),
1520 tcg_opc_m1 (TCG_REG_P7
, OPC_LD8_M1
, TCG_REG_R1
, TCG_REG_R2
),
1521 tcg_opc_i12(TCG_REG_P6
, OPC_DEP_Z_I12
,
1522 TCG_REG_R8
, TCG_REG_R8
, 15, 15));
1523 } else if (bswap
&& s_bits
== 2) {
1524 tcg_out_bundle(s
, MmI
,
1525 tcg_opc_m1 (TCG_REG_P6
, opc_ld_m1
[s_bits
],
1526 TCG_REG_R8
, TCG_REG_R3
),
1527 tcg_opc_m1 (TCG_REG_P7
, OPC_LD8_M1
, TCG_REG_R1
, TCG_REG_R2
),
1528 tcg_opc_i12(TCG_REG_P6
, OPC_DEP_Z_I12
,
1529 TCG_REG_R8
, TCG_REG_R8
, 31, 31));
1531 tcg_out_bundle(s
, mmI
,
1532 tcg_opc_m1 (TCG_REG_P6
, opc_ld_m1
[s_bits
],
1533 TCG_REG_R8
, TCG_REG_R3
),
1534 tcg_opc_m1 (TCG_REG_P7
, OPC_LD8_M1
, TCG_REG_R1
, TCG_REG_R2
),
1535 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0));
1537 if (!bswap
|| s_bits
== 0) {
1538 tcg_out_bundle(s
, miB
,
1539 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1540 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1541 tcg_opc_b5 (TCG_REG_P7
, OPC_BR_CALL_SPTK_MANY_B5
,
1542 TCG_REG_B0
, TCG_REG_B6
));
1544 tcg_out_bundle(s
, miB
,
1545 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1546 tcg_opc_i3 (TCG_REG_P6
, OPC_MUX1_I3
,
1547 TCG_REG_R8
, TCG_REG_R8
, 0xb),
1548 tcg_opc_b5 (TCG_REG_P7
, OPC_BR_CALL_SPTK_MANY_B5
,
1549 TCG_REG_B0
, TCG_REG_B6
));
1553 tcg_out_bundle(s
, miI
,
1554 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1555 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1556 tcg_opc_a4 (TCG_REG_P0
, OPC_ADDS_A4
,
1557 data_reg
, 0, TCG_REG_R8
));
1559 tcg_out_bundle(s
, miI
,
1560 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1561 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1562 tcg_opc_i29(TCG_REG_P0
, opc_ext_i29
[opc
],
1563 data_reg
, TCG_REG_R8
));
1567 static void *qemu_st_helpers
[4] = {
1574 static inline void tcg_out_qemu_st(TCGContext
*s
, const TCGArg
*args
, int opc
)
1576 int addr_reg
, data_reg
, mem_index
, bswap
;
1577 uint64_t opc_st_m4
[4] = { OPC_ST1_M4
, OPC_ST2_M4
, OPC_ST4_M4
, OPC_ST8_M4
};
1583 #ifdef TARGET_WORDS_BIGENDIAN
1589 tcg_out_qemu_tlb(s
, addr_reg
, opc
,
1590 offsetof(CPUState
, tlb_table
[mem_index
][0].addr_write
),
1591 offsetof(CPUState
, tlb_table
[mem_index
][0].addend
));
1593 /* P6 is the fast path, and P7 the slow path */
1594 tcg_out_bundle(s
, mLX
,
1595 tcg_opc_a4(TCG_REG_P7
, OPC_ADDS_A4
, TCG_REG_R57
,
1597 tcg_opc_l2 ((tcg_target_long
) qemu_st_helpers
[opc
]),
1598 tcg_opc_x2 (TCG_REG_P7
, OPC_MOVL_X2
, TCG_REG_R2
,
1599 (tcg_target_long
) qemu_st_helpers
[opc
]));
1600 tcg_out_bundle(s
, MmI
,
1601 tcg_opc_m3 (TCG_REG_P0
, OPC_LD8_M3
, TCG_REG_R3
,
1603 tcg_opc_a1 (TCG_REG_P6
, OPC_ADD_A1
, TCG_REG_R3
,
1604 TCG_REG_R3
, TCG_REG_R56
),
1605 tcg_opc_i21(TCG_REG_P7
, OPC_MOV_I21
, TCG_REG_B6
,
1608 if (!bswap
|| opc
== 0) {
1609 tcg_out_bundle(s
, mII
,
1610 tcg_opc_m1 (TCG_REG_P7
, OPC_LD8_M1
,
1611 TCG_REG_R1
, TCG_REG_R2
),
1612 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1613 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0));
1614 } else if (opc
== 1) {
1615 tcg_out_bundle(s
, mII
,
1616 tcg_opc_m1 (TCG_REG_P7
, OPC_LD8_M1
,
1617 TCG_REG_R1
, TCG_REG_R2
),
1618 tcg_opc_i12(TCG_REG_P6
, OPC_DEP_Z_I12
,
1619 TCG_REG_R2
, data_reg
, 15, 15),
1620 tcg_opc_i3 (TCG_REG_P6
, OPC_MUX1_I3
,
1621 TCG_REG_R2
, TCG_REG_R2
, 0xb));
1622 data_reg
= TCG_REG_R2
;
1623 } else if (opc
== 2) {
1624 tcg_out_bundle(s
, mII
,
1625 tcg_opc_m1 (TCG_REG_P7
, OPC_LD8_M1
,
1626 TCG_REG_R1
, TCG_REG_R2
),
1627 tcg_opc_i12(TCG_REG_P6
, OPC_DEP_Z_I12
,
1628 TCG_REG_R2
, data_reg
, 31, 31),
1629 tcg_opc_i3 (TCG_REG_P6
, OPC_MUX1_I3
,
1630 TCG_REG_R2
, TCG_REG_R2
, 0xb));
1631 data_reg
= TCG_REG_R2
;
1632 } else if (opc
== 3) {
1633 tcg_out_bundle(s
, miI
,
1634 tcg_opc_m1 (TCG_REG_P7
, OPC_LD8_M1
,
1635 TCG_REG_R1
, TCG_REG_R2
),
1636 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1637 tcg_opc_i3 (TCG_REG_P6
, OPC_MUX1_I3
,
1638 TCG_REG_R2
, data_reg
, 0xb));
1639 data_reg
= TCG_REG_R2
;
1642 tcg_out_bundle(s
, miB
,
1643 tcg_opc_m4 (TCG_REG_P6
, opc_st_m4
[opc
],
1644 data_reg
, TCG_REG_R3
),
1645 tcg_opc_a5 (TCG_REG_P7
, OPC_ADDL_A5
, TCG_REG_R58
,
1646 mem_index
, TCG_REG_R0
),
1647 tcg_opc_b5 (TCG_REG_P7
, OPC_BR_CALL_SPTK_MANY_B5
,
1648 TCG_REG_B0
, TCG_REG_B6
));
1651 #else /* !CONFIG_SOFTMMU */
1653 static inline void tcg_out_qemu_ld(TCGContext
*s
, const TCGArg
*args
, int opc
)
1655 static uint64_t const opc_ld_m1
[4] = {
1656 OPC_LD1_M1
, OPC_LD2_M1
, OPC_LD4_M1
, OPC_LD8_M1
1658 static uint64_t const opc_sxt_i29
[4] = {
1659 OPC_SXT1_I29
, OPC_SXT2_I29
, OPC_SXT4_I29
, 0
1661 int addr_reg
, data_reg
, mem_index
, s_bits
, bswap
;
1668 #ifdef TARGET_WORDS_BIGENDIAN
1674 #if TARGET_LONG_BITS == 32
1675 if (GUEST_BASE
!= 0) {
1676 tcg_out_bundle(s
, mII
,
1677 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1678 tcg_opc_i29(TCG_REG_P0
, OPC_ZXT4_I29
,
1679 TCG_REG_R3
, addr_reg
),
1680 tcg_opc_a1 (TCG_REG_P0
, OPC_ADD_A1
, TCG_REG_R2
,
1681 TCG_GUEST_BASE_REG
, TCG_REG_R3
));
1683 tcg_out_bundle(s
, miI
,
1684 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1685 tcg_opc_i29(TCG_REG_P0
, OPC_ZXT4_I29
,
1686 TCG_REG_R2
, addr_reg
),
1687 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0));
1690 if (!bswap
|| s_bits
== 0) {
1691 if (s_bits
== opc
) {
1692 tcg_out_bundle(s
, miI
,
1693 tcg_opc_m1 (TCG_REG_P0
, opc_ld_m1
[s_bits
],
1694 data_reg
, TCG_REG_R2
),
1695 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1696 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0));
1698 tcg_out_bundle(s
, mII
,
1699 tcg_opc_m1 (TCG_REG_P0
, opc_ld_m1
[s_bits
],
1700 data_reg
, TCG_REG_R2
),
1701 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1702 tcg_opc_i29(TCG_REG_P0
, opc_sxt_i29
[s_bits
],
1703 data_reg
, data_reg
));
1705 } else if (s_bits
== 3) {
1706 tcg_out_bundle(s
, mII
,
1707 tcg_opc_m1 (TCG_REG_P0
, opc_ld_m1
[s_bits
],
1708 data_reg
, TCG_REG_R2
),
1709 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1710 tcg_opc_i3 (TCG_REG_P0
, OPC_MUX1_I3
,
1711 data_reg
, data_reg
, 0xb));
1714 tcg_out_bundle(s
, mII
,
1715 tcg_opc_m1 (TCG_REG_P0
, opc_ld_m1
[s_bits
],
1716 data_reg
, TCG_REG_R2
),
1717 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1718 tcg_opc_i12(TCG_REG_P0
, OPC_DEP_Z_I12
,
1719 data_reg
, data_reg
, 15, 15));
1721 tcg_out_bundle(s
, mII
,
1722 tcg_opc_m1 (TCG_REG_P0
, opc_ld_m1
[s_bits
],
1723 data_reg
, TCG_REG_R2
),
1724 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1725 tcg_opc_i12(TCG_REG_P0
, OPC_DEP_Z_I12
,
1726 data_reg
, data_reg
, 31, 31));
1728 if (opc
== s_bits
) {
1729 tcg_out_bundle(s
, miI
,
1730 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1731 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1732 tcg_opc_i3 (TCG_REG_P0
, OPC_MUX1_I3
,
1733 data_reg
, data_reg
, 0xb));
1735 tcg_out_bundle(s
, mII
,
1736 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1737 tcg_opc_i3 (TCG_REG_P0
, OPC_MUX1_I3
,
1738 data_reg
, data_reg
, 0xb),
1739 tcg_opc_i29(TCG_REG_P0
, opc_sxt_i29
[s_bits
],
1740 data_reg
, data_reg
));
1744 if (GUEST_BASE
!= 0) {
1745 tcg_out_bundle(s
, MmI
,
1746 tcg_opc_a1 (TCG_REG_P0
, OPC_ADD_A1
, TCG_REG_R2
,
1747 TCG_GUEST_BASE_REG
, addr_reg
),
1748 tcg_opc_m1 (TCG_REG_P0
, opc_ld_m1
[s_bits
],
1749 data_reg
, TCG_REG_R2
),
1750 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0));
1752 tcg_out_bundle(s
, mmI
,
1753 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1754 tcg_opc_m1 (TCG_REG_P0
, opc_ld_m1
[s_bits
],
1755 data_reg
, addr_reg
),
1756 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0));
1759 if (bswap
&& s_bits
== 1) {
1760 tcg_out_bundle(s
, mII
,
1761 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1762 tcg_opc_i12(TCG_REG_P0
, OPC_DEP_Z_I12
,
1763 data_reg
, data_reg
, 15, 15),
1764 tcg_opc_i3 (TCG_REG_P0
, OPC_MUX1_I3
,
1765 data_reg
, data_reg
, 0xb));
1766 } else if (bswap
&& s_bits
== 2) {
1767 tcg_out_bundle(s
, mII
,
1768 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1769 tcg_opc_i12(TCG_REG_P0
, OPC_DEP_Z_I12
,
1770 data_reg
, data_reg
, 31, 31),
1771 tcg_opc_i3 (TCG_REG_P0
, OPC_MUX1_I3
,
1772 data_reg
, data_reg
, 0xb));
1773 } else if (bswap
&& s_bits
== 3) {
1774 tcg_out_bundle(s
, miI
,
1775 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1776 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1777 tcg_opc_i3 (TCG_REG_P0
, OPC_MUX1_I3
,
1778 data_reg
, data_reg
, 0xb));
1780 if (s_bits
!= opc
) {
1781 tcg_out_bundle(s
, miI
,
1782 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1783 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1784 tcg_opc_i29(TCG_REG_P0
, opc_sxt_i29
[s_bits
],
1785 data_reg
, data_reg
));
1790 static inline void tcg_out_qemu_st(TCGContext
*s
, const TCGArg
*args
, int opc
)
1792 static uint64_t const opc_st_m4
[4] = {
1793 OPC_ST1_M4
, OPC_ST2_M4
, OPC_ST4_M4
, OPC_ST8_M4
1795 int addr_reg
, data_reg
, bswap
;
1796 #if TARGET_LONG_BITS == 64
1797 uint64_t add_guest_base
;
1803 #ifdef TARGET_WORDS_BIGENDIAN
1809 #if TARGET_LONG_BITS == 32
1810 if (GUEST_BASE
!= 0) {
1811 tcg_out_bundle(s
, mII
,
1812 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1813 tcg_opc_i29(TCG_REG_P0
, OPC_ZXT4_I29
,
1814 TCG_REG_R3
, addr_reg
),
1815 tcg_opc_a1 (TCG_REG_P0
, OPC_ADD_A1
, TCG_REG_R2
,
1816 TCG_GUEST_BASE_REG
, TCG_REG_R3
));
1818 tcg_out_bundle(s
, miI
,
1819 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1820 tcg_opc_i29(TCG_REG_P0
, OPC_ZXT4_I29
,
1821 TCG_REG_R2
, addr_reg
),
1822 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0));
1827 tcg_out_bundle(s
, mII
,
1828 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1829 tcg_opc_i12(TCG_REG_P0
, OPC_DEP_Z_I12
,
1830 TCG_REG_R3
, data_reg
, 15, 15),
1831 tcg_opc_i3 (TCG_REG_P0
, OPC_MUX1_I3
,
1832 TCG_REG_R3
, TCG_REG_R3
, 0xb));
1833 data_reg
= TCG_REG_R3
;
1834 } else if (opc
== 2) {
1835 tcg_out_bundle(s
, mII
,
1836 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1837 tcg_opc_i12(TCG_REG_P0
, OPC_DEP_Z_I12
,
1838 TCG_REG_R3
, data_reg
, 31, 31),
1839 tcg_opc_i3 (TCG_REG_P0
, OPC_MUX1_I3
,
1840 TCG_REG_R3
, TCG_REG_R3
, 0xb));
1841 data_reg
= TCG_REG_R3
;
1842 } else if (opc
== 3) {
1843 tcg_out_bundle(s
, miI
,
1844 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1845 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1846 tcg_opc_i3 (TCG_REG_P0
, OPC_MUX1_I3
,
1847 TCG_REG_R3
, data_reg
, 0xb));
1848 data_reg
= TCG_REG_R3
;
1851 tcg_out_bundle(s
, mmI
,
1852 tcg_opc_m4 (TCG_REG_P0
, opc_st_m4
[opc
],
1853 data_reg
, TCG_REG_R2
),
1854 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
1855 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0));
1857 if (GUEST_BASE
!= 0) {
1858 add_guest_base
= tcg_opc_a1 (TCG_REG_P0
, OPC_ADD_A1
, TCG_REG_R2
,
1859 TCG_GUEST_BASE_REG
, addr_reg
);
1860 addr_reg
= TCG_REG_R2
;
1862 add_guest_base
= tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0);
1865 if (!bswap
|| opc
== 0) {
1866 tcg_out_bundle(s
, (GUEST_BASE
? MmI
: mmI
),
1868 tcg_opc_m4 (TCG_REG_P0
, opc_st_m4
[opc
],
1869 data_reg
, addr_reg
),
1870 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0));
1873 tcg_out_bundle(s
, mII
,
1875 tcg_opc_i12(TCG_REG_P0
, OPC_DEP_Z_I12
,
1876 TCG_REG_R3
, data_reg
, 15, 15),
1877 tcg_opc_i3 (TCG_REG_P0
, OPC_MUX1_I3
,
1878 TCG_REG_R3
, TCG_REG_R3
, 0xb));
1879 data_reg
= TCG_REG_R3
;
1880 } else if (opc
== 2) {
1881 tcg_out_bundle(s
, mII
,
1883 tcg_opc_i12(TCG_REG_P0
, OPC_DEP_Z_I12
,
1884 TCG_REG_R3
, data_reg
, 31, 31),
1885 tcg_opc_i3 (TCG_REG_P0
, OPC_MUX1_I3
,
1886 TCG_REG_R3
, TCG_REG_R3
, 0xb));
1887 data_reg
= TCG_REG_R3
;
1888 } else if (opc
== 3) {
1889 tcg_out_bundle(s
, miI
,
1891 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1892 tcg_opc_i3 (TCG_REG_P0
, OPC_MUX1_I3
,
1893 TCG_REG_R3
, data_reg
, 0xb));
1894 data_reg
= TCG_REG_R3
;
1896 tcg_out_bundle(s
, miI
,
1897 tcg_opc_m4 (TCG_REG_P0
, opc_st_m4
[opc
],
1898 data_reg
, addr_reg
),
1899 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0),
1900 tcg_opc_i18(TCG_REG_P0
, OPC_NOP_I18
, 0));
1907 static inline void tcg_out_op(TCGContext
*s
, TCGOpcode opc
,
1908 const TCGArg
*args
, const int *const_args
)
1911 case INDEX_op_exit_tb
:
1912 tcg_out_exit_tb(s
, args
[0]);
1915 tcg_out_br(s
, args
[0]);
1918 tcg_out_call(s
, args
[0]);
1920 case INDEX_op_goto_tb
:
1921 tcg_out_goto_tb(s
, args
[0]);
1924 tcg_out_jmp(s
, args
[0]);
1927 case INDEX_op_movi_i32
:
1928 tcg_out_movi(s
, TCG_TYPE_I32
, args
[0], args
[1]);
1930 case INDEX_op_movi_i64
:
1931 tcg_out_movi(s
, TCG_TYPE_I64
, args
[0], args
[1]);
1934 case INDEX_op_ld8u_i32
:
1935 case INDEX_op_ld8u_i64
:
1936 tcg_out_ld_rel(s
, OPC_LD1_M1
, args
[0], args
[1], args
[2]);
1938 case INDEX_op_ld8s_i32
:
1939 case INDEX_op_ld8s_i64
:
1940 tcg_out_ld_rel(s
, OPC_LD1_M1
, args
[0], args
[1], args
[2]);
1941 tcg_out_ext(s
, OPC_SXT1_I29
, args
[0], args
[0]);
1943 case INDEX_op_ld16u_i32
:
1944 case INDEX_op_ld16u_i64
:
1945 tcg_out_ld_rel(s
, OPC_LD2_M1
, args
[0], args
[1], args
[2]);
1947 case INDEX_op_ld16s_i32
:
1948 case INDEX_op_ld16s_i64
:
1949 tcg_out_ld_rel(s
, OPC_LD2_M1
, args
[0], args
[1], args
[2]);
1950 tcg_out_ext(s
, OPC_SXT2_I29
, args
[0], args
[0]);
1952 case INDEX_op_ld_i32
:
1953 case INDEX_op_ld32u_i64
:
1954 tcg_out_ld_rel(s
, OPC_LD4_M1
, args
[0], args
[1], args
[2]);
1956 case INDEX_op_ld32s_i64
:
1957 tcg_out_ld_rel(s
, OPC_LD4_M1
, args
[0], args
[1], args
[2]);
1958 tcg_out_ext(s
, OPC_SXT4_I29
, args
[0], args
[0]);
1960 case INDEX_op_ld_i64
:
1961 tcg_out_ld_rel(s
, OPC_LD8_M1
, args
[0], args
[1], args
[2]);
1963 case INDEX_op_st8_i32
:
1964 case INDEX_op_st8_i64
:
1965 tcg_out_st_rel(s
, OPC_ST1_M4
, args
[0], args
[1], args
[2]);
1967 case INDEX_op_st16_i32
:
1968 case INDEX_op_st16_i64
:
1969 tcg_out_st_rel(s
, OPC_ST2_M4
, args
[0], args
[1], args
[2]);
1971 case INDEX_op_st_i32
:
1972 case INDEX_op_st32_i64
:
1973 tcg_out_st_rel(s
, OPC_ST4_M4
, args
[0], args
[1], args
[2]);
1975 case INDEX_op_st_i64
:
1976 tcg_out_st_rel(s
, OPC_ST8_M4
, args
[0], args
[1], args
[2]);
1979 case INDEX_op_add_i32
:
1980 case INDEX_op_add_i64
:
1981 tcg_out_alu(s
, OPC_ADD_A1
, args
[0], args
[1], const_args
[1],
1982 args
[2], const_args
[2]);
1984 case INDEX_op_sub_i32
:
1985 case INDEX_op_sub_i64
:
1986 tcg_out_alu(s
, OPC_SUB_A1
, args
[0], args
[1], const_args
[1],
1987 args
[2], const_args
[2]);
1990 case INDEX_op_and_i32
:
1991 case INDEX_op_and_i64
:
1992 tcg_out_alu(s
, OPC_AND_A1
, args
[0], args
[1], const_args
[1],
1993 args
[2], const_args
[2]);
1995 case INDEX_op_andc_i32
:
1996 case INDEX_op_andc_i64
:
1997 tcg_out_alu(s
, OPC_ANDCM_A1
, args
[0], args
[1], const_args
[1],
1998 args
[2], const_args
[2]);
2000 case INDEX_op_eqv_i32
:
2001 case INDEX_op_eqv_i64
:
2002 tcg_out_eqv(s
, args
[0], args
[1], const_args
[1],
2003 args
[2], const_args
[2]);
2005 case INDEX_op_nand_i32
:
2006 case INDEX_op_nand_i64
:
2007 tcg_out_nand(s
, args
[0], args
[1], const_args
[1],
2008 args
[2], const_args
[2]);
2010 case INDEX_op_nor_i32
:
2011 case INDEX_op_nor_i64
:
2012 tcg_out_nor(s
, args
[0], args
[1], const_args
[1],
2013 args
[2], const_args
[2]);
2015 case INDEX_op_or_i32
:
2016 case INDEX_op_or_i64
:
2017 tcg_out_alu(s
, OPC_OR_A1
, args
[0], args
[1], const_args
[1],
2018 args
[2], const_args
[2]);
2020 case INDEX_op_orc_i32
:
2021 case INDEX_op_orc_i64
:
2022 tcg_out_orc(s
, args
[0], args
[1], const_args
[1],
2023 args
[2], const_args
[2]);
2025 case INDEX_op_xor_i32
:
2026 case INDEX_op_xor_i64
:
2027 tcg_out_alu(s
, OPC_XOR_A1
, args
[0], args
[1], const_args
[1],
2028 args
[2], const_args
[2]);
2031 case INDEX_op_mul_i32
:
2032 case INDEX_op_mul_i64
:
2033 tcg_out_mul(s
, args
[0], args
[1], args
[2]);
2036 case INDEX_op_sar_i32
:
2037 tcg_out_sar_i32(s
, args
[0], args
[1], args
[2], const_args
[2]);
2039 case INDEX_op_sar_i64
:
2040 tcg_out_sar_i64(s
, args
[0], args
[1], args
[2], const_args
[2]);
2042 case INDEX_op_shl_i32
:
2043 tcg_out_shl_i32(s
, args
[0], args
[1], args
[2], const_args
[2]);
2045 case INDEX_op_shl_i64
:
2046 tcg_out_shl_i64(s
, args
[0], args
[1], args
[2], const_args
[2]);
2048 case INDEX_op_shr_i32
:
2049 tcg_out_shr_i32(s
, args
[0], args
[1], args
[2], const_args
[2]);
2051 case INDEX_op_shr_i64
:
2052 tcg_out_shr_i64(s
, args
[0], args
[1], args
[2], const_args
[2]);
2054 case INDEX_op_rotl_i32
:
2055 tcg_out_rotl_i32(s
, args
[0], args
[1], args
[2], const_args
[2]);
2057 case INDEX_op_rotl_i64
:
2058 tcg_out_rotl_i64(s
, args
[0], args
[1], args
[2], const_args
[2]);
2060 case INDEX_op_rotr_i32
:
2061 tcg_out_rotr_i32(s
, args
[0], args
[1], args
[2], const_args
[2]);
2063 case INDEX_op_rotr_i64
:
2064 tcg_out_rotr_i64(s
, args
[0], args
[1], args
[2], const_args
[2]);
2067 case INDEX_op_ext8s_i32
:
2068 case INDEX_op_ext8s_i64
:
2069 tcg_out_ext(s
, OPC_SXT1_I29
, args
[0], args
[1]);
2071 case INDEX_op_ext8u_i32
:
2072 case INDEX_op_ext8u_i64
:
2073 tcg_out_ext(s
, OPC_ZXT1_I29
, args
[0], args
[1]);
2075 case INDEX_op_ext16s_i32
:
2076 case INDEX_op_ext16s_i64
:
2077 tcg_out_ext(s
, OPC_SXT2_I29
, args
[0], args
[1]);
2079 case INDEX_op_ext16u_i32
:
2080 case INDEX_op_ext16u_i64
:
2081 tcg_out_ext(s
, OPC_ZXT2_I29
, args
[0], args
[1]);
2083 case INDEX_op_ext32s_i64
:
2084 tcg_out_ext(s
, OPC_SXT4_I29
, args
[0], args
[1]);
2086 case INDEX_op_ext32u_i64
:
2087 tcg_out_ext(s
, OPC_ZXT4_I29
, args
[0], args
[1]);
2090 case INDEX_op_bswap16_i32
:
2091 case INDEX_op_bswap16_i64
:
2092 tcg_out_bswap16(s
, args
[0], args
[1]);
2094 case INDEX_op_bswap32_i32
:
2095 case INDEX_op_bswap32_i64
:
2096 tcg_out_bswap32(s
, args
[0], args
[1]);
2098 case INDEX_op_bswap64_i64
:
2099 tcg_out_bswap64(s
, args
[0], args
[1]);
2102 case INDEX_op_brcond_i32
:
2103 tcg_out_brcond(s
, args
[2], args
[0], const_args
[0],
2104 args
[1], const_args
[1], args
[3], 1);
2106 case INDEX_op_brcond_i64
:
2107 tcg_out_brcond(s
, args
[2], args
[0], const_args
[0],
2108 args
[1], const_args
[1], args
[3], 0);
2110 case INDEX_op_setcond_i32
:
2111 tcg_out_setcond(s
, args
[3], args
[0], args
[1], args
[2], 1);
2113 case INDEX_op_setcond_i64
:
2114 tcg_out_setcond(s
, args
[3], args
[0], args
[1], args
[2], 0);
2117 case INDEX_op_qemu_ld8u
:
2118 tcg_out_qemu_ld(s
, args
, 0);
2120 case INDEX_op_qemu_ld8s
:
2121 tcg_out_qemu_ld(s
, args
, 0 | 4);
2123 case INDEX_op_qemu_ld16u
:
2124 tcg_out_qemu_ld(s
, args
, 1);
2126 case INDEX_op_qemu_ld16s
:
2127 tcg_out_qemu_ld(s
, args
, 1 | 4);
2129 case INDEX_op_qemu_ld32
:
2130 case INDEX_op_qemu_ld32u
:
2131 tcg_out_qemu_ld(s
, args
, 2);
2133 case INDEX_op_qemu_ld32s
:
2134 tcg_out_qemu_ld(s
, args
, 2 | 4);
2136 case INDEX_op_qemu_ld64
:
2137 tcg_out_qemu_ld(s
, args
, 3);
2140 case INDEX_op_qemu_st8
:
2141 tcg_out_qemu_st(s
, args
, 0);
2143 case INDEX_op_qemu_st16
:
2144 tcg_out_qemu_st(s
, args
, 1);
2146 case INDEX_op_qemu_st32
:
2147 tcg_out_qemu_st(s
, args
, 2);
2149 case INDEX_op_qemu_st64
:
2150 tcg_out_qemu_st(s
, args
, 3);
2158 static const TCGTargetOpDef ia64_op_defs
[] = {
2159 { INDEX_op_br
, { } },
2160 { INDEX_op_call
, { "r" } },
2161 { INDEX_op_exit_tb
, { } },
2162 { INDEX_op_goto_tb
, { } },
2163 { INDEX_op_jmp
, { "r" } },
2165 { INDEX_op_mov_i32
, { "r", "r" } },
2166 { INDEX_op_movi_i32
, { "r" } },
2168 { INDEX_op_ld8u_i32
, { "r", "r" } },
2169 { INDEX_op_ld8s_i32
, { "r", "r" } },
2170 { INDEX_op_ld16u_i32
, { "r", "r" } },
2171 { INDEX_op_ld16s_i32
, { "r", "r" } },
2172 { INDEX_op_ld_i32
, { "r", "r" } },
2173 { INDEX_op_st8_i32
, { "rZ", "r" } },
2174 { INDEX_op_st16_i32
, { "rZ", "r" } },
2175 { INDEX_op_st_i32
, { "rZ", "r" } },
2177 { INDEX_op_add_i32
, { "r", "rI", "rI" } },
2178 { INDEX_op_sub_i32
, { "r", "rI", "rI" } },
2180 { INDEX_op_and_i32
, { "r", "rI", "rI" } },
2181 { INDEX_op_andc_i32
, { "r", "rI", "rI" } },
2182 { INDEX_op_eqv_i32
, { "r", "rZ", "rZ" } },
2183 { INDEX_op_nand_i32
, { "r", "rZ", "rZ" } },
2184 { INDEX_op_nor_i32
, { "r", "rZ", "rZ" } },
2185 { INDEX_op_or_i32
, { "r", "rI", "rI" } },
2186 { INDEX_op_orc_i32
, { "r", "rZ", "rZ" } },
2187 { INDEX_op_xor_i32
, { "r", "rI", "rI" } },
2189 { INDEX_op_mul_i32
, { "r", "rZ", "rZ" } },
2191 { INDEX_op_sar_i32
, { "r", "rZ", "ri" } },
2192 { INDEX_op_shl_i32
, { "r", "rZ", "ri" } },
2193 { INDEX_op_shr_i32
, { "r", "rZ", "ri" } },
2194 { INDEX_op_rotl_i32
, { "r", "rZ", "ri" } },
2195 { INDEX_op_rotr_i32
, { "r", "rZ", "ri" } },
2197 { INDEX_op_ext8s_i32
, { "r", "rZ"} },
2198 { INDEX_op_ext8u_i32
, { "r", "rZ"} },
2199 { INDEX_op_ext16s_i32
, { "r", "rZ"} },
2200 { INDEX_op_ext16u_i32
, { "r", "rZ"} },
2202 { INDEX_op_bswap16_i32
, { "r", "rZ" } },
2203 { INDEX_op_bswap32_i32
, { "r", "rZ" } },
2205 { INDEX_op_brcond_i32
, { "rI", "rI" } },
2206 { INDEX_op_setcond_i32
, { "r", "rZ", "rZ" } },
2208 { INDEX_op_mov_i64
, { "r", "r" } },
2209 { INDEX_op_movi_i64
, { "r" } },
2211 { INDEX_op_ld8u_i64
, { "r", "r" } },
2212 { INDEX_op_ld8s_i64
, { "r", "r" } },
2213 { INDEX_op_ld16u_i64
, { "r", "r" } },
2214 { INDEX_op_ld16s_i64
, { "r", "r" } },
2215 { INDEX_op_ld32u_i64
, { "r", "r" } },
2216 { INDEX_op_ld32s_i64
, { "r", "r" } },
2217 { INDEX_op_ld_i64
, { "r", "r" } },
2218 { INDEX_op_st8_i64
, { "rZ", "r" } },
2219 { INDEX_op_st16_i64
, { "rZ", "r" } },
2220 { INDEX_op_st32_i64
, { "rZ", "r" } },
2221 { INDEX_op_st_i64
, { "rZ", "r" } },
2223 { INDEX_op_add_i64
, { "r", "rI", "rI" } },
2224 { INDEX_op_sub_i64
, { "r", "rI", "rI" } },
2226 { INDEX_op_and_i64
, { "r", "rI", "rI" } },
2227 { INDEX_op_andc_i64
, { "r", "rI", "rI" } },
2228 { INDEX_op_eqv_i64
, { "r", "rZ", "rZ" } },
2229 { INDEX_op_nand_i64
, { "r", "rZ", "rZ" } },
2230 { INDEX_op_nor_i64
, { "r", "rZ", "rZ" } },
2231 { INDEX_op_or_i64
, { "r", "rI", "rI" } },
2232 { INDEX_op_orc_i64
, { "r", "rZ", "rZ" } },
2233 { INDEX_op_xor_i64
, { "r", "rI", "rI" } },
2235 { INDEX_op_mul_i64
, { "r", "rZ", "rZ" } },
2237 { INDEX_op_sar_i64
, { "r", "rZ", "ri" } },
2238 { INDEX_op_shl_i64
, { "r", "rZ", "ri" } },
2239 { INDEX_op_shr_i64
, { "r", "rZ", "ri" } },
2240 { INDEX_op_rotl_i64
, { "r", "rZ", "ri" } },
2241 { INDEX_op_rotr_i64
, { "r", "rZ", "ri" } },
2243 { INDEX_op_ext8s_i64
, { "r", "rZ"} },
2244 { INDEX_op_ext8u_i64
, { "r", "rZ"} },
2245 { INDEX_op_ext16s_i64
, { "r", "rZ"} },
2246 { INDEX_op_ext16u_i64
, { "r", "rZ"} },
2247 { INDEX_op_ext32s_i64
, { "r", "rZ"} },
2248 { INDEX_op_ext32u_i64
, { "r", "rZ"} },
2250 { INDEX_op_bswap16_i64
, { "r", "rZ" } },
2251 { INDEX_op_bswap32_i64
, { "r", "rZ" } },
2252 { INDEX_op_bswap64_i64
, { "r", "rZ" } },
2254 { INDEX_op_brcond_i64
, { "rI", "rI" } },
2255 { INDEX_op_setcond_i64
, { "r", "rZ", "rZ" } },
2257 { INDEX_op_qemu_ld8u
, { "r", "r" } },
2258 { INDEX_op_qemu_ld8s
, { "r", "r" } },
2259 { INDEX_op_qemu_ld16u
, { "r", "r" } },
2260 { INDEX_op_qemu_ld16s
, { "r", "r" } },
2261 { INDEX_op_qemu_ld32
, { "r", "r" } },
2262 { INDEX_op_qemu_ld32u
, { "r", "r" } },
2263 { INDEX_op_qemu_ld32s
, { "r", "r" } },
2264 { INDEX_op_qemu_ld64
, { "r", "r" } },
2266 { INDEX_op_qemu_st8
, { "SZ", "r" } },
2267 { INDEX_op_qemu_st16
, { "SZ", "r" } },
2268 { INDEX_op_qemu_st32
, { "SZ", "r" } },
2269 { INDEX_op_qemu_st64
, { "SZ", "r" } },
2274 /* Generate global QEMU prologue and epilogue code */
2275 static void tcg_target_qemu_prologue(TCGContext
*s
)
2279 /* reserve some stack space */
2280 frame_size
= TCG_STATIC_CALL_ARGS_SIZE
;
2281 frame_size
= (frame_size
+ TCG_TARGET_STACK_ALIGN
- 1) &
2282 ~(TCG_TARGET_STACK_ALIGN
- 1);
2284 /* First emit adhoc function descriptor */
2285 *(uint64_t *)(s
->code_ptr
) = (uint64_t)s
->code_ptr
+ 16; /* entry point */
2286 s
->code_ptr
+= 16; /* skip GP */
2289 tcg_out_bundle(s
, mII
,
2290 tcg_opc_m34(TCG_REG_P0
, OPC_ALLOC_M34
,
2291 TCG_REG_R33
, 32, 24, 0),
2292 tcg_opc_i21(TCG_REG_P0
, OPC_MOV_I21
,
2293 TCG_REG_B6
, TCG_REG_R32
, 0),
2294 tcg_opc_i22(TCG_REG_P0
, OPC_MOV_I22
,
2295 TCG_REG_R32
, TCG_REG_B0
));
2297 /* ??? If GUEST_BASE < 0x200000, we could load the register via
2298 an ADDL in the M slot of the next bundle. */
2299 if (GUEST_BASE
!= 0) {
2300 tcg_out_bundle(s
, mlx
,
2301 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
2302 tcg_opc_l2 (GUEST_BASE
),
2303 tcg_opc_x2 (TCG_REG_P0
, OPC_MOVL_X2
,
2304 TCG_GUEST_BASE_REG
, GUEST_BASE
));
2305 tcg_regset_set_reg(s
->reserved_regs
, TCG_GUEST_BASE_REG
);
2308 tcg_out_bundle(s
, miB
,
2309 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
2310 tcg_opc_a4 (TCG_REG_P0
, OPC_ADDS_A4
,
2311 TCG_REG_R12
, -frame_size
, TCG_REG_R12
),
2312 tcg_opc_b4 (TCG_REG_P0
, OPC_BR_SPTK_MANY_B4
, TCG_REG_B6
));
2315 tb_ret_addr
= s
->code_ptr
;
2316 tcg_out_bundle(s
, miI
,
2317 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
2318 tcg_opc_i21(TCG_REG_P0
, OPC_MOV_I21
,
2319 TCG_REG_B0
, TCG_REG_R32
, 0),
2320 tcg_opc_a4 (TCG_REG_P0
, OPC_ADDS_A4
,
2321 TCG_REG_R12
, frame_size
, TCG_REG_R12
));
2322 tcg_out_bundle(s
, miB
,
2323 tcg_opc_m48(TCG_REG_P0
, OPC_NOP_M48
, 0),
2324 tcg_opc_i26(TCG_REG_P0
, OPC_MOV_I_I26
,
2325 TCG_REG_PFS
, TCG_REG_R33
),
2326 tcg_opc_b4 (TCG_REG_P0
, OPC_BR_RET_SPTK_MANY_B4
,
2330 static void tcg_target_init(TCGContext
*s
)
2332 tcg_regset_set(tcg_target_available_regs
[TCG_TYPE_I32
],
2333 0xffffffffffffffffull
);
2334 tcg_regset_set(tcg_target_available_regs
[TCG_TYPE_I64
],
2335 0xffffffffffffffffull
);
2337 tcg_regset_clear(tcg_target_call_clobber_regs
);
2338 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R8
);
2339 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R9
);
2340 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R10
);
2341 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R11
);
2342 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R14
);
2343 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R15
);
2344 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R16
);
2345 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R17
);
2346 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R18
);
2347 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R19
);
2348 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R20
);
2349 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R21
);
2350 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R22
);
2351 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R23
);
2352 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R24
);
2353 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R25
);
2354 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R26
);
2355 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R27
);
2356 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R28
);
2357 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R29
);
2358 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R30
);
2359 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R31
);
2360 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R56
);
2361 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R57
);
2362 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R58
);
2363 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R59
);
2364 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R60
);
2365 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R61
);
2366 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R62
);
2367 tcg_regset_set_reg(tcg_target_call_clobber_regs
, TCG_REG_R63
);
2369 tcg_regset_clear(s
->reserved_regs
);
2370 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R0
); /* zero register */
2371 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R1
); /* global pointer */
2372 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R2
); /* internal use */
2373 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R3
); /* internal use */
2374 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R12
); /* stack pointer */
2375 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R13
); /* thread pointer */
2376 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R32
); /* return address */
2377 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R33
); /* PFS */
2379 /* The following 3 are not in use, are call-saved, but *not* saved
2380 by the prologue. Therefore we cannot use them without modifying
2381 the prologue. There doesn't seem to be any good reason to use
2382 these as opposed to the windowed registers. */
2383 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R4
);
2384 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R5
);
2385 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_R6
);
2387 tcg_add_target_add_op_defs(ia64_op_defs
);