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tcg/ia64: remove suboptimal register shifting in qemu_ld/st ops
[qemu.git] / tcg / ia64 / tcg-target.c
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2009-2010 Aurelien Jarno <aurelien@aurel32.net>
5 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 /*
27 * Register definitions
28 */
29
30 #ifndef NDEBUG
31 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
32 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
33 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
34 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
35 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
36 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
37 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
38 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
39 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
40 };
41 #endif
42
43 #ifdef CONFIG_USE_GUEST_BASE
44 #define TCG_GUEST_BASE_REG TCG_REG_R55
45 #else
46 #define TCG_GUEST_BASE_REG TCG_REG_R0
47 #endif
48 #ifndef GUEST_BASE
49 #define GUEST_BASE 0
50 #endif
51
52 /* Branch registers */
53 enum {
54 TCG_REG_B0 = 0,
55 TCG_REG_B1,
56 TCG_REG_B2,
57 TCG_REG_B3,
58 TCG_REG_B4,
59 TCG_REG_B5,
60 TCG_REG_B6,
61 TCG_REG_B7,
62 };
63
64 /* Floating point registers */
65 enum {
66 TCG_REG_F0 = 0,
67 TCG_REG_F1,
68 TCG_REG_F2,
69 TCG_REG_F3,
70 TCG_REG_F4,
71 TCG_REG_F5,
72 TCG_REG_F6,
73 TCG_REG_F7,
74 TCG_REG_F8,
75 TCG_REG_F9,
76 TCG_REG_F10,
77 TCG_REG_F11,
78 TCG_REG_F12,
79 TCG_REG_F13,
80 TCG_REG_F14,
81 TCG_REG_F15,
82 };
83
84 /* Predicate registers */
85 enum {
86 TCG_REG_P0 = 0,
87 TCG_REG_P1,
88 TCG_REG_P2,
89 TCG_REG_P3,
90 TCG_REG_P4,
91 TCG_REG_P5,
92 TCG_REG_P6,
93 TCG_REG_P7,
94 TCG_REG_P8,
95 TCG_REG_P9,
96 TCG_REG_P10,
97 TCG_REG_P11,
98 TCG_REG_P12,
99 TCG_REG_P13,
100 TCG_REG_P14,
101 TCG_REG_P15,
102 };
103
104 /* Application registers */
105 enum {
106 TCG_REG_PFS = 64,
107 };
108
109 static const int tcg_target_reg_alloc_order[] = {
110 TCG_REG_R33,
111 TCG_REG_R35,
112 TCG_REG_R36,
113 TCG_REG_R37,
114 TCG_REG_R38,
115 TCG_REG_R39,
116 TCG_REG_R40,
117 TCG_REG_R41,
118 TCG_REG_R42,
119 TCG_REG_R43,
120 TCG_REG_R44,
121 TCG_REG_R45,
122 TCG_REG_R46,
123 TCG_REG_R47,
124 TCG_REG_R48,
125 TCG_REG_R49,
126 TCG_REG_R50,
127 TCG_REG_R51,
128 TCG_REG_R52,
129 TCG_REG_R53,
130 TCG_REG_R54,
131 TCG_REG_R55,
132 TCG_REG_R14,
133 TCG_REG_R15,
134 TCG_REG_R16,
135 TCG_REG_R17,
136 TCG_REG_R18,
137 TCG_REG_R19,
138 TCG_REG_R20,
139 TCG_REG_R21,
140 TCG_REG_R22,
141 TCG_REG_R23,
142 TCG_REG_R24,
143 TCG_REG_R25,
144 TCG_REG_R26,
145 TCG_REG_R27,
146 TCG_REG_R28,
147 TCG_REG_R29,
148 TCG_REG_R30,
149 TCG_REG_R31,
150 TCG_REG_R56,
151 TCG_REG_R57,
152 TCG_REG_R58,
153 TCG_REG_R59,
154 TCG_REG_R60,
155 TCG_REG_R61,
156 TCG_REG_R62,
157 TCG_REG_R63,
158 TCG_REG_R8,
159 TCG_REG_R9,
160 TCG_REG_R10,
161 TCG_REG_R11
162 };
163
164 static const int tcg_target_call_iarg_regs[8] = {
165 TCG_REG_R56,
166 TCG_REG_R57,
167 TCG_REG_R58,
168 TCG_REG_R59,
169 TCG_REG_R60,
170 TCG_REG_R61,
171 TCG_REG_R62,
172 TCG_REG_R63,
173 };
174
175 static const int tcg_target_call_oarg_regs[] = {
176 TCG_REG_R8
177 };
178
179 /*
180 * opcode formation
181 */
182
183 /* bundle templates: stops (double bar in the IA64 manual) are marked with
184 an uppercase letter. */
185 enum {
186 mii = 0x00,
187 miI = 0x01,
188 mIi = 0x02,
189 mII = 0x03,
190 mlx = 0x04,
191 mLX = 0x05,
192 mmi = 0x08,
193 mmI = 0x09,
194 Mmi = 0x0a,
195 MmI = 0x0b,
196 mfi = 0x0c,
197 mfI = 0x0d,
198 mmf = 0x0e,
199 mmF = 0x0f,
200 mib = 0x10,
201 miB = 0x11,
202 mbb = 0x12,
203 mbB = 0x13,
204 bbb = 0x16,
205 bbB = 0x17,
206 mmb = 0x18,
207 mmB = 0x19,
208 mfb = 0x1c,
209 mfB = 0x1d,
210 };
211
212 enum {
213 OPC_ADD_A1 = 0x10000000000ull,
214 OPC_AND_A1 = 0x10060000000ull,
215 OPC_AND_A3 = 0x10160000000ull,
216 OPC_ANDCM_A1 = 0x10068000000ull,
217 OPC_ANDCM_A3 = 0x10168000000ull,
218 OPC_ADDS_A4 = 0x10800000000ull,
219 OPC_ADDL_A5 = 0x12000000000ull,
220 OPC_ALLOC_M34 = 0x02c00000000ull,
221 OPC_BR_DPTK_FEW_B1 = 0x08400000000ull,
222 OPC_BR_SPTK_MANY_B1 = 0x08000001000ull,
223 OPC_BR_SPTK_MANY_B4 = 0x00100001000ull,
224 OPC_BR_CALL_SPTK_MANY_B5 = 0x02100001000ull,
225 OPC_BR_RET_SPTK_MANY_B4 = 0x00108001100ull,
226 OPC_BRL_SPTK_MANY_X3 = 0x18000001000ull,
227 OPC_CMP_LT_A6 = 0x18000000000ull,
228 OPC_CMP_LTU_A6 = 0x1a000000000ull,
229 OPC_CMP_EQ_A6 = 0x1c000000000ull,
230 OPC_CMP4_LT_A6 = 0x18400000000ull,
231 OPC_CMP4_LTU_A6 = 0x1a400000000ull,
232 OPC_CMP4_EQ_A6 = 0x1c400000000ull,
233 OPC_DEP_Z_I12 = 0x0a600000000ull,
234 OPC_EXTR_I11 = 0x0a400002000ull,
235 OPC_EXTR_U_I11 = 0x0a400000000ull,
236 OPC_FCVT_FX_TRUNC_S1_F10 = 0x004d0000000ull,
237 OPC_FCVT_FXU_TRUNC_S1_F10 = 0x004d8000000ull,
238 OPC_FCVT_XF_F11 = 0x000e0000000ull,
239 OPC_FMA_S1_F1 = 0x10400000000ull,
240 OPC_FNMA_S1_F1 = 0x18400000000ull,
241 OPC_FRCPA_S1_F6 = 0x00600000000ull,
242 OPC_GETF_SIG_M19 = 0x08708000000ull,
243 OPC_LD1_M1 = 0x08000000000ull,
244 OPC_LD1_M3 = 0x0a000000000ull,
245 OPC_LD2_M1 = 0x08040000000ull,
246 OPC_LD2_M3 = 0x0a040000000ull,
247 OPC_LD4_M1 = 0x08080000000ull,
248 OPC_LD4_M3 = 0x0a080000000ull,
249 OPC_LD8_M1 = 0x080c0000000ull,
250 OPC_LD8_M3 = 0x0a0c0000000ull,
251 OPC_MUX1_I3 = 0x0eca0000000ull,
252 OPC_NOP_B9 = 0x04008000000ull,
253 OPC_NOP_F16 = 0x00008000000ull,
254 OPC_NOP_I18 = 0x00008000000ull,
255 OPC_NOP_M48 = 0x00008000000ull,
256 OPC_MOV_I21 = 0x00e00100000ull,
257 OPC_MOV_RET_I21 = 0x00e00500000ull,
258 OPC_MOV_I22 = 0x00188000000ull,
259 OPC_MOV_I_I26 = 0x00150000000ull,
260 OPC_MOVL_X2 = 0x0c000000000ull,
261 OPC_OR_A1 = 0x10070000000ull,
262 OPC_SETF_EXP_M18 = 0x0c748000000ull,
263 OPC_SETF_SIG_M18 = 0x0c708000000ull,
264 OPC_SHL_I7 = 0x0f240000000ull,
265 OPC_SHR_I5 = 0x0f220000000ull,
266 OPC_SHR_U_I5 = 0x0f200000000ull,
267 OPC_SHRP_I10 = 0x0ac00000000ull,
268 OPC_SXT1_I29 = 0x000a0000000ull,
269 OPC_SXT2_I29 = 0x000a8000000ull,
270 OPC_SXT4_I29 = 0x000b0000000ull,
271 OPC_ST1_M4 = 0x08c00000000ull,
272 OPC_ST2_M4 = 0x08c40000000ull,
273 OPC_ST4_M4 = 0x08c80000000ull,
274 OPC_ST8_M4 = 0x08cc0000000ull,
275 OPC_SUB_A1 = 0x10028000000ull,
276 OPC_SUB_A3 = 0x10128000000ull,
277 OPC_UNPACK4_L_I2 = 0x0f860000000ull,
278 OPC_XMA_L_F2 = 0x1d000000000ull,
279 OPC_XOR_A1 = 0x10078000000ull,
280 OPC_ZXT1_I29 = 0x00080000000ull,
281 OPC_ZXT2_I29 = 0x00088000000ull,
282 OPC_ZXT4_I29 = 0x00090000000ull,
283 };
284
285 static inline uint64_t tcg_opc_a1(int qp, uint64_t opc, int r1,
286 int r2, int r3)
287 {
288 return opc
289 | ((r3 & 0x7f) << 20)
290 | ((r2 & 0x7f) << 13)
291 | ((r1 & 0x7f) << 6)
292 | (qp & 0x3f);
293 }
294
295 static inline uint64_t tcg_opc_a3(int qp, uint64_t opc, int r1,
296 uint64_t imm, int r3)
297 {
298 return opc
299 | ((imm & 0x80) << 29) /* s */
300 | ((imm & 0x7f) << 13) /* imm7b */
301 | ((r3 & 0x7f) << 20)
302 | ((r1 & 0x7f) << 6)
303 | (qp & 0x3f);
304 }
305
306 static inline uint64_t tcg_opc_a4(int qp, uint64_t opc, int r1,
307 uint64_t imm, int r3)
308 {
309 return opc
310 | ((imm & 0x2000) << 23) /* s */
311 | ((imm & 0x1f80) << 20) /* imm6d */
312 | ((imm & 0x007f) << 13) /* imm7b */
313 | ((r3 & 0x7f) << 20)
314 | ((r1 & 0x7f) << 6)
315 | (qp & 0x3f);
316 }
317
318 static inline uint64_t tcg_opc_a5(int qp, uint64_t opc, int r1,
319 uint64_t imm, int r3)
320 {
321 return opc
322 | ((imm & 0x200000) << 15) /* s */
323 | ((imm & 0x1f0000) << 6) /* imm5c */
324 | ((imm & 0x00ff80) << 20) /* imm9d */
325 | ((imm & 0x00007f) << 13) /* imm7b */
326 | ((r3 & 0x03) << 20)
327 | ((r1 & 0x7f) << 6)
328 | (qp & 0x3f);
329 }
330
331 static inline uint64_t tcg_opc_a6(int qp, uint64_t opc, int p1,
332 int p2, int r2, int r3)
333 {
334 return opc
335 | ((p2 & 0x3f) << 27)
336 | ((r3 & 0x7f) << 20)
337 | ((r2 & 0x7f) << 13)
338 | ((p1 & 0x3f) << 6)
339 | (qp & 0x3f);
340 }
341
342 static inline uint64_t tcg_opc_b1(int qp, uint64_t opc, uint64_t imm)
343 {
344 return opc
345 | ((imm & 0x100000) << 16) /* s */
346 | ((imm & 0x0fffff) << 13) /* imm20b */
347 | (qp & 0x3f);
348 }
349
350 static inline uint64_t tcg_opc_b4(int qp, uint64_t opc, int b2)
351 {
352 return opc
353 | ((b2 & 0x7) << 13)
354 | (qp & 0x3f);
355 }
356
357 static inline uint64_t tcg_opc_b5(int qp, uint64_t opc, int b1, int b2)
358 {
359 return opc
360 | ((b2 & 0x7) << 13)
361 | ((b1 & 0x7) << 6)
362 | (qp & 0x3f);
363 }
364
365
366 static inline uint64_t tcg_opc_b9(int qp, uint64_t opc, uint64_t imm)
367 {
368 return opc
369 | ((imm & 0x100000) << 16) /* i */
370 | ((imm & 0x0fffff) << 6) /* imm20a */
371 | (qp & 0x3f);
372 }
373
374 static inline uint64_t tcg_opc_f1(int qp, uint64_t opc, int f1,
375 int f3, int f4, int f2)
376 {
377 return opc
378 | ((f4 & 0x7f) << 27)
379 | ((f3 & 0x7f) << 20)
380 | ((f2 & 0x7f) << 13)
381 | ((f1 & 0x7f) << 6)
382 | (qp & 0x3f);
383 }
384
385 static inline uint64_t tcg_opc_f2(int qp, uint64_t opc, int f1,
386 int f3, int f4, int f2)
387 {
388 return opc
389 | ((f4 & 0x7f) << 27)
390 | ((f3 & 0x7f) << 20)
391 | ((f2 & 0x7f) << 13)
392 | ((f1 & 0x7f) << 6)
393 | (qp & 0x3f);
394 }
395
396 static inline uint64_t tcg_opc_f6(int qp, uint64_t opc, int f1,
397 int p2, int f2, int f3)
398 {
399 return opc
400 | ((p2 & 0x3f) << 27)
401 | ((f3 & 0x7f) << 20)
402 | ((f2 & 0x7f) << 13)
403 | ((f1 & 0x7f) << 6)
404 | (qp & 0x3f);
405 }
406
407 static inline uint64_t tcg_opc_f10(int qp, uint64_t opc, int f1, int f2)
408 {
409 return opc
410 | ((f2 & 0x7f) << 13)
411 | ((f1 & 0x7f) << 6)
412 | (qp & 0x3f);
413 }
414
415 static inline uint64_t tcg_opc_f11(int qp, uint64_t opc, int f1, int f2)
416 {
417 return opc
418 | ((f2 & 0x7f) << 13)
419 | ((f1 & 0x7f) << 6)
420 | (qp & 0x3f);
421 }
422
423 static inline uint64_t tcg_opc_f16(int qp, uint64_t opc, uint64_t imm)
424 {
425 return opc
426 | ((imm & 0x100000) << 16) /* i */
427 | ((imm & 0x0fffff) << 6) /* imm20a */
428 | (qp & 0x3f);
429 }
430
431 static inline uint64_t tcg_opc_i2(int qp, uint64_t opc, int r1,
432 int r2, int r3)
433 {
434 return opc
435 | ((r3 & 0x7f) << 20)
436 | ((r2 & 0x7f) << 13)
437 | ((r1 & 0x7f) << 6)
438 | (qp & 0x3f);
439 }
440
441 static inline uint64_t tcg_opc_i3(int qp, uint64_t opc, int r1,
442 int r2, int mbtype)
443 {
444 return opc
445 | ((mbtype & 0x0f) << 20)
446 | ((r2 & 0x7f) << 13)
447 | ((r1 & 0x7f) << 6)
448 | (qp & 0x3f);
449 }
450
451 static inline uint64_t tcg_opc_i5(int qp, uint64_t opc, int r1,
452 int r3, int r2)
453 {
454 return opc
455 | ((r3 & 0x7f) << 20)
456 | ((r2 & 0x7f) << 13)
457 | ((r1 & 0x7f) << 6)
458 | (qp & 0x3f);
459 }
460
461 static inline uint64_t tcg_opc_i7(int qp, uint64_t opc, int r1,
462 int r2, int r3)
463 {
464 return opc
465 | ((r3 & 0x7f) << 20)
466 | ((r2 & 0x7f) << 13)
467 | ((r1 & 0x7f) << 6)
468 | (qp & 0x3f);
469 }
470
471 static inline uint64_t tcg_opc_i10(int qp, uint64_t opc, int r1,
472 int r2, int r3, uint64_t count)
473 {
474 return opc
475 | ((count & 0x3f) << 27)
476 | ((r3 & 0x7f) << 20)
477 | ((r2 & 0x7f) << 13)
478 | ((r1 & 0x7f) << 6)
479 | (qp & 0x3f);
480 }
481
482 static inline uint64_t tcg_opc_i11(int qp, uint64_t opc, int r1,
483 int r3, uint64_t pos, uint64_t len)
484 {
485 return opc
486 | ((len & 0x3f) << 27)
487 | ((r3 & 0x7f) << 20)
488 | ((pos & 0x3f) << 14)
489 | ((r1 & 0x7f) << 6)
490 | (qp & 0x3f);
491 }
492
493 static inline uint64_t tcg_opc_i12(int qp, uint64_t opc, int r1,
494 int r2, uint64_t pos, uint64_t len)
495 {
496 return opc
497 | ((len & 0x3f) << 27)
498 | ((pos & 0x3f) << 20)
499 | ((r2 & 0x7f) << 13)
500 | ((r1 & 0x7f) << 6)
501 | (qp & 0x3f);
502 }
503
504 static inline uint64_t tcg_opc_i18(int qp, uint64_t opc, uint64_t imm)
505 {
506 return opc
507 | ((imm & 0x100000) << 16) /* i */
508 | ((imm & 0x0fffff) << 6) /* imm20a */
509 | (qp & 0x3f);
510 }
511
512 static inline uint64_t tcg_opc_i21(int qp, uint64_t opc, int b1,
513 int r2, uint64_t imm)
514 {
515 return opc
516 | ((imm & 0x1ff) << 24)
517 | ((r2 & 0x7f) << 13)
518 | ((b1 & 0x7) << 6)
519 | (qp & 0x3f);
520 }
521
522 static inline uint64_t tcg_opc_i22(int qp, uint64_t opc, int r1, int b2)
523 {
524 return opc
525 | ((b2 & 0x7) << 13)
526 | ((r1 & 0x7f) << 6)
527 | (qp & 0x3f);
528 }
529
530 static inline uint64_t tcg_opc_i26(int qp, uint64_t opc, int ar3, int r2)
531 {
532 return opc
533 | ((ar3 & 0x7f) << 20)
534 | ((r2 & 0x7f) << 13)
535 | (qp & 0x3f);
536 }
537
538 static inline uint64_t tcg_opc_i29(int qp, uint64_t opc, int r1, int r3)
539 {
540 return opc
541 | ((r3 & 0x7f) << 20)
542 | ((r1 & 0x7f) << 6)
543 | (qp & 0x3f);
544 }
545
546 static inline uint64_t tcg_opc_l2(uint64_t imm)
547 {
548 return (imm & 0x7fffffffffc00000ull) >> 22;
549 }
550
551 static inline uint64_t tcg_opc_l3(uint64_t imm)
552 {
553 return (imm & 0x07fffffffff00000ull) >> 18;
554 }
555
556 static inline uint64_t tcg_opc_m1(int qp, uint64_t opc, int r1, int r3)
557 {
558 return opc
559 | ((r3 & 0x7f) << 20)
560 | ((r1 & 0x7f) << 6)
561 | (qp & 0x3f);
562 }
563
564 static inline uint64_t tcg_opc_m3(int qp, uint64_t opc, int r1,
565 int r3, uint64_t imm)
566 {
567 return opc
568 | ((imm & 0x100) << 28) /* s */
569 | ((imm & 0x080) << 20) /* i */
570 | ((imm & 0x07f) << 13) /* imm7b */
571 | ((r3 & 0x7f) << 20)
572 | ((r1 & 0x7f) << 6)
573 | (qp & 0x3f);
574 }
575
576 static inline uint64_t tcg_opc_m4(int qp, uint64_t opc, int r2, int r3)
577 {
578 return opc
579 | ((r3 & 0x7f) << 20)
580 | ((r2 & 0x7f) << 13)
581 | (qp & 0x3f);
582 }
583
584 static inline uint64_t tcg_opc_m18(int qp, uint64_t opc, int f1, int r2)
585 {
586 return opc
587 | ((r2 & 0x7f) << 13)
588 | ((f1 & 0x7f) << 6)
589 | (qp & 0x3f);
590 }
591
592 static inline uint64_t tcg_opc_m19(int qp, uint64_t opc, int r1, int f2)
593 {
594 return opc
595 | ((f2 & 0x7f) << 13)
596 | ((r1 & 0x7f) << 6)
597 | (qp & 0x3f);
598 }
599
600 static inline uint64_t tcg_opc_m34(int qp, uint64_t opc, int r1,
601 int sof, int sol, int sor)
602 {
603 return opc
604 | ((sor & 0x0f) << 27)
605 | ((sol & 0x7f) << 20)
606 | ((sof & 0x7f) << 13)
607 | ((r1 & 0x7f) << 6)
608 | (qp & 0x3f);
609 }
610
611 static inline uint64_t tcg_opc_m48(int qp, uint64_t opc, uint64_t imm)
612 {
613 return opc
614 | ((imm & 0x100000) << 16) /* i */
615 | ((imm & 0x0fffff) << 6) /* imm20a */
616 | (qp & 0x3f);
617 }
618
619 static inline uint64_t tcg_opc_x2(int qp, uint64_t opc,
620 int r1, uint64_t imm)
621 {
622 return opc
623 | ((imm & 0x8000000000000000ull) >> 27) /* i */
624 | (imm & 0x0000000000200000ull) /* ic */
625 | ((imm & 0x00000000001f0000ull) << 6) /* imm5c */
626 | ((imm & 0x000000000000ff80ull) << 20) /* imm9d */
627 | ((imm & 0x000000000000007full) << 13) /* imm7b */
628 | ((r1 & 0x7f) << 6)
629 | (qp & 0x3f);
630 }
631
632 static inline uint64_t tcg_opc_x3(int qp, uint64_t opc, uint64_t imm)
633 {
634 return opc
635 | ((imm & 0x0800000000000000ull) >> 23) /* i */
636 | ((imm & 0x00000000000fffffull) << 13) /* imm20b */
637 | (qp & 0x3f);
638 }
639
640
641 /*
642 * Relocations
643 */
644
645 static inline void reloc_pcrel21b (void *pc, tcg_target_long target)
646 {
647 uint64_t imm;
648 int64_t disp;
649 int slot;
650
651 slot = (tcg_target_long) pc & 3;
652 pc = (void *)((tcg_target_long) pc & ~3);
653
654 disp = target - (tcg_target_long) pc;
655 imm = (uint64_t) disp >> 4;
656
657 switch(slot) {
658 case 0:
659 *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 8) & 0xfffffdc00003ffffull)
660 | ((imm & 0x100000) << 21) /* s */
661 | ((imm & 0x0fffff) << 18); /* imm20b */
662 break;
663 case 1:
664 *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xfffffffffffb8000ull)
665 | ((imm & 0x100000) >> 2) /* s */
666 | ((imm & 0x0fffe0) >> 5); /* imm20b */
667 *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x07ffffffffffffffull)
668 | ((imm & 0x00001f) << 59); /* imm20b */
669 break;
670 case 2:
671 *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fffffffffull)
672 | ((imm & 0x100000) << 39) /* s */
673 | ((imm & 0x0fffff) << 36); /* imm20b */
674 break;
675 }
676 }
677
678 static inline uint64_t get_reloc_pcrel21b (void *pc)
679 {
680 int64_t low, high;
681 int slot;
682
683 slot = (tcg_target_long) pc & 3;
684 pc = (void *)((tcg_target_long) pc & ~3);
685
686 low = (*(uint64_t *)(pc + 0));
687 high = (*(uint64_t *)(pc + 8));
688
689 switch(slot) {
690 case 0:
691 return ((low >> 21) & 0x100000) + /* s */
692 ((low >> 18) & 0x0fffff); /* imm20b */
693 case 1:
694 return ((high << 2) & 0x100000) + /* s */
695 ((high << 5) & 0x0fffe0) + /* imm20b */
696 ((low >> 59) & 0x00001f); /* imm20b */
697 case 2:
698 return ((high >> 39) & 0x100000) + /* s */
699 ((high >> 36) & 0x0fffff); /* imm20b */
700 default:
701 tcg_abort();
702 }
703 }
704
705 static inline void reloc_pcrel60b (void *pc, tcg_target_long target)
706 {
707 int64_t disp;
708 uint64_t imm;
709
710 disp = target - (tcg_target_long) pc;
711 imm = (uint64_t) disp >> 4;
712
713 *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fff800000ull)
714 | (imm & 0x0800000000000000ull) /* s */
715 | ((imm & 0x07fffff000000000ull) >> 36) /* imm39 */
716 | ((imm & 0x00000000000fffffull) << 36); /* imm20b */
717 *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x00003fffffffffffull)
718 | ((imm & 0x0000000ffff00000ull) << 28); /* imm39 */
719 }
720
721 static inline uint64_t get_reloc_pcrel60b (void *pc)
722 {
723 int64_t low, high;
724
725 low = (*(uint64_t *)(pc + 0));
726 high = (*(uint64_t *)(pc + 8));
727
728 return ((high) & 0x0800000000000000ull) + /* s */
729 ((high >> 36) & 0x00000000000fffffull) + /* imm20b */
730 ((high << 36) & 0x07fffff000000000ull) + /* imm39 */
731 ((low >> 28) & 0x0000000ffff00000ull); /* imm39 */
732 }
733
734
735 static void patch_reloc(uint8_t *code_ptr, int type,
736 tcg_target_long value, tcg_target_long addend)
737 {
738 value += addend;
739 switch (type) {
740 case R_IA64_PCREL21B:
741 reloc_pcrel21b(code_ptr, value);
742 break;
743 case R_IA64_PCREL60B:
744 reloc_pcrel60b(code_ptr, value);
745 default:
746 tcg_abort();
747 }
748 }
749
750 /*
751 * Constraints
752 */
753
754 /* parse target specific constraints */
755 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
756 {
757 const char *ct_str;
758
759 ct_str = *pct_str;
760 switch(ct_str[0]) {
761 case 'r':
762 ct->ct |= TCG_CT_REG;
763 tcg_regset_set(ct->u.regs, 0xffffffffffffffffull);
764 break;
765 case 'I':
766 ct->ct |= TCG_CT_CONST_S22;
767 break;
768 case 'S':
769 ct->ct |= TCG_CT_REG;
770 tcg_regset_set(ct->u.regs, 0xffffffffffffffffull);
771 #if defined(CONFIG_SOFTMMU)
772 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R56);
773 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R57);
774 #endif
775 break;
776 case 'Z':
777 /* We are cheating a bit here, using the fact that the register
778 r0 is also the register number 0. Hence there is no need
779 to check for const_args in each instruction. */
780 ct->ct |= TCG_CT_CONST_ZERO;
781 break;
782 default:
783 return -1;
784 }
785 ct_str++;
786 *pct_str = ct_str;
787 return 0;
788 }
789
790 /* test if a constant matches the constraint */
791 static inline int tcg_target_const_match(tcg_target_long val,
792 const TCGArgConstraint *arg_ct)
793 {
794 int ct;
795 ct = arg_ct->ct;
796 if (ct & TCG_CT_CONST)
797 return 1;
798 else if ((ct & TCG_CT_CONST_ZERO) && val == 0)
799 return 1;
800 else if ((ct & TCG_CT_CONST_S22) && val == ((int32_t)val << 10) >> 10)
801 return 1;
802 else
803 return 0;
804 }
805
806 /*
807 * Code generation
808 */
809
810 static uint8_t *tb_ret_addr;
811
812 static inline void tcg_out_bundle(TCGContext *s, int template,
813 uint64_t slot0, uint64_t slot1,
814 uint64_t slot2)
815 {
816 template &= 0x1f; /* 5 bits */
817 slot0 &= 0x1ffffffffffull; /* 41 bits */
818 slot1 &= 0x1ffffffffffull; /* 41 bits */
819 slot2 &= 0x1ffffffffffull; /* 41 bits */
820
821 *(uint64_t *)(s->code_ptr + 0) = (slot1 << 46) | (slot0 << 5) | template;
822 *(uint64_t *)(s->code_ptr + 8) = (slot2 << 23) | (slot1 >> 18);
823 s->code_ptr += 16;
824 }
825
826 static inline void tcg_out_mov(TCGContext *s, TCGType type,
827 TCGReg ret, TCGReg arg)
828 {
829 tcg_out_bundle(s, mmI,
830 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
831 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
832 tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, ret, 0, arg));
833 }
834
835 static inline void tcg_out_movi(TCGContext *s, TCGType type,
836 TCGReg reg, tcg_target_long arg)
837 {
838 tcg_out_bundle(s, mLX,
839 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
840 tcg_opc_l2 (arg),
841 tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, reg, arg));
842 }
843
844 static void tcg_out_br(TCGContext *s, int label_index)
845 {
846 TCGLabel *l = &s->labels[label_index];
847
848 /* We pay attention here to not modify the branch target by reading
849 the existing value and using it again. This ensure that caches and
850 memory are kept coherent during retranslation. */
851 tcg_out_bundle(s, mmB,
852 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
853 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
854 tcg_opc_b1 (TCG_REG_P0, OPC_BR_SPTK_MANY_B1,
855 get_reloc_pcrel21b(s->code_ptr + 2)));
856
857 if (l->has_value) {
858 reloc_pcrel21b((s->code_ptr - 16) + 2, l->u.value);
859 } else {
860 tcg_out_reloc(s, (s->code_ptr - 16) + 2,
861 R_IA64_PCREL21B, label_index, 0);
862 }
863 }
864
865 static inline void tcg_out_call(TCGContext *s, TCGArg addr)
866 {
867 tcg_out_bundle(s, MmI,
868 tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R2, addr),
869 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R3, 8, addr),
870 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
871 TCG_REG_B6, TCG_REG_R2, 0));
872 tcg_out_bundle(s, mmB,
873 tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R3),
874 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
875 tcg_opc_b5 (TCG_REG_P0, OPC_BR_CALL_SPTK_MANY_B5,
876 TCG_REG_B0, TCG_REG_B6));
877 }
878
879 static void tcg_out_exit_tb(TCGContext *s, tcg_target_long arg)
880 {
881 int64_t disp;
882 uint64_t imm;
883
884 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R8, arg);
885
886 disp = tb_ret_addr - s->code_ptr;
887 imm = (uint64_t)disp >> 4;
888
889 tcg_out_bundle(s, mLX,
890 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
891 tcg_opc_l3 (imm),
892 tcg_opc_x3 (TCG_REG_P0, OPC_BRL_SPTK_MANY_X3, imm));
893 }
894
895 static inline void tcg_out_goto_tb(TCGContext *s, TCGArg arg)
896 {
897 if (s->tb_jmp_offset) {
898 /* direct jump method */
899 tcg_abort();
900 } else {
901 /* indirect jump method */
902 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2,
903 (tcg_target_long)(s->tb_next + arg));
904 tcg_out_bundle(s, MmI,
905 tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1,
906 TCG_REG_R2, TCG_REG_R2),
907 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
908 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6,
909 TCG_REG_R2, 0));
910 tcg_out_bundle(s, mmB,
911 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
912 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
913 tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4,
914 TCG_REG_B6));
915 }
916 s->tb_next_offset[arg] = s->code_ptr - s->code_buf;
917 }
918
919 static inline void tcg_out_jmp(TCGContext *s, TCGArg addr)
920 {
921 tcg_out_bundle(s, mmI,
922 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
923 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
924 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6, addr, 0));
925 tcg_out_bundle(s, mmB,
926 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
927 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
928 tcg_opc_b4(TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6));
929 }
930
931 static inline void tcg_out_ld_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg,
932 TCGArg arg1, tcg_target_long arg2)
933 {
934 if (arg2 == ((int16_t)arg2 >> 2) << 2) {
935 tcg_out_bundle(s, MmI,
936 tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4,
937 TCG_REG_R2, arg2, arg1),
938 tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
939 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
940 } else {
941 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2);
942 tcg_out_bundle(s, MmI,
943 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1,
944 TCG_REG_R2, TCG_REG_R2, arg1),
945 tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
946 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
947 }
948 }
949
950 static inline void tcg_out_st_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg,
951 TCGArg arg1, tcg_target_long arg2)
952 {
953 if (arg2 == ((int16_t)arg2 >> 2) << 2) {
954 tcg_out_bundle(s, MmI,
955 tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4,
956 TCG_REG_R2, arg2, arg1),
957 tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
958 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
959 } else {
960 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2);
961 tcg_out_bundle(s, MmI,
962 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1,
963 TCG_REG_R2, TCG_REG_R2, arg1),
964 tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
965 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
966 }
967 }
968
969 static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
970 TCGReg arg1, tcg_target_long arg2)
971 {
972 if (type == TCG_TYPE_I32) {
973 tcg_out_ld_rel(s, OPC_LD4_M1, arg, arg1, arg2);
974 } else {
975 tcg_out_ld_rel(s, OPC_LD8_M1, arg, arg1, arg2);
976 }
977 }
978
979 static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
980 TCGReg arg1, tcg_target_long arg2)
981 {
982 if (type == TCG_TYPE_I32) {
983 tcg_out_st_rel(s, OPC_ST4_M4, arg, arg1, arg2);
984 } else {
985 tcg_out_st_rel(s, OPC_ST8_M4, arg, arg1, arg2);
986 }
987 }
988
989 static inline void tcg_out_alu(TCGContext *s, uint64_t opc_a1, TCGArg ret,
990 TCGArg arg1, int const_arg1,
991 TCGArg arg2, int const_arg2)
992 {
993 uint64_t opc1, opc2;
994
995 if (const_arg1 && arg1 != 0) {
996 opc1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
997 TCG_REG_R2, arg1, TCG_REG_R0);
998 arg1 = TCG_REG_R2;
999 } else {
1000 opc1 = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
1001 }
1002
1003 if (const_arg2 && arg2 != 0) {
1004 opc2 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
1005 TCG_REG_R3, arg2, TCG_REG_R0);
1006 arg2 = TCG_REG_R3;
1007 } else {
1008 opc2 = tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0);
1009 }
1010
1011 tcg_out_bundle(s, mII,
1012 opc1,
1013 opc2,
1014 tcg_opc_a1(TCG_REG_P0, opc_a1, ret, arg1, arg2));
1015 }
1016
1017 static inline void tcg_out_eqv(TCGContext *s, TCGArg ret,
1018 TCGArg arg1, int const_arg1,
1019 TCGArg arg2, int const_arg2)
1020 {
1021 tcg_out_bundle(s, mII,
1022 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1023 tcg_opc_a1 (TCG_REG_P0, OPC_XOR_A1, ret, arg1, arg2),
1024 tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
1025 }
1026
1027 static inline void tcg_out_nand(TCGContext *s, TCGArg ret,
1028 TCGArg arg1, int const_arg1,
1029 TCGArg arg2, int const_arg2)
1030 {
1031 tcg_out_bundle(s, mII,
1032 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1033 tcg_opc_a1 (TCG_REG_P0, OPC_AND_A1, ret, arg1, arg2),
1034 tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
1035 }
1036
1037 static inline void tcg_out_nor(TCGContext *s, TCGArg ret,
1038 TCGArg arg1, int const_arg1,
1039 TCGArg arg2, int const_arg2)
1040 {
1041 tcg_out_bundle(s, mII,
1042 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1043 tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, arg2),
1044 tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
1045 }
1046
1047 static inline void tcg_out_orc(TCGContext *s, TCGArg ret,
1048 TCGArg arg1, int const_arg1,
1049 TCGArg arg2, int const_arg2)
1050 {
1051 tcg_out_bundle(s, mII,
1052 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1053 tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, TCG_REG_R2, -1, arg2),
1054 tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, TCG_REG_R2));
1055 }
1056
1057 static inline void tcg_out_mul(TCGContext *s, TCGArg ret,
1058 TCGArg arg1, TCGArg arg2)
1059 {
1060 tcg_out_bundle(s, mmI,
1061 tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F6, arg1),
1062 tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F7, arg2),
1063 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1064 tcg_out_bundle(s, mmF,
1065 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1066 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1067 tcg_opc_f2 (TCG_REG_P0, OPC_XMA_L_F2, TCG_REG_F6, TCG_REG_F6,
1068 TCG_REG_F7, TCG_REG_F0));
1069 tcg_out_bundle(s, miI,
1070 tcg_opc_m19(TCG_REG_P0, OPC_GETF_SIG_M19, ret, TCG_REG_F6),
1071 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1072 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1073 }
1074
1075 static inline void tcg_out_sar_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1076 TCGArg arg2, int const_arg2)
1077 {
1078 if (const_arg2) {
1079 tcg_out_bundle(s, miI,
1080 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1081 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1082 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11,
1083 ret, arg1, arg2, 31 - arg2));
1084 } else {
1085 tcg_out_bundle(s, mII,
1086 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3,
1087 TCG_REG_R3, 0x1f, arg2),
1088 tcg_opc_i29(TCG_REG_P0, OPC_SXT4_I29, TCG_REG_R2, arg1),
1089 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret,
1090 TCG_REG_R2, TCG_REG_R3));
1091 }
1092 }
1093
1094 static inline void tcg_out_sar_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1095 TCGArg arg2, int const_arg2)
1096 {
1097 if (const_arg2) {
1098 tcg_out_bundle(s, miI,
1099 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1100 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1101 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11,
1102 ret, arg1, arg2, 63 - arg2));
1103 } else {
1104 tcg_out_bundle(s, miI,
1105 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1106 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1107 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret, arg1, arg2));
1108 }
1109 }
1110
1111 static inline void tcg_out_shl_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1112 TCGArg arg2, int const_arg2)
1113 {
1114 if (const_arg2) {
1115 tcg_out_bundle(s, miI,
1116 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1117 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1118 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret,
1119 arg1, 63 - arg2, 31 - arg2));
1120 } else {
1121 tcg_out_bundle(s, mII,
1122 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1123 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R2,
1124 0x1f, arg2),
1125 tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret,
1126 arg1, TCG_REG_R2));
1127 }
1128 }
1129
1130 static inline void tcg_out_shl_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1131 TCGArg arg2, int const_arg2)
1132 {
1133 if (const_arg2) {
1134 tcg_out_bundle(s, miI,
1135 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1136 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1137 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret,
1138 arg1, 63 - arg2, 63 - arg2));
1139 } else {
1140 tcg_out_bundle(s, miI,
1141 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1142 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1143 tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret,
1144 arg1, arg2));
1145 }
1146 }
1147
1148 static inline void tcg_out_shr_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1149 TCGArg arg2, int const_arg2)
1150 {
1151 if (const_arg2) {
1152 tcg_out_bundle(s, miI,
1153 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1154 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1155 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1156 arg1, arg2, 31 - arg2));
1157 } else {
1158 tcg_out_bundle(s, mII,
1159 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
1160 0x1f, arg2),
1161 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R2, arg1),
1162 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1163 TCG_REG_R2, TCG_REG_R3));
1164 }
1165 }
1166
1167 static inline void tcg_out_shr_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1168 TCGArg arg2, int const_arg2)
1169 {
1170 if (const_arg2) {
1171 tcg_out_bundle(s, miI,
1172 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1173 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1174 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1175 arg1, arg2, 63 - arg2));
1176 } else {
1177 tcg_out_bundle(s, miI,
1178 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1179 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1180 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1181 arg1, arg2));
1182 }
1183 }
1184
1185 static inline void tcg_out_rotl_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1186 TCGArg arg2, int const_arg2)
1187 {
1188 if (const_arg2) {
1189 tcg_out_bundle(s, mII,
1190 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1191 tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1192 TCG_REG_R2, arg1, arg1),
1193 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1194 TCG_REG_R2, 32 - arg2, 31));
1195 } else {
1196 tcg_out_bundle(s, miI,
1197 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1198 tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1199 TCG_REG_R2, arg1, arg1),
1200 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
1201 0x1f, arg2));
1202 tcg_out_bundle(s, mII,
1203 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1204 tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R3,
1205 0x20, TCG_REG_R3),
1206 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1207 TCG_REG_R2, TCG_REG_R3));
1208 }
1209 }
1210
1211 static inline void tcg_out_rotl_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1212 TCGArg arg2, int const_arg2)
1213 {
1214 if (const_arg2) {
1215 tcg_out_bundle(s, miI,
1216 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1217 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1218 tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1,
1219 arg1, 0x40 - arg2));
1220 } else {
1221 tcg_out_bundle(s, mII,
1222 tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2,
1223 0x40, arg2),
1224 tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R3,
1225 arg1, arg2),
1226 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R2,
1227 arg1, TCG_REG_R2));
1228 tcg_out_bundle(s, miI,
1229 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1230 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1231 tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret,
1232 TCG_REG_R2, TCG_REG_R3));
1233 }
1234 }
1235
1236 static inline void tcg_out_rotr_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1237 TCGArg arg2, int const_arg2)
1238 {
1239 if (const_arg2) {
1240 tcg_out_bundle(s, mII,
1241 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1242 tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1243 TCG_REG_R2, arg1, arg1),
1244 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1245 TCG_REG_R2, arg2, 31));
1246 } else {
1247 tcg_out_bundle(s, mII,
1248 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
1249 0x1f, arg2),
1250 tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1251 TCG_REG_R2, arg1, arg1),
1252 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1253 TCG_REG_R2, TCG_REG_R3));
1254 }
1255 }
1256
1257 static inline void tcg_out_rotr_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1258 TCGArg arg2, int const_arg2)
1259 {
1260 if (const_arg2) {
1261 tcg_out_bundle(s, miI,
1262 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1263 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1264 tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1,
1265 arg1, arg2));
1266 } else {
1267 tcg_out_bundle(s, mII,
1268 tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2,
1269 0x40, arg2),
1270 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R3,
1271 arg1, arg2),
1272 tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R2,
1273 arg1, TCG_REG_R2));
1274 tcg_out_bundle(s, miI,
1275 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1276 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1277 tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret,
1278 TCG_REG_R2, TCG_REG_R3));
1279 }
1280 }
1281
1282 static inline void tcg_out_ext(TCGContext *s, uint64_t opc_i29,
1283 TCGArg ret, TCGArg arg)
1284 {
1285 tcg_out_bundle(s, miI,
1286 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1287 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1288 tcg_opc_i29(TCG_REG_P0, opc_i29, ret, arg));
1289 }
1290
1291 static inline void tcg_out_bswap16(TCGContext *s, TCGArg ret, TCGArg arg)
1292 {
1293 tcg_out_bundle(s, mII,
1294 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1295 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 15, 15),
1296 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, ret, 0xb));
1297 }
1298
1299 static inline void tcg_out_bswap32(TCGContext *s, TCGArg ret, TCGArg arg)
1300 {
1301 tcg_out_bundle(s, mII,
1302 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1303 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 31, 31),
1304 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, ret, 0xb));
1305 }
1306
1307 static inline void tcg_out_bswap64(TCGContext *s, TCGArg ret, TCGArg arg)
1308 {
1309 tcg_out_bundle(s, miI,
1310 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1311 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1312 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, arg, 0xb));
1313 }
1314
1315 static inline uint64_t tcg_opc_cmp_a(int qp, TCGCond cond, TCGArg arg1,
1316 TCGArg arg2, int cmp4)
1317 {
1318 uint64_t opc_eq_a6, opc_lt_a6, opc_ltu_a6;
1319
1320 if (cmp4) {
1321 opc_eq_a6 = OPC_CMP4_EQ_A6;
1322 opc_lt_a6 = OPC_CMP4_LT_A6;
1323 opc_ltu_a6 = OPC_CMP4_LTU_A6;
1324 } else {
1325 opc_eq_a6 = OPC_CMP_EQ_A6;
1326 opc_lt_a6 = OPC_CMP_LT_A6;
1327 opc_ltu_a6 = OPC_CMP_LTU_A6;
1328 }
1329
1330 switch (cond) {
1331 case TCG_COND_EQ:
1332 return tcg_opc_a6 (qp, opc_eq_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
1333 case TCG_COND_NE:
1334 return tcg_opc_a6 (qp, opc_eq_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
1335 case TCG_COND_LT:
1336 return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
1337 case TCG_COND_LTU:
1338 return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
1339 case TCG_COND_GE:
1340 return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
1341 case TCG_COND_GEU:
1342 return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
1343 case TCG_COND_LE:
1344 return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P7, TCG_REG_P6, arg2, arg1);
1345 case TCG_COND_LEU:
1346 return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg2, arg1);
1347 case TCG_COND_GT:
1348 return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P6, TCG_REG_P7, arg2, arg1);
1349 case TCG_COND_GTU:
1350 return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg2, arg1);
1351 default:
1352 tcg_abort();
1353 break;
1354 }
1355 }
1356
1357 static inline void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGArg arg1,
1358 int const_arg1, TCGArg arg2, int const_arg2,
1359 int label_index, int cmp4)
1360 {
1361 TCGLabel *l = &s->labels[label_index];
1362 uint64_t opc1, opc2;
1363
1364 if (const_arg1 && arg1 != 0) {
1365 opc1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R2,
1366 arg1, TCG_REG_R0);
1367 arg1 = TCG_REG_R2;
1368 } else {
1369 opc1 = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
1370 }
1371
1372 if (const_arg2 && arg2 != 0) {
1373 opc2 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R3,
1374 arg2, TCG_REG_R0);
1375 arg2 = TCG_REG_R3;
1376 } else {
1377 opc2 = tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0);
1378 }
1379
1380 tcg_out_bundle(s, mII,
1381 opc1,
1382 opc2,
1383 tcg_opc_cmp_a(TCG_REG_P0, cond, arg1, arg2, cmp4));
1384 tcg_out_bundle(s, mmB,
1385 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1386 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1387 tcg_opc_b1 (TCG_REG_P6, OPC_BR_DPTK_FEW_B1,
1388 get_reloc_pcrel21b(s->code_ptr + 2)));
1389
1390 if (l->has_value) {
1391 reloc_pcrel21b((s->code_ptr - 16) + 2, l->u.value);
1392 } else {
1393 tcg_out_reloc(s, (s->code_ptr - 16) + 2,
1394 R_IA64_PCREL21B, label_index, 0);
1395 }
1396 }
1397
1398 static inline void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGArg ret,
1399 TCGArg arg1, TCGArg arg2, int cmp4)
1400 {
1401 tcg_out_bundle(s, MmI,
1402 tcg_opc_cmp_a(TCG_REG_P0, cond, arg1, arg2, cmp4),
1403 tcg_opc_a5(TCG_REG_P6, OPC_ADDL_A5, ret, 1, TCG_REG_R0),
1404 tcg_opc_a5(TCG_REG_P7, OPC_ADDL_A5, ret, 0, TCG_REG_R0));
1405 }
1406
1407 static inline void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGArg ret,
1408 TCGArg c1, TCGArg c2,
1409 TCGArg v1, int const_v1,
1410 TCGArg v2, int const_v2, int cmp4)
1411 {
1412 uint64_t opc1, opc2;
1413
1414 if (const_v1) {
1415 opc1 = tcg_opc_a5(TCG_REG_P6, OPC_ADDL_A5, ret, v1, TCG_REG_R0);
1416 } else if (ret == v1) {
1417 opc1 = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
1418 } else {
1419 opc1 = tcg_opc_a4(TCG_REG_P6, OPC_ADDS_A4, ret, 0, v1);
1420 }
1421 if (const_v2) {
1422 opc2 = tcg_opc_a5(TCG_REG_P7, OPC_ADDL_A5, ret, v2, TCG_REG_R0);
1423 } else if (ret == v2) {
1424 opc2 = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
1425 } else {
1426 opc2 = tcg_opc_a4(TCG_REG_P7, OPC_ADDS_A4, ret, 0, v2);
1427 }
1428
1429 tcg_out_bundle(s, MmI,
1430 tcg_opc_cmp_a(TCG_REG_P0, cond, c1, c2, cmp4),
1431 opc1,
1432 opc2);
1433 }
1434
1435 #if defined(CONFIG_SOFTMMU)
1436
1437 #include "../../softmmu_defs.h"
1438
1439 /* Load and compare a TLB entry, and return the result in (p6, p7).
1440 R2 is loaded with the address of the addend TLB entry.
1441 R57 is loaded with the address, zero extented on 32-bit targets. */
1442 static inline void tcg_out_qemu_tlb(TCGContext *s, TCGArg addr_reg,
1443 int s_bits, uint64_t offset_rw,
1444 uint64_t offset_addend)
1445 {
1446 tcg_out_bundle(s, mII,
1447 tcg_opc_a5 (TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R3,
1448 TARGET_PAGE_MASK | ((1 << s_bits) - 1),
1449 TCG_REG_R0),
1450 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, TCG_REG_R2,
1451 addr_reg, TARGET_PAGE_BITS, CPU_TLB_BITS - 1),
1452 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, TCG_REG_R2,
1453 TCG_REG_R2, 63 - CPU_TLB_ENTRY_BITS,
1454 63 - CPU_TLB_ENTRY_BITS));
1455 tcg_out_bundle(s, mII,
1456 tcg_opc_a5 (TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R2,
1457 offset_rw, TCG_REG_R2),
1458 #if TARGET_LONG_BITS == 32
1459 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R57, addr_reg),
1460 #else
1461 tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R57,
1462 0, addr_reg),
1463 #endif
1464 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1465 TCG_REG_R2, TCG_AREG0));
1466 tcg_out_bundle(s, mII,
1467 tcg_opc_m3 (TCG_REG_P0,
1468 (TARGET_LONG_BITS == 32
1469 ? OPC_LD4_M3 : OPC_LD8_M3), TCG_REG_R56,
1470 TCG_REG_R2, offset_addend - offset_rw),
1471 tcg_opc_a1 (TCG_REG_P0, OPC_AND_A1, TCG_REG_R3,
1472 TCG_REG_R3, TCG_REG_R57),
1473 tcg_opc_a6 (TCG_REG_P0, OPC_CMP_EQ_A6, TCG_REG_P6,
1474 TCG_REG_P7, TCG_REG_R3, TCG_REG_R56));
1475 }
1476
1477 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
1478 int mmu_idx) */
1479 static const void * const qemu_ld_helpers[4] = {
1480 helper_ldb_mmu,
1481 helper_ldw_mmu,
1482 helper_ldl_mmu,
1483 helper_ldq_mmu,
1484 };
1485
1486 static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
1487 {
1488 int addr_reg, data_reg, mem_index, s_bits, bswap;
1489 uint64_t opc_ld_m1[4] = { OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1 };
1490 uint64_t opc_ext_i29[8] = { OPC_ZXT1_I29, OPC_ZXT2_I29, OPC_ZXT4_I29, 0,
1491 OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0 };
1492
1493 data_reg = *args++;
1494 addr_reg = *args++;
1495 mem_index = *args;
1496 s_bits = opc & 3;
1497
1498 #ifdef TARGET_WORDS_BIGENDIAN
1499 bswap = 1;
1500 #else
1501 bswap = 0;
1502 #endif
1503
1504 /* Read the TLB entry */
1505 tcg_out_qemu_tlb(s, addr_reg, s_bits,
1506 offsetof(CPUArchState, tlb_table[mem_index][0].addr_read),
1507 offsetof(CPUArchState, tlb_table[mem_index][0].addend));
1508
1509 /* P6 is the fast path, and P7 the slow path */
1510 tcg_out_bundle(s, mLX,
1511 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4,
1512 TCG_REG_R56, 0, TCG_AREG0),
1513 tcg_opc_l2 ((tcg_target_long) qemu_ld_helpers[s_bits]),
1514 tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2,
1515 (tcg_target_long) qemu_ld_helpers[s_bits]));
1516 tcg_out_bundle(s, MmI,
1517 tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3,
1518 TCG_REG_R2, 8),
1519 tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3,
1520 TCG_REG_R3, TCG_REG_R57),
1521 tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6,
1522 TCG_REG_R3, 0));
1523 if (bswap && s_bits == 1) {
1524 tcg_out_bundle(s, MmI,
1525 tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
1526 TCG_REG_R8, TCG_REG_R3),
1527 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
1528 tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1529 TCG_REG_R8, TCG_REG_R8, 15, 15));
1530 } else if (bswap && s_bits == 2) {
1531 tcg_out_bundle(s, MmI,
1532 tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
1533 TCG_REG_R8, TCG_REG_R3),
1534 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
1535 tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1536 TCG_REG_R8, TCG_REG_R8, 31, 31));
1537 } else {
1538 tcg_out_bundle(s, mmI,
1539 tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
1540 TCG_REG_R8, TCG_REG_R3),
1541 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
1542 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1543 }
1544 if (!bswap || s_bits == 0) {
1545 tcg_out_bundle(s, miB,
1546 tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58,
1547 mem_index, TCG_REG_R0),
1548 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1549 tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
1550 TCG_REG_B0, TCG_REG_B6));
1551 } else {
1552 tcg_out_bundle(s, miB,
1553 tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58,
1554 mem_index, TCG_REG_R0),
1555 tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1556 TCG_REG_R8, TCG_REG_R8, 0xb),
1557 tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
1558 TCG_REG_B0, TCG_REG_B6));
1559 }
1560
1561 if (opc == 3) {
1562 tcg_out_bundle(s, miI,
1563 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1564 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1565 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
1566 data_reg, 0, TCG_REG_R8));
1567 } else {
1568 tcg_out_bundle(s, miI,
1569 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1570 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1571 tcg_opc_i29(TCG_REG_P0, opc_ext_i29[opc],
1572 data_reg, TCG_REG_R8));
1573 }
1574 }
1575
1576 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
1577 uintxx_t val, int mmu_idx) */
1578 static const void * const qemu_st_helpers[4] = {
1579 helper_stb_mmu,
1580 helper_stw_mmu,
1581 helper_stl_mmu,
1582 helper_stq_mmu,
1583 };
1584
1585 static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
1586 {
1587 int addr_reg, data_reg, mem_index, bswap;
1588 uint64_t opc_st_m4[4] = { OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4 };
1589
1590 data_reg = *args++;
1591 addr_reg = *args++;
1592 mem_index = *args;
1593
1594 #ifdef TARGET_WORDS_BIGENDIAN
1595 bswap = 1;
1596 #else
1597 bswap = 0;
1598 #endif
1599
1600 tcg_out_qemu_tlb(s, addr_reg, opc,
1601 offsetof(CPUArchState, tlb_table[mem_index][0].addr_write),
1602 offsetof(CPUArchState, tlb_table[mem_index][0].addend));
1603
1604 /* P6 is the fast path, and P7 the slow path */
1605 tcg_out_bundle(s, mLX,
1606 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4,
1607 TCG_REG_R56, 0, TCG_AREG0),
1608 tcg_opc_l2 ((tcg_target_long) qemu_st_helpers[opc]),
1609 tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2,
1610 (tcg_target_long) qemu_st_helpers[opc]));
1611 tcg_out_bundle(s, MmI,
1612 tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3,
1613 TCG_REG_R2, 8),
1614 tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3,
1615 TCG_REG_R3, TCG_REG_R57),
1616 tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6,
1617 TCG_REG_R3, 0));
1618
1619 if (!bswap || opc == 0) {
1620 tcg_out_bundle(s, mii,
1621 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1622 TCG_REG_R1, TCG_REG_R2),
1623 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58,
1624 0, data_reg),
1625 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1626 } else if (opc == 1) {
1627 tcg_out_bundle(s, miI,
1628 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1629 TCG_REG_R1, TCG_REG_R2),
1630 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1631 tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1632 TCG_REG_R2, data_reg, 15, 15));
1633 tcg_out_bundle(s, miI,
1634 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58,
1635 0, data_reg),
1636 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1637 tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1638 TCG_REG_R2, TCG_REG_R2, 0xb));
1639 data_reg = TCG_REG_R2;
1640 } else if (opc == 2) {
1641 tcg_out_bundle(s, miI,
1642 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1643 TCG_REG_R1, TCG_REG_R2),
1644 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1645 tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1646 TCG_REG_R2, data_reg, 31, 31));
1647 tcg_out_bundle(s, miI,
1648 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58,
1649 0, data_reg),
1650 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1651 tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1652 TCG_REG_R2, TCG_REG_R2, 0xb));
1653 data_reg = TCG_REG_R2;
1654 } else if (opc == 3) {
1655 tcg_out_bundle(s, miI,
1656 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1657 TCG_REG_R1, TCG_REG_R2),
1658 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58,
1659 0, data_reg),
1660 tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1661 TCG_REG_R2, data_reg, 0xb));
1662 data_reg = TCG_REG_R2;
1663 }
1664
1665 tcg_out_bundle(s, miB,
1666 tcg_opc_m4 (TCG_REG_P6, opc_st_m4[opc],
1667 data_reg, TCG_REG_R3),
1668 tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R59,
1669 mem_index, TCG_REG_R0),
1670 tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
1671 TCG_REG_B0, TCG_REG_B6));
1672 }
1673
1674 #else /* !CONFIG_SOFTMMU */
1675
1676 static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
1677 {
1678 static uint64_t const opc_ld_m1[4] = {
1679 OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1
1680 };
1681 static uint64_t const opc_sxt_i29[4] = {
1682 OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0
1683 };
1684 int addr_reg, data_reg, s_bits, bswap;
1685
1686 data_reg = *args++;
1687 addr_reg = *args++;
1688 s_bits = opc & 3;
1689
1690 #ifdef TARGET_WORDS_BIGENDIAN
1691 bswap = 1;
1692 #else
1693 bswap = 0;
1694 #endif
1695
1696 #if TARGET_LONG_BITS == 32
1697 if (GUEST_BASE != 0) {
1698 tcg_out_bundle(s, mII,
1699 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1700 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1701 TCG_REG_R3, addr_reg),
1702 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1703 TCG_GUEST_BASE_REG, TCG_REG_R3));
1704 } else {
1705 tcg_out_bundle(s, miI,
1706 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1707 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1708 TCG_REG_R2, addr_reg),
1709 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1710 }
1711
1712 if (!bswap || s_bits == 0) {
1713 if (s_bits == opc) {
1714 tcg_out_bundle(s, miI,
1715 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1716 data_reg, TCG_REG_R2),
1717 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1718 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1719 } else {
1720 tcg_out_bundle(s, mII,
1721 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1722 data_reg, TCG_REG_R2),
1723 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1724 tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits],
1725 data_reg, data_reg));
1726 }
1727 } else if (s_bits == 3) {
1728 tcg_out_bundle(s, mII,
1729 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1730 data_reg, TCG_REG_R2),
1731 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1732 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1733 data_reg, data_reg, 0xb));
1734 } else {
1735 if (s_bits == 1) {
1736 tcg_out_bundle(s, mII,
1737 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1738 data_reg, TCG_REG_R2),
1739 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1740 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1741 data_reg, data_reg, 15, 15));
1742 } else {
1743 tcg_out_bundle(s, mII,
1744 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1745 data_reg, TCG_REG_R2),
1746 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1747 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1748 data_reg, data_reg, 31, 31));
1749 }
1750 if (opc == s_bits) {
1751 tcg_out_bundle(s, miI,
1752 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1753 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1754 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1755 data_reg, data_reg, 0xb));
1756 } else {
1757 tcg_out_bundle(s, mII,
1758 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1759 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1760 data_reg, data_reg, 0xb),
1761 tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits],
1762 data_reg, data_reg));
1763 }
1764 }
1765 #else
1766 if (GUEST_BASE != 0) {
1767 tcg_out_bundle(s, MmI,
1768 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1769 TCG_GUEST_BASE_REG, addr_reg),
1770 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1771 data_reg, TCG_REG_R2),
1772 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1773 } else {
1774 tcg_out_bundle(s, mmI,
1775 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1776 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1777 data_reg, addr_reg),
1778 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1779 }
1780
1781 if (bswap && s_bits == 1) {
1782 tcg_out_bundle(s, mII,
1783 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1784 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1785 data_reg, data_reg, 15, 15),
1786 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1787 data_reg, data_reg, 0xb));
1788 } else if (bswap && s_bits == 2) {
1789 tcg_out_bundle(s, mII,
1790 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1791 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1792 data_reg, data_reg, 31, 31),
1793 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1794 data_reg, data_reg, 0xb));
1795 } else if (bswap && s_bits == 3) {
1796 tcg_out_bundle(s, miI,
1797 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1798 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1799 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1800 data_reg, data_reg, 0xb));
1801 }
1802 if (s_bits != opc) {
1803 tcg_out_bundle(s, miI,
1804 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1805 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1806 tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits],
1807 data_reg, data_reg));
1808 }
1809 #endif
1810 }
1811
1812 static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
1813 {
1814 static uint64_t const opc_st_m4[4] = {
1815 OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4
1816 };
1817 int addr_reg, data_reg, bswap;
1818 #if TARGET_LONG_BITS == 64
1819 uint64_t add_guest_base;
1820 #endif
1821
1822 data_reg = *args++;
1823 addr_reg = *args++;
1824
1825 #ifdef TARGET_WORDS_BIGENDIAN
1826 bswap = 1;
1827 #else
1828 bswap = 0;
1829 #endif
1830
1831 #if TARGET_LONG_BITS == 32
1832 if (GUEST_BASE != 0) {
1833 tcg_out_bundle(s, mII,
1834 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1835 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1836 TCG_REG_R3, addr_reg),
1837 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1838 TCG_GUEST_BASE_REG, TCG_REG_R3));
1839 } else {
1840 tcg_out_bundle(s, miI,
1841 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1842 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1843 TCG_REG_R2, addr_reg),
1844 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1845 }
1846
1847 if (bswap) {
1848 if (opc == 1) {
1849 tcg_out_bundle(s, mII,
1850 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1851 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1852 TCG_REG_R3, data_reg, 15, 15),
1853 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1854 TCG_REG_R3, TCG_REG_R3, 0xb));
1855 data_reg = TCG_REG_R3;
1856 } else if (opc == 2) {
1857 tcg_out_bundle(s, mII,
1858 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1859 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1860 TCG_REG_R3, data_reg, 31, 31),
1861 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1862 TCG_REG_R3, TCG_REG_R3, 0xb));
1863 data_reg = TCG_REG_R3;
1864 } else if (opc == 3) {
1865 tcg_out_bundle(s, miI,
1866 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1867 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1868 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1869 TCG_REG_R3, data_reg, 0xb));
1870 data_reg = TCG_REG_R3;
1871 }
1872 }
1873 tcg_out_bundle(s, mmI,
1874 tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc],
1875 data_reg, TCG_REG_R2),
1876 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1877 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1878 #else
1879 if (GUEST_BASE != 0) {
1880 add_guest_base = tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1881 TCG_GUEST_BASE_REG, addr_reg);
1882 addr_reg = TCG_REG_R2;
1883 } else {
1884 add_guest_base = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
1885 }
1886
1887 if (!bswap || opc == 0) {
1888 tcg_out_bundle(s, (GUEST_BASE ? MmI : mmI),
1889 add_guest_base,
1890 tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc],
1891 data_reg, addr_reg),
1892 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1893 } else {
1894 if (opc == 1) {
1895 tcg_out_bundle(s, mII,
1896 add_guest_base,
1897 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1898 TCG_REG_R3, data_reg, 15, 15),
1899 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1900 TCG_REG_R3, TCG_REG_R3, 0xb));
1901 data_reg = TCG_REG_R3;
1902 } else if (opc == 2) {
1903 tcg_out_bundle(s, mII,
1904 add_guest_base,
1905 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1906 TCG_REG_R3, data_reg, 31, 31),
1907 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1908 TCG_REG_R3, TCG_REG_R3, 0xb));
1909 data_reg = TCG_REG_R3;
1910 } else if (opc == 3) {
1911 tcg_out_bundle(s, miI,
1912 add_guest_base,
1913 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1914 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1915 TCG_REG_R3, data_reg, 0xb));
1916 data_reg = TCG_REG_R3;
1917 }
1918 tcg_out_bundle(s, miI,
1919 tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc],
1920 data_reg, addr_reg),
1921 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1922 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1923 }
1924 #endif
1925 }
1926
1927 #endif
1928
1929 static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
1930 const TCGArg *args, const int *const_args)
1931 {
1932 switch(opc) {
1933 case INDEX_op_exit_tb:
1934 tcg_out_exit_tb(s, args[0]);
1935 break;
1936 case INDEX_op_br:
1937 tcg_out_br(s, args[0]);
1938 break;
1939 case INDEX_op_call:
1940 tcg_out_call(s, args[0]);
1941 break;
1942 case INDEX_op_goto_tb:
1943 tcg_out_goto_tb(s, args[0]);
1944 break;
1945
1946 case INDEX_op_movi_i32:
1947 tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
1948 break;
1949 case INDEX_op_movi_i64:
1950 tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
1951 break;
1952
1953 case INDEX_op_ld8u_i32:
1954 case INDEX_op_ld8u_i64:
1955 tcg_out_ld_rel(s, OPC_LD1_M1, args[0], args[1], args[2]);
1956 break;
1957 case INDEX_op_ld8s_i32:
1958 case INDEX_op_ld8s_i64:
1959 tcg_out_ld_rel(s, OPC_LD1_M1, args[0], args[1], args[2]);
1960 tcg_out_ext(s, OPC_SXT1_I29, args[0], args[0]);
1961 break;
1962 case INDEX_op_ld16u_i32:
1963 case INDEX_op_ld16u_i64:
1964 tcg_out_ld_rel(s, OPC_LD2_M1, args[0], args[1], args[2]);
1965 break;
1966 case INDEX_op_ld16s_i32:
1967 case INDEX_op_ld16s_i64:
1968 tcg_out_ld_rel(s, OPC_LD2_M1, args[0], args[1], args[2]);
1969 tcg_out_ext(s, OPC_SXT2_I29, args[0], args[0]);
1970 break;
1971 case INDEX_op_ld_i32:
1972 case INDEX_op_ld32u_i64:
1973 tcg_out_ld_rel(s, OPC_LD4_M1, args[0], args[1], args[2]);
1974 break;
1975 case INDEX_op_ld32s_i64:
1976 tcg_out_ld_rel(s, OPC_LD4_M1, args[0], args[1], args[2]);
1977 tcg_out_ext(s, OPC_SXT4_I29, args[0], args[0]);
1978 break;
1979 case INDEX_op_ld_i64:
1980 tcg_out_ld_rel(s, OPC_LD8_M1, args[0], args[1], args[2]);
1981 break;
1982 case INDEX_op_st8_i32:
1983 case INDEX_op_st8_i64:
1984 tcg_out_st_rel(s, OPC_ST1_M4, args[0], args[1], args[2]);
1985 break;
1986 case INDEX_op_st16_i32:
1987 case INDEX_op_st16_i64:
1988 tcg_out_st_rel(s, OPC_ST2_M4, args[0], args[1], args[2]);
1989 break;
1990 case INDEX_op_st_i32:
1991 case INDEX_op_st32_i64:
1992 tcg_out_st_rel(s, OPC_ST4_M4, args[0], args[1], args[2]);
1993 break;
1994 case INDEX_op_st_i64:
1995 tcg_out_st_rel(s, OPC_ST8_M4, args[0], args[1], args[2]);
1996 break;
1997
1998 case INDEX_op_add_i32:
1999 case INDEX_op_add_i64:
2000 tcg_out_alu(s, OPC_ADD_A1, args[0], args[1], const_args[1],
2001 args[2], const_args[2]);
2002 break;
2003 case INDEX_op_sub_i32:
2004 case INDEX_op_sub_i64:
2005 tcg_out_alu(s, OPC_SUB_A1, args[0], args[1], const_args[1],
2006 args[2], const_args[2]);
2007 break;
2008
2009 case INDEX_op_and_i32:
2010 case INDEX_op_and_i64:
2011 tcg_out_alu(s, OPC_AND_A1, args[0], args[1], const_args[1],
2012 args[2], const_args[2]);
2013 break;
2014 case INDEX_op_andc_i32:
2015 case INDEX_op_andc_i64:
2016 tcg_out_alu(s, OPC_ANDCM_A1, args[0], args[1], const_args[1],
2017 args[2], const_args[2]);
2018 break;
2019 case INDEX_op_eqv_i32:
2020 case INDEX_op_eqv_i64:
2021 tcg_out_eqv(s, args[0], args[1], const_args[1],
2022 args[2], const_args[2]);
2023 break;
2024 case INDEX_op_nand_i32:
2025 case INDEX_op_nand_i64:
2026 tcg_out_nand(s, args[0], args[1], const_args[1],
2027 args[2], const_args[2]);
2028 break;
2029 case INDEX_op_nor_i32:
2030 case INDEX_op_nor_i64:
2031 tcg_out_nor(s, args[0], args[1], const_args[1],
2032 args[2], const_args[2]);
2033 break;
2034 case INDEX_op_or_i32:
2035 case INDEX_op_or_i64:
2036 tcg_out_alu(s, OPC_OR_A1, args[0], args[1], const_args[1],
2037 args[2], const_args[2]);
2038 break;
2039 case INDEX_op_orc_i32:
2040 case INDEX_op_orc_i64:
2041 tcg_out_orc(s, args[0], args[1], const_args[1],
2042 args[2], const_args[2]);
2043 break;
2044 case INDEX_op_xor_i32:
2045 case INDEX_op_xor_i64:
2046 tcg_out_alu(s, OPC_XOR_A1, args[0], args[1], const_args[1],
2047 args[2], const_args[2]);
2048 break;
2049
2050 case INDEX_op_mul_i32:
2051 case INDEX_op_mul_i64:
2052 tcg_out_mul(s, args[0], args[1], args[2]);
2053 break;
2054
2055 case INDEX_op_sar_i32:
2056 tcg_out_sar_i32(s, args[0], args[1], args[2], const_args[2]);
2057 break;
2058 case INDEX_op_sar_i64:
2059 tcg_out_sar_i64(s, args[0], args[1], args[2], const_args[2]);
2060 break;
2061 case INDEX_op_shl_i32:
2062 tcg_out_shl_i32(s, args[0], args[1], args[2], const_args[2]);
2063 break;
2064 case INDEX_op_shl_i64:
2065 tcg_out_shl_i64(s, args[0], args[1], args[2], const_args[2]);
2066 break;
2067 case INDEX_op_shr_i32:
2068 tcg_out_shr_i32(s, args[0], args[1], args[2], const_args[2]);
2069 break;
2070 case INDEX_op_shr_i64:
2071 tcg_out_shr_i64(s, args[0], args[1], args[2], const_args[2]);
2072 break;
2073 case INDEX_op_rotl_i32:
2074 tcg_out_rotl_i32(s, args[0], args[1], args[2], const_args[2]);
2075 break;
2076 case INDEX_op_rotl_i64:
2077 tcg_out_rotl_i64(s, args[0], args[1], args[2], const_args[2]);
2078 break;
2079 case INDEX_op_rotr_i32:
2080 tcg_out_rotr_i32(s, args[0], args[1], args[2], const_args[2]);
2081 break;
2082 case INDEX_op_rotr_i64:
2083 tcg_out_rotr_i64(s, args[0], args[1], args[2], const_args[2]);
2084 break;
2085
2086 case INDEX_op_ext8s_i32:
2087 case INDEX_op_ext8s_i64:
2088 tcg_out_ext(s, OPC_SXT1_I29, args[0], args[1]);
2089 break;
2090 case INDEX_op_ext8u_i32:
2091 case INDEX_op_ext8u_i64:
2092 tcg_out_ext(s, OPC_ZXT1_I29, args[0], args[1]);
2093 break;
2094 case INDEX_op_ext16s_i32:
2095 case INDEX_op_ext16s_i64:
2096 tcg_out_ext(s, OPC_SXT2_I29, args[0], args[1]);
2097 break;
2098 case INDEX_op_ext16u_i32:
2099 case INDEX_op_ext16u_i64:
2100 tcg_out_ext(s, OPC_ZXT2_I29, args[0], args[1]);
2101 break;
2102 case INDEX_op_ext32s_i64:
2103 tcg_out_ext(s, OPC_SXT4_I29, args[0], args[1]);
2104 break;
2105 case INDEX_op_ext32u_i64:
2106 tcg_out_ext(s, OPC_ZXT4_I29, args[0], args[1]);
2107 break;
2108
2109 case INDEX_op_bswap16_i32:
2110 case INDEX_op_bswap16_i64:
2111 tcg_out_bswap16(s, args[0], args[1]);
2112 break;
2113 case INDEX_op_bswap32_i32:
2114 case INDEX_op_bswap32_i64:
2115 tcg_out_bswap32(s, args[0], args[1]);
2116 break;
2117 case INDEX_op_bswap64_i64:
2118 tcg_out_bswap64(s, args[0], args[1]);
2119 break;
2120
2121 case INDEX_op_brcond_i32:
2122 tcg_out_brcond(s, args[2], args[0], const_args[0],
2123 args[1], const_args[1], args[3], 1);
2124 break;
2125 case INDEX_op_brcond_i64:
2126 tcg_out_brcond(s, args[2], args[0], const_args[0],
2127 args[1], const_args[1], args[3], 0);
2128 break;
2129 case INDEX_op_setcond_i32:
2130 tcg_out_setcond(s, args[3], args[0], args[1], args[2], 1);
2131 break;
2132 case INDEX_op_setcond_i64:
2133 tcg_out_setcond(s, args[3], args[0], args[1], args[2], 0);
2134 break;
2135 case INDEX_op_movcond_i32:
2136 tcg_out_movcond(s, args[5], args[0], args[1], args[2],
2137 args[3], const_args[3], args[4], const_args[4], 1);
2138 break;
2139 case INDEX_op_movcond_i64:
2140 tcg_out_movcond(s, args[5], args[0], args[1], args[2],
2141 args[3], const_args[3], args[4], const_args[4], 0);
2142 break;
2143
2144 case INDEX_op_qemu_ld8u:
2145 tcg_out_qemu_ld(s, args, 0);
2146 break;
2147 case INDEX_op_qemu_ld8s:
2148 tcg_out_qemu_ld(s, args, 0 | 4);
2149 break;
2150 case INDEX_op_qemu_ld16u:
2151 tcg_out_qemu_ld(s, args, 1);
2152 break;
2153 case INDEX_op_qemu_ld16s:
2154 tcg_out_qemu_ld(s, args, 1 | 4);
2155 break;
2156 case INDEX_op_qemu_ld32:
2157 case INDEX_op_qemu_ld32u:
2158 tcg_out_qemu_ld(s, args, 2);
2159 break;
2160 case INDEX_op_qemu_ld32s:
2161 tcg_out_qemu_ld(s, args, 2 | 4);
2162 break;
2163 case INDEX_op_qemu_ld64:
2164 tcg_out_qemu_ld(s, args, 3);
2165 break;
2166
2167 case INDEX_op_qemu_st8:
2168 tcg_out_qemu_st(s, args, 0);
2169 break;
2170 case INDEX_op_qemu_st16:
2171 tcg_out_qemu_st(s, args, 1);
2172 break;
2173 case INDEX_op_qemu_st32:
2174 tcg_out_qemu_st(s, args, 2);
2175 break;
2176 case INDEX_op_qemu_st64:
2177 tcg_out_qemu_st(s, args, 3);
2178 break;
2179
2180 default:
2181 tcg_abort();
2182 }
2183 }
2184
2185 static const TCGTargetOpDef ia64_op_defs[] = {
2186 { INDEX_op_br, { } },
2187 { INDEX_op_call, { "r" } },
2188 { INDEX_op_exit_tb, { } },
2189 { INDEX_op_goto_tb, { } },
2190
2191 { INDEX_op_mov_i32, { "r", "r" } },
2192 { INDEX_op_movi_i32, { "r" } },
2193
2194 { INDEX_op_ld8u_i32, { "r", "r" } },
2195 { INDEX_op_ld8s_i32, { "r", "r" } },
2196 { INDEX_op_ld16u_i32, { "r", "r" } },
2197 { INDEX_op_ld16s_i32, { "r", "r" } },
2198 { INDEX_op_ld_i32, { "r", "r" } },
2199 { INDEX_op_st8_i32, { "rZ", "r" } },
2200 { INDEX_op_st16_i32, { "rZ", "r" } },
2201 { INDEX_op_st_i32, { "rZ", "r" } },
2202
2203 { INDEX_op_add_i32, { "r", "rI", "rI" } },
2204 { INDEX_op_sub_i32, { "r", "rI", "rI" } },
2205
2206 { INDEX_op_and_i32, { "r", "rI", "rI" } },
2207 { INDEX_op_andc_i32, { "r", "rI", "rI" } },
2208 { INDEX_op_eqv_i32, { "r", "rZ", "rZ" } },
2209 { INDEX_op_nand_i32, { "r", "rZ", "rZ" } },
2210 { INDEX_op_nor_i32, { "r", "rZ", "rZ" } },
2211 { INDEX_op_or_i32, { "r", "rI", "rI" } },
2212 { INDEX_op_orc_i32, { "r", "rZ", "rZ" } },
2213 { INDEX_op_xor_i32, { "r", "rI", "rI" } },
2214
2215 { INDEX_op_mul_i32, { "r", "rZ", "rZ" } },
2216
2217 { INDEX_op_sar_i32, { "r", "rZ", "ri" } },
2218 { INDEX_op_shl_i32, { "r", "rZ", "ri" } },
2219 { INDEX_op_shr_i32, { "r", "rZ", "ri" } },
2220 { INDEX_op_rotl_i32, { "r", "rZ", "ri" } },
2221 { INDEX_op_rotr_i32, { "r", "rZ", "ri" } },
2222
2223 { INDEX_op_ext8s_i32, { "r", "rZ"} },
2224 { INDEX_op_ext8u_i32, { "r", "rZ"} },
2225 { INDEX_op_ext16s_i32, { "r", "rZ"} },
2226 { INDEX_op_ext16u_i32, { "r", "rZ"} },
2227
2228 { INDEX_op_bswap16_i32, { "r", "rZ" } },
2229 { INDEX_op_bswap32_i32, { "r", "rZ" } },
2230
2231 { INDEX_op_brcond_i32, { "rI", "rI" } },
2232 { INDEX_op_setcond_i32, { "r", "rZ", "rZ" } },
2233 { INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rI", "rI" } },
2234
2235 { INDEX_op_mov_i64, { "r", "r" } },
2236 { INDEX_op_movi_i64, { "r" } },
2237
2238 { INDEX_op_ld8u_i64, { "r", "r" } },
2239 { INDEX_op_ld8s_i64, { "r", "r" } },
2240 { INDEX_op_ld16u_i64, { "r", "r" } },
2241 { INDEX_op_ld16s_i64, { "r", "r" } },
2242 { INDEX_op_ld32u_i64, { "r", "r" } },
2243 { INDEX_op_ld32s_i64, { "r", "r" } },
2244 { INDEX_op_ld_i64, { "r", "r" } },
2245 { INDEX_op_st8_i64, { "rZ", "r" } },
2246 { INDEX_op_st16_i64, { "rZ", "r" } },
2247 { INDEX_op_st32_i64, { "rZ", "r" } },
2248 { INDEX_op_st_i64, { "rZ", "r" } },
2249
2250 { INDEX_op_add_i64, { "r", "rI", "rI" } },
2251 { INDEX_op_sub_i64, { "r", "rI", "rI" } },
2252
2253 { INDEX_op_and_i64, { "r", "rI", "rI" } },
2254 { INDEX_op_andc_i64, { "r", "rI", "rI" } },
2255 { INDEX_op_eqv_i64, { "r", "rZ", "rZ" } },
2256 { INDEX_op_nand_i64, { "r", "rZ", "rZ" } },
2257 { INDEX_op_nor_i64, { "r", "rZ", "rZ" } },
2258 { INDEX_op_or_i64, { "r", "rI", "rI" } },
2259 { INDEX_op_orc_i64, { "r", "rZ", "rZ" } },
2260 { INDEX_op_xor_i64, { "r", "rI", "rI" } },
2261
2262 { INDEX_op_mul_i64, { "r", "rZ", "rZ" } },
2263
2264 { INDEX_op_sar_i64, { "r", "rZ", "ri" } },
2265 { INDEX_op_shl_i64, { "r", "rZ", "ri" } },
2266 { INDEX_op_shr_i64, { "r", "rZ", "ri" } },
2267 { INDEX_op_rotl_i64, { "r", "rZ", "ri" } },
2268 { INDEX_op_rotr_i64, { "r", "rZ", "ri" } },
2269
2270 { INDEX_op_ext8s_i64, { "r", "rZ"} },
2271 { INDEX_op_ext8u_i64, { "r", "rZ"} },
2272 { INDEX_op_ext16s_i64, { "r", "rZ"} },
2273 { INDEX_op_ext16u_i64, { "r", "rZ"} },
2274 { INDEX_op_ext32s_i64, { "r", "rZ"} },
2275 { INDEX_op_ext32u_i64, { "r", "rZ"} },
2276
2277 { INDEX_op_bswap16_i64, { "r", "rZ" } },
2278 { INDEX_op_bswap32_i64, { "r", "rZ" } },
2279 { INDEX_op_bswap64_i64, { "r", "rZ" } },
2280
2281 { INDEX_op_brcond_i64, { "rI", "rI" } },
2282 { INDEX_op_setcond_i64, { "r", "rZ", "rZ" } },
2283 { INDEX_op_movcond_i64, { "r", "rZ", "rZ", "rI", "rI" } },
2284
2285 { INDEX_op_qemu_ld8u, { "r", "r" } },
2286 { INDEX_op_qemu_ld8s, { "r", "r" } },
2287 { INDEX_op_qemu_ld16u, { "r", "r" } },
2288 { INDEX_op_qemu_ld16s, { "r", "r" } },
2289 { INDEX_op_qemu_ld32, { "r", "r" } },
2290 { INDEX_op_qemu_ld32u, { "r", "r" } },
2291 { INDEX_op_qemu_ld32s, { "r", "r" } },
2292 { INDEX_op_qemu_ld64, { "r", "r" } },
2293
2294 { INDEX_op_qemu_st8, { "SZ", "r" } },
2295 { INDEX_op_qemu_st16, { "SZ", "r" } },
2296 { INDEX_op_qemu_st32, { "SZ", "r" } },
2297 { INDEX_op_qemu_st64, { "SZ", "r" } },
2298
2299 { -1 },
2300 };
2301
2302 /* Generate global QEMU prologue and epilogue code */
2303 static void tcg_target_qemu_prologue(TCGContext *s)
2304 {
2305 int frame_size;
2306
2307 /* reserve some stack space */
2308 frame_size = TCG_STATIC_CALL_ARGS_SIZE +
2309 CPU_TEMP_BUF_NLONGS * sizeof(long);
2310 frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
2311 ~(TCG_TARGET_STACK_ALIGN - 1);
2312 tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE,
2313 CPU_TEMP_BUF_NLONGS * sizeof(long));
2314
2315 /* First emit adhoc function descriptor */
2316 *(uint64_t *)(s->code_ptr) = (uint64_t)s->code_ptr + 16; /* entry point */
2317 s->code_ptr += 16; /* skip GP */
2318
2319 /* prologue */
2320 tcg_out_bundle(s, miI,
2321 tcg_opc_m34(TCG_REG_P0, OPC_ALLOC_M34,
2322 TCG_REG_R34, 32, 24, 0),
2323 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
2324 TCG_AREG0, 0, TCG_REG_R32),
2325 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
2326 TCG_REG_B6, TCG_REG_R33, 0));
2327
2328 /* ??? If GUEST_BASE < 0x200000, we could load the register via
2329 an ADDL in the M slot of the next bundle. */
2330 if (GUEST_BASE != 0) {
2331 tcg_out_bundle(s, mlx,
2332 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
2333 tcg_opc_l2 (GUEST_BASE),
2334 tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2,
2335 TCG_GUEST_BASE_REG, GUEST_BASE));
2336 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2337 }
2338
2339 tcg_out_bundle(s, miB,
2340 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
2341 TCG_REG_R12, -frame_size, TCG_REG_R12),
2342 tcg_opc_i22(TCG_REG_P0, OPC_MOV_I22,
2343 TCG_REG_R32, TCG_REG_B0),
2344 tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6));
2345
2346 /* epilogue */
2347 tb_ret_addr = s->code_ptr;
2348 tcg_out_bundle(s, miI,
2349 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
2350 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
2351 TCG_REG_B0, TCG_REG_R32, 0),
2352 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
2353 TCG_REG_R12, frame_size, TCG_REG_R12));
2354 tcg_out_bundle(s, miB,
2355 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
2356 tcg_opc_i26(TCG_REG_P0, OPC_MOV_I_I26,
2357 TCG_REG_PFS, TCG_REG_R34),
2358 tcg_opc_b4 (TCG_REG_P0, OPC_BR_RET_SPTK_MANY_B4,
2359 TCG_REG_B0));
2360 }
2361
2362 static void tcg_target_init(TCGContext *s)
2363 {
2364 tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I32],
2365 0xffffffffffffffffull);
2366 tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I64],
2367 0xffffffffffffffffull);
2368
2369 tcg_regset_clear(tcg_target_call_clobber_regs);
2370 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8);
2371 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9);
2372 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10);
2373 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11);
2374 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);
2375 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R15);
2376 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R16);
2377 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R17);
2378 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R18);
2379 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R19);
2380 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R20);
2381 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R21);
2382 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R22);
2383 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R23);
2384 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R24);
2385 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R25);
2386 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R26);
2387 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R27);
2388 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R28);
2389 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R29);
2390 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R30);
2391 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R31);
2392 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R56);
2393 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R57);
2394 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R58);
2395 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R59);
2396 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R60);
2397 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R61);
2398 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R62);
2399 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R63);
2400
2401 tcg_regset_clear(s->reserved_regs);
2402 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* zero register */
2403 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* global pointer */
2404 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* internal use */
2405 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R3); /* internal use */
2406 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R12); /* stack pointer */
2407 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
2408 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R32); /* return address */
2409 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R34); /* PFS */
2410
2411 /* The following 3 are not in use, are call-saved, but *not* saved
2412 by the prologue. Therefore we cannot use them without modifying
2413 the prologue. There doesn't seem to be any good reason to use
2414 these as opposed to the windowed registers. */
2415 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R4);
2416 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R5);
2417 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R6);
2418
2419 tcg_add_target_add_op_defs(ia64_op_defs);
2420 }
Qemu copy for testing