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tcg/ia64: slightly optimize TLB access code
[qemu.git] / tcg / ia64 / tcg-target.c
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2009-2010 Aurelien Jarno <aurelien@aurel32.net>
5 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 /*
27 * Register definitions
28 */
29
30 #ifndef NDEBUG
31 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
32 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
33 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
34 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
35 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
36 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
37 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
38 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
39 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
40 };
41 #endif
42
43 #ifdef CONFIG_USE_GUEST_BASE
44 #define TCG_GUEST_BASE_REG TCG_REG_R55
45 #else
46 #define TCG_GUEST_BASE_REG TCG_REG_R0
47 #endif
48 #ifndef GUEST_BASE
49 #define GUEST_BASE 0
50 #endif
51
52 /* Branch registers */
53 enum {
54 TCG_REG_B0 = 0,
55 TCG_REG_B1,
56 TCG_REG_B2,
57 TCG_REG_B3,
58 TCG_REG_B4,
59 TCG_REG_B5,
60 TCG_REG_B6,
61 TCG_REG_B7,
62 };
63
64 /* Floating point registers */
65 enum {
66 TCG_REG_F0 = 0,
67 TCG_REG_F1,
68 TCG_REG_F2,
69 TCG_REG_F3,
70 TCG_REG_F4,
71 TCG_REG_F5,
72 TCG_REG_F6,
73 TCG_REG_F7,
74 TCG_REG_F8,
75 TCG_REG_F9,
76 TCG_REG_F10,
77 TCG_REG_F11,
78 TCG_REG_F12,
79 TCG_REG_F13,
80 TCG_REG_F14,
81 TCG_REG_F15,
82 };
83
84 /* Predicate registers */
85 enum {
86 TCG_REG_P0 = 0,
87 TCG_REG_P1,
88 TCG_REG_P2,
89 TCG_REG_P3,
90 TCG_REG_P4,
91 TCG_REG_P5,
92 TCG_REG_P6,
93 TCG_REG_P7,
94 TCG_REG_P8,
95 TCG_REG_P9,
96 TCG_REG_P10,
97 TCG_REG_P11,
98 TCG_REG_P12,
99 TCG_REG_P13,
100 TCG_REG_P14,
101 TCG_REG_P15,
102 };
103
104 /* Application registers */
105 enum {
106 TCG_REG_PFS = 64,
107 };
108
109 static const int tcg_target_reg_alloc_order[] = {
110 TCG_REG_R33,
111 TCG_REG_R35,
112 TCG_REG_R36,
113 TCG_REG_R37,
114 TCG_REG_R38,
115 TCG_REG_R39,
116 TCG_REG_R40,
117 TCG_REG_R41,
118 TCG_REG_R42,
119 TCG_REG_R43,
120 TCG_REG_R44,
121 TCG_REG_R45,
122 TCG_REG_R46,
123 TCG_REG_R47,
124 TCG_REG_R48,
125 TCG_REG_R49,
126 TCG_REG_R50,
127 TCG_REG_R51,
128 TCG_REG_R52,
129 TCG_REG_R53,
130 TCG_REG_R54,
131 TCG_REG_R55,
132 TCG_REG_R14,
133 TCG_REG_R15,
134 TCG_REG_R16,
135 TCG_REG_R17,
136 TCG_REG_R18,
137 TCG_REG_R19,
138 TCG_REG_R20,
139 TCG_REG_R21,
140 TCG_REG_R22,
141 TCG_REG_R23,
142 TCG_REG_R24,
143 TCG_REG_R25,
144 TCG_REG_R26,
145 TCG_REG_R27,
146 TCG_REG_R28,
147 TCG_REG_R29,
148 TCG_REG_R30,
149 TCG_REG_R31,
150 TCG_REG_R56,
151 TCG_REG_R57,
152 TCG_REG_R58,
153 TCG_REG_R59,
154 TCG_REG_R60,
155 TCG_REG_R61,
156 TCG_REG_R62,
157 TCG_REG_R63,
158 TCG_REG_R8,
159 TCG_REG_R9,
160 TCG_REG_R10,
161 TCG_REG_R11
162 };
163
164 static const int tcg_target_call_iarg_regs[8] = {
165 TCG_REG_R56,
166 TCG_REG_R57,
167 TCG_REG_R58,
168 TCG_REG_R59,
169 TCG_REG_R60,
170 TCG_REG_R61,
171 TCG_REG_R62,
172 TCG_REG_R63,
173 };
174
175 static const int tcg_target_call_oarg_regs[] = {
176 TCG_REG_R8
177 };
178
179 /*
180 * opcode formation
181 */
182
183 /* bundle templates: stops (double bar in the IA64 manual) are marked with
184 an uppercase letter. */
185 enum {
186 mii = 0x00,
187 miI = 0x01,
188 mIi = 0x02,
189 mII = 0x03,
190 mlx = 0x04,
191 mLX = 0x05,
192 mmi = 0x08,
193 mmI = 0x09,
194 Mmi = 0x0a,
195 MmI = 0x0b,
196 mfi = 0x0c,
197 mfI = 0x0d,
198 mmf = 0x0e,
199 mmF = 0x0f,
200 mib = 0x10,
201 miB = 0x11,
202 mbb = 0x12,
203 mbB = 0x13,
204 bbb = 0x16,
205 bbB = 0x17,
206 mmb = 0x18,
207 mmB = 0x19,
208 mfb = 0x1c,
209 mfB = 0x1d,
210 };
211
212 enum {
213 OPC_ADD_A1 = 0x10000000000ull,
214 OPC_AND_A1 = 0x10060000000ull,
215 OPC_AND_A3 = 0x10160000000ull,
216 OPC_ANDCM_A1 = 0x10068000000ull,
217 OPC_ANDCM_A3 = 0x10168000000ull,
218 OPC_ADDS_A4 = 0x10800000000ull,
219 OPC_ADDL_A5 = 0x12000000000ull,
220 OPC_ALLOC_M34 = 0x02c00000000ull,
221 OPC_BR_DPTK_FEW_B1 = 0x08400000000ull,
222 OPC_BR_SPTK_MANY_B1 = 0x08000001000ull,
223 OPC_BR_SPTK_MANY_B4 = 0x00100001000ull,
224 OPC_BR_CALL_SPTK_MANY_B5 = 0x02100001000ull,
225 OPC_BR_RET_SPTK_MANY_B4 = 0x00108001100ull,
226 OPC_BRL_SPTK_MANY_X3 = 0x18000001000ull,
227 OPC_CMP_LT_A6 = 0x18000000000ull,
228 OPC_CMP_LTU_A6 = 0x1a000000000ull,
229 OPC_CMP_EQ_A6 = 0x1c000000000ull,
230 OPC_CMP4_LT_A6 = 0x18400000000ull,
231 OPC_CMP4_LTU_A6 = 0x1a400000000ull,
232 OPC_CMP4_EQ_A6 = 0x1c400000000ull,
233 OPC_DEP_I14 = 0x0ae00000000ull,
234 OPC_DEP_Z_I12 = 0x0a600000000ull,
235 OPC_EXTR_I11 = 0x0a400002000ull,
236 OPC_EXTR_U_I11 = 0x0a400000000ull,
237 OPC_FCVT_FX_TRUNC_S1_F10 = 0x004d0000000ull,
238 OPC_FCVT_FXU_TRUNC_S1_F10 = 0x004d8000000ull,
239 OPC_FCVT_XF_F11 = 0x000e0000000ull,
240 OPC_FMA_S1_F1 = 0x10400000000ull,
241 OPC_FNMA_S1_F1 = 0x18400000000ull,
242 OPC_FRCPA_S1_F6 = 0x00600000000ull,
243 OPC_GETF_SIG_M19 = 0x08708000000ull,
244 OPC_LD1_M1 = 0x08000000000ull,
245 OPC_LD1_M3 = 0x0a000000000ull,
246 OPC_LD2_M1 = 0x08040000000ull,
247 OPC_LD2_M3 = 0x0a040000000ull,
248 OPC_LD4_M1 = 0x08080000000ull,
249 OPC_LD4_M3 = 0x0a080000000ull,
250 OPC_LD8_M1 = 0x080c0000000ull,
251 OPC_LD8_M3 = 0x0a0c0000000ull,
252 OPC_MUX1_I3 = 0x0eca0000000ull,
253 OPC_NOP_B9 = 0x04008000000ull,
254 OPC_NOP_F16 = 0x00008000000ull,
255 OPC_NOP_I18 = 0x00008000000ull,
256 OPC_NOP_M48 = 0x00008000000ull,
257 OPC_MOV_I21 = 0x00e00100000ull,
258 OPC_MOV_RET_I21 = 0x00e00500000ull,
259 OPC_MOV_I22 = 0x00188000000ull,
260 OPC_MOV_I_I26 = 0x00150000000ull,
261 OPC_MOVL_X2 = 0x0c000000000ull,
262 OPC_OR_A1 = 0x10070000000ull,
263 OPC_SETF_EXP_M18 = 0x0c748000000ull,
264 OPC_SETF_SIG_M18 = 0x0c708000000ull,
265 OPC_SHL_I7 = 0x0f240000000ull,
266 OPC_SHR_I5 = 0x0f220000000ull,
267 OPC_SHR_U_I5 = 0x0f200000000ull,
268 OPC_SHRP_I10 = 0x0ac00000000ull,
269 OPC_SXT1_I29 = 0x000a0000000ull,
270 OPC_SXT2_I29 = 0x000a8000000ull,
271 OPC_SXT4_I29 = 0x000b0000000ull,
272 OPC_ST1_M4 = 0x08c00000000ull,
273 OPC_ST2_M4 = 0x08c40000000ull,
274 OPC_ST4_M4 = 0x08c80000000ull,
275 OPC_ST8_M4 = 0x08cc0000000ull,
276 OPC_SUB_A1 = 0x10028000000ull,
277 OPC_SUB_A3 = 0x10128000000ull,
278 OPC_UNPACK4_L_I2 = 0x0f860000000ull,
279 OPC_XMA_L_F2 = 0x1d000000000ull,
280 OPC_XOR_A1 = 0x10078000000ull,
281 OPC_ZXT1_I29 = 0x00080000000ull,
282 OPC_ZXT2_I29 = 0x00088000000ull,
283 OPC_ZXT4_I29 = 0x00090000000ull,
284 };
285
286 static inline uint64_t tcg_opc_a1(int qp, uint64_t opc, int r1,
287 int r2, int r3)
288 {
289 return opc
290 | ((r3 & 0x7f) << 20)
291 | ((r2 & 0x7f) << 13)
292 | ((r1 & 0x7f) << 6)
293 | (qp & 0x3f);
294 }
295
296 static inline uint64_t tcg_opc_a3(int qp, uint64_t opc, int r1,
297 uint64_t imm, int r3)
298 {
299 return opc
300 | ((imm & 0x80) << 29) /* s */
301 | ((imm & 0x7f) << 13) /* imm7b */
302 | ((r3 & 0x7f) << 20)
303 | ((r1 & 0x7f) << 6)
304 | (qp & 0x3f);
305 }
306
307 static inline uint64_t tcg_opc_a4(int qp, uint64_t opc, int r1,
308 uint64_t imm, int r3)
309 {
310 return opc
311 | ((imm & 0x2000) << 23) /* s */
312 | ((imm & 0x1f80) << 20) /* imm6d */
313 | ((imm & 0x007f) << 13) /* imm7b */
314 | ((r3 & 0x7f) << 20)
315 | ((r1 & 0x7f) << 6)
316 | (qp & 0x3f);
317 }
318
319 static inline uint64_t tcg_opc_a5(int qp, uint64_t opc, int r1,
320 uint64_t imm, int r3)
321 {
322 return opc
323 | ((imm & 0x200000) << 15) /* s */
324 | ((imm & 0x1f0000) << 6) /* imm5c */
325 | ((imm & 0x00ff80) << 20) /* imm9d */
326 | ((imm & 0x00007f) << 13) /* imm7b */
327 | ((r3 & 0x03) << 20)
328 | ((r1 & 0x7f) << 6)
329 | (qp & 0x3f);
330 }
331
332 static inline uint64_t tcg_opc_a6(int qp, uint64_t opc, int p1,
333 int p2, int r2, int r3)
334 {
335 return opc
336 | ((p2 & 0x3f) << 27)
337 | ((r3 & 0x7f) << 20)
338 | ((r2 & 0x7f) << 13)
339 | ((p1 & 0x3f) << 6)
340 | (qp & 0x3f);
341 }
342
343 static inline uint64_t tcg_opc_b1(int qp, uint64_t opc, uint64_t imm)
344 {
345 return opc
346 | ((imm & 0x100000) << 16) /* s */
347 | ((imm & 0x0fffff) << 13) /* imm20b */
348 | (qp & 0x3f);
349 }
350
351 static inline uint64_t tcg_opc_b4(int qp, uint64_t opc, int b2)
352 {
353 return opc
354 | ((b2 & 0x7) << 13)
355 | (qp & 0x3f);
356 }
357
358 static inline uint64_t tcg_opc_b5(int qp, uint64_t opc, int b1, int b2)
359 {
360 return opc
361 | ((b2 & 0x7) << 13)
362 | ((b1 & 0x7) << 6)
363 | (qp & 0x3f);
364 }
365
366
367 static inline uint64_t tcg_opc_b9(int qp, uint64_t opc, uint64_t imm)
368 {
369 return opc
370 | ((imm & 0x100000) << 16) /* i */
371 | ((imm & 0x0fffff) << 6) /* imm20a */
372 | (qp & 0x3f);
373 }
374
375 static inline uint64_t tcg_opc_f1(int qp, uint64_t opc, int f1,
376 int f3, int f4, int f2)
377 {
378 return opc
379 | ((f4 & 0x7f) << 27)
380 | ((f3 & 0x7f) << 20)
381 | ((f2 & 0x7f) << 13)
382 | ((f1 & 0x7f) << 6)
383 | (qp & 0x3f);
384 }
385
386 static inline uint64_t tcg_opc_f2(int qp, uint64_t opc, int f1,
387 int f3, int f4, int f2)
388 {
389 return opc
390 | ((f4 & 0x7f) << 27)
391 | ((f3 & 0x7f) << 20)
392 | ((f2 & 0x7f) << 13)
393 | ((f1 & 0x7f) << 6)
394 | (qp & 0x3f);
395 }
396
397 static inline uint64_t tcg_opc_f6(int qp, uint64_t opc, int f1,
398 int p2, int f2, int f3)
399 {
400 return opc
401 | ((p2 & 0x3f) << 27)
402 | ((f3 & 0x7f) << 20)
403 | ((f2 & 0x7f) << 13)
404 | ((f1 & 0x7f) << 6)
405 | (qp & 0x3f);
406 }
407
408 static inline uint64_t tcg_opc_f10(int qp, uint64_t opc, int f1, int f2)
409 {
410 return opc
411 | ((f2 & 0x7f) << 13)
412 | ((f1 & 0x7f) << 6)
413 | (qp & 0x3f);
414 }
415
416 static inline uint64_t tcg_opc_f11(int qp, uint64_t opc, int f1, int f2)
417 {
418 return opc
419 | ((f2 & 0x7f) << 13)
420 | ((f1 & 0x7f) << 6)
421 | (qp & 0x3f);
422 }
423
424 static inline uint64_t tcg_opc_f16(int qp, uint64_t opc, uint64_t imm)
425 {
426 return opc
427 | ((imm & 0x100000) << 16) /* i */
428 | ((imm & 0x0fffff) << 6) /* imm20a */
429 | (qp & 0x3f);
430 }
431
432 static inline uint64_t tcg_opc_i2(int qp, uint64_t opc, int r1,
433 int r2, int r3)
434 {
435 return opc
436 | ((r3 & 0x7f) << 20)
437 | ((r2 & 0x7f) << 13)
438 | ((r1 & 0x7f) << 6)
439 | (qp & 0x3f);
440 }
441
442 static inline uint64_t tcg_opc_i3(int qp, uint64_t opc, int r1,
443 int r2, int mbtype)
444 {
445 return opc
446 | ((mbtype & 0x0f) << 20)
447 | ((r2 & 0x7f) << 13)
448 | ((r1 & 0x7f) << 6)
449 | (qp & 0x3f);
450 }
451
452 static inline uint64_t tcg_opc_i5(int qp, uint64_t opc, int r1,
453 int r3, int r2)
454 {
455 return opc
456 | ((r3 & 0x7f) << 20)
457 | ((r2 & 0x7f) << 13)
458 | ((r1 & 0x7f) << 6)
459 | (qp & 0x3f);
460 }
461
462 static inline uint64_t tcg_opc_i7(int qp, uint64_t opc, int r1,
463 int r2, int r3)
464 {
465 return opc
466 | ((r3 & 0x7f) << 20)
467 | ((r2 & 0x7f) << 13)
468 | ((r1 & 0x7f) << 6)
469 | (qp & 0x3f);
470 }
471
472 static inline uint64_t tcg_opc_i10(int qp, uint64_t opc, int r1,
473 int r2, int r3, uint64_t count)
474 {
475 return opc
476 | ((count & 0x3f) << 27)
477 | ((r3 & 0x7f) << 20)
478 | ((r2 & 0x7f) << 13)
479 | ((r1 & 0x7f) << 6)
480 | (qp & 0x3f);
481 }
482
483 static inline uint64_t tcg_opc_i11(int qp, uint64_t opc, int r1,
484 int r3, uint64_t pos, uint64_t len)
485 {
486 return opc
487 | ((len & 0x3f) << 27)
488 | ((r3 & 0x7f) << 20)
489 | ((pos & 0x3f) << 14)
490 | ((r1 & 0x7f) << 6)
491 | (qp & 0x3f);
492 }
493
494 static inline uint64_t tcg_opc_i12(int qp, uint64_t opc, int r1,
495 int r2, uint64_t pos, uint64_t len)
496 {
497 return opc
498 | ((len & 0x3f) << 27)
499 | ((pos & 0x3f) << 20)
500 | ((r2 & 0x7f) << 13)
501 | ((r1 & 0x7f) << 6)
502 | (qp & 0x3f);
503 }
504
505 static inline uint64_t tcg_opc_i14(int qp, uint64_t opc, int r1, uint64_t imm,
506 int r3, uint64_t pos, uint64_t len)
507 {
508 return opc
509 | ((imm & 0x01) << 36)
510 | ((len & 0x3f) << 27)
511 | ((r3 & 0x7f) << 20)
512 | ((pos & 0x3f) << 14)
513 | ((r1 & 0x7f) << 6)
514 | (qp & 0x3f);
515 }
516
517 static inline uint64_t tcg_opc_i18(int qp, uint64_t opc, uint64_t imm)
518 {
519 return opc
520 | ((imm & 0x100000) << 16) /* i */
521 | ((imm & 0x0fffff) << 6) /* imm20a */
522 | (qp & 0x3f);
523 }
524
525 static inline uint64_t tcg_opc_i21(int qp, uint64_t opc, int b1,
526 int r2, uint64_t imm)
527 {
528 return opc
529 | ((imm & 0x1ff) << 24)
530 | ((r2 & 0x7f) << 13)
531 | ((b1 & 0x7) << 6)
532 | (qp & 0x3f);
533 }
534
535 static inline uint64_t tcg_opc_i22(int qp, uint64_t opc, int r1, int b2)
536 {
537 return opc
538 | ((b2 & 0x7) << 13)
539 | ((r1 & 0x7f) << 6)
540 | (qp & 0x3f);
541 }
542
543 static inline uint64_t tcg_opc_i26(int qp, uint64_t opc, int ar3, int r2)
544 {
545 return opc
546 | ((ar3 & 0x7f) << 20)
547 | ((r2 & 0x7f) << 13)
548 | (qp & 0x3f);
549 }
550
551 static inline uint64_t tcg_opc_i29(int qp, uint64_t opc, int r1, int r3)
552 {
553 return opc
554 | ((r3 & 0x7f) << 20)
555 | ((r1 & 0x7f) << 6)
556 | (qp & 0x3f);
557 }
558
559 static inline uint64_t tcg_opc_l2(uint64_t imm)
560 {
561 return (imm & 0x7fffffffffc00000ull) >> 22;
562 }
563
564 static inline uint64_t tcg_opc_l3(uint64_t imm)
565 {
566 return (imm & 0x07fffffffff00000ull) >> 18;
567 }
568
569 static inline uint64_t tcg_opc_m1(int qp, uint64_t opc, int r1, int r3)
570 {
571 return opc
572 | ((r3 & 0x7f) << 20)
573 | ((r1 & 0x7f) << 6)
574 | (qp & 0x3f);
575 }
576
577 static inline uint64_t tcg_opc_m3(int qp, uint64_t opc, int r1,
578 int r3, uint64_t imm)
579 {
580 return opc
581 | ((imm & 0x100) << 28) /* s */
582 | ((imm & 0x080) << 20) /* i */
583 | ((imm & 0x07f) << 13) /* imm7b */
584 | ((r3 & 0x7f) << 20)
585 | ((r1 & 0x7f) << 6)
586 | (qp & 0x3f);
587 }
588
589 static inline uint64_t tcg_opc_m4(int qp, uint64_t opc, int r2, int r3)
590 {
591 return opc
592 | ((r3 & 0x7f) << 20)
593 | ((r2 & 0x7f) << 13)
594 | (qp & 0x3f);
595 }
596
597 static inline uint64_t tcg_opc_m18(int qp, uint64_t opc, int f1, int r2)
598 {
599 return opc
600 | ((r2 & 0x7f) << 13)
601 | ((f1 & 0x7f) << 6)
602 | (qp & 0x3f);
603 }
604
605 static inline uint64_t tcg_opc_m19(int qp, uint64_t opc, int r1, int f2)
606 {
607 return opc
608 | ((f2 & 0x7f) << 13)
609 | ((r1 & 0x7f) << 6)
610 | (qp & 0x3f);
611 }
612
613 static inline uint64_t tcg_opc_m34(int qp, uint64_t opc, int r1,
614 int sof, int sol, int sor)
615 {
616 return opc
617 | ((sor & 0x0f) << 27)
618 | ((sol & 0x7f) << 20)
619 | ((sof & 0x7f) << 13)
620 | ((r1 & 0x7f) << 6)
621 | (qp & 0x3f);
622 }
623
624 static inline uint64_t tcg_opc_m48(int qp, uint64_t opc, uint64_t imm)
625 {
626 return opc
627 | ((imm & 0x100000) << 16) /* i */
628 | ((imm & 0x0fffff) << 6) /* imm20a */
629 | (qp & 0x3f);
630 }
631
632 static inline uint64_t tcg_opc_x2(int qp, uint64_t opc,
633 int r1, uint64_t imm)
634 {
635 return opc
636 | ((imm & 0x8000000000000000ull) >> 27) /* i */
637 | (imm & 0x0000000000200000ull) /* ic */
638 | ((imm & 0x00000000001f0000ull) << 6) /* imm5c */
639 | ((imm & 0x000000000000ff80ull) << 20) /* imm9d */
640 | ((imm & 0x000000000000007full) << 13) /* imm7b */
641 | ((r1 & 0x7f) << 6)
642 | (qp & 0x3f);
643 }
644
645 static inline uint64_t tcg_opc_x3(int qp, uint64_t opc, uint64_t imm)
646 {
647 return opc
648 | ((imm & 0x0800000000000000ull) >> 23) /* i */
649 | ((imm & 0x00000000000fffffull) << 13) /* imm20b */
650 | (qp & 0x3f);
651 }
652
653
654 /*
655 * Relocations
656 */
657
658 static inline void reloc_pcrel21b (void *pc, tcg_target_long target)
659 {
660 uint64_t imm;
661 int64_t disp;
662 int slot;
663
664 slot = (tcg_target_long) pc & 3;
665 pc = (void *)((tcg_target_long) pc & ~3);
666
667 disp = target - (tcg_target_long) pc;
668 imm = (uint64_t) disp >> 4;
669
670 switch(slot) {
671 case 0:
672 *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 8) & 0xfffffdc00003ffffull)
673 | ((imm & 0x100000) << 21) /* s */
674 | ((imm & 0x0fffff) << 18); /* imm20b */
675 break;
676 case 1:
677 *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xfffffffffffb8000ull)
678 | ((imm & 0x100000) >> 2) /* s */
679 | ((imm & 0x0fffe0) >> 5); /* imm20b */
680 *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x07ffffffffffffffull)
681 | ((imm & 0x00001f) << 59); /* imm20b */
682 break;
683 case 2:
684 *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fffffffffull)
685 | ((imm & 0x100000) << 39) /* s */
686 | ((imm & 0x0fffff) << 36); /* imm20b */
687 break;
688 }
689 }
690
691 static inline uint64_t get_reloc_pcrel21b (void *pc)
692 {
693 int64_t low, high;
694 int slot;
695
696 slot = (tcg_target_long) pc & 3;
697 pc = (void *)((tcg_target_long) pc & ~3);
698
699 low = (*(uint64_t *)(pc + 0));
700 high = (*(uint64_t *)(pc + 8));
701
702 switch(slot) {
703 case 0:
704 return ((low >> 21) & 0x100000) + /* s */
705 ((low >> 18) & 0x0fffff); /* imm20b */
706 case 1:
707 return ((high << 2) & 0x100000) + /* s */
708 ((high << 5) & 0x0fffe0) + /* imm20b */
709 ((low >> 59) & 0x00001f); /* imm20b */
710 case 2:
711 return ((high >> 39) & 0x100000) + /* s */
712 ((high >> 36) & 0x0fffff); /* imm20b */
713 default:
714 tcg_abort();
715 }
716 }
717
718 static inline void reloc_pcrel60b (void *pc, tcg_target_long target)
719 {
720 int64_t disp;
721 uint64_t imm;
722
723 disp = target - (tcg_target_long) pc;
724 imm = (uint64_t) disp >> 4;
725
726 *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fff800000ull)
727 | (imm & 0x0800000000000000ull) /* s */
728 | ((imm & 0x07fffff000000000ull) >> 36) /* imm39 */
729 | ((imm & 0x00000000000fffffull) << 36); /* imm20b */
730 *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x00003fffffffffffull)
731 | ((imm & 0x0000000ffff00000ull) << 28); /* imm39 */
732 }
733
734 static inline uint64_t get_reloc_pcrel60b (void *pc)
735 {
736 int64_t low, high;
737
738 low = (*(uint64_t *)(pc + 0));
739 high = (*(uint64_t *)(pc + 8));
740
741 return ((high) & 0x0800000000000000ull) + /* s */
742 ((high >> 36) & 0x00000000000fffffull) + /* imm20b */
743 ((high << 36) & 0x07fffff000000000ull) + /* imm39 */
744 ((low >> 28) & 0x0000000ffff00000ull); /* imm39 */
745 }
746
747
748 static void patch_reloc(uint8_t *code_ptr, int type,
749 tcg_target_long value, tcg_target_long addend)
750 {
751 value += addend;
752 switch (type) {
753 case R_IA64_PCREL21B:
754 reloc_pcrel21b(code_ptr, value);
755 break;
756 case R_IA64_PCREL60B:
757 reloc_pcrel60b(code_ptr, value);
758 default:
759 tcg_abort();
760 }
761 }
762
763 /*
764 * Constraints
765 */
766
767 /* parse target specific constraints */
768 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
769 {
770 const char *ct_str;
771
772 ct_str = *pct_str;
773 switch(ct_str[0]) {
774 case 'r':
775 ct->ct |= TCG_CT_REG;
776 tcg_regset_set(ct->u.regs, 0xffffffffffffffffull);
777 break;
778 case 'I':
779 ct->ct |= TCG_CT_CONST_S22;
780 break;
781 case 'S':
782 ct->ct |= TCG_CT_REG;
783 tcg_regset_set(ct->u.regs, 0xffffffffffffffffull);
784 #if defined(CONFIG_SOFTMMU)
785 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R56);
786 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R57);
787 #endif
788 break;
789 case 'Z':
790 /* We are cheating a bit here, using the fact that the register
791 r0 is also the register number 0. Hence there is no need
792 to check for const_args in each instruction. */
793 ct->ct |= TCG_CT_CONST_ZERO;
794 break;
795 default:
796 return -1;
797 }
798 ct_str++;
799 *pct_str = ct_str;
800 return 0;
801 }
802
803 /* test if a constant matches the constraint */
804 static inline int tcg_target_const_match(tcg_target_long val,
805 const TCGArgConstraint *arg_ct)
806 {
807 int ct;
808 ct = arg_ct->ct;
809 if (ct & TCG_CT_CONST)
810 return 1;
811 else if ((ct & TCG_CT_CONST_ZERO) && val == 0)
812 return 1;
813 else if ((ct & TCG_CT_CONST_S22) && val == ((int32_t)val << 10) >> 10)
814 return 1;
815 else
816 return 0;
817 }
818
819 /*
820 * Code generation
821 */
822
823 static uint8_t *tb_ret_addr;
824
825 static inline void tcg_out_bundle(TCGContext *s, int template,
826 uint64_t slot0, uint64_t slot1,
827 uint64_t slot2)
828 {
829 template &= 0x1f; /* 5 bits */
830 slot0 &= 0x1ffffffffffull; /* 41 bits */
831 slot1 &= 0x1ffffffffffull; /* 41 bits */
832 slot2 &= 0x1ffffffffffull; /* 41 bits */
833
834 *(uint64_t *)(s->code_ptr + 0) = (slot1 << 46) | (slot0 << 5) | template;
835 *(uint64_t *)(s->code_ptr + 8) = (slot2 << 23) | (slot1 >> 18);
836 s->code_ptr += 16;
837 }
838
839 static inline void tcg_out_mov(TCGContext *s, TCGType type,
840 TCGReg ret, TCGReg arg)
841 {
842 tcg_out_bundle(s, mmI,
843 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
844 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
845 tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, ret, 0, arg));
846 }
847
848 static inline void tcg_out_movi(TCGContext *s, TCGType type,
849 TCGReg reg, tcg_target_long arg)
850 {
851 tcg_out_bundle(s, mLX,
852 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
853 tcg_opc_l2 (arg),
854 tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, reg, arg));
855 }
856
857 static void tcg_out_br(TCGContext *s, int label_index)
858 {
859 TCGLabel *l = &s->labels[label_index];
860
861 /* We pay attention here to not modify the branch target by reading
862 the existing value and using it again. This ensure that caches and
863 memory are kept coherent during retranslation. */
864 tcg_out_bundle(s, mmB,
865 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
866 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
867 tcg_opc_b1 (TCG_REG_P0, OPC_BR_SPTK_MANY_B1,
868 get_reloc_pcrel21b(s->code_ptr + 2)));
869
870 if (l->has_value) {
871 reloc_pcrel21b((s->code_ptr - 16) + 2, l->u.value);
872 } else {
873 tcg_out_reloc(s, (s->code_ptr - 16) + 2,
874 R_IA64_PCREL21B, label_index, 0);
875 }
876 }
877
878 static inline void tcg_out_call(TCGContext *s, TCGArg addr)
879 {
880 tcg_out_bundle(s, MmI,
881 tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R2, addr),
882 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R3, 8, addr),
883 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
884 TCG_REG_B6, TCG_REG_R2, 0));
885 tcg_out_bundle(s, mmB,
886 tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R3),
887 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
888 tcg_opc_b5 (TCG_REG_P0, OPC_BR_CALL_SPTK_MANY_B5,
889 TCG_REG_B0, TCG_REG_B6));
890 }
891
892 static void tcg_out_exit_tb(TCGContext *s, tcg_target_long arg)
893 {
894 int64_t disp;
895 uint64_t imm;
896
897 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R8, arg);
898
899 disp = tb_ret_addr - s->code_ptr;
900 imm = (uint64_t)disp >> 4;
901
902 tcg_out_bundle(s, mLX,
903 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
904 tcg_opc_l3 (imm),
905 tcg_opc_x3 (TCG_REG_P0, OPC_BRL_SPTK_MANY_X3, imm));
906 }
907
908 static inline void tcg_out_goto_tb(TCGContext *s, TCGArg arg)
909 {
910 if (s->tb_jmp_offset) {
911 /* direct jump method */
912 tcg_abort();
913 } else {
914 /* indirect jump method */
915 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2,
916 (tcg_target_long)(s->tb_next + arg));
917 tcg_out_bundle(s, MmI,
918 tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1,
919 TCG_REG_R2, TCG_REG_R2),
920 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
921 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6,
922 TCG_REG_R2, 0));
923 tcg_out_bundle(s, mmB,
924 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
925 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
926 tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4,
927 TCG_REG_B6));
928 }
929 s->tb_next_offset[arg] = s->code_ptr - s->code_buf;
930 }
931
932 static inline void tcg_out_jmp(TCGContext *s, TCGArg addr)
933 {
934 tcg_out_bundle(s, mmI,
935 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
936 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
937 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6, addr, 0));
938 tcg_out_bundle(s, mmB,
939 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
940 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
941 tcg_opc_b4(TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6));
942 }
943
944 static inline void tcg_out_ld_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg,
945 TCGArg arg1, tcg_target_long arg2)
946 {
947 if (arg2 == ((int16_t)arg2 >> 2) << 2) {
948 tcg_out_bundle(s, MmI,
949 tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4,
950 TCG_REG_R2, arg2, arg1),
951 tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
952 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
953 } else {
954 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2);
955 tcg_out_bundle(s, MmI,
956 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1,
957 TCG_REG_R2, TCG_REG_R2, arg1),
958 tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
959 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
960 }
961 }
962
963 static inline void tcg_out_st_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg,
964 TCGArg arg1, tcg_target_long arg2)
965 {
966 if (arg2 == ((int16_t)arg2 >> 2) << 2) {
967 tcg_out_bundle(s, MmI,
968 tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4,
969 TCG_REG_R2, arg2, arg1),
970 tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
971 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
972 } else {
973 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2);
974 tcg_out_bundle(s, MmI,
975 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1,
976 TCG_REG_R2, TCG_REG_R2, arg1),
977 tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
978 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
979 }
980 }
981
982 static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
983 TCGReg arg1, tcg_target_long arg2)
984 {
985 if (type == TCG_TYPE_I32) {
986 tcg_out_ld_rel(s, OPC_LD4_M1, arg, arg1, arg2);
987 } else {
988 tcg_out_ld_rel(s, OPC_LD8_M1, arg, arg1, arg2);
989 }
990 }
991
992 static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
993 TCGReg arg1, tcg_target_long arg2)
994 {
995 if (type == TCG_TYPE_I32) {
996 tcg_out_st_rel(s, OPC_ST4_M4, arg, arg1, arg2);
997 } else {
998 tcg_out_st_rel(s, OPC_ST8_M4, arg, arg1, arg2);
999 }
1000 }
1001
1002 static inline void tcg_out_alu(TCGContext *s, uint64_t opc_a1, TCGArg ret,
1003 TCGArg arg1, int const_arg1,
1004 TCGArg arg2, int const_arg2)
1005 {
1006 uint64_t opc1, opc2;
1007
1008 if (const_arg1 && arg1 != 0) {
1009 opc1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
1010 TCG_REG_R2, arg1, TCG_REG_R0);
1011 arg1 = TCG_REG_R2;
1012 } else {
1013 opc1 = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
1014 }
1015
1016 if (const_arg2 && arg2 != 0) {
1017 opc2 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
1018 TCG_REG_R3, arg2, TCG_REG_R0);
1019 arg2 = TCG_REG_R3;
1020 } else {
1021 opc2 = tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0);
1022 }
1023
1024 tcg_out_bundle(s, mII,
1025 opc1,
1026 opc2,
1027 tcg_opc_a1(TCG_REG_P0, opc_a1, ret, arg1, arg2));
1028 }
1029
1030 static inline void tcg_out_eqv(TCGContext *s, TCGArg ret,
1031 TCGArg arg1, int const_arg1,
1032 TCGArg arg2, int const_arg2)
1033 {
1034 tcg_out_bundle(s, mII,
1035 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1036 tcg_opc_a1 (TCG_REG_P0, OPC_XOR_A1, ret, arg1, arg2),
1037 tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
1038 }
1039
1040 static inline void tcg_out_nand(TCGContext *s, TCGArg ret,
1041 TCGArg arg1, int const_arg1,
1042 TCGArg arg2, int const_arg2)
1043 {
1044 tcg_out_bundle(s, mII,
1045 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1046 tcg_opc_a1 (TCG_REG_P0, OPC_AND_A1, ret, arg1, arg2),
1047 tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
1048 }
1049
1050 static inline void tcg_out_nor(TCGContext *s, TCGArg ret,
1051 TCGArg arg1, int const_arg1,
1052 TCGArg arg2, int const_arg2)
1053 {
1054 tcg_out_bundle(s, mII,
1055 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1056 tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, arg2),
1057 tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
1058 }
1059
1060 static inline void tcg_out_orc(TCGContext *s, TCGArg ret,
1061 TCGArg arg1, int const_arg1,
1062 TCGArg arg2, int const_arg2)
1063 {
1064 tcg_out_bundle(s, mII,
1065 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1066 tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, TCG_REG_R2, -1, arg2),
1067 tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, TCG_REG_R2));
1068 }
1069
1070 static inline void tcg_out_mul(TCGContext *s, TCGArg ret,
1071 TCGArg arg1, TCGArg arg2)
1072 {
1073 tcg_out_bundle(s, mmI,
1074 tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F6, arg1),
1075 tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F7, arg2),
1076 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1077 tcg_out_bundle(s, mmF,
1078 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1079 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1080 tcg_opc_f2 (TCG_REG_P0, OPC_XMA_L_F2, TCG_REG_F6, TCG_REG_F6,
1081 TCG_REG_F7, TCG_REG_F0));
1082 tcg_out_bundle(s, miI,
1083 tcg_opc_m19(TCG_REG_P0, OPC_GETF_SIG_M19, ret, TCG_REG_F6),
1084 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1085 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1086 }
1087
1088 static inline void tcg_out_sar_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1089 TCGArg arg2, int const_arg2)
1090 {
1091 if (const_arg2) {
1092 tcg_out_bundle(s, miI,
1093 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1094 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1095 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11,
1096 ret, arg1, arg2, 31 - arg2));
1097 } else {
1098 tcg_out_bundle(s, mII,
1099 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3,
1100 TCG_REG_R3, 0x1f, arg2),
1101 tcg_opc_i29(TCG_REG_P0, OPC_SXT4_I29, TCG_REG_R2, arg1),
1102 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret,
1103 TCG_REG_R2, TCG_REG_R3));
1104 }
1105 }
1106
1107 static inline void tcg_out_sar_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1108 TCGArg arg2, int const_arg2)
1109 {
1110 if (const_arg2) {
1111 tcg_out_bundle(s, miI,
1112 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1113 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1114 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11,
1115 ret, arg1, arg2, 63 - arg2));
1116 } else {
1117 tcg_out_bundle(s, miI,
1118 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1119 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1120 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret, arg1, arg2));
1121 }
1122 }
1123
1124 static inline void tcg_out_shl_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1125 TCGArg arg2, int const_arg2)
1126 {
1127 if (const_arg2) {
1128 tcg_out_bundle(s, miI,
1129 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1130 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1131 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret,
1132 arg1, 63 - arg2, 31 - arg2));
1133 } else {
1134 tcg_out_bundle(s, mII,
1135 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1136 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R2,
1137 0x1f, arg2),
1138 tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret,
1139 arg1, TCG_REG_R2));
1140 }
1141 }
1142
1143 static inline void tcg_out_shl_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1144 TCGArg arg2, int const_arg2)
1145 {
1146 if (const_arg2) {
1147 tcg_out_bundle(s, miI,
1148 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1149 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1150 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret,
1151 arg1, 63 - arg2, 63 - arg2));
1152 } else {
1153 tcg_out_bundle(s, miI,
1154 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1155 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1156 tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret,
1157 arg1, arg2));
1158 }
1159 }
1160
1161 static inline void tcg_out_shr_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1162 TCGArg arg2, int const_arg2)
1163 {
1164 if (const_arg2) {
1165 tcg_out_bundle(s, miI,
1166 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1167 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1168 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1169 arg1, arg2, 31 - arg2));
1170 } else {
1171 tcg_out_bundle(s, mII,
1172 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
1173 0x1f, arg2),
1174 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R2, arg1),
1175 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1176 TCG_REG_R2, TCG_REG_R3));
1177 }
1178 }
1179
1180 static inline void tcg_out_shr_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1181 TCGArg arg2, int const_arg2)
1182 {
1183 if (const_arg2) {
1184 tcg_out_bundle(s, miI,
1185 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1186 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1187 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1188 arg1, arg2, 63 - arg2));
1189 } else {
1190 tcg_out_bundle(s, miI,
1191 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1192 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1193 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1194 arg1, arg2));
1195 }
1196 }
1197
1198 static inline void tcg_out_rotl_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1199 TCGArg arg2, int const_arg2)
1200 {
1201 if (const_arg2) {
1202 tcg_out_bundle(s, mII,
1203 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1204 tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1205 TCG_REG_R2, arg1, arg1),
1206 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1207 TCG_REG_R2, 32 - arg2, 31));
1208 } else {
1209 tcg_out_bundle(s, miI,
1210 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1211 tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1212 TCG_REG_R2, arg1, arg1),
1213 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
1214 0x1f, arg2));
1215 tcg_out_bundle(s, mII,
1216 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1217 tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R3,
1218 0x20, TCG_REG_R3),
1219 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1220 TCG_REG_R2, TCG_REG_R3));
1221 }
1222 }
1223
1224 static inline void tcg_out_rotl_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1225 TCGArg arg2, int const_arg2)
1226 {
1227 if (const_arg2) {
1228 tcg_out_bundle(s, miI,
1229 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1230 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1231 tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1,
1232 arg1, 0x40 - arg2));
1233 } else {
1234 tcg_out_bundle(s, mII,
1235 tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2,
1236 0x40, arg2),
1237 tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R3,
1238 arg1, arg2),
1239 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R2,
1240 arg1, TCG_REG_R2));
1241 tcg_out_bundle(s, miI,
1242 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1243 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1244 tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret,
1245 TCG_REG_R2, TCG_REG_R3));
1246 }
1247 }
1248
1249 static inline void tcg_out_rotr_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1250 TCGArg arg2, int const_arg2)
1251 {
1252 if (const_arg2) {
1253 tcg_out_bundle(s, mII,
1254 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1255 tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1256 TCG_REG_R2, arg1, arg1),
1257 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1258 TCG_REG_R2, arg2, 31));
1259 } else {
1260 tcg_out_bundle(s, mII,
1261 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
1262 0x1f, arg2),
1263 tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1264 TCG_REG_R2, arg1, arg1),
1265 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1266 TCG_REG_R2, TCG_REG_R3));
1267 }
1268 }
1269
1270 static inline void tcg_out_rotr_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1271 TCGArg arg2, int const_arg2)
1272 {
1273 if (const_arg2) {
1274 tcg_out_bundle(s, miI,
1275 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1276 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1277 tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1,
1278 arg1, arg2));
1279 } else {
1280 tcg_out_bundle(s, mII,
1281 tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2,
1282 0x40, arg2),
1283 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R3,
1284 arg1, arg2),
1285 tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R2,
1286 arg1, TCG_REG_R2));
1287 tcg_out_bundle(s, miI,
1288 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1289 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1290 tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret,
1291 TCG_REG_R2, TCG_REG_R3));
1292 }
1293 }
1294
1295 static inline void tcg_out_ext(TCGContext *s, uint64_t opc_i29,
1296 TCGArg ret, TCGArg arg)
1297 {
1298 tcg_out_bundle(s, miI,
1299 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1300 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1301 tcg_opc_i29(TCG_REG_P0, opc_i29, ret, arg));
1302 }
1303
1304 static inline void tcg_out_bswap16(TCGContext *s, TCGArg ret, TCGArg arg)
1305 {
1306 tcg_out_bundle(s, mII,
1307 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1308 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 15, 15),
1309 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, ret, 0xb));
1310 }
1311
1312 static inline void tcg_out_bswap32(TCGContext *s, TCGArg ret, TCGArg arg)
1313 {
1314 tcg_out_bundle(s, mII,
1315 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1316 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 31, 31),
1317 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, ret, 0xb));
1318 }
1319
1320 static inline void tcg_out_bswap64(TCGContext *s, TCGArg ret, TCGArg arg)
1321 {
1322 tcg_out_bundle(s, miI,
1323 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1324 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1325 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, arg, 0xb));
1326 }
1327
1328 static inline uint64_t tcg_opc_cmp_a(int qp, TCGCond cond, TCGArg arg1,
1329 TCGArg arg2, int cmp4)
1330 {
1331 uint64_t opc_eq_a6, opc_lt_a6, opc_ltu_a6;
1332
1333 if (cmp4) {
1334 opc_eq_a6 = OPC_CMP4_EQ_A6;
1335 opc_lt_a6 = OPC_CMP4_LT_A6;
1336 opc_ltu_a6 = OPC_CMP4_LTU_A6;
1337 } else {
1338 opc_eq_a6 = OPC_CMP_EQ_A6;
1339 opc_lt_a6 = OPC_CMP_LT_A6;
1340 opc_ltu_a6 = OPC_CMP_LTU_A6;
1341 }
1342
1343 switch (cond) {
1344 case TCG_COND_EQ:
1345 return tcg_opc_a6 (qp, opc_eq_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
1346 case TCG_COND_NE:
1347 return tcg_opc_a6 (qp, opc_eq_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
1348 case TCG_COND_LT:
1349 return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
1350 case TCG_COND_LTU:
1351 return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
1352 case TCG_COND_GE:
1353 return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
1354 case TCG_COND_GEU:
1355 return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
1356 case TCG_COND_LE:
1357 return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P7, TCG_REG_P6, arg2, arg1);
1358 case TCG_COND_LEU:
1359 return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg2, arg1);
1360 case TCG_COND_GT:
1361 return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P6, TCG_REG_P7, arg2, arg1);
1362 case TCG_COND_GTU:
1363 return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg2, arg1);
1364 default:
1365 tcg_abort();
1366 break;
1367 }
1368 }
1369
1370 static inline void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGArg arg1,
1371 int const_arg1, TCGArg arg2, int const_arg2,
1372 int label_index, int cmp4)
1373 {
1374 TCGLabel *l = &s->labels[label_index];
1375 uint64_t opc1, opc2;
1376
1377 if (const_arg1 && arg1 != 0) {
1378 opc1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R2,
1379 arg1, TCG_REG_R0);
1380 arg1 = TCG_REG_R2;
1381 } else {
1382 opc1 = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
1383 }
1384
1385 if (const_arg2 && arg2 != 0) {
1386 opc2 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R3,
1387 arg2, TCG_REG_R0);
1388 arg2 = TCG_REG_R3;
1389 } else {
1390 opc2 = tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0);
1391 }
1392
1393 tcg_out_bundle(s, mII,
1394 opc1,
1395 opc2,
1396 tcg_opc_cmp_a(TCG_REG_P0, cond, arg1, arg2, cmp4));
1397 tcg_out_bundle(s, mmB,
1398 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1399 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1400 tcg_opc_b1 (TCG_REG_P6, OPC_BR_DPTK_FEW_B1,
1401 get_reloc_pcrel21b(s->code_ptr + 2)));
1402
1403 if (l->has_value) {
1404 reloc_pcrel21b((s->code_ptr - 16) + 2, l->u.value);
1405 } else {
1406 tcg_out_reloc(s, (s->code_ptr - 16) + 2,
1407 R_IA64_PCREL21B, label_index, 0);
1408 }
1409 }
1410
1411 static inline void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGArg ret,
1412 TCGArg arg1, TCGArg arg2, int cmp4)
1413 {
1414 tcg_out_bundle(s, MmI,
1415 tcg_opc_cmp_a(TCG_REG_P0, cond, arg1, arg2, cmp4),
1416 tcg_opc_a5(TCG_REG_P6, OPC_ADDL_A5, ret, 1, TCG_REG_R0),
1417 tcg_opc_a5(TCG_REG_P7, OPC_ADDL_A5, ret, 0, TCG_REG_R0));
1418 }
1419
1420 static inline void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGArg ret,
1421 TCGArg c1, TCGArg c2,
1422 TCGArg v1, int const_v1,
1423 TCGArg v2, int const_v2, int cmp4)
1424 {
1425 uint64_t opc1, opc2;
1426
1427 if (const_v1) {
1428 opc1 = tcg_opc_a5(TCG_REG_P6, OPC_ADDL_A5, ret, v1, TCG_REG_R0);
1429 } else if (ret == v1) {
1430 opc1 = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
1431 } else {
1432 opc1 = tcg_opc_a4(TCG_REG_P6, OPC_ADDS_A4, ret, 0, v1);
1433 }
1434 if (const_v2) {
1435 opc2 = tcg_opc_a5(TCG_REG_P7, OPC_ADDL_A5, ret, v2, TCG_REG_R0);
1436 } else if (ret == v2) {
1437 opc2 = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
1438 } else {
1439 opc2 = tcg_opc_a4(TCG_REG_P7, OPC_ADDS_A4, ret, 0, v2);
1440 }
1441
1442 tcg_out_bundle(s, MmI,
1443 tcg_opc_cmp_a(TCG_REG_P0, cond, c1, c2, cmp4),
1444 opc1,
1445 opc2);
1446 }
1447
1448 #if defined(CONFIG_SOFTMMU)
1449
1450 #include "../../softmmu_defs.h"
1451
1452 /* Load and compare a TLB entry, and return the result in (p6, p7).
1453 R2 is loaded with the address of the addend TLB entry.
1454 R57 is loaded with the address, zero extented on 32-bit targets. */
1455 static inline void tcg_out_qemu_tlb(TCGContext *s, TCGArg addr_reg,
1456 int s_bits, uint64_t offset_rw,
1457 uint64_t offset_addend)
1458 {
1459 tcg_out_bundle(s, mII,
1460 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1461 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, TCG_REG_R2,
1462 addr_reg, TARGET_PAGE_BITS, CPU_TLB_BITS - 1),
1463 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, TCG_REG_R2,
1464 TCG_REG_R2, 63 - CPU_TLB_ENTRY_BITS,
1465 63 - CPU_TLB_ENTRY_BITS));
1466 tcg_out_bundle(s, mII,
1467 tcg_opc_a5 (TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R2,
1468 offset_rw, TCG_REG_R2),
1469 #if TARGET_LONG_BITS == 32
1470 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R57, addr_reg),
1471 #else
1472 tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R57,
1473 0, addr_reg),
1474 #endif
1475 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1476 TCG_REG_R2, TCG_AREG0));
1477 tcg_out_bundle(s, mII,
1478 tcg_opc_m3 (TCG_REG_P0,
1479 (TARGET_LONG_BITS == 32
1480 ? OPC_LD4_M3 : OPC_LD8_M3), TCG_REG_R56,
1481 TCG_REG_R2, offset_addend - offset_rw),
1482 tcg_opc_i14(TCG_REG_P0, OPC_DEP_I14, TCG_REG_R3, 0,
1483 TCG_REG_R57, 63 - s_bits,
1484 TARGET_PAGE_BITS - s_bits - 1),
1485 tcg_opc_a6 (TCG_REG_P0, OPC_CMP_EQ_A6, TCG_REG_P6,
1486 TCG_REG_P7, TCG_REG_R3, TCG_REG_R56));
1487 }
1488
1489 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
1490 int mmu_idx) */
1491 static const void * const qemu_ld_helpers[4] = {
1492 helper_ldb_mmu,
1493 helper_ldw_mmu,
1494 helper_ldl_mmu,
1495 helper_ldq_mmu,
1496 };
1497
1498 static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
1499 {
1500 int addr_reg, data_reg, mem_index, s_bits, bswap;
1501 uint64_t opc_ld_m1[4] = { OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1 };
1502 uint64_t opc_ext_i29[8] = { OPC_ZXT1_I29, OPC_ZXT2_I29, OPC_ZXT4_I29, 0,
1503 OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0 };
1504
1505 data_reg = *args++;
1506 addr_reg = *args++;
1507 mem_index = *args;
1508 s_bits = opc & 3;
1509
1510 #ifdef TARGET_WORDS_BIGENDIAN
1511 bswap = 1;
1512 #else
1513 bswap = 0;
1514 #endif
1515
1516 /* Read the TLB entry */
1517 tcg_out_qemu_tlb(s, addr_reg, s_bits,
1518 offsetof(CPUArchState, tlb_table[mem_index][0].addr_read),
1519 offsetof(CPUArchState, tlb_table[mem_index][0].addend));
1520
1521 /* P6 is the fast path, and P7 the slow path */
1522 tcg_out_bundle(s, mLX,
1523 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4,
1524 TCG_REG_R56, 0, TCG_AREG0),
1525 tcg_opc_l2 ((tcg_target_long) qemu_ld_helpers[s_bits]),
1526 tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2,
1527 (tcg_target_long) qemu_ld_helpers[s_bits]));
1528 tcg_out_bundle(s, MmI,
1529 tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3,
1530 TCG_REG_R2, 8),
1531 tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3,
1532 TCG_REG_R3, TCG_REG_R57),
1533 tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6,
1534 TCG_REG_R3, 0));
1535 if (bswap && s_bits == 1) {
1536 tcg_out_bundle(s, MmI,
1537 tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
1538 TCG_REG_R8, TCG_REG_R3),
1539 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
1540 tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1541 TCG_REG_R8, TCG_REG_R8, 15, 15));
1542 } else if (bswap && s_bits == 2) {
1543 tcg_out_bundle(s, MmI,
1544 tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
1545 TCG_REG_R8, TCG_REG_R3),
1546 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
1547 tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1548 TCG_REG_R8, TCG_REG_R8, 31, 31));
1549 } else {
1550 tcg_out_bundle(s, mmI,
1551 tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
1552 TCG_REG_R8, TCG_REG_R3),
1553 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
1554 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1555 }
1556 if (!bswap || s_bits == 0) {
1557 tcg_out_bundle(s, miB,
1558 tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58,
1559 mem_index, TCG_REG_R0),
1560 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1561 tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
1562 TCG_REG_B0, TCG_REG_B6));
1563 } else {
1564 tcg_out_bundle(s, miB,
1565 tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58,
1566 mem_index, TCG_REG_R0),
1567 tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1568 TCG_REG_R8, TCG_REG_R8, 0xb),
1569 tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
1570 TCG_REG_B0, TCG_REG_B6));
1571 }
1572
1573 if (opc == 3) {
1574 tcg_out_bundle(s, miI,
1575 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1576 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1577 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
1578 data_reg, 0, TCG_REG_R8));
1579 } else {
1580 tcg_out_bundle(s, miI,
1581 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1582 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1583 tcg_opc_i29(TCG_REG_P0, opc_ext_i29[opc],
1584 data_reg, TCG_REG_R8));
1585 }
1586 }
1587
1588 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
1589 uintxx_t val, int mmu_idx) */
1590 static const void * const qemu_st_helpers[4] = {
1591 helper_stb_mmu,
1592 helper_stw_mmu,
1593 helper_stl_mmu,
1594 helper_stq_mmu,
1595 };
1596
1597 static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
1598 {
1599 int addr_reg, data_reg, mem_index, bswap;
1600 uint64_t opc_st_m4[4] = { OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4 };
1601
1602 data_reg = *args++;
1603 addr_reg = *args++;
1604 mem_index = *args;
1605
1606 #ifdef TARGET_WORDS_BIGENDIAN
1607 bswap = 1;
1608 #else
1609 bswap = 0;
1610 #endif
1611
1612 tcg_out_qemu_tlb(s, addr_reg, opc,
1613 offsetof(CPUArchState, tlb_table[mem_index][0].addr_write),
1614 offsetof(CPUArchState, tlb_table[mem_index][0].addend));
1615
1616 /* P6 is the fast path, and P7 the slow path */
1617 tcg_out_bundle(s, mLX,
1618 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4,
1619 TCG_REG_R56, 0, TCG_AREG0),
1620 tcg_opc_l2 ((tcg_target_long) qemu_st_helpers[opc]),
1621 tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2,
1622 (tcg_target_long) qemu_st_helpers[opc]));
1623 tcg_out_bundle(s, MmI,
1624 tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3,
1625 TCG_REG_R2, 8),
1626 tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3,
1627 TCG_REG_R3, TCG_REG_R57),
1628 tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6,
1629 TCG_REG_R3, 0));
1630
1631 if (!bswap || opc == 0) {
1632 tcg_out_bundle(s, mii,
1633 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1634 TCG_REG_R1, TCG_REG_R2),
1635 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58,
1636 0, data_reg),
1637 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1638 } else if (opc == 1) {
1639 tcg_out_bundle(s, miI,
1640 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1641 TCG_REG_R1, TCG_REG_R2),
1642 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1643 tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1644 TCG_REG_R2, data_reg, 15, 15));
1645 tcg_out_bundle(s, miI,
1646 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58,
1647 0, data_reg),
1648 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1649 tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1650 TCG_REG_R2, TCG_REG_R2, 0xb));
1651 data_reg = TCG_REG_R2;
1652 } else if (opc == 2) {
1653 tcg_out_bundle(s, miI,
1654 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1655 TCG_REG_R1, TCG_REG_R2),
1656 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1657 tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1658 TCG_REG_R2, data_reg, 31, 31));
1659 tcg_out_bundle(s, miI,
1660 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58,
1661 0, data_reg),
1662 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1663 tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1664 TCG_REG_R2, TCG_REG_R2, 0xb));
1665 data_reg = TCG_REG_R2;
1666 } else if (opc == 3) {
1667 tcg_out_bundle(s, miI,
1668 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1669 TCG_REG_R1, TCG_REG_R2),
1670 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58,
1671 0, data_reg),
1672 tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1673 TCG_REG_R2, data_reg, 0xb));
1674 data_reg = TCG_REG_R2;
1675 }
1676
1677 tcg_out_bundle(s, miB,
1678 tcg_opc_m4 (TCG_REG_P6, opc_st_m4[opc],
1679 data_reg, TCG_REG_R3),
1680 tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R59,
1681 mem_index, TCG_REG_R0),
1682 tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
1683 TCG_REG_B0, TCG_REG_B6));
1684 }
1685
1686 #else /* !CONFIG_SOFTMMU */
1687
1688 static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
1689 {
1690 static uint64_t const opc_ld_m1[4] = {
1691 OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1
1692 };
1693 static uint64_t const opc_sxt_i29[4] = {
1694 OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0
1695 };
1696 int addr_reg, data_reg, s_bits, bswap;
1697
1698 data_reg = *args++;
1699 addr_reg = *args++;
1700 s_bits = opc & 3;
1701
1702 #ifdef TARGET_WORDS_BIGENDIAN
1703 bswap = 1;
1704 #else
1705 bswap = 0;
1706 #endif
1707
1708 #if TARGET_LONG_BITS == 32
1709 if (GUEST_BASE != 0) {
1710 tcg_out_bundle(s, mII,
1711 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1712 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1713 TCG_REG_R3, addr_reg),
1714 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1715 TCG_GUEST_BASE_REG, TCG_REG_R3));
1716 } else {
1717 tcg_out_bundle(s, miI,
1718 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1719 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1720 TCG_REG_R2, addr_reg),
1721 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1722 }
1723
1724 if (!bswap || s_bits == 0) {
1725 if (s_bits == opc) {
1726 tcg_out_bundle(s, miI,
1727 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1728 data_reg, TCG_REG_R2),
1729 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1730 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1731 } else {
1732 tcg_out_bundle(s, mII,
1733 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1734 data_reg, TCG_REG_R2),
1735 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1736 tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits],
1737 data_reg, data_reg));
1738 }
1739 } else if (s_bits == 3) {
1740 tcg_out_bundle(s, mII,
1741 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1742 data_reg, TCG_REG_R2),
1743 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1744 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1745 data_reg, data_reg, 0xb));
1746 } else {
1747 if (s_bits == 1) {
1748 tcg_out_bundle(s, mII,
1749 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1750 data_reg, TCG_REG_R2),
1751 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1752 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1753 data_reg, data_reg, 15, 15));
1754 } else {
1755 tcg_out_bundle(s, mII,
1756 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1757 data_reg, TCG_REG_R2),
1758 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1759 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1760 data_reg, data_reg, 31, 31));
1761 }
1762 if (opc == s_bits) {
1763 tcg_out_bundle(s, miI,
1764 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1765 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1766 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1767 data_reg, data_reg, 0xb));
1768 } else {
1769 tcg_out_bundle(s, mII,
1770 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1771 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1772 data_reg, data_reg, 0xb),
1773 tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits],
1774 data_reg, data_reg));
1775 }
1776 }
1777 #else
1778 if (GUEST_BASE != 0) {
1779 tcg_out_bundle(s, MmI,
1780 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1781 TCG_GUEST_BASE_REG, addr_reg),
1782 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1783 data_reg, TCG_REG_R2),
1784 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1785 } else {
1786 tcg_out_bundle(s, mmI,
1787 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1788 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1789 data_reg, addr_reg),
1790 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1791 }
1792
1793 if (bswap && s_bits == 1) {
1794 tcg_out_bundle(s, mII,
1795 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1796 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1797 data_reg, data_reg, 15, 15),
1798 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1799 data_reg, data_reg, 0xb));
1800 } else if (bswap && s_bits == 2) {
1801 tcg_out_bundle(s, mII,
1802 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1803 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1804 data_reg, data_reg, 31, 31),
1805 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1806 data_reg, data_reg, 0xb));
1807 } else if (bswap && s_bits == 3) {
1808 tcg_out_bundle(s, miI,
1809 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1810 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1811 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1812 data_reg, data_reg, 0xb));
1813 }
1814 if (s_bits != opc) {
1815 tcg_out_bundle(s, miI,
1816 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1817 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1818 tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits],
1819 data_reg, data_reg));
1820 }
1821 #endif
1822 }
1823
1824 static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
1825 {
1826 static uint64_t const opc_st_m4[4] = {
1827 OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4
1828 };
1829 int addr_reg, data_reg, bswap;
1830 #if TARGET_LONG_BITS == 64
1831 uint64_t add_guest_base;
1832 #endif
1833
1834 data_reg = *args++;
1835 addr_reg = *args++;
1836
1837 #ifdef TARGET_WORDS_BIGENDIAN
1838 bswap = 1;
1839 #else
1840 bswap = 0;
1841 #endif
1842
1843 #if TARGET_LONG_BITS == 32
1844 if (GUEST_BASE != 0) {
1845 tcg_out_bundle(s, mII,
1846 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1847 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1848 TCG_REG_R3, addr_reg),
1849 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1850 TCG_GUEST_BASE_REG, TCG_REG_R3));
1851 } else {
1852 tcg_out_bundle(s, miI,
1853 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1854 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1855 TCG_REG_R2, addr_reg),
1856 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1857 }
1858
1859 if (bswap) {
1860 if (opc == 1) {
1861 tcg_out_bundle(s, mII,
1862 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1863 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1864 TCG_REG_R3, data_reg, 15, 15),
1865 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1866 TCG_REG_R3, TCG_REG_R3, 0xb));
1867 data_reg = TCG_REG_R3;
1868 } else if (opc == 2) {
1869 tcg_out_bundle(s, mII,
1870 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1871 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1872 TCG_REG_R3, data_reg, 31, 31),
1873 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1874 TCG_REG_R3, TCG_REG_R3, 0xb));
1875 data_reg = TCG_REG_R3;
1876 } else if (opc == 3) {
1877 tcg_out_bundle(s, miI,
1878 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1879 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1880 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1881 TCG_REG_R3, data_reg, 0xb));
1882 data_reg = TCG_REG_R3;
1883 }
1884 }
1885 tcg_out_bundle(s, mmI,
1886 tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc],
1887 data_reg, TCG_REG_R2),
1888 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1889 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1890 #else
1891 if (GUEST_BASE != 0) {
1892 add_guest_base = tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1893 TCG_GUEST_BASE_REG, addr_reg);
1894 addr_reg = TCG_REG_R2;
1895 } else {
1896 add_guest_base = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
1897 }
1898
1899 if (!bswap || opc == 0) {
1900 tcg_out_bundle(s, (GUEST_BASE ? MmI : mmI),
1901 add_guest_base,
1902 tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc],
1903 data_reg, addr_reg),
1904 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1905 } else {
1906 if (opc == 1) {
1907 tcg_out_bundle(s, mII,
1908 add_guest_base,
1909 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1910 TCG_REG_R3, data_reg, 15, 15),
1911 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1912 TCG_REG_R3, TCG_REG_R3, 0xb));
1913 data_reg = TCG_REG_R3;
1914 } else if (opc == 2) {
1915 tcg_out_bundle(s, mII,
1916 add_guest_base,
1917 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1918 TCG_REG_R3, data_reg, 31, 31),
1919 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1920 TCG_REG_R3, TCG_REG_R3, 0xb));
1921 data_reg = TCG_REG_R3;
1922 } else if (opc == 3) {
1923 tcg_out_bundle(s, miI,
1924 add_guest_base,
1925 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1926 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1927 TCG_REG_R3, data_reg, 0xb));
1928 data_reg = TCG_REG_R3;
1929 }
1930 tcg_out_bundle(s, miI,
1931 tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc],
1932 data_reg, addr_reg),
1933 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1934 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1935 }
1936 #endif
1937 }
1938
1939 #endif
1940
1941 static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
1942 const TCGArg *args, const int *const_args)
1943 {
1944 switch(opc) {
1945 case INDEX_op_exit_tb:
1946 tcg_out_exit_tb(s, args[0]);
1947 break;
1948 case INDEX_op_br:
1949 tcg_out_br(s, args[0]);
1950 break;
1951 case INDEX_op_call:
1952 tcg_out_call(s, args[0]);
1953 break;
1954 case INDEX_op_goto_tb:
1955 tcg_out_goto_tb(s, args[0]);
1956 break;
1957
1958 case INDEX_op_movi_i32:
1959 tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
1960 break;
1961 case INDEX_op_movi_i64:
1962 tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
1963 break;
1964
1965 case INDEX_op_ld8u_i32:
1966 case INDEX_op_ld8u_i64:
1967 tcg_out_ld_rel(s, OPC_LD1_M1, args[0], args[1], args[2]);
1968 break;
1969 case INDEX_op_ld8s_i32:
1970 case INDEX_op_ld8s_i64:
1971 tcg_out_ld_rel(s, OPC_LD1_M1, args[0], args[1], args[2]);
1972 tcg_out_ext(s, OPC_SXT1_I29, args[0], args[0]);
1973 break;
1974 case INDEX_op_ld16u_i32:
1975 case INDEX_op_ld16u_i64:
1976 tcg_out_ld_rel(s, OPC_LD2_M1, args[0], args[1], args[2]);
1977 break;
1978 case INDEX_op_ld16s_i32:
1979 case INDEX_op_ld16s_i64:
1980 tcg_out_ld_rel(s, OPC_LD2_M1, args[0], args[1], args[2]);
1981 tcg_out_ext(s, OPC_SXT2_I29, args[0], args[0]);
1982 break;
1983 case INDEX_op_ld_i32:
1984 case INDEX_op_ld32u_i64:
1985 tcg_out_ld_rel(s, OPC_LD4_M1, args[0], args[1], args[2]);
1986 break;
1987 case INDEX_op_ld32s_i64:
1988 tcg_out_ld_rel(s, OPC_LD4_M1, args[0], args[1], args[2]);
1989 tcg_out_ext(s, OPC_SXT4_I29, args[0], args[0]);
1990 break;
1991 case INDEX_op_ld_i64:
1992 tcg_out_ld_rel(s, OPC_LD8_M1, args[0], args[1], args[2]);
1993 break;
1994 case INDEX_op_st8_i32:
1995 case INDEX_op_st8_i64:
1996 tcg_out_st_rel(s, OPC_ST1_M4, args[0], args[1], args[2]);
1997 break;
1998 case INDEX_op_st16_i32:
1999 case INDEX_op_st16_i64:
2000 tcg_out_st_rel(s, OPC_ST2_M4, args[0], args[1], args[2]);
2001 break;
2002 case INDEX_op_st_i32:
2003 case INDEX_op_st32_i64:
2004 tcg_out_st_rel(s, OPC_ST4_M4, args[0], args[1], args[2]);
2005 break;
2006 case INDEX_op_st_i64:
2007 tcg_out_st_rel(s, OPC_ST8_M4, args[0], args[1], args[2]);
2008 break;
2009
2010 case INDEX_op_add_i32:
2011 case INDEX_op_add_i64:
2012 tcg_out_alu(s, OPC_ADD_A1, args[0], args[1], const_args[1],
2013 args[2], const_args[2]);
2014 break;
2015 case INDEX_op_sub_i32:
2016 case INDEX_op_sub_i64:
2017 tcg_out_alu(s, OPC_SUB_A1, args[0], args[1], const_args[1],
2018 args[2], const_args[2]);
2019 break;
2020
2021 case INDEX_op_and_i32:
2022 case INDEX_op_and_i64:
2023 tcg_out_alu(s, OPC_AND_A1, args[0], args[1], const_args[1],
2024 args[2], const_args[2]);
2025 break;
2026 case INDEX_op_andc_i32:
2027 case INDEX_op_andc_i64:
2028 tcg_out_alu(s, OPC_ANDCM_A1, args[0], args[1], const_args[1],
2029 args[2], const_args[2]);
2030 break;
2031 case INDEX_op_eqv_i32:
2032 case INDEX_op_eqv_i64:
2033 tcg_out_eqv(s, args[0], args[1], const_args[1],
2034 args[2], const_args[2]);
2035 break;
2036 case INDEX_op_nand_i32:
2037 case INDEX_op_nand_i64:
2038 tcg_out_nand(s, args[0], args[1], const_args[1],
2039 args[2], const_args[2]);
2040 break;
2041 case INDEX_op_nor_i32:
2042 case INDEX_op_nor_i64:
2043 tcg_out_nor(s, args[0], args[1], const_args[1],
2044 args[2], const_args[2]);
2045 break;
2046 case INDEX_op_or_i32:
2047 case INDEX_op_or_i64:
2048 tcg_out_alu(s, OPC_OR_A1, args[0], args[1], const_args[1],
2049 args[2], const_args[2]);
2050 break;
2051 case INDEX_op_orc_i32:
2052 case INDEX_op_orc_i64:
2053 tcg_out_orc(s, args[0], args[1], const_args[1],
2054 args[2], const_args[2]);
2055 break;
2056 case INDEX_op_xor_i32:
2057 case INDEX_op_xor_i64:
2058 tcg_out_alu(s, OPC_XOR_A1, args[0], args[1], const_args[1],
2059 args[2], const_args[2]);
2060 break;
2061
2062 case INDEX_op_mul_i32:
2063 case INDEX_op_mul_i64:
2064 tcg_out_mul(s, args[0], args[1], args[2]);
2065 break;
2066
2067 case INDEX_op_sar_i32:
2068 tcg_out_sar_i32(s, args[0], args[1], args[2], const_args[2]);
2069 break;
2070 case INDEX_op_sar_i64:
2071 tcg_out_sar_i64(s, args[0], args[1], args[2], const_args[2]);
2072 break;
2073 case INDEX_op_shl_i32:
2074 tcg_out_shl_i32(s, args[0], args[1], args[2], const_args[2]);
2075 break;
2076 case INDEX_op_shl_i64:
2077 tcg_out_shl_i64(s, args[0], args[1], args[2], const_args[2]);
2078 break;
2079 case INDEX_op_shr_i32:
2080 tcg_out_shr_i32(s, args[0], args[1], args[2], const_args[2]);
2081 break;
2082 case INDEX_op_shr_i64:
2083 tcg_out_shr_i64(s, args[0], args[1], args[2], const_args[2]);
2084 break;
2085 case INDEX_op_rotl_i32:
2086 tcg_out_rotl_i32(s, args[0], args[1], args[2], const_args[2]);
2087 break;
2088 case INDEX_op_rotl_i64:
2089 tcg_out_rotl_i64(s, args[0], args[1], args[2], const_args[2]);
2090 break;
2091 case INDEX_op_rotr_i32:
2092 tcg_out_rotr_i32(s, args[0], args[1], args[2], const_args[2]);
2093 break;
2094 case INDEX_op_rotr_i64:
2095 tcg_out_rotr_i64(s, args[0], args[1], args[2], const_args[2]);
2096 break;
2097
2098 case INDEX_op_ext8s_i32:
2099 case INDEX_op_ext8s_i64:
2100 tcg_out_ext(s, OPC_SXT1_I29, args[0], args[1]);
2101 break;
2102 case INDEX_op_ext8u_i32:
2103 case INDEX_op_ext8u_i64:
2104 tcg_out_ext(s, OPC_ZXT1_I29, args[0], args[1]);
2105 break;
2106 case INDEX_op_ext16s_i32:
2107 case INDEX_op_ext16s_i64:
2108 tcg_out_ext(s, OPC_SXT2_I29, args[0], args[1]);
2109 break;
2110 case INDEX_op_ext16u_i32:
2111 case INDEX_op_ext16u_i64:
2112 tcg_out_ext(s, OPC_ZXT2_I29, args[0], args[1]);
2113 break;
2114 case INDEX_op_ext32s_i64:
2115 tcg_out_ext(s, OPC_SXT4_I29, args[0], args[1]);
2116 break;
2117 case INDEX_op_ext32u_i64:
2118 tcg_out_ext(s, OPC_ZXT4_I29, args[0], args[1]);
2119 break;
2120
2121 case INDEX_op_bswap16_i32:
2122 case INDEX_op_bswap16_i64:
2123 tcg_out_bswap16(s, args[0], args[1]);
2124 break;
2125 case INDEX_op_bswap32_i32:
2126 case INDEX_op_bswap32_i64:
2127 tcg_out_bswap32(s, args[0], args[1]);
2128 break;
2129 case INDEX_op_bswap64_i64:
2130 tcg_out_bswap64(s, args[0], args[1]);
2131 break;
2132
2133 case INDEX_op_brcond_i32:
2134 tcg_out_brcond(s, args[2], args[0], const_args[0],
2135 args[1], const_args[1], args[3], 1);
2136 break;
2137 case INDEX_op_brcond_i64:
2138 tcg_out_brcond(s, args[2], args[0], const_args[0],
2139 args[1], const_args[1], args[3], 0);
2140 break;
2141 case INDEX_op_setcond_i32:
2142 tcg_out_setcond(s, args[3], args[0], args[1], args[2], 1);
2143 break;
2144 case INDEX_op_setcond_i64:
2145 tcg_out_setcond(s, args[3], args[0], args[1], args[2], 0);
2146 break;
2147 case INDEX_op_movcond_i32:
2148 tcg_out_movcond(s, args[5], args[0], args[1], args[2],
2149 args[3], const_args[3], args[4], const_args[4], 1);
2150 break;
2151 case INDEX_op_movcond_i64:
2152 tcg_out_movcond(s, args[5], args[0], args[1], args[2],
2153 args[3], const_args[3], args[4], const_args[4], 0);
2154 break;
2155
2156 case INDEX_op_qemu_ld8u:
2157 tcg_out_qemu_ld(s, args, 0);
2158 break;
2159 case INDEX_op_qemu_ld8s:
2160 tcg_out_qemu_ld(s, args, 0 | 4);
2161 break;
2162 case INDEX_op_qemu_ld16u:
2163 tcg_out_qemu_ld(s, args, 1);
2164 break;
2165 case INDEX_op_qemu_ld16s:
2166 tcg_out_qemu_ld(s, args, 1 | 4);
2167 break;
2168 case INDEX_op_qemu_ld32:
2169 case INDEX_op_qemu_ld32u:
2170 tcg_out_qemu_ld(s, args, 2);
2171 break;
2172 case INDEX_op_qemu_ld32s:
2173 tcg_out_qemu_ld(s, args, 2 | 4);
2174 break;
2175 case INDEX_op_qemu_ld64:
2176 tcg_out_qemu_ld(s, args, 3);
2177 break;
2178
2179 case INDEX_op_qemu_st8:
2180 tcg_out_qemu_st(s, args, 0);
2181 break;
2182 case INDEX_op_qemu_st16:
2183 tcg_out_qemu_st(s, args, 1);
2184 break;
2185 case INDEX_op_qemu_st32:
2186 tcg_out_qemu_st(s, args, 2);
2187 break;
2188 case INDEX_op_qemu_st64:
2189 tcg_out_qemu_st(s, args, 3);
2190 break;
2191
2192 default:
2193 tcg_abort();
2194 }
2195 }
2196
2197 static const TCGTargetOpDef ia64_op_defs[] = {
2198 { INDEX_op_br, { } },
2199 { INDEX_op_call, { "r" } },
2200 { INDEX_op_exit_tb, { } },
2201 { INDEX_op_goto_tb, { } },
2202
2203 { INDEX_op_mov_i32, { "r", "r" } },
2204 { INDEX_op_movi_i32, { "r" } },
2205
2206 { INDEX_op_ld8u_i32, { "r", "r" } },
2207 { INDEX_op_ld8s_i32, { "r", "r" } },
2208 { INDEX_op_ld16u_i32, { "r", "r" } },
2209 { INDEX_op_ld16s_i32, { "r", "r" } },
2210 { INDEX_op_ld_i32, { "r", "r" } },
2211 { INDEX_op_st8_i32, { "rZ", "r" } },
2212 { INDEX_op_st16_i32, { "rZ", "r" } },
2213 { INDEX_op_st_i32, { "rZ", "r" } },
2214
2215 { INDEX_op_add_i32, { "r", "rI", "rI" } },
2216 { INDEX_op_sub_i32, { "r", "rI", "rI" } },
2217
2218 { INDEX_op_and_i32, { "r", "rI", "rI" } },
2219 { INDEX_op_andc_i32, { "r", "rI", "rI" } },
2220 { INDEX_op_eqv_i32, { "r", "rZ", "rZ" } },
2221 { INDEX_op_nand_i32, { "r", "rZ", "rZ" } },
2222 { INDEX_op_nor_i32, { "r", "rZ", "rZ" } },
2223 { INDEX_op_or_i32, { "r", "rI", "rI" } },
2224 { INDEX_op_orc_i32, { "r", "rZ", "rZ" } },
2225 { INDEX_op_xor_i32, { "r", "rI", "rI" } },
2226
2227 { INDEX_op_mul_i32, { "r", "rZ", "rZ" } },
2228
2229 { INDEX_op_sar_i32, { "r", "rZ", "ri" } },
2230 { INDEX_op_shl_i32, { "r", "rZ", "ri" } },
2231 { INDEX_op_shr_i32, { "r", "rZ", "ri" } },
2232 { INDEX_op_rotl_i32, { "r", "rZ", "ri" } },
2233 { INDEX_op_rotr_i32, { "r", "rZ", "ri" } },
2234
2235 { INDEX_op_ext8s_i32, { "r", "rZ"} },
2236 { INDEX_op_ext8u_i32, { "r", "rZ"} },
2237 { INDEX_op_ext16s_i32, { "r", "rZ"} },
2238 { INDEX_op_ext16u_i32, { "r", "rZ"} },
2239
2240 { INDEX_op_bswap16_i32, { "r", "rZ" } },
2241 { INDEX_op_bswap32_i32, { "r", "rZ" } },
2242
2243 { INDEX_op_brcond_i32, { "rI", "rI" } },
2244 { INDEX_op_setcond_i32, { "r", "rZ", "rZ" } },
2245 { INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rI", "rI" } },
2246
2247 { INDEX_op_mov_i64, { "r", "r" } },
2248 { INDEX_op_movi_i64, { "r" } },
2249
2250 { INDEX_op_ld8u_i64, { "r", "r" } },
2251 { INDEX_op_ld8s_i64, { "r", "r" } },
2252 { INDEX_op_ld16u_i64, { "r", "r" } },
2253 { INDEX_op_ld16s_i64, { "r", "r" } },
2254 { INDEX_op_ld32u_i64, { "r", "r" } },
2255 { INDEX_op_ld32s_i64, { "r", "r" } },
2256 { INDEX_op_ld_i64, { "r", "r" } },
2257 { INDEX_op_st8_i64, { "rZ", "r" } },
2258 { INDEX_op_st16_i64, { "rZ", "r" } },
2259 { INDEX_op_st32_i64, { "rZ", "r" } },
2260 { INDEX_op_st_i64, { "rZ", "r" } },
2261
2262 { INDEX_op_add_i64, { "r", "rI", "rI" } },
2263 { INDEX_op_sub_i64, { "r", "rI", "rI" } },
2264
2265 { INDEX_op_and_i64, { "r", "rI", "rI" } },
2266 { INDEX_op_andc_i64, { "r", "rI", "rI" } },
2267 { INDEX_op_eqv_i64, { "r", "rZ", "rZ" } },
2268 { INDEX_op_nand_i64, { "r", "rZ", "rZ" } },
2269 { INDEX_op_nor_i64, { "r", "rZ", "rZ" } },
2270 { INDEX_op_or_i64, { "r", "rI", "rI" } },
2271 { INDEX_op_orc_i64, { "r", "rZ", "rZ" } },
2272 { INDEX_op_xor_i64, { "r", "rI", "rI" } },
2273
2274 { INDEX_op_mul_i64, { "r", "rZ", "rZ" } },
2275
2276 { INDEX_op_sar_i64, { "r", "rZ", "ri" } },
2277 { INDEX_op_shl_i64, { "r", "rZ", "ri" } },
2278 { INDEX_op_shr_i64, { "r", "rZ", "ri" } },
2279 { INDEX_op_rotl_i64, { "r", "rZ", "ri" } },
2280 { INDEX_op_rotr_i64, { "r", "rZ", "ri" } },
2281
2282 { INDEX_op_ext8s_i64, { "r", "rZ"} },
2283 { INDEX_op_ext8u_i64, { "r", "rZ"} },
2284 { INDEX_op_ext16s_i64, { "r", "rZ"} },
2285 { INDEX_op_ext16u_i64, { "r", "rZ"} },
2286 { INDEX_op_ext32s_i64, { "r", "rZ"} },
2287 { INDEX_op_ext32u_i64, { "r", "rZ"} },
2288
2289 { INDEX_op_bswap16_i64, { "r", "rZ" } },
2290 { INDEX_op_bswap32_i64, { "r", "rZ" } },
2291 { INDEX_op_bswap64_i64, { "r", "rZ" } },
2292
2293 { INDEX_op_brcond_i64, { "rI", "rI" } },
2294 { INDEX_op_setcond_i64, { "r", "rZ", "rZ" } },
2295 { INDEX_op_movcond_i64, { "r", "rZ", "rZ", "rI", "rI" } },
2296
2297 { INDEX_op_qemu_ld8u, { "r", "r" } },
2298 { INDEX_op_qemu_ld8s, { "r", "r" } },
2299 { INDEX_op_qemu_ld16u, { "r", "r" } },
2300 { INDEX_op_qemu_ld16s, { "r", "r" } },
2301 { INDEX_op_qemu_ld32, { "r", "r" } },
2302 { INDEX_op_qemu_ld32u, { "r", "r" } },
2303 { INDEX_op_qemu_ld32s, { "r", "r" } },
2304 { INDEX_op_qemu_ld64, { "r", "r" } },
2305
2306 { INDEX_op_qemu_st8, { "SZ", "r" } },
2307 { INDEX_op_qemu_st16, { "SZ", "r" } },
2308 { INDEX_op_qemu_st32, { "SZ", "r" } },
2309 { INDEX_op_qemu_st64, { "SZ", "r" } },
2310
2311 { -1 },
2312 };
2313
2314 /* Generate global QEMU prologue and epilogue code */
2315 static void tcg_target_qemu_prologue(TCGContext *s)
2316 {
2317 int frame_size;
2318
2319 /* reserve some stack space */
2320 frame_size = TCG_STATIC_CALL_ARGS_SIZE +
2321 CPU_TEMP_BUF_NLONGS * sizeof(long);
2322 frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
2323 ~(TCG_TARGET_STACK_ALIGN - 1);
2324 tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE,
2325 CPU_TEMP_BUF_NLONGS * sizeof(long));
2326
2327 /* First emit adhoc function descriptor */
2328 *(uint64_t *)(s->code_ptr) = (uint64_t)s->code_ptr + 16; /* entry point */
2329 s->code_ptr += 16; /* skip GP */
2330
2331 /* prologue */
2332 tcg_out_bundle(s, miI,
2333 tcg_opc_m34(TCG_REG_P0, OPC_ALLOC_M34,
2334 TCG_REG_R34, 32, 24, 0),
2335 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
2336 TCG_AREG0, 0, TCG_REG_R32),
2337 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
2338 TCG_REG_B6, TCG_REG_R33, 0));
2339
2340 /* ??? If GUEST_BASE < 0x200000, we could load the register via
2341 an ADDL in the M slot of the next bundle. */
2342 if (GUEST_BASE != 0) {
2343 tcg_out_bundle(s, mlx,
2344 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
2345 tcg_opc_l2 (GUEST_BASE),
2346 tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2,
2347 TCG_GUEST_BASE_REG, GUEST_BASE));
2348 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2349 }
2350
2351 tcg_out_bundle(s, miB,
2352 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
2353 TCG_REG_R12, -frame_size, TCG_REG_R12),
2354 tcg_opc_i22(TCG_REG_P0, OPC_MOV_I22,
2355 TCG_REG_R32, TCG_REG_B0),
2356 tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6));
2357
2358 /* epilogue */
2359 tb_ret_addr = s->code_ptr;
2360 tcg_out_bundle(s, miI,
2361 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
2362 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
2363 TCG_REG_B0, TCG_REG_R32, 0),
2364 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
2365 TCG_REG_R12, frame_size, TCG_REG_R12));
2366 tcg_out_bundle(s, miB,
2367 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
2368 tcg_opc_i26(TCG_REG_P0, OPC_MOV_I_I26,
2369 TCG_REG_PFS, TCG_REG_R34),
2370 tcg_opc_b4 (TCG_REG_P0, OPC_BR_RET_SPTK_MANY_B4,
2371 TCG_REG_B0));
2372 }
2373
2374 static void tcg_target_init(TCGContext *s)
2375 {
2376 tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I32],
2377 0xffffffffffffffffull);
2378 tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I64],
2379 0xffffffffffffffffull);
2380
2381 tcg_regset_clear(tcg_target_call_clobber_regs);
2382 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8);
2383 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9);
2384 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10);
2385 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11);
2386 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);
2387 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R15);
2388 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R16);
2389 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R17);
2390 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R18);
2391 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R19);
2392 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R20);
2393 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R21);
2394 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R22);
2395 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R23);
2396 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R24);
2397 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R25);
2398 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R26);
2399 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R27);
2400 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R28);
2401 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R29);
2402 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R30);
2403 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R31);
2404 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R56);
2405 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R57);
2406 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R58);
2407 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R59);
2408 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R60);
2409 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R61);
2410 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R62);
2411 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R63);
2412
2413 tcg_regset_clear(s->reserved_regs);
2414 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* zero register */
2415 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* global pointer */
2416 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* internal use */
2417 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R3); /* internal use */
2418 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R12); /* stack pointer */
2419 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
2420 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R32); /* return address */
2421 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R34); /* PFS */
2422
2423 /* The following 3 are not in use, are call-saved, but *not* saved
2424 by the prologue. Therefore we cannot use them without modifying
2425 the prologue. There doesn't seem to be any good reason to use
2426 these as opposed to the windowed registers. */
2427 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R4);
2428 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R5);
2429 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R6);
2430
2431 tcg_add_target_add_op_defs(ia64_op_defs);
2432 }
Qemu copy for testing