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tcg/ia64: fix and optimize ld/st slow path
[qemu.git] / tcg / ia64 / tcg-target.c
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2009-2010 Aurelien Jarno <aurelien@aurel32.net>
5 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 /*
27 * Register definitions
28 */
29
30 #ifndef NDEBUG
31 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
32 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
33 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
34 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
35 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
36 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
37 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
38 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
39 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
40 };
41 #endif
42
43 #ifdef CONFIG_USE_GUEST_BASE
44 #define TCG_GUEST_BASE_REG TCG_REG_R55
45 #else
46 #define TCG_GUEST_BASE_REG TCG_REG_R0
47 #endif
48 #ifndef GUEST_BASE
49 #define GUEST_BASE 0
50 #endif
51
52 /* Branch registers */
53 enum {
54 TCG_REG_B0 = 0,
55 TCG_REG_B1,
56 TCG_REG_B2,
57 TCG_REG_B3,
58 TCG_REG_B4,
59 TCG_REG_B5,
60 TCG_REG_B6,
61 TCG_REG_B7,
62 };
63
64 /* Floating point registers */
65 enum {
66 TCG_REG_F0 = 0,
67 TCG_REG_F1,
68 TCG_REG_F2,
69 TCG_REG_F3,
70 TCG_REG_F4,
71 TCG_REG_F5,
72 TCG_REG_F6,
73 TCG_REG_F7,
74 TCG_REG_F8,
75 TCG_REG_F9,
76 TCG_REG_F10,
77 TCG_REG_F11,
78 TCG_REG_F12,
79 TCG_REG_F13,
80 TCG_REG_F14,
81 TCG_REG_F15,
82 };
83
84 /* Predicate registers */
85 enum {
86 TCG_REG_P0 = 0,
87 TCG_REG_P1,
88 TCG_REG_P2,
89 TCG_REG_P3,
90 TCG_REG_P4,
91 TCG_REG_P5,
92 TCG_REG_P6,
93 TCG_REG_P7,
94 TCG_REG_P8,
95 TCG_REG_P9,
96 TCG_REG_P10,
97 TCG_REG_P11,
98 TCG_REG_P12,
99 TCG_REG_P13,
100 TCG_REG_P14,
101 TCG_REG_P15,
102 };
103
104 /* Application registers */
105 enum {
106 TCG_REG_PFS = 64,
107 };
108
109 static const int tcg_target_reg_alloc_order[] = {
110 TCG_REG_R33,
111 TCG_REG_R35,
112 TCG_REG_R36,
113 TCG_REG_R37,
114 TCG_REG_R38,
115 TCG_REG_R39,
116 TCG_REG_R40,
117 TCG_REG_R41,
118 TCG_REG_R42,
119 TCG_REG_R43,
120 TCG_REG_R44,
121 TCG_REG_R45,
122 TCG_REG_R46,
123 TCG_REG_R47,
124 TCG_REG_R48,
125 TCG_REG_R49,
126 TCG_REG_R50,
127 TCG_REG_R51,
128 TCG_REG_R52,
129 TCG_REG_R53,
130 TCG_REG_R54,
131 TCG_REG_R55,
132 TCG_REG_R14,
133 TCG_REG_R15,
134 TCG_REG_R16,
135 TCG_REG_R17,
136 TCG_REG_R18,
137 TCG_REG_R19,
138 TCG_REG_R20,
139 TCG_REG_R21,
140 TCG_REG_R22,
141 TCG_REG_R23,
142 TCG_REG_R24,
143 TCG_REG_R25,
144 TCG_REG_R26,
145 TCG_REG_R27,
146 TCG_REG_R28,
147 TCG_REG_R29,
148 TCG_REG_R30,
149 TCG_REG_R31,
150 TCG_REG_R56,
151 TCG_REG_R57,
152 TCG_REG_R58,
153 TCG_REG_R59,
154 TCG_REG_R60,
155 TCG_REG_R61,
156 TCG_REG_R62,
157 TCG_REG_R63,
158 TCG_REG_R8,
159 TCG_REG_R9,
160 TCG_REG_R10,
161 TCG_REG_R11
162 };
163
164 static const int tcg_target_call_iarg_regs[8] = {
165 TCG_REG_R56,
166 TCG_REG_R57,
167 TCG_REG_R58,
168 TCG_REG_R59,
169 TCG_REG_R60,
170 TCG_REG_R61,
171 TCG_REG_R62,
172 TCG_REG_R63,
173 };
174
175 static const int tcg_target_call_oarg_regs[] = {
176 TCG_REG_R8
177 };
178
179 /* maximum number of register used for input function arguments */
180 static inline int tcg_target_get_call_iarg_regs_count(int flags)
181 {
182 return 8;
183 }
184
185 /*
186 * opcode formation
187 */
188
189 /* bundle templates: stops (double bar in the IA64 manual) are marked with
190 an uppercase letter. */
191 enum {
192 mii = 0x00,
193 miI = 0x01,
194 mIi = 0x02,
195 mII = 0x03,
196 mlx = 0x04,
197 mLX = 0x05,
198 mmi = 0x08,
199 mmI = 0x09,
200 Mmi = 0x0a,
201 MmI = 0x0b,
202 mfi = 0x0c,
203 mfI = 0x0d,
204 mmf = 0x0e,
205 mmF = 0x0f,
206 mib = 0x10,
207 miB = 0x11,
208 mbb = 0x12,
209 mbB = 0x13,
210 bbb = 0x16,
211 bbB = 0x17,
212 mmb = 0x18,
213 mmB = 0x19,
214 mfb = 0x1c,
215 mfB = 0x1d,
216 };
217
218 enum {
219 OPC_ADD_A1 = 0x10000000000ull,
220 OPC_AND_A1 = 0x10060000000ull,
221 OPC_AND_A3 = 0x10160000000ull,
222 OPC_ANDCM_A1 = 0x10068000000ull,
223 OPC_ANDCM_A3 = 0x10168000000ull,
224 OPC_ADDS_A4 = 0x10800000000ull,
225 OPC_ADDL_A5 = 0x12000000000ull,
226 OPC_ALLOC_M34 = 0x02c00000000ull,
227 OPC_BR_DPTK_FEW_B1 = 0x08400000000ull,
228 OPC_BR_SPTK_MANY_B1 = 0x08000001000ull,
229 OPC_BR_SPTK_MANY_B4 = 0x00100001000ull,
230 OPC_BR_CALL_SPTK_MANY_B5 = 0x02100001000ull,
231 OPC_BR_RET_SPTK_MANY_B4 = 0x00108001100ull,
232 OPC_BRL_SPTK_MANY_X3 = 0x18000001000ull,
233 OPC_CMP_LT_A6 = 0x18000000000ull,
234 OPC_CMP_LTU_A6 = 0x1a000000000ull,
235 OPC_CMP_EQ_A6 = 0x1c000000000ull,
236 OPC_CMP4_LT_A6 = 0x18400000000ull,
237 OPC_CMP4_LTU_A6 = 0x1a400000000ull,
238 OPC_CMP4_EQ_A6 = 0x1c400000000ull,
239 OPC_DEP_Z_I12 = 0x0a600000000ull,
240 OPC_EXTR_I11 = 0x0a400002000ull,
241 OPC_EXTR_U_I11 = 0x0a400000000ull,
242 OPC_FCVT_FX_TRUNC_S1_F10 = 0x004d0000000ull,
243 OPC_FCVT_FXU_TRUNC_S1_F10 = 0x004d8000000ull,
244 OPC_FCVT_XF_F11 = 0x000e0000000ull,
245 OPC_FMA_S1_F1 = 0x10400000000ull,
246 OPC_FNMA_S1_F1 = 0x18400000000ull,
247 OPC_FRCPA_S1_F6 = 0x00600000000ull,
248 OPC_GETF_SIG_M19 = 0x08708000000ull,
249 OPC_LD1_M1 = 0x08000000000ull,
250 OPC_LD1_M3 = 0x0a000000000ull,
251 OPC_LD2_M1 = 0x08040000000ull,
252 OPC_LD2_M3 = 0x0a040000000ull,
253 OPC_LD4_M1 = 0x08080000000ull,
254 OPC_LD4_M3 = 0x0a080000000ull,
255 OPC_LD8_M1 = 0x080c0000000ull,
256 OPC_LD8_M3 = 0x0a0c0000000ull,
257 OPC_MUX1_I3 = 0x0eca0000000ull,
258 OPC_NOP_B9 = 0x04008000000ull,
259 OPC_NOP_F16 = 0x00008000000ull,
260 OPC_NOP_I18 = 0x00008000000ull,
261 OPC_NOP_M48 = 0x00008000000ull,
262 OPC_MOV_I21 = 0x00e00100000ull,
263 OPC_MOV_RET_I21 = 0x00e00500000ull,
264 OPC_MOV_I22 = 0x00188000000ull,
265 OPC_MOV_I_I26 = 0x00150000000ull,
266 OPC_MOVL_X2 = 0x0c000000000ull,
267 OPC_OR_A1 = 0x10070000000ull,
268 OPC_SETF_EXP_M18 = 0x0c748000000ull,
269 OPC_SETF_SIG_M18 = 0x0c708000000ull,
270 OPC_SHL_I7 = 0x0f240000000ull,
271 OPC_SHR_I5 = 0x0f220000000ull,
272 OPC_SHR_U_I5 = 0x0f200000000ull,
273 OPC_SHRP_I10 = 0x0ac00000000ull,
274 OPC_SXT1_I29 = 0x000a0000000ull,
275 OPC_SXT2_I29 = 0x000a8000000ull,
276 OPC_SXT4_I29 = 0x000b0000000ull,
277 OPC_ST1_M4 = 0x08c00000000ull,
278 OPC_ST2_M4 = 0x08c40000000ull,
279 OPC_ST4_M4 = 0x08c80000000ull,
280 OPC_ST8_M4 = 0x08cc0000000ull,
281 OPC_SUB_A1 = 0x10028000000ull,
282 OPC_SUB_A3 = 0x10128000000ull,
283 OPC_UNPACK4_L_I2 = 0x0f860000000ull,
284 OPC_XMA_L_F2 = 0x1d000000000ull,
285 OPC_XOR_A1 = 0x10078000000ull,
286 OPC_ZXT1_I29 = 0x00080000000ull,
287 OPC_ZXT2_I29 = 0x00088000000ull,
288 OPC_ZXT4_I29 = 0x00090000000ull,
289 };
290
291 static inline uint64_t tcg_opc_a1(int qp, uint64_t opc, int r1,
292 int r2, int r3)
293 {
294 return opc
295 | ((r3 & 0x7f) << 20)
296 | ((r2 & 0x7f) << 13)
297 | ((r1 & 0x7f) << 6)
298 | (qp & 0x3f);
299 }
300
301 static inline uint64_t tcg_opc_a3(int qp, uint64_t opc, int r1,
302 uint64_t imm, int r3)
303 {
304 return opc
305 | ((imm & 0x80) << 29) /* s */
306 | ((imm & 0x7f) << 13) /* imm7b */
307 | ((r3 & 0x7f) << 20)
308 | ((r1 & 0x7f) << 6)
309 | (qp & 0x3f);
310 }
311
312 static inline uint64_t tcg_opc_a4(int qp, uint64_t opc, int r1,
313 uint64_t imm, int r3)
314 {
315 return opc
316 | ((imm & 0x2000) << 23) /* s */
317 | ((imm & 0x1f80) << 20) /* imm6d */
318 | ((imm & 0x007f) << 13) /* imm7b */
319 | ((r3 & 0x7f) << 20)
320 | ((r1 & 0x7f) << 6)
321 | (qp & 0x3f);
322 }
323
324 static inline uint64_t tcg_opc_a5(int qp, uint64_t opc, int r1,
325 uint64_t imm, int r3)
326 {
327 return opc
328 | ((imm & 0x200000) << 15) /* s */
329 | ((imm & 0x1f0000) << 6) /* imm5c */
330 | ((imm & 0x00ff80) << 20) /* imm9d */
331 | ((imm & 0x00007f) << 13) /* imm7b */
332 | ((r3 & 0x03) << 20)
333 | ((r1 & 0x7f) << 6)
334 | (qp & 0x3f);
335 }
336
337 static inline uint64_t tcg_opc_a6(int qp, uint64_t opc, int p1,
338 int p2, int r2, int r3)
339 {
340 return opc
341 | ((p2 & 0x3f) << 27)
342 | ((r3 & 0x7f) << 20)
343 | ((r2 & 0x7f) << 13)
344 | ((p1 & 0x3f) << 6)
345 | (qp & 0x3f);
346 }
347
348 static inline uint64_t tcg_opc_b1(int qp, uint64_t opc, uint64_t imm)
349 {
350 return opc
351 | ((imm & 0x100000) << 16) /* s */
352 | ((imm & 0x0fffff) << 13) /* imm20b */
353 | (qp & 0x3f);
354 }
355
356 static inline uint64_t tcg_opc_b4(int qp, uint64_t opc, int b2)
357 {
358 return opc
359 | ((b2 & 0x7) << 13)
360 | (qp & 0x3f);
361 }
362
363 static inline uint64_t tcg_opc_b5(int qp, uint64_t opc, int b1, int b2)
364 {
365 return opc
366 | ((b2 & 0x7) << 13)
367 | ((b1 & 0x7) << 6)
368 | (qp & 0x3f);
369 }
370
371
372 static inline uint64_t tcg_opc_b9(int qp, uint64_t opc, uint64_t imm)
373 {
374 return opc
375 | ((imm & 0x100000) << 16) /* i */
376 | ((imm & 0x0fffff) << 6) /* imm20a */
377 | (qp & 0x3f);
378 }
379
380 static inline uint64_t tcg_opc_f1(int qp, uint64_t opc, int f1,
381 int f3, int f4, int f2)
382 {
383 return opc
384 | ((f4 & 0x7f) << 27)
385 | ((f3 & 0x7f) << 20)
386 | ((f2 & 0x7f) << 13)
387 | ((f1 & 0x7f) << 6)
388 | (qp & 0x3f);
389 }
390
391 static inline uint64_t tcg_opc_f2(int qp, uint64_t opc, int f1,
392 int f3, int f4, int f2)
393 {
394 return opc
395 | ((f4 & 0x7f) << 27)
396 | ((f3 & 0x7f) << 20)
397 | ((f2 & 0x7f) << 13)
398 | ((f1 & 0x7f) << 6)
399 | (qp & 0x3f);
400 }
401
402 static inline uint64_t tcg_opc_f6(int qp, uint64_t opc, int f1,
403 int p2, int f2, int f3)
404 {
405 return opc
406 | ((p2 & 0x3f) << 27)
407 | ((f3 & 0x7f) << 20)
408 | ((f2 & 0x7f) << 13)
409 | ((f1 & 0x7f) << 6)
410 | (qp & 0x3f);
411 }
412
413 static inline uint64_t tcg_opc_f10(int qp, uint64_t opc, int f1, int f2)
414 {
415 return opc
416 | ((f2 & 0x7f) << 13)
417 | ((f1 & 0x7f) << 6)
418 | (qp & 0x3f);
419 }
420
421 static inline uint64_t tcg_opc_f11(int qp, uint64_t opc, int f1, int f2)
422 {
423 return opc
424 | ((f2 & 0x7f) << 13)
425 | ((f1 & 0x7f) << 6)
426 | (qp & 0x3f);
427 }
428
429 static inline uint64_t tcg_opc_f16(int qp, uint64_t opc, uint64_t imm)
430 {
431 return opc
432 | ((imm & 0x100000) << 16) /* i */
433 | ((imm & 0x0fffff) << 6) /* imm20a */
434 | (qp & 0x3f);
435 }
436
437 static inline uint64_t tcg_opc_i2(int qp, uint64_t opc, int r1,
438 int r2, int r3)
439 {
440 return opc
441 | ((r3 & 0x7f) << 20)
442 | ((r2 & 0x7f) << 13)
443 | ((r1 & 0x7f) << 6)
444 | (qp & 0x3f);
445 }
446
447 static inline uint64_t tcg_opc_i3(int qp, uint64_t opc, int r1,
448 int r2, int mbtype)
449 {
450 return opc
451 | ((mbtype & 0x0f) << 20)
452 | ((r2 & 0x7f) << 13)
453 | ((r1 & 0x7f) << 6)
454 | (qp & 0x3f);
455 }
456
457 static inline uint64_t tcg_opc_i5(int qp, uint64_t opc, int r1,
458 int r3, int r2)
459 {
460 return opc
461 | ((r3 & 0x7f) << 20)
462 | ((r2 & 0x7f) << 13)
463 | ((r1 & 0x7f) << 6)
464 | (qp & 0x3f);
465 }
466
467 static inline uint64_t tcg_opc_i7(int qp, uint64_t opc, int r1,
468 int r2, int r3)
469 {
470 return opc
471 | ((r3 & 0x7f) << 20)
472 | ((r2 & 0x7f) << 13)
473 | ((r1 & 0x7f) << 6)
474 | (qp & 0x3f);
475 }
476
477 static inline uint64_t tcg_opc_i10(int qp, uint64_t opc, int r1,
478 int r2, int r3, uint64_t count)
479 {
480 return opc
481 | ((count & 0x3f) << 27)
482 | ((r3 & 0x7f) << 20)
483 | ((r2 & 0x7f) << 13)
484 | ((r1 & 0x7f) << 6)
485 | (qp & 0x3f);
486 }
487
488 static inline uint64_t tcg_opc_i11(int qp, uint64_t opc, int r1,
489 int r3, uint64_t pos, uint64_t len)
490 {
491 return opc
492 | ((len & 0x3f) << 27)
493 | ((r3 & 0x7f) << 20)
494 | ((pos & 0x3f) << 14)
495 | ((r1 & 0x7f) << 6)
496 | (qp & 0x3f);
497 }
498
499 static inline uint64_t tcg_opc_i12(int qp, uint64_t opc, int r1,
500 int r2, uint64_t pos, uint64_t len)
501 {
502 return opc
503 | ((len & 0x3f) << 27)
504 | ((pos & 0x3f) << 20)
505 | ((r2 & 0x7f) << 13)
506 | ((r1 & 0x7f) << 6)
507 | (qp & 0x3f);
508 }
509
510 static inline uint64_t tcg_opc_i18(int qp, uint64_t opc, uint64_t imm)
511 {
512 return opc
513 | ((imm & 0x100000) << 16) /* i */
514 | ((imm & 0x0fffff) << 6) /* imm20a */
515 | (qp & 0x3f);
516 }
517
518 static inline uint64_t tcg_opc_i21(int qp, uint64_t opc, int b1,
519 int r2, uint64_t imm)
520 {
521 return opc
522 | ((imm & 0x1ff) << 24)
523 | ((r2 & 0x7f) << 13)
524 | ((b1 & 0x7) << 6)
525 | (qp & 0x3f);
526 }
527
528 static inline uint64_t tcg_opc_i22(int qp, uint64_t opc, int r1, int b2)
529 {
530 return opc
531 | ((b2 & 0x7) << 13)
532 | ((r1 & 0x7f) << 6)
533 | (qp & 0x3f);
534 }
535
536 static inline uint64_t tcg_opc_i26(int qp, uint64_t opc, int ar3, int r2)
537 {
538 return opc
539 | ((ar3 & 0x7f) << 20)
540 | ((r2 & 0x7f) << 13)
541 | (qp & 0x3f);
542 }
543
544 static inline uint64_t tcg_opc_i29(int qp, uint64_t opc, int r1, int r3)
545 {
546 return opc
547 | ((r3 & 0x7f) << 20)
548 | ((r1 & 0x7f) << 6)
549 | (qp & 0x3f);
550 }
551
552 static inline uint64_t tcg_opc_l2(uint64_t imm)
553 {
554 return (imm & 0x7fffffffffc00000ull) >> 22;
555 }
556
557 static inline uint64_t tcg_opc_l3(uint64_t imm)
558 {
559 return (imm & 0x07fffffffff00000ull) >> 18;
560 }
561
562 static inline uint64_t tcg_opc_m1(int qp, uint64_t opc, int r1, int r3)
563 {
564 return opc
565 | ((r3 & 0x7f) << 20)
566 | ((r1 & 0x7f) << 6)
567 | (qp & 0x3f);
568 }
569
570 static inline uint64_t tcg_opc_m3(int qp, uint64_t opc, int r1,
571 int r3, uint64_t imm)
572 {
573 return opc
574 | ((imm & 0x100) << 28) /* s */
575 | ((imm & 0x080) << 20) /* i */
576 | ((imm & 0x07f) << 13) /* imm7b */
577 | ((r3 & 0x7f) << 20)
578 | ((r1 & 0x7f) << 6)
579 | (qp & 0x3f);
580 }
581
582 static inline uint64_t tcg_opc_m4(int qp, uint64_t opc, int r2, int r3)
583 {
584 return opc
585 | ((r3 & 0x7f) << 20)
586 | ((r2 & 0x7f) << 13)
587 | (qp & 0x3f);
588 }
589
590 static inline uint64_t tcg_opc_m18(int qp, uint64_t opc, int f1, int r2)
591 {
592 return opc
593 | ((r2 & 0x7f) << 13)
594 | ((f1 & 0x7f) << 6)
595 | (qp & 0x3f);
596 }
597
598 static inline uint64_t tcg_opc_m19(int qp, uint64_t opc, int r1, int f2)
599 {
600 return opc
601 | ((f2 & 0x7f) << 13)
602 | ((r1 & 0x7f) << 6)
603 | (qp & 0x3f);
604 }
605
606 static inline uint64_t tcg_opc_m34(int qp, uint64_t opc, int r1,
607 int sof, int sol, int sor)
608 {
609 return opc
610 | ((sor & 0x0f) << 27)
611 | ((sol & 0x7f) << 20)
612 | ((sof & 0x7f) << 13)
613 | ((r1 & 0x7f) << 6)
614 | (qp & 0x3f);
615 }
616
617 static inline uint64_t tcg_opc_m48(int qp, uint64_t opc, uint64_t imm)
618 {
619 return opc
620 | ((imm & 0x100000) << 16) /* i */
621 | ((imm & 0x0fffff) << 6) /* imm20a */
622 | (qp & 0x3f);
623 }
624
625 static inline uint64_t tcg_opc_x2(int qp, uint64_t opc,
626 int r1, uint64_t imm)
627 {
628 return opc
629 | ((imm & 0x8000000000000000ull) >> 27) /* i */
630 | (imm & 0x0000000000200000ull) /* ic */
631 | ((imm & 0x00000000001f0000ull) << 6) /* imm5c */
632 | ((imm & 0x000000000000ff80ull) << 20) /* imm9d */
633 | ((imm & 0x000000000000007full) << 13) /* imm7b */
634 | ((r1 & 0x7f) << 6)
635 | (qp & 0x3f);
636 }
637
638 static inline uint64_t tcg_opc_x3(int qp, uint64_t opc, uint64_t imm)
639 {
640 return opc
641 | ((imm & 0x0800000000000000ull) >> 23) /* i */
642 | ((imm & 0x00000000000fffffull) << 13) /* imm20b */
643 | (qp & 0x3f);
644 }
645
646
647 /*
648 * Relocations
649 */
650
651 static inline void reloc_pcrel21b (void *pc, tcg_target_long target)
652 {
653 uint64_t imm;
654 int64_t disp;
655 int slot;
656
657 slot = (tcg_target_long) pc & 3;
658 pc = (void *)((tcg_target_long) pc & ~3);
659
660 disp = target - (tcg_target_long) pc;
661 imm = (uint64_t) disp >> 4;
662
663 switch(slot) {
664 case 0:
665 *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 8) & 0xfffffdc00003ffffull)
666 | ((imm & 0x100000) << 21) /* s */
667 | ((imm & 0x0fffff) << 18); /* imm20b */
668 break;
669 case 1:
670 *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xfffffffffffb8000ull)
671 | ((imm & 0x100000) >> 2) /* s */
672 | ((imm & 0x0fffe0) >> 5); /* imm20b */
673 *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x07ffffffffffffffull)
674 | ((imm & 0x00001f) << 59); /* imm20b */
675 break;
676 case 2:
677 *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fffffffffull)
678 | ((imm & 0x100000) << 39) /* s */
679 | ((imm & 0x0fffff) << 36); /* imm20b */
680 break;
681 }
682 }
683
684 static inline uint64_t get_reloc_pcrel21b (void *pc)
685 {
686 int64_t low, high;
687 int slot;
688
689 slot = (tcg_target_long) pc & 3;
690 pc = (void *)((tcg_target_long) pc & ~3);
691
692 low = (*(uint64_t *)(pc + 0));
693 high = (*(uint64_t *)(pc + 8));
694
695 switch(slot) {
696 case 0:
697 return ((low >> 21) & 0x100000) + /* s */
698 ((low >> 18) & 0x0fffff); /* imm20b */
699 case 1:
700 return ((high << 2) & 0x100000) + /* s */
701 ((high << 5) & 0x0fffe0) + /* imm20b */
702 ((low >> 59) & 0x00001f); /* imm20b */
703 case 2:
704 return ((high >> 39) & 0x100000) + /* s */
705 ((high >> 36) & 0x0fffff); /* imm20b */
706 default:
707 tcg_abort();
708 }
709 }
710
711 static inline void reloc_pcrel60b (void *pc, tcg_target_long target)
712 {
713 int64_t disp;
714 uint64_t imm;
715
716 disp = target - (tcg_target_long) pc;
717 imm = (uint64_t) disp >> 4;
718
719 *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fff800000ull)
720 | (imm & 0x0800000000000000ull) /* s */
721 | ((imm & 0x07fffff000000000ull) >> 36) /* imm39 */
722 | ((imm & 0x00000000000fffffull) << 36); /* imm20b */
723 *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x00003fffffffffffull)
724 | ((imm & 0x0000000ffff00000ull) << 28); /* imm39 */
725 }
726
727 static inline uint64_t get_reloc_pcrel60b (void *pc)
728 {
729 int64_t low, high;
730
731 low = (*(uint64_t *)(pc + 0));
732 high = (*(uint64_t *)(pc + 8));
733
734 return ((high) & 0x0800000000000000ull) + /* s */
735 ((high >> 36) & 0x00000000000fffffull) + /* imm20b */
736 ((high << 36) & 0x07fffff000000000ull) + /* imm39 */
737 ((low >> 28) & 0x0000000ffff00000ull); /* imm39 */
738 }
739
740
741 static void patch_reloc(uint8_t *code_ptr, int type,
742 tcg_target_long value, tcg_target_long addend)
743 {
744 value += addend;
745 switch (type) {
746 case R_IA64_PCREL21B:
747 reloc_pcrel21b(code_ptr, value);
748 break;
749 case R_IA64_PCREL60B:
750 reloc_pcrel60b(code_ptr, value);
751 default:
752 tcg_abort();
753 }
754 }
755
756 /*
757 * Constraints
758 */
759
760 /* parse target specific constraints */
761 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
762 {
763 const char *ct_str;
764
765 ct_str = *pct_str;
766 switch(ct_str[0]) {
767 case 'r':
768 ct->ct |= TCG_CT_REG;
769 tcg_regset_set(ct->u.regs, 0xffffffffffffffffull);
770 break;
771 case 'I':
772 ct->ct |= TCG_CT_CONST_S22;
773 break;
774 case 'S':
775 ct->ct |= TCG_CT_REG;
776 tcg_regset_set(ct->u.regs, 0xffffffffffffffffull);
777 #if defined(CONFIG_SOFTMMU)
778 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R56);
779 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R57);
780 #endif
781 break;
782 case 'Z':
783 /* We are cheating a bit here, using the fact that the register
784 r0 is also the register number 0. Hence there is no need
785 to check for const_args in each instruction. */
786 ct->ct |= TCG_CT_CONST_ZERO;
787 break;
788 default:
789 return -1;
790 }
791 ct_str++;
792 *pct_str = ct_str;
793 return 0;
794 }
795
796 /* test if a constant matches the constraint */
797 static inline int tcg_target_const_match(tcg_target_long val,
798 const TCGArgConstraint *arg_ct)
799 {
800 int ct;
801 ct = arg_ct->ct;
802 if (ct & TCG_CT_CONST)
803 return 1;
804 else if ((ct & TCG_CT_CONST_ZERO) && val == 0)
805 return 1;
806 else if ((ct & TCG_CT_CONST_S22) && val == ((int32_t)val << 10) >> 10)
807 return 1;
808 else
809 return 0;
810 }
811
812 /*
813 * Code generation
814 */
815
816 static uint8_t *tb_ret_addr;
817
818 static inline void tcg_out_bundle(TCGContext *s, int template,
819 uint64_t slot0, uint64_t slot1,
820 uint64_t slot2)
821 {
822 template &= 0x1f; /* 5 bits */
823 slot0 &= 0x1ffffffffffull; /* 41 bits */
824 slot1 &= 0x1ffffffffffull; /* 41 bits */
825 slot2 &= 0x1ffffffffffull; /* 41 bits */
826
827 *(uint64_t *)(s->code_ptr + 0) = (slot1 << 46) | (slot0 << 5) | template;
828 *(uint64_t *)(s->code_ptr + 8) = (slot2 << 23) | (slot1 >> 18);
829 s->code_ptr += 16;
830 }
831
832 static inline void tcg_out_mov(TCGContext *s, TCGType type,
833 TCGReg ret, TCGReg arg)
834 {
835 tcg_out_bundle(s, mmI,
836 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
837 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
838 tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, ret, 0, arg));
839 }
840
841 static inline void tcg_out_movi(TCGContext *s, TCGType type,
842 TCGReg reg, tcg_target_long arg)
843 {
844 tcg_out_bundle(s, mLX,
845 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
846 tcg_opc_l2 (arg),
847 tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, reg, arg));
848 }
849
850 static void tcg_out_br(TCGContext *s, int label_index)
851 {
852 TCGLabel *l = &s->labels[label_index];
853
854 /* We pay attention here to not modify the branch target by reading
855 the existing value and using it again. This ensure that caches and
856 memory are kept coherent during retranslation. */
857 tcg_out_bundle(s, mmB,
858 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
859 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
860 tcg_opc_b1 (TCG_REG_P0, OPC_BR_SPTK_MANY_B1,
861 get_reloc_pcrel21b(s->code_ptr + 2)));
862
863 if (l->has_value) {
864 reloc_pcrel21b((s->code_ptr - 16) + 2, l->u.value);
865 } else {
866 tcg_out_reloc(s, (s->code_ptr - 16) + 2,
867 R_IA64_PCREL21B, label_index, 0);
868 }
869 }
870
871 static inline void tcg_out_call(TCGContext *s, TCGArg addr)
872 {
873 tcg_out_bundle(s, MmI,
874 tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R2, addr),
875 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R3, 8, addr),
876 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
877 TCG_REG_B6, TCG_REG_R2, 0));
878 tcg_out_bundle(s, mmB,
879 tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R3),
880 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
881 tcg_opc_b5 (TCG_REG_P0, OPC_BR_CALL_SPTK_MANY_B5,
882 TCG_REG_B0, TCG_REG_B6));
883 }
884
885 static void tcg_out_exit_tb(TCGContext *s, tcg_target_long arg)
886 {
887 int64_t disp;
888 uint64_t imm;
889
890 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R8, arg);
891
892 disp = tb_ret_addr - s->code_ptr;
893 imm = (uint64_t)disp >> 4;
894
895 tcg_out_bundle(s, mLX,
896 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
897 tcg_opc_l3 (imm),
898 tcg_opc_x3 (TCG_REG_P0, OPC_BRL_SPTK_MANY_X3, imm));
899 }
900
901 static inline void tcg_out_goto_tb(TCGContext *s, TCGArg arg)
902 {
903 if (s->tb_jmp_offset) {
904 /* direct jump method */
905 tcg_abort();
906 } else {
907 /* indirect jump method */
908 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2,
909 (tcg_target_long)(s->tb_next + arg));
910 tcg_out_bundle(s, MmI,
911 tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1,
912 TCG_REG_R2, TCG_REG_R2),
913 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
914 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6,
915 TCG_REG_R2, 0));
916 tcg_out_bundle(s, mmB,
917 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
918 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
919 tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4,
920 TCG_REG_B6));
921 }
922 s->tb_next_offset[arg] = s->code_ptr - s->code_buf;
923 }
924
925 static inline void tcg_out_jmp(TCGContext *s, TCGArg addr)
926 {
927 tcg_out_bundle(s, mmI,
928 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
929 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
930 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6, addr, 0));
931 tcg_out_bundle(s, mmB,
932 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
933 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
934 tcg_opc_b4(TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6));
935 }
936
937 static inline void tcg_out_ld_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg,
938 TCGArg arg1, tcg_target_long arg2)
939 {
940 if (arg2 == ((int16_t)arg2 >> 2) << 2) {
941 tcg_out_bundle(s, MmI,
942 tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4,
943 TCG_REG_R2, arg2, arg1),
944 tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
945 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
946 } else {
947 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2);
948 tcg_out_bundle(s, MmI,
949 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1,
950 TCG_REG_R2, TCG_REG_R2, arg1),
951 tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
952 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
953 }
954 }
955
956 static inline void tcg_out_st_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg,
957 TCGArg arg1, tcg_target_long arg2)
958 {
959 if (arg2 == ((int16_t)arg2 >> 2) << 2) {
960 tcg_out_bundle(s, MmI,
961 tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4,
962 TCG_REG_R2, arg2, arg1),
963 tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
964 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
965 } else {
966 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2);
967 tcg_out_bundle(s, MmI,
968 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1,
969 TCG_REG_R2, TCG_REG_R2, arg1),
970 tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
971 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
972 }
973 }
974
975 static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
976 TCGReg arg1, tcg_target_long arg2)
977 {
978 if (type == TCG_TYPE_I32) {
979 tcg_out_ld_rel(s, OPC_LD4_M1, arg, arg1, arg2);
980 } else {
981 tcg_out_ld_rel(s, OPC_LD8_M1, arg, arg1, arg2);
982 }
983 }
984
985 static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
986 TCGReg arg1, tcg_target_long arg2)
987 {
988 if (type == TCG_TYPE_I32) {
989 tcg_out_st_rel(s, OPC_ST4_M4, arg, arg1, arg2);
990 } else {
991 tcg_out_st_rel(s, OPC_ST8_M4, arg, arg1, arg2);
992 }
993 }
994
995 static inline void tcg_out_alu(TCGContext *s, uint64_t opc_a1, TCGArg ret,
996 TCGArg arg1, int const_arg1,
997 TCGArg arg2, int const_arg2)
998 {
999 uint64_t opc1, opc2;
1000
1001 if (const_arg1 && arg1 != 0) {
1002 opc1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
1003 TCG_REG_R2, arg1, TCG_REG_R0);
1004 arg1 = TCG_REG_R2;
1005 } else {
1006 opc1 = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
1007 }
1008
1009 if (const_arg2 && arg2 != 0) {
1010 opc2 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
1011 TCG_REG_R3, arg2, TCG_REG_R0);
1012 arg2 = TCG_REG_R3;
1013 } else {
1014 opc2 = tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0);
1015 }
1016
1017 tcg_out_bundle(s, mII,
1018 opc1,
1019 opc2,
1020 tcg_opc_a1(TCG_REG_P0, opc_a1, ret, arg1, arg2));
1021 }
1022
1023 static inline void tcg_out_eqv(TCGContext *s, TCGArg ret,
1024 TCGArg arg1, int const_arg1,
1025 TCGArg arg2, int const_arg2)
1026 {
1027 tcg_out_bundle(s, mII,
1028 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1029 tcg_opc_a1 (TCG_REG_P0, OPC_XOR_A1, ret, arg1, arg2),
1030 tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
1031 }
1032
1033 static inline void tcg_out_nand(TCGContext *s, TCGArg ret,
1034 TCGArg arg1, int const_arg1,
1035 TCGArg arg2, int const_arg2)
1036 {
1037 tcg_out_bundle(s, mII,
1038 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1039 tcg_opc_a1 (TCG_REG_P0, OPC_AND_A1, ret, arg1, arg2),
1040 tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
1041 }
1042
1043 static inline void tcg_out_nor(TCGContext *s, TCGArg ret,
1044 TCGArg arg1, int const_arg1,
1045 TCGArg arg2, int const_arg2)
1046 {
1047 tcg_out_bundle(s, mII,
1048 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1049 tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, arg2),
1050 tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
1051 }
1052
1053 static inline void tcg_out_orc(TCGContext *s, TCGArg ret,
1054 TCGArg arg1, int const_arg1,
1055 TCGArg arg2, int const_arg2)
1056 {
1057 tcg_out_bundle(s, mII,
1058 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1059 tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, TCG_REG_R2, -1, arg2),
1060 tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, TCG_REG_R2));
1061 }
1062
1063 static inline void tcg_out_mul(TCGContext *s, TCGArg ret,
1064 TCGArg arg1, TCGArg arg2)
1065 {
1066 tcg_out_bundle(s, mmI,
1067 tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F6, arg1),
1068 tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F7, arg2),
1069 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1070 tcg_out_bundle(s, mmF,
1071 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1072 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1073 tcg_opc_f2 (TCG_REG_P0, OPC_XMA_L_F2, TCG_REG_F6, TCG_REG_F6,
1074 TCG_REG_F7, TCG_REG_F0));
1075 tcg_out_bundle(s, miI,
1076 tcg_opc_m19(TCG_REG_P0, OPC_GETF_SIG_M19, ret, TCG_REG_F6),
1077 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1078 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1079 }
1080
1081 static inline void tcg_out_sar_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1082 TCGArg arg2, int const_arg2)
1083 {
1084 if (const_arg2) {
1085 tcg_out_bundle(s, miI,
1086 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1087 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1088 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11,
1089 ret, arg1, arg2, 31 - arg2));
1090 } else {
1091 tcg_out_bundle(s, mII,
1092 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3,
1093 TCG_REG_R3, 0x1f, arg2),
1094 tcg_opc_i29(TCG_REG_P0, OPC_SXT4_I29, TCG_REG_R2, arg1),
1095 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret,
1096 TCG_REG_R2, TCG_REG_R3));
1097 }
1098 }
1099
1100 static inline void tcg_out_sar_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1101 TCGArg arg2, int const_arg2)
1102 {
1103 if (const_arg2) {
1104 tcg_out_bundle(s, miI,
1105 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1106 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1107 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11,
1108 ret, arg1, arg2, 63 - arg2));
1109 } else {
1110 tcg_out_bundle(s, miI,
1111 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1112 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1113 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret, arg1, arg2));
1114 }
1115 }
1116
1117 static inline void tcg_out_shl_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1118 TCGArg arg2, int const_arg2)
1119 {
1120 if (const_arg2) {
1121 tcg_out_bundle(s, miI,
1122 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1123 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1124 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret,
1125 arg1, 63 - arg2, 31 - arg2));
1126 } else {
1127 tcg_out_bundle(s, mII,
1128 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1129 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R2,
1130 0x1f, arg2),
1131 tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret,
1132 arg1, TCG_REG_R2));
1133 }
1134 }
1135
1136 static inline void tcg_out_shl_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1137 TCGArg arg2, int const_arg2)
1138 {
1139 if (const_arg2) {
1140 tcg_out_bundle(s, miI,
1141 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1142 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1143 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret,
1144 arg1, 63 - arg2, 63 - arg2));
1145 } else {
1146 tcg_out_bundle(s, miI,
1147 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1148 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1149 tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret,
1150 arg1, arg2));
1151 }
1152 }
1153
1154 static inline void tcg_out_shr_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1155 TCGArg arg2, int const_arg2)
1156 {
1157 if (const_arg2) {
1158 tcg_out_bundle(s, miI,
1159 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1160 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1161 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1162 arg1, arg2, 31 - arg2));
1163 } else {
1164 tcg_out_bundle(s, mII,
1165 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
1166 0x1f, arg2),
1167 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R2, arg1),
1168 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1169 TCG_REG_R2, TCG_REG_R3));
1170 }
1171 }
1172
1173 static inline void tcg_out_shr_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1174 TCGArg arg2, int const_arg2)
1175 {
1176 if (const_arg2) {
1177 tcg_out_bundle(s, miI,
1178 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1179 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1180 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1181 arg1, arg2, 63 - arg2));
1182 } else {
1183 tcg_out_bundle(s, miI,
1184 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1185 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1186 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1187 arg1, arg2));
1188 }
1189 }
1190
1191 static inline void tcg_out_rotl_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1192 TCGArg arg2, int const_arg2)
1193 {
1194 if (const_arg2) {
1195 tcg_out_bundle(s, mII,
1196 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1197 tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1198 TCG_REG_R2, arg1, arg1),
1199 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1200 TCG_REG_R2, 32 - arg2, 31));
1201 } else {
1202 tcg_out_bundle(s, miI,
1203 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1204 tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1205 TCG_REG_R2, arg1, arg1),
1206 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
1207 0x1f, arg2));
1208 tcg_out_bundle(s, mII,
1209 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1210 tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R3,
1211 0x20, TCG_REG_R3),
1212 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1213 TCG_REG_R2, TCG_REG_R3));
1214 }
1215 }
1216
1217 static inline void tcg_out_rotl_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1218 TCGArg arg2, int const_arg2)
1219 {
1220 if (const_arg2) {
1221 tcg_out_bundle(s, miI,
1222 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1223 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1224 tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1,
1225 arg1, 0x40 - arg2));
1226 } else {
1227 tcg_out_bundle(s, mII,
1228 tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2,
1229 0x40, arg2),
1230 tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R3,
1231 arg1, arg2),
1232 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R2,
1233 arg1, TCG_REG_R2));
1234 tcg_out_bundle(s, miI,
1235 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1236 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1237 tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret,
1238 TCG_REG_R2, TCG_REG_R3));
1239 }
1240 }
1241
1242 static inline void tcg_out_rotr_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1243 TCGArg arg2, int const_arg2)
1244 {
1245 if (const_arg2) {
1246 tcg_out_bundle(s, mII,
1247 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1248 tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1249 TCG_REG_R2, arg1, arg1),
1250 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1251 TCG_REG_R2, arg2, 31));
1252 } else {
1253 tcg_out_bundle(s, mII,
1254 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
1255 0x1f, arg2),
1256 tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1257 TCG_REG_R2, arg1, arg1),
1258 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1259 TCG_REG_R2, TCG_REG_R3));
1260 }
1261 }
1262
1263 static inline void tcg_out_rotr_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1264 TCGArg arg2, int const_arg2)
1265 {
1266 if (const_arg2) {
1267 tcg_out_bundle(s, miI,
1268 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1269 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1270 tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1,
1271 arg1, arg2));
1272 } else {
1273 tcg_out_bundle(s, mII,
1274 tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2,
1275 0x40, arg2),
1276 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R3,
1277 arg1, arg2),
1278 tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R2,
1279 arg1, TCG_REG_R2));
1280 tcg_out_bundle(s, miI,
1281 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1282 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1283 tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret,
1284 TCG_REG_R2, TCG_REG_R3));
1285 }
1286 }
1287
1288 static inline void tcg_out_ext(TCGContext *s, uint64_t opc_i29,
1289 TCGArg ret, TCGArg arg)
1290 {
1291 tcg_out_bundle(s, miI,
1292 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1293 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1294 tcg_opc_i29(TCG_REG_P0, opc_i29, ret, arg));
1295 }
1296
1297 static inline void tcg_out_bswap16(TCGContext *s, TCGArg ret, TCGArg arg)
1298 {
1299 tcg_out_bundle(s, mII,
1300 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1301 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 15, 15),
1302 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, ret, 0xb));
1303 }
1304
1305 static inline void tcg_out_bswap32(TCGContext *s, TCGArg ret, TCGArg arg)
1306 {
1307 tcg_out_bundle(s, mII,
1308 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1309 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 31, 31),
1310 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, ret, 0xb));
1311 }
1312
1313 static inline void tcg_out_bswap64(TCGContext *s, TCGArg ret, TCGArg arg)
1314 {
1315 tcg_out_bundle(s, miI,
1316 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1317 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1318 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, arg, 0xb));
1319 }
1320
1321 static inline uint64_t tcg_opc_cmp_a(int qp, TCGCond cond, TCGArg arg1,
1322 TCGArg arg2, int cmp4)
1323 {
1324 uint64_t opc_eq_a6, opc_lt_a6, opc_ltu_a6;
1325
1326 if (cmp4) {
1327 opc_eq_a6 = OPC_CMP4_EQ_A6;
1328 opc_lt_a6 = OPC_CMP4_LT_A6;
1329 opc_ltu_a6 = OPC_CMP4_LTU_A6;
1330 } else {
1331 opc_eq_a6 = OPC_CMP_EQ_A6;
1332 opc_lt_a6 = OPC_CMP_LT_A6;
1333 opc_ltu_a6 = OPC_CMP_LTU_A6;
1334 }
1335
1336 switch (cond) {
1337 case TCG_COND_EQ:
1338 return tcg_opc_a6 (qp, opc_eq_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
1339 case TCG_COND_NE:
1340 return tcg_opc_a6 (qp, opc_eq_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
1341 case TCG_COND_LT:
1342 return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
1343 case TCG_COND_LTU:
1344 return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
1345 case TCG_COND_GE:
1346 return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
1347 case TCG_COND_GEU:
1348 return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
1349 case TCG_COND_LE:
1350 return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P7, TCG_REG_P6, arg2, arg1);
1351 case TCG_COND_LEU:
1352 return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg2, arg1);
1353 case TCG_COND_GT:
1354 return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P6, TCG_REG_P7, arg2, arg1);
1355 case TCG_COND_GTU:
1356 return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg2, arg1);
1357 default:
1358 tcg_abort();
1359 break;
1360 }
1361 }
1362
1363 static inline void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGArg arg1,
1364 int const_arg1, TCGArg arg2, int const_arg2,
1365 int label_index, int cmp4)
1366 {
1367 TCGLabel *l = &s->labels[label_index];
1368 uint64_t opc1, opc2;
1369
1370 if (const_arg1 && arg1 != 0) {
1371 opc1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R2,
1372 arg1, TCG_REG_R0);
1373 arg1 = TCG_REG_R2;
1374 } else {
1375 opc1 = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
1376 }
1377
1378 if (const_arg2 && arg2 != 0) {
1379 opc2 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R3,
1380 arg2, TCG_REG_R0);
1381 arg2 = TCG_REG_R3;
1382 } else {
1383 opc2 = tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0);
1384 }
1385
1386 tcg_out_bundle(s, mII,
1387 opc1,
1388 opc2,
1389 tcg_opc_cmp_a(TCG_REG_P0, cond, arg1, arg2, cmp4));
1390 tcg_out_bundle(s, mmB,
1391 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1392 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1393 tcg_opc_b1 (TCG_REG_P6, OPC_BR_DPTK_FEW_B1,
1394 get_reloc_pcrel21b(s->code_ptr + 2)));
1395
1396 if (l->has_value) {
1397 reloc_pcrel21b((s->code_ptr - 16) + 2, l->u.value);
1398 } else {
1399 tcg_out_reloc(s, (s->code_ptr - 16) + 2,
1400 R_IA64_PCREL21B, label_index, 0);
1401 }
1402 }
1403
1404 static inline void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGArg ret,
1405 TCGArg arg1, TCGArg arg2, int cmp4)
1406 {
1407 tcg_out_bundle(s, MmI,
1408 tcg_opc_cmp_a(TCG_REG_P0, cond, arg1, arg2, cmp4),
1409 tcg_opc_a5(TCG_REG_P6, OPC_ADDL_A5, ret, 1, TCG_REG_R0),
1410 tcg_opc_a5(TCG_REG_P7, OPC_ADDL_A5, ret, 0, TCG_REG_R0));
1411 }
1412
1413 #if defined(CONFIG_SOFTMMU)
1414
1415 #include "../../softmmu_defs.h"
1416
1417 /* Load and compare a TLB entry, and return the result in (p6, p7).
1418 R2 is loaded with the address of the addend TLB entry.
1419 R56 is loaded with the address, zero extented on 32-bit targets. */
1420 static inline void tcg_out_qemu_tlb(TCGContext *s, TCGArg addr_reg,
1421 int s_bits, uint64_t offset_rw,
1422 uint64_t offset_addend)
1423 {
1424 tcg_out_bundle(s, mII,
1425 tcg_opc_a5 (TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R3,
1426 TARGET_PAGE_MASK | ((1 << s_bits) - 1),
1427 TCG_REG_R0),
1428 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, TCG_REG_R2,
1429 addr_reg, TARGET_PAGE_BITS, CPU_TLB_BITS - 1),
1430 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, TCG_REG_R2,
1431 TCG_REG_R2, 63 - CPU_TLB_ENTRY_BITS,
1432 63 - CPU_TLB_ENTRY_BITS));
1433 tcg_out_bundle(s, mII,
1434 tcg_opc_a5 (TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R2,
1435 offset_rw, TCG_REG_R2),
1436 #if TARGET_LONG_BITS == 32
1437 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R56, addr_reg),
1438 #else
1439 tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R56,
1440 0, addr_reg),
1441 #endif
1442 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1443 TCG_REG_R2, TCG_AREG0));
1444 tcg_out_bundle(s, mII,
1445 tcg_opc_m3 (TCG_REG_P0,
1446 (TARGET_LONG_BITS == 32
1447 ? OPC_LD4_M3 : OPC_LD8_M3), TCG_REG_R57,
1448 TCG_REG_R2, offset_addend - offset_rw),
1449 tcg_opc_a1 (TCG_REG_P0, OPC_AND_A1, TCG_REG_R3,
1450 TCG_REG_R3, TCG_REG_R56),
1451 tcg_opc_a6 (TCG_REG_P0, OPC_CMP_EQ_A6, TCG_REG_P6,
1452 TCG_REG_P7, TCG_REG_R3, TCG_REG_R57));
1453 }
1454
1455 #ifdef CONFIG_TCG_PASS_AREG0
1456 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
1457 int mmu_idx) */
1458 static const void * const qemu_ld_helpers[4] = {
1459 helper_ldb_mmu,
1460 helper_ldw_mmu,
1461 helper_ldl_mmu,
1462 helper_ldq_mmu,
1463 };
1464 #else
1465 /* legacy helper signature: __ld_mmu(target_ulong addr, int
1466 mmu_idx) */
1467 static void *qemu_ld_helpers[4] = {
1468 __ldb_mmu,
1469 __ldw_mmu,
1470 __ldl_mmu,
1471 __ldq_mmu,
1472 };
1473 #endif
1474
1475 static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
1476 {
1477 int addr_reg, data_reg, mem_index, s_bits, bswap;
1478 uint64_t opc_ld_m1[4] = { OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1 };
1479 uint64_t opc_ext_i29[8] = { OPC_ZXT1_I29, OPC_ZXT2_I29, OPC_ZXT4_I29, 0,
1480 OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0 };
1481
1482 data_reg = *args++;
1483 addr_reg = *args++;
1484 mem_index = *args;
1485 s_bits = opc & 3;
1486
1487 #ifdef TARGET_WORDS_BIGENDIAN
1488 bswap = 1;
1489 #else
1490 bswap = 0;
1491 #endif
1492
1493 /* Read the TLB entry */
1494 tcg_out_qemu_tlb(s, addr_reg, s_bits,
1495 offsetof(CPUArchState, tlb_table[mem_index][0].addr_read),
1496 offsetof(CPUArchState, tlb_table[mem_index][0].addend));
1497
1498 /* P6 is the fast path, and P7 the slow path */
1499 tcg_out_bundle(s, mLX,
1500 tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R57,
1501 mem_index, TCG_REG_R0),
1502 tcg_opc_l2 ((tcg_target_long) qemu_ld_helpers[s_bits]),
1503 tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2,
1504 (tcg_target_long) qemu_ld_helpers[s_bits]));
1505 tcg_out_bundle(s, MmI,
1506 tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3,
1507 TCG_REG_R2, 8),
1508 tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3,
1509 TCG_REG_R3, TCG_REG_R56),
1510 tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6,
1511 TCG_REG_R3, 0));
1512 if (bswap && s_bits == 1) {
1513 tcg_out_bundle(s, MmI,
1514 tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
1515 TCG_REG_R8, TCG_REG_R3),
1516 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
1517 tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1518 TCG_REG_R8, TCG_REG_R8, 15, 15));
1519 } else if (bswap && s_bits == 2) {
1520 tcg_out_bundle(s, MmI,
1521 tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
1522 TCG_REG_R8, TCG_REG_R3),
1523 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
1524 tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1525 TCG_REG_R8, TCG_REG_R8, 31, 31));
1526 } else {
1527 tcg_out_bundle(s, mmI,
1528 tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
1529 TCG_REG_R8, TCG_REG_R3),
1530 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
1531 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1532 }
1533 #ifdef CONFIG_TCG_PASS_AREG0
1534 /* XXX/FIXME: suboptimal */
1535 tcg_out_bundle(s, mII,
1536 tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58,
1537 mem_index, TCG_REG_R0),
1538 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4,
1539 TCG_REG_R57, 0, TCG_REG_R56),
1540 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4,
1541 TCG_REG_R56, 0, TCG_AREG0));
1542 #endif
1543 if (!bswap || s_bits == 0) {
1544 tcg_out_bundle(s, miB,
1545 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1546 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1547 tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
1548 TCG_REG_B0, TCG_REG_B6));
1549 } else {
1550 tcg_out_bundle(s, miB,
1551 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1552 tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1553 TCG_REG_R8, TCG_REG_R8, 0xb),
1554 tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
1555 TCG_REG_B0, TCG_REG_B6));
1556 }
1557
1558 if (opc == 3) {
1559 tcg_out_bundle(s, miI,
1560 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1561 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1562 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
1563 data_reg, 0, TCG_REG_R8));
1564 } else {
1565 tcg_out_bundle(s, miI,
1566 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1567 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1568 tcg_opc_i29(TCG_REG_P0, opc_ext_i29[opc],
1569 data_reg, TCG_REG_R8));
1570 }
1571 }
1572
1573 #ifdef CONFIG_TCG_PASS_AREG0
1574 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
1575 uintxx_t val, int mmu_idx) */
1576 static const void * const qemu_st_helpers[4] = {
1577 helper_stb_mmu,
1578 helper_stw_mmu,
1579 helper_stl_mmu,
1580 helper_stq_mmu,
1581 };
1582 #else
1583 /* legacy helper signature: __st_mmu(target_ulong addr, uintxx_t val,
1584 int mmu_idx) */
1585 static void *qemu_st_helpers[4] = {
1586 __stb_mmu,
1587 __stw_mmu,
1588 __stl_mmu,
1589 __stq_mmu,
1590 };
1591 #endif
1592
1593 static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
1594 {
1595 int addr_reg, data_reg, mem_index, bswap;
1596 uint64_t opc_st_m4[4] = { OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4 };
1597
1598 data_reg = *args++;
1599 addr_reg = *args++;
1600 mem_index = *args;
1601
1602 #ifdef TARGET_WORDS_BIGENDIAN
1603 bswap = 1;
1604 #else
1605 bswap = 0;
1606 #endif
1607
1608 tcg_out_qemu_tlb(s, addr_reg, opc,
1609 offsetof(CPUArchState, tlb_table[mem_index][0].addr_write),
1610 offsetof(CPUArchState, tlb_table[mem_index][0].addend));
1611
1612 /* P6 is the fast path, and P7 the slow path */
1613 tcg_out_bundle(s, mLX,
1614 tcg_opc_a4(TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R57,
1615 0, data_reg),
1616 tcg_opc_l2 ((tcg_target_long) qemu_st_helpers[opc]),
1617 tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2,
1618 (tcg_target_long) qemu_st_helpers[opc]));
1619 tcg_out_bundle(s, MmI,
1620 tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3,
1621 TCG_REG_R2, 8),
1622 tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3,
1623 TCG_REG_R3, TCG_REG_R56),
1624 tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6,
1625 TCG_REG_R3, 0));
1626
1627 if (!bswap || opc == 0) {
1628 tcg_out_bundle(s, mII,
1629 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1630 TCG_REG_R1, TCG_REG_R2),
1631 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1632 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1633 } else if (opc == 1) {
1634 tcg_out_bundle(s, mII,
1635 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1636 TCG_REG_R1, TCG_REG_R2),
1637 tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1638 TCG_REG_R2, data_reg, 15, 15),
1639 tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1640 TCG_REG_R2, TCG_REG_R2, 0xb));
1641 data_reg = TCG_REG_R2;
1642 } else if (opc == 2) {
1643 tcg_out_bundle(s, mII,
1644 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1645 TCG_REG_R1, TCG_REG_R2),
1646 tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1647 TCG_REG_R2, data_reg, 31, 31),
1648 tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1649 TCG_REG_R2, TCG_REG_R2, 0xb));
1650 data_reg = TCG_REG_R2;
1651 } else if (opc == 3) {
1652 tcg_out_bundle(s, miI,
1653 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1654 TCG_REG_R1, TCG_REG_R2),
1655 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1656 tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1657 TCG_REG_R2, data_reg, 0xb));
1658 data_reg = TCG_REG_R2;
1659 }
1660
1661 #ifdef CONFIG_TCG_PASS_AREG0
1662 /* XXX/FIXME: suboptimal */
1663 tcg_out_bundle(s, mII,
1664 tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R59,
1665 mem_index, TCG_REG_R0),
1666 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4,
1667 TCG_REG_R58, 0, TCG_REG_R57),
1668 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4,
1669 TCG_REG_R57, 0, TCG_REG_R56));
1670 tcg_out_bundle(s, miB,
1671 tcg_opc_m4 (TCG_REG_P6, opc_st_m4[opc],
1672 data_reg, TCG_REG_R3),
1673 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4,
1674 TCG_REG_R56, 0, TCG_AREG0),
1675 tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
1676 TCG_REG_B0, TCG_REG_B6));
1677 #else
1678 tcg_out_bundle(s, miB,
1679 tcg_opc_m4 (TCG_REG_P6, opc_st_m4[opc],
1680 data_reg, TCG_REG_R3),
1681 tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58,
1682 mem_index, TCG_REG_R0),
1683 tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
1684 TCG_REG_B0, TCG_REG_B6));
1685 #endif
1686 }
1687
1688 #else /* !CONFIG_SOFTMMU */
1689
1690 static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
1691 {
1692 static uint64_t const opc_ld_m1[4] = {
1693 OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1
1694 };
1695 static uint64_t const opc_sxt_i29[4] = {
1696 OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0
1697 };
1698 int addr_reg, data_reg, s_bits, bswap;
1699
1700 data_reg = *args++;
1701 addr_reg = *args++;
1702 s_bits = opc & 3;
1703
1704 #ifdef TARGET_WORDS_BIGENDIAN
1705 bswap = 1;
1706 #else
1707 bswap = 0;
1708 #endif
1709
1710 #if TARGET_LONG_BITS == 32
1711 if (GUEST_BASE != 0) {
1712 tcg_out_bundle(s, mII,
1713 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1714 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1715 TCG_REG_R3, addr_reg),
1716 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1717 TCG_GUEST_BASE_REG, TCG_REG_R3));
1718 } else {
1719 tcg_out_bundle(s, miI,
1720 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1721 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1722 TCG_REG_R2, addr_reg),
1723 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1724 }
1725
1726 if (!bswap || s_bits == 0) {
1727 if (s_bits == opc) {
1728 tcg_out_bundle(s, miI,
1729 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1730 data_reg, TCG_REG_R2),
1731 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1732 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1733 } else {
1734 tcg_out_bundle(s, mII,
1735 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1736 data_reg, TCG_REG_R2),
1737 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1738 tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits],
1739 data_reg, data_reg));
1740 }
1741 } else if (s_bits == 3) {
1742 tcg_out_bundle(s, mII,
1743 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1744 data_reg, TCG_REG_R2),
1745 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1746 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1747 data_reg, data_reg, 0xb));
1748 } else {
1749 if (s_bits == 1) {
1750 tcg_out_bundle(s, mII,
1751 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1752 data_reg, TCG_REG_R2),
1753 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1754 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1755 data_reg, data_reg, 15, 15));
1756 } else {
1757 tcg_out_bundle(s, mII,
1758 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1759 data_reg, TCG_REG_R2),
1760 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1761 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1762 data_reg, data_reg, 31, 31));
1763 }
1764 if (opc == s_bits) {
1765 tcg_out_bundle(s, miI,
1766 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1767 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1768 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1769 data_reg, data_reg, 0xb));
1770 } else {
1771 tcg_out_bundle(s, mII,
1772 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1773 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1774 data_reg, data_reg, 0xb),
1775 tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits],
1776 data_reg, data_reg));
1777 }
1778 }
1779 #else
1780 if (GUEST_BASE != 0) {
1781 tcg_out_bundle(s, MmI,
1782 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1783 TCG_GUEST_BASE_REG, addr_reg),
1784 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1785 data_reg, TCG_REG_R2),
1786 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1787 } else {
1788 tcg_out_bundle(s, mmI,
1789 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1790 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1791 data_reg, addr_reg),
1792 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1793 }
1794
1795 if (bswap && s_bits == 1) {
1796 tcg_out_bundle(s, mII,
1797 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1798 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1799 data_reg, data_reg, 15, 15),
1800 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1801 data_reg, data_reg, 0xb));
1802 } else if (bswap && s_bits == 2) {
1803 tcg_out_bundle(s, mII,
1804 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1805 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1806 data_reg, data_reg, 31, 31),
1807 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1808 data_reg, data_reg, 0xb));
1809 } else if (bswap && s_bits == 3) {
1810 tcg_out_bundle(s, miI,
1811 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1812 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1813 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1814 data_reg, data_reg, 0xb));
1815 }
1816 if (s_bits != opc) {
1817 tcg_out_bundle(s, miI,
1818 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1819 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1820 tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits],
1821 data_reg, data_reg));
1822 }
1823 #endif
1824 }
1825
1826 static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
1827 {
1828 static uint64_t const opc_st_m4[4] = {
1829 OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4
1830 };
1831 int addr_reg, data_reg, bswap;
1832 #if TARGET_LONG_BITS == 64
1833 uint64_t add_guest_base;
1834 #endif
1835
1836 data_reg = *args++;
1837 addr_reg = *args++;
1838
1839 #ifdef TARGET_WORDS_BIGENDIAN
1840 bswap = 1;
1841 #else
1842 bswap = 0;
1843 #endif
1844
1845 #if TARGET_LONG_BITS == 32
1846 if (GUEST_BASE != 0) {
1847 tcg_out_bundle(s, mII,
1848 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1849 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1850 TCG_REG_R3, addr_reg),
1851 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1852 TCG_GUEST_BASE_REG, TCG_REG_R3));
1853 } else {
1854 tcg_out_bundle(s, miI,
1855 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1856 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1857 TCG_REG_R2, addr_reg),
1858 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1859 }
1860
1861 if (bswap) {
1862 if (opc == 1) {
1863 tcg_out_bundle(s, mII,
1864 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1865 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1866 TCG_REG_R3, data_reg, 15, 15),
1867 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1868 TCG_REG_R3, TCG_REG_R3, 0xb));
1869 data_reg = TCG_REG_R3;
1870 } else if (opc == 2) {
1871 tcg_out_bundle(s, mII,
1872 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1873 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1874 TCG_REG_R3, data_reg, 31, 31),
1875 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1876 TCG_REG_R3, TCG_REG_R3, 0xb));
1877 data_reg = TCG_REG_R3;
1878 } else if (opc == 3) {
1879 tcg_out_bundle(s, miI,
1880 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1881 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1882 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1883 TCG_REG_R3, data_reg, 0xb));
1884 data_reg = TCG_REG_R3;
1885 }
1886 }
1887 tcg_out_bundle(s, mmI,
1888 tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc],
1889 data_reg, TCG_REG_R2),
1890 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1891 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1892 #else
1893 if (GUEST_BASE != 0) {
1894 add_guest_base = tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1895 TCG_GUEST_BASE_REG, addr_reg);
1896 addr_reg = TCG_REG_R2;
1897 } else {
1898 add_guest_base = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
1899 }
1900
1901 if (!bswap || opc == 0) {
1902 tcg_out_bundle(s, (GUEST_BASE ? MmI : mmI),
1903 add_guest_base,
1904 tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc],
1905 data_reg, addr_reg),
1906 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1907 } else {
1908 if (opc == 1) {
1909 tcg_out_bundle(s, mII,
1910 add_guest_base,
1911 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1912 TCG_REG_R3, data_reg, 15, 15),
1913 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1914 TCG_REG_R3, TCG_REG_R3, 0xb));
1915 data_reg = TCG_REG_R3;
1916 } else if (opc == 2) {
1917 tcg_out_bundle(s, mII,
1918 add_guest_base,
1919 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1920 TCG_REG_R3, data_reg, 31, 31),
1921 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1922 TCG_REG_R3, TCG_REG_R3, 0xb));
1923 data_reg = TCG_REG_R3;
1924 } else if (opc == 3) {
1925 tcg_out_bundle(s, miI,
1926 add_guest_base,
1927 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1928 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1929 TCG_REG_R3, data_reg, 0xb));
1930 data_reg = TCG_REG_R3;
1931 }
1932 tcg_out_bundle(s, miI,
1933 tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc],
1934 data_reg, addr_reg),
1935 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1936 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1937 }
1938 #endif
1939 }
1940
1941 #endif
1942
1943 static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
1944 const TCGArg *args, const int *const_args)
1945 {
1946 switch(opc) {
1947 case INDEX_op_exit_tb:
1948 tcg_out_exit_tb(s, args[0]);
1949 break;
1950 case INDEX_op_br:
1951 tcg_out_br(s, args[0]);
1952 break;
1953 case INDEX_op_call:
1954 tcg_out_call(s, args[0]);
1955 break;
1956 case INDEX_op_goto_tb:
1957 tcg_out_goto_tb(s, args[0]);
1958 break;
1959 case INDEX_op_jmp:
1960 tcg_out_jmp(s, args[0]);
1961 break;
1962
1963 case INDEX_op_movi_i32:
1964 tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
1965 break;
1966 case INDEX_op_movi_i64:
1967 tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
1968 break;
1969
1970 case INDEX_op_ld8u_i32:
1971 case INDEX_op_ld8u_i64:
1972 tcg_out_ld_rel(s, OPC_LD1_M1, args[0], args[1], args[2]);
1973 break;
1974 case INDEX_op_ld8s_i32:
1975 case INDEX_op_ld8s_i64:
1976 tcg_out_ld_rel(s, OPC_LD1_M1, args[0], args[1], args[2]);
1977 tcg_out_ext(s, OPC_SXT1_I29, args[0], args[0]);
1978 break;
1979 case INDEX_op_ld16u_i32:
1980 case INDEX_op_ld16u_i64:
1981 tcg_out_ld_rel(s, OPC_LD2_M1, args[0], args[1], args[2]);
1982 break;
1983 case INDEX_op_ld16s_i32:
1984 case INDEX_op_ld16s_i64:
1985 tcg_out_ld_rel(s, OPC_LD2_M1, args[0], args[1], args[2]);
1986 tcg_out_ext(s, OPC_SXT2_I29, args[0], args[0]);
1987 break;
1988 case INDEX_op_ld_i32:
1989 case INDEX_op_ld32u_i64:
1990 tcg_out_ld_rel(s, OPC_LD4_M1, args[0], args[1], args[2]);
1991 break;
1992 case INDEX_op_ld32s_i64:
1993 tcg_out_ld_rel(s, OPC_LD4_M1, args[0], args[1], args[2]);
1994 tcg_out_ext(s, OPC_SXT4_I29, args[0], args[0]);
1995 break;
1996 case INDEX_op_ld_i64:
1997 tcg_out_ld_rel(s, OPC_LD8_M1, args[0], args[1], args[2]);
1998 break;
1999 case INDEX_op_st8_i32:
2000 case INDEX_op_st8_i64:
2001 tcg_out_st_rel(s, OPC_ST1_M4, args[0], args[1], args[2]);
2002 break;
2003 case INDEX_op_st16_i32:
2004 case INDEX_op_st16_i64:
2005 tcg_out_st_rel(s, OPC_ST2_M4, args[0], args[1], args[2]);
2006 break;
2007 case INDEX_op_st_i32:
2008 case INDEX_op_st32_i64:
2009 tcg_out_st_rel(s, OPC_ST4_M4, args[0], args[1], args[2]);
2010 break;
2011 case INDEX_op_st_i64:
2012 tcg_out_st_rel(s, OPC_ST8_M4, args[0], args[1], args[2]);
2013 break;
2014
2015 case INDEX_op_add_i32:
2016 case INDEX_op_add_i64:
2017 tcg_out_alu(s, OPC_ADD_A1, args[0], args[1], const_args[1],
2018 args[2], const_args[2]);
2019 break;
2020 case INDEX_op_sub_i32:
2021 case INDEX_op_sub_i64:
2022 tcg_out_alu(s, OPC_SUB_A1, args[0], args[1], const_args[1],
2023 args[2], const_args[2]);
2024 break;
2025
2026 case INDEX_op_and_i32:
2027 case INDEX_op_and_i64:
2028 tcg_out_alu(s, OPC_AND_A1, args[0], args[1], const_args[1],
2029 args[2], const_args[2]);
2030 break;
2031 case INDEX_op_andc_i32:
2032 case INDEX_op_andc_i64:
2033 tcg_out_alu(s, OPC_ANDCM_A1, args[0], args[1], const_args[1],
2034 args[2], const_args[2]);
2035 break;
2036 case INDEX_op_eqv_i32:
2037 case INDEX_op_eqv_i64:
2038 tcg_out_eqv(s, args[0], args[1], const_args[1],
2039 args[2], const_args[2]);
2040 break;
2041 case INDEX_op_nand_i32:
2042 case INDEX_op_nand_i64:
2043 tcg_out_nand(s, args[0], args[1], const_args[1],
2044 args[2], const_args[2]);
2045 break;
2046 case INDEX_op_nor_i32:
2047 case INDEX_op_nor_i64:
2048 tcg_out_nor(s, args[0], args[1], const_args[1],
2049 args[2], const_args[2]);
2050 break;
2051 case INDEX_op_or_i32:
2052 case INDEX_op_or_i64:
2053 tcg_out_alu(s, OPC_OR_A1, args[0], args[1], const_args[1],
2054 args[2], const_args[2]);
2055 break;
2056 case INDEX_op_orc_i32:
2057 case INDEX_op_orc_i64:
2058 tcg_out_orc(s, args[0], args[1], const_args[1],
2059 args[2], const_args[2]);
2060 break;
2061 case INDEX_op_xor_i32:
2062 case INDEX_op_xor_i64:
2063 tcg_out_alu(s, OPC_XOR_A1, args[0], args[1], const_args[1],
2064 args[2], const_args[2]);
2065 break;
2066
2067 case INDEX_op_mul_i32:
2068 case INDEX_op_mul_i64:
2069 tcg_out_mul(s, args[0], args[1], args[2]);
2070 break;
2071
2072 case INDEX_op_sar_i32:
2073 tcg_out_sar_i32(s, args[0], args[1], args[2], const_args[2]);
2074 break;
2075 case INDEX_op_sar_i64:
2076 tcg_out_sar_i64(s, args[0], args[1], args[2], const_args[2]);
2077 break;
2078 case INDEX_op_shl_i32:
2079 tcg_out_shl_i32(s, args[0], args[1], args[2], const_args[2]);
2080 break;
2081 case INDEX_op_shl_i64:
2082 tcg_out_shl_i64(s, args[0], args[1], args[2], const_args[2]);
2083 break;
2084 case INDEX_op_shr_i32:
2085 tcg_out_shr_i32(s, args[0], args[1], args[2], const_args[2]);
2086 break;
2087 case INDEX_op_shr_i64:
2088 tcg_out_shr_i64(s, args[0], args[1], args[2], const_args[2]);
2089 break;
2090 case INDEX_op_rotl_i32:
2091 tcg_out_rotl_i32(s, args[0], args[1], args[2], const_args[2]);
2092 break;
2093 case INDEX_op_rotl_i64:
2094 tcg_out_rotl_i64(s, args[0], args[1], args[2], const_args[2]);
2095 break;
2096 case INDEX_op_rotr_i32:
2097 tcg_out_rotr_i32(s, args[0], args[1], args[2], const_args[2]);
2098 break;
2099 case INDEX_op_rotr_i64:
2100 tcg_out_rotr_i64(s, args[0], args[1], args[2], const_args[2]);
2101 break;
2102
2103 case INDEX_op_ext8s_i32:
2104 case INDEX_op_ext8s_i64:
2105 tcg_out_ext(s, OPC_SXT1_I29, args[0], args[1]);
2106 break;
2107 case INDEX_op_ext8u_i32:
2108 case INDEX_op_ext8u_i64:
2109 tcg_out_ext(s, OPC_ZXT1_I29, args[0], args[1]);
2110 break;
2111 case INDEX_op_ext16s_i32:
2112 case INDEX_op_ext16s_i64:
2113 tcg_out_ext(s, OPC_SXT2_I29, args[0], args[1]);
2114 break;
2115 case INDEX_op_ext16u_i32:
2116 case INDEX_op_ext16u_i64:
2117 tcg_out_ext(s, OPC_ZXT2_I29, args[0], args[1]);
2118 break;
2119 case INDEX_op_ext32s_i64:
2120 tcg_out_ext(s, OPC_SXT4_I29, args[0], args[1]);
2121 break;
2122 case INDEX_op_ext32u_i64:
2123 tcg_out_ext(s, OPC_ZXT4_I29, args[0], args[1]);
2124 break;
2125
2126 case INDEX_op_bswap16_i32:
2127 case INDEX_op_bswap16_i64:
2128 tcg_out_bswap16(s, args[0], args[1]);
2129 break;
2130 case INDEX_op_bswap32_i32:
2131 case INDEX_op_bswap32_i64:
2132 tcg_out_bswap32(s, args[0], args[1]);
2133 break;
2134 case INDEX_op_bswap64_i64:
2135 tcg_out_bswap64(s, args[0], args[1]);
2136 break;
2137
2138 case INDEX_op_brcond_i32:
2139 tcg_out_brcond(s, args[2], args[0], const_args[0],
2140 args[1], const_args[1], args[3], 1);
2141 break;
2142 case INDEX_op_brcond_i64:
2143 tcg_out_brcond(s, args[2], args[0], const_args[0],
2144 args[1], const_args[1], args[3], 0);
2145 break;
2146 case INDEX_op_setcond_i32:
2147 tcg_out_setcond(s, args[3], args[0], args[1], args[2], 1);
2148 break;
2149 case INDEX_op_setcond_i64:
2150 tcg_out_setcond(s, args[3], args[0], args[1], args[2], 0);
2151 break;
2152
2153 case INDEX_op_qemu_ld8u:
2154 tcg_out_qemu_ld(s, args, 0);
2155 break;
2156 case INDEX_op_qemu_ld8s:
2157 tcg_out_qemu_ld(s, args, 0 | 4);
2158 break;
2159 case INDEX_op_qemu_ld16u:
2160 tcg_out_qemu_ld(s, args, 1);
2161 break;
2162 case INDEX_op_qemu_ld16s:
2163 tcg_out_qemu_ld(s, args, 1 | 4);
2164 break;
2165 case INDEX_op_qemu_ld32:
2166 case INDEX_op_qemu_ld32u:
2167 tcg_out_qemu_ld(s, args, 2);
2168 break;
2169 case INDEX_op_qemu_ld32s:
2170 tcg_out_qemu_ld(s, args, 2 | 4);
2171 break;
2172 case INDEX_op_qemu_ld64:
2173 tcg_out_qemu_ld(s, args, 3);
2174 break;
2175
2176 case INDEX_op_qemu_st8:
2177 tcg_out_qemu_st(s, args, 0);
2178 break;
2179 case INDEX_op_qemu_st16:
2180 tcg_out_qemu_st(s, args, 1);
2181 break;
2182 case INDEX_op_qemu_st32:
2183 tcg_out_qemu_st(s, args, 2);
2184 break;
2185 case INDEX_op_qemu_st64:
2186 tcg_out_qemu_st(s, args, 3);
2187 break;
2188
2189 default:
2190 tcg_abort();
2191 }
2192 }
2193
2194 static const TCGTargetOpDef ia64_op_defs[] = {
2195 { INDEX_op_br, { } },
2196 { INDEX_op_call, { "r" } },
2197 { INDEX_op_exit_tb, { } },
2198 { INDEX_op_goto_tb, { } },
2199 { INDEX_op_jmp, { "r" } },
2200
2201 { INDEX_op_mov_i32, { "r", "r" } },
2202 { INDEX_op_movi_i32, { "r" } },
2203
2204 { INDEX_op_ld8u_i32, { "r", "r" } },
2205 { INDEX_op_ld8s_i32, { "r", "r" } },
2206 { INDEX_op_ld16u_i32, { "r", "r" } },
2207 { INDEX_op_ld16s_i32, { "r", "r" } },
2208 { INDEX_op_ld_i32, { "r", "r" } },
2209 { INDEX_op_st8_i32, { "rZ", "r" } },
2210 { INDEX_op_st16_i32, { "rZ", "r" } },
2211 { INDEX_op_st_i32, { "rZ", "r" } },
2212
2213 { INDEX_op_add_i32, { "r", "rI", "rI" } },
2214 { INDEX_op_sub_i32, { "r", "rI", "rI" } },
2215
2216 { INDEX_op_and_i32, { "r", "rI", "rI" } },
2217 { INDEX_op_andc_i32, { "r", "rI", "rI" } },
2218 { INDEX_op_eqv_i32, { "r", "rZ", "rZ" } },
2219 { INDEX_op_nand_i32, { "r", "rZ", "rZ" } },
2220 { INDEX_op_nor_i32, { "r", "rZ", "rZ" } },
2221 { INDEX_op_or_i32, { "r", "rI", "rI" } },
2222 { INDEX_op_orc_i32, { "r", "rZ", "rZ" } },
2223 { INDEX_op_xor_i32, { "r", "rI", "rI" } },
2224
2225 { INDEX_op_mul_i32, { "r", "rZ", "rZ" } },
2226
2227 { INDEX_op_sar_i32, { "r", "rZ", "ri" } },
2228 { INDEX_op_shl_i32, { "r", "rZ", "ri" } },
2229 { INDEX_op_shr_i32, { "r", "rZ", "ri" } },
2230 { INDEX_op_rotl_i32, { "r", "rZ", "ri" } },
2231 { INDEX_op_rotr_i32, { "r", "rZ", "ri" } },
2232
2233 { INDEX_op_ext8s_i32, { "r", "rZ"} },
2234 { INDEX_op_ext8u_i32, { "r", "rZ"} },
2235 { INDEX_op_ext16s_i32, { "r", "rZ"} },
2236 { INDEX_op_ext16u_i32, { "r", "rZ"} },
2237
2238 { INDEX_op_bswap16_i32, { "r", "rZ" } },
2239 { INDEX_op_bswap32_i32, { "r", "rZ" } },
2240
2241 { INDEX_op_brcond_i32, { "rI", "rI" } },
2242 { INDEX_op_setcond_i32, { "r", "rZ", "rZ" } },
2243
2244 { INDEX_op_mov_i64, { "r", "r" } },
2245 { INDEX_op_movi_i64, { "r" } },
2246
2247 { INDEX_op_ld8u_i64, { "r", "r" } },
2248 { INDEX_op_ld8s_i64, { "r", "r" } },
2249 { INDEX_op_ld16u_i64, { "r", "r" } },
2250 { INDEX_op_ld16s_i64, { "r", "r" } },
2251 { INDEX_op_ld32u_i64, { "r", "r" } },
2252 { INDEX_op_ld32s_i64, { "r", "r" } },
2253 { INDEX_op_ld_i64, { "r", "r" } },
2254 { INDEX_op_st8_i64, { "rZ", "r" } },
2255 { INDEX_op_st16_i64, { "rZ", "r" } },
2256 { INDEX_op_st32_i64, { "rZ", "r" } },
2257 { INDEX_op_st_i64, { "rZ", "r" } },
2258
2259 { INDEX_op_add_i64, { "r", "rI", "rI" } },
2260 { INDEX_op_sub_i64, { "r", "rI", "rI" } },
2261
2262 { INDEX_op_and_i64, { "r", "rI", "rI" } },
2263 { INDEX_op_andc_i64, { "r", "rI", "rI" } },
2264 { INDEX_op_eqv_i64, { "r", "rZ", "rZ" } },
2265 { INDEX_op_nand_i64, { "r", "rZ", "rZ" } },
2266 { INDEX_op_nor_i64, { "r", "rZ", "rZ" } },
2267 { INDEX_op_or_i64, { "r", "rI", "rI" } },
2268 { INDEX_op_orc_i64, { "r", "rZ", "rZ" } },
2269 { INDEX_op_xor_i64, { "r", "rI", "rI" } },
2270
2271 { INDEX_op_mul_i64, { "r", "rZ", "rZ" } },
2272
2273 { INDEX_op_sar_i64, { "r", "rZ", "ri" } },
2274 { INDEX_op_shl_i64, { "r", "rZ", "ri" } },
2275 { INDEX_op_shr_i64, { "r", "rZ", "ri" } },
2276 { INDEX_op_rotl_i64, { "r", "rZ", "ri" } },
2277 { INDEX_op_rotr_i64, { "r", "rZ", "ri" } },
2278
2279 { INDEX_op_ext8s_i64, { "r", "rZ"} },
2280 { INDEX_op_ext8u_i64, { "r", "rZ"} },
2281 { INDEX_op_ext16s_i64, { "r", "rZ"} },
2282 { INDEX_op_ext16u_i64, { "r", "rZ"} },
2283 { INDEX_op_ext32s_i64, { "r", "rZ"} },
2284 { INDEX_op_ext32u_i64, { "r", "rZ"} },
2285
2286 { INDEX_op_bswap16_i64, { "r", "rZ" } },
2287 { INDEX_op_bswap32_i64, { "r", "rZ" } },
2288 { INDEX_op_bswap64_i64, { "r", "rZ" } },
2289
2290 { INDEX_op_brcond_i64, { "rI", "rI" } },
2291 { INDEX_op_setcond_i64, { "r", "rZ", "rZ" } },
2292
2293 { INDEX_op_qemu_ld8u, { "r", "r" } },
2294 { INDEX_op_qemu_ld8s, { "r", "r" } },
2295 { INDEX_op_qemu_ld16u, { "r", "r" } },
2296 { INDEX_op_qemu_ld16s, { "r", "r" } },
2297 { INDEX_op_qemu_ld32, { "r", "r" } },
2298 { INDEX_op_qemu_ld32u, { "r", "r" } },
2299 { INDEX_op_qemu_ld32s, { "r", "r" } },
2300 { INDEX_op_qemu_ld64, { "r", "r" } },
2301
2302 { INDEX_op_qemu_st8, { "SZ", "r" } },
2303 { INDEX_op_qemu_st16, { "SZ", "r" } },
2304 { INDEX_op_qemu_st32, { "SZ", "r" } },
2305 { INDEX_op_qemu_st64, { "SZ", "r" } },
2306
2307 { -1 },
2308 };
2309
2310 /* Generate global QEMU prologue and epilogue code */
2311 static void tcg_target_qemu_prologue(TCGContext *s)
2312 {
2313 int frame_size;
2314
2315 /* reserve some stack space */
2316 frame_size = TCG_STATIC_CALL_ARGS_SIZE;
2317 frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
2318 ~(TCG_TARGET_STACK_ALIGN - 1);
2319
2320 /* First emit adhoc function descriptor */
2321 *(uint64_t *)(s->code_ptr) = (uint64_t)s->code_ptr + 16; /* entry point */
2322 s->code_ptr += 16; /* skip GP */
2323
2324 /* prologue */
2325 tcg_out_bundle(s, miI,
2326 tcg_opc_m34(TCG_REG_P0, OPC_ALLOC_M34,
2327 TCG_REG_R34, 32, 24, 0),
2328 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
2329 TCG_AREG0, 0, TCG_REG_R32),
2330 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
2331 TCG_REG_B6, TCG_REG_R33, 0));
2332
2333 /* ??? If GUEST_BASE < 0x200000, we could load the register via
2334 an ADDL in the M slot of the next bundle. */
2335 if (GUEST_BASE != 0) {
2336 tcg_out_bundle(s, mlx,
2337 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
2338 tcg_opc_l2 (GUEST_BASE),
2339 tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2,
2340 TCG_GUEST_BASE_REG, GUEST_BASE));
2341 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2342 }
2343
2344 tcg_out_bundle(s, miB,
2345 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
2346 TCG_REG_R12, -frame_size, TCG_REG_R12),
2347 tcg_opc_i22(TCG_REG_P0, OPC_MOV_I22,
2348 TCG_REG_R32, TCG_REG_B0),
2349 tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6));
2350
2351 /* epilogue */
2352 tb_ret_addr = s->code_ptr;
2353 tcg_out_bundle(s, miI,
2354 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
2355 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
2356 TCG_REG_B0, TCG_REG_R32, 0),
2357 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
2358 TCG_REG_R12, frame_size, TCG_REG_R12));
2359 tcg_out_bundle(s, miB,
2360 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
2361 tcg_opc_i26(TCG_REG_P0, OPC_MOV_I_I26,
2362 TCG_REG_PFS, TCG_REG_R34),
2363 tcg_opc_b4 (TCG_REG_P0, OPC_BR_RET_SPTK_MANY_B4,
2364 TCG_REG_B0));
2365 }
2366
2367 static void tcg_target_init(TCGContext *s)
2368 {
2369 tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I32],
2370 0xffffffffffffffffull);
2371 tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I64],
2372 0xffffffffffffffffull);
2373
2374 tcg_regset_clear(tcg_target_call_clobber_regs);
2375 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8);
2376 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9);
2377 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10);
2378 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11);
2379 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);
2380 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R15);
2381 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R16);
2382 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R17);
2383 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R18);
2384 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R19);
2385 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R20);
2386 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R21);
2387 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R22);
2388 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R23);
2389 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R24);
2390 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R25);
2391 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R26);
2392 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R27);
2393 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R28);
2394 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R29);
2395 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R30);
2396 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R31);
2397 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R56);
2398 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R57);
2399 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R58);
2400 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R59);
2401 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R60);
2402 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R61);
2403 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R62);
2404 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R63);
2405
2406 tcg_regset_clear(s->reserved_regs);
2407 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* zero register */
2408 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* global pointer */
2409 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* internal use */
2410 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R3); /* internal use */
2411 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R12); /* stack pointer */
2412 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
2413 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R32); /* return address */
2414 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R34); /* PFS */
2415
2416 /* The following 3 are not in use, are call-saved, but *not* saved
2417 by the prologue. Therefore we cannot use them without modifying
2418 the prologue. There doesn't seem to be any good reason to use
2419 these as opposed to the windowed registers. */
2420 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R4);
2421 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R5);
2422 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R6);
2423
2424 tcg_add_target_add_op_defs(ia64_op_defs);
2425 tcg_set_frame(s, TCG_AREG0, offsetof(CPUArchState, temp_buf),
2426 CPU_TEMP_BUF_NLONGS * sizeof(long));
2427 }
Qemu copy for testing