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tcg-ia64: Use TCGMemOp within qemu_ldst routines
[qemu.git] / tcg / ia64 / tcg-target.c
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2009-2010 Aurelien Jarno <aurelien@aurel32.net>
5 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 #include "tcg-be-null.h"
27
28 /*
29 * Register definitions
30 */
31
32 #ifndef NDEBUG
33 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
34 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
35 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
36 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
37 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
38 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
39 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
40 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
41 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
42 };
43 #endif
44
45 #ifdef CONFIG_USE_GUEST_BASE
46 #define TCG_GUEST_BASE_REG TCG_REG_R55
47 #else
48 #define TCG_GUEST_BASE_REG TCG_REG_R0
49 #endif
50 #ifndef GUEST_BASE
51 #define GUEST_BASE 0
52 #endif
53
54 /* Branch registers */
55 enum {
56 TCG_REG_B0 = 0,
57 TCG_REG_B1,
58 TCG_REG_B2,
59 TCG_REG_B3,
60 TCG_REG_B4,
61 TCG_REG_B5,
62 TCG_REG_B6,
63 TCG_REG_B7,
64 };
65
66 /* Floating point registers */
67 enum {
68 TCG_REG_F0 = 0,
69 TCG_REG_F1,
70 TCG_REG_F2,
71 TCG_REG_F3,
72 TCG_REG_F4,
73 TCG_REG_F5,
74 TCG_REG_F6,
75 TCG_REG_F7,
76 TCG_REG_F8,
77 TCG_REG_F9,
78 TCG_REG_F10,
79 TCG_REG_F11,
80 TCG_REG_F12,
81 TCG_REG_F13,
82 TCG_REG_F14,
83 TCG_REG_F15,
84 };
85
86 /* Predicate registers */
87 enum {
88 TCG_REG_P0 = 0,
89 TCG_REG_P1,
90 TCG_REG_P2,
91 TCG_REG_P3,
92 TCG_REG_P4,
93 TCG_REG_P5,
94 TCG_REG_P6,
95 TCG_REG_P7,
96 TCG_REG_P8,
97 TCG_REG_P9,
98 TCG_REG_P10,
99 TCG_REG_P11,
100 TCG_REG_P12,
101 TCG_REG_P13,
102 TCG_REG_P14,
103 TCG_REG_P15,
104 };
105
106 /* Application registers */
107 enum {
108 TCG_REG_PFS = 64,
109 };
110
111 static const int tcg_target_reg_alloc_order[] = {
112 TCG_REG_R33,
113 TCG_REG_R35,
114 TCG_REG_R36,
115 TCG_REG_R37,
116 TCG_REG_R38,
117 TCG_REG_R39,
118 TCG_REG_R40,
119 TCG_REG_R41,
120 TCG_REG_R42,
121 TCG_REG_R43,
122 TCG_REG_R44,
123 TCG_REG_R45,
124 TCG_REG_R46,
125 TCG_REG_R47,
126 TCG_REG_R48,
127 TCG_REG_R49,
128 TCG_REG_R50,
129 TCG_REG_R51,
130 TCG_REG_R52,
131 TCG_REG_R53,
132 TCG_REG_R54,
133 TCG_REG_R55,
134 TCG_REG_R14,
135 TCG_REG_R15,
136 TCG_REG_R16,
137 TCG_REG_R17,
138 TCG_REG_R18,
139 TCG_REG_R19,
140 TCG_REG_R20,
141 TCG_REG_R21,
142 TCG_REG_R22,
143 TCG_REG_R23,
144 TCG_REG_R24,
145 TCG_REG_R25,
146 TCG_REG_R26,
147 TCG_REG_R27,
148 TCG_REG_R28,
149 TCG_REG_R29,
150 TCG_REG_R30,
151 TCG_REG_R31,
152 TCG_REG_R56,
153 TCG_REG_R57,
154 TCG_REG_R58,
155 TCG_REG_R59,
156 TCG_REG_R60,
157 TCG_REG_R61,
158 TCG_REG_R62,
159 TCG_REG_R63,
160 TCG_REG_R8,
161 TCG_REG_R9,
162 TCG_REG_R10,
163 TCG_REG_R11
164 };
165
166 static const int tcg_target_call_iarg_regs[8] = {
167 TCG_REG_R56,
168 TCG_REG_R57,
169 TCG_REG_R58,
170 TCG_REG_R59,
171 TCG_REG_R60,
172 TCG_REG_R61,
173 TCG_REG_R62,
174 TCG_REG_R63,
175 };
176
177 static const int tcg_target_call_oarg_regs[] = {
178 TCG_REG_R8
179 };
180
181 /*
182 * opcode formation
183 */
184
185 /* bundle templates: stops (double bar in the IA64 manual) are marked with
186 an uppercase letter. */
187 enum {
188 mii = 0x00,
189 miI = 0x01,
190 mIi = 0x02,
191 mII = 0x03,
192 mlx = 0x04,
193 mLX = 0x05,
194 mmi = 0x08,
195 mmI = 0x09,
196 Mmi = 0x0a,
197 MmI = 0x0b,
198 mfi = 0x0c,
199 mfI = 0x0d,
200 mmf = 0x0e,
201 mmF = 0x0f,
202 mib = 0x10,
203 miB = 0x11,
204 mbb = 0x12,
205 mbB = 0x13,
206 bbb = 0x16,
207 bbB = 0x17,
208 mmb = 0x18,
209 mmB = 0x19,
210 mfb = 0x1c,
211 mfB = 0x1d,
212 };
213
214 enum {
215 OPC_ADD_A1 = 0x10000000000ull,
216 OPC_AND_A1 = 0x10060000000ull,
217 OPC_AND_A3 = 0x10160000000ull,
218 OPC_ANDCM_A1 = 0x10068000000ull,
219 OPC_ANDCM_A3 = 0x10168000000ull,
220 OPC_ADDS_A4 = 0x10800000000ull,
221 OPC_ADDL_A5 = 0x12000000000ull,
222 OPC_ALLOC_M34 = 0x02c00000000ull,
223 OPC_BR_DPTK_FEW_B1 = 0x08400000000ull,
224 OPC_BR_SPTK_MANY_B1 = 0x08000001000ull,
225 OPC_BR_SPTK_MANY_B4 = 0x00100001000ull,
226 OPC_BR_CALL_SPTK_MANY_B5 = 0x02100001000ull,
227 OPC_BR_RET_SPTK_MANY_B4 = 0x00108001100ull,
228 OPC_BRL_SPTK_MANY_X3 = 0x18000001000ull,
229 OPC_CMP_LT_A6 = 0x18000000000ull,
230 OPC_CMP_LTU_A6 = 0x1a000000000ull,
231 OPC_CMP_EQ_A6 = 0x1c000000000ull,
232 OPC_CMP4_LT_A6 = 0x18400000000ull,
233 OPC_CMP4_LTU_A6 = 0x1a400000000ull,
234 OPC_CMP4_EQ_A6 = 0x1c400000000ull,
235 OPC_DEP_I14 = 0x0ae00000000ull,
236 OPC_DEP_I15 = 0x08000000000ull,
237 OPC_DEP_Z_I12 = 0x0a600000000ull,
238 OPC_EXTR_I11 = 0x0a400002000ull,
239 OPC_EXTR_U_I11 = 0x0a400000000ull,
240 OPC_FCVT_FX_TRUNC_S1_F10 = 0x004d0000000ull,
241 OPC_FCVT_FXU_TRUNC_S1_F10 = 0x004d8000000ull,
242 OPC_FCVT_XF_F11 = 0x000e0000000ull,
243 OPC_FMA_S1_F1 = 0x10400000000ull,
244 OPC_FNMA_S1_F1 = 0x18400000000ull,
245 OPC_FRCPA_S1_F6 = 0x00600000000ull,
246 OPC_GETF_SIG_M19 = 0x08708000000ull,
247 OPC_LD1_M1 = 0x08000000000ull,
248 OPC_LD1_M3 = 0x0a000000000ull,
249 OPC_LD2_M1 = 0x08040000000ull,
250 OPC_LD2_M3 = 0x0a040000000ull,
251 OPC_LD4_M1 = 0x08080000000ull,
252 OPC_LD4_M3 = 0x0a080000000ull,
253 OPC_LD8_M1 = 0x080c0000000ull,
254 OPC_LD8_M3 = 0x0a0c0000000ull,
255 OPC_MUX1_I3 = 0x0eca0000000ull,
256 OPC_NOP_B9 = 0x04008000000ull,
257 OPC_NOP_F16 = 0x00008000000ull,
258 OPC_NOP_I18 = 0x00008000000ull,
259 OPC_NOP_M48 = 0x00008000000ull,
260 OPC_MOV_I21 = 0x00e00100000ull,
261 OPC_MOV_RET_I21 = 0x00e00500000ull,
262 OPC_MOV_I22 = 0x00188000000ull,
263 OPC_MOV_I_I26 = 0x00150000000ull,
264 OPC_MOVL_X2 = 0x0c000000000ull,
265 OPC_OR_A1 = 0x10070000000ull,
266 OPC_SETF_EXP_M18 = 0x0c748000000ull,
267 OPC_SETF_SIG_M18 = 0x0c708000000ull,
268 OPC_SHL_I7 = 0x0f240000000ull,
269 OPC_SHR_I5 = 0x0f220000000ull,
270 OPC_SHR_U_I5 = 0x0f200000000ull,
271 OPC_SHRP_I10 = 0x0ac00000000ull,
272 OPC_SXT1_I29 = 0x000a0000000ull,
273 OPC_SXT2_I29 = 0x000a8000000ull,
274 OPC_SXT4_I29 = 0x000b0000000ull,
275 OPC_ST1_M4 = 0x08c00000000ull,
276 OPC_ST2_M4 = 0x08c40000000ull,
277 OPC_ST4_M4 = 0x08c80000000ull,
278 OPC_ST8_M4 = 0x08cc0000000ull,
279 OPC_SUB_A1 = 0x10028000000ull,
280 OPC_SUB_A3 = 0x10128000000ull,
281 OPC_UNPACK4_L_I2 = 0x0f860000000ull,
282 OPC_XMA_L_F2 = 0x1d000000000ull,
283 OPC_XOR_A1 = 0x10078000000ull,
284 OPC_ZXT1_I29 = 0x00080000000ull,
285 OPC_ZXT2_I29 = 0x00088000000ull,
286 OPC_ZXT4_I29 = 0x00090000000ull,
287 };
288
289 static inline uint64_t tcg_opc_a1(int qp, uint64_t opc, int r1,
290 int r2, int r3)
291 {
292 return opc
293 | ((r3 & 0x7f) << 20)
294 | ((r2 & 0x7f) << 13)
295 | ((r1 & 0x7f) << 6)
296 | (qp & 0x3f);
297 }
298
299 static inline uint64_t tcg_opc_a3(int qp, uint64_t opc, int r1,
300 uint64_t imm, int r3)
301 {
302 return opc
303 | ((imm & 0x80) << 29) /* s */
304 | ((imm & 0x7f) << 13) /* imm7b */
305 | ((r3 & 0x7f) << 20)
306 | ((r1 & 0x7f) << 6)
307 | (qp & 0x3f);
308 }
309
310 static inline uint64_t tcg_opc_a4(int qp, uint64_t opc, int r1,
311 uint64_t imm, int r3)
312 {
313 return opc
314 | ((imm & 0x2000) << 23) /* s */
315 | ((imm & 0x1f80) << 20) /* imm6d */
316 | ((imm & 0x007f) << 13) /* imm7b */
317 | ((r3 & 0x7f) << 20)
318 | ((r1 & 0x7f) << 6)
319 | (qp & 0x3f);
320 }
321
322 static inline uint64_t tcg_opc_a5(int qp, uint64_t opc, int r1,
323 uint64_t imm, int r3)
324 {
325 return opc
326 | ((imm & 0x200000) << 15) /* s */
327 | ((imm & 0x1f0000) << 6) /* imm5c */
328 | ((imm & 0x00ff80) << 20) /* imm9d */
329 | ((imm & 0x00007f) << 13) /* imm7b */
330 | ((r3 & 0x03) << 20)
331 | ((r1 & 0x7f) << 6)
332 | (qp & 0x3f);
333 }
334
335 static inline uint64_t tcg_opc_a6(int qp, uint64_t opc, int p1,
336 int p2, int r2, int r3)
337 {
338 return opc
339 | ((p2 & 0x3f) << 27)
340 | ((r3 & 0x7f) << 20)
341 | ((r2 & 0x7f) << 13)
342 | ((p1 & 0x3f) << 6)
343 | (qp & 0x3f);
344 }
345
346 static inline uint64_t tcg_opc_b1(int qp, uint64_t opc, uint64_t imm)
347 {
348 return opc
349 | ((imm & 0x100000) << 16) /* s */
350 | ((imm & 0x0fffff) << 13) /* imm20b */
351 | (qp & 0x3f);
352 }
353
354 static inline uint64_t tcg_opc_b4(int qp, uint64_t opc, int b2)
355 {
356 return opc
357 | ((b2 & 0x7) << 13)
358 | (qp & 0x3f);
359 }
360
361 static inline uint64_t tcg_opc_b5(int qp, uint64_t opc, int b1, int b2)
362 {
363 return opc
364 | ((b2 & 0x7) << 13)
365 | ((b1 & 0x7) << 6)
366 | (qp & 0x3f);
367 }
368
369
370 static inline uint64_t tcg_opc_b9(int qp, uint64_t opc, uint64_t imm)
371 {
372 return opc
373 | ((imm & 0x100000) << 16) /* i */
374 | ((imm & 0x0fffff) << 6) /* imm20a */
375 | (qp & 0x3f);
376 }
377
378 static inline uint64_t tcg_opc_f1(int qp, uint64_t opc, int f1,
379 int f3, int f4, int f2)
380 {
381 return opc
382 | ((f4 & 0x7f) << 27)
383 | ((f3 & 0x7f) << 20)
384 | ((f2 & 0x7f) << 13)
385 | ((f1 & 0x7f) << 6)
386 | (qp & 0x3f);
387 }
388
389 static inline uint64_t tcg_opc_f2(int qp, uint64_t opc, int f1,
390 int f3, int f4, int f2)
391 {
392 return opc
393 | ((f4 & 0x7f) << 27)
394 | ((f3 & 0x7f) << 20)
395 | ((f2 & 0x7f) << 13)
396 | ((f1 & 0x7f) << 6)
397 | (qp & 0x3f);
398 }
399
400 static inline uint64_t tcg_opc_f6(int qp, uint64_t opc, int f1,
401 int p2, int f2, int f3)
402 {
403 return opc
404 | ((p2 & 0x3f) << 27)
405 | ((f3 & 0x7f) << 20)
406 | ((f2 & 0x7f) << 13)
407 | ((f1 & 0x7f) << 6)
408 | (qp & 0x3f);
409 }
410
411 static inline uint64_t tcg_opc_f10(int qp, uint64_t opc, int f1, int f2)
412 {
413 return opc
414 | ((f2 & 0x7f) << 13)
415 | ((f1 & 0x7f) << 6)
416 | (qp & 0x3f);
417 }
418
419 static inline uint64_t tcg_opc_f11(int qp, uint64_t opc, int f1, int f2)
420 {
421 return opc
422 | ((f2 & 0x7f) << 13)
423 | ((f1 & 0x7f) << 6)
424 | (qp & 0x3f);
425 }
426
427 static inline uint64_t tcg_opc_f16(int qp, uint64_t opc, uint64_t imm)
428 {
429 return opc
430 | ((imm & 0x100000) << 16) /* i */
431 | ((imm & 0x0fffff) << 6) /* imm20a */
432 | (qp & 0x3f);
433 }
434
435 static inline uint64_t tcg_opc_i2(int qp, uint64_t opc, int r1,
436 int r2, int r3)
437 {
438 return opc
439 | ((r3 & 0x7f) << 20)
440 | ((r2 & 0x7f) << 13)
441 | ((r1 & 0x7f) << 6)
442 | (qp & 0x3f);
443 }
444
445 static inline uint64_t tcg_opc_i3(int qp, uint64_t opc, int r1,
446 int r2, int mbtype)
447 {
448 return opc
449 | ((mbtype & 0x0f) << 20)
450 | ((r2 & 0x7f) << 13)
451 | ((r1 & 0x7f) << 6)
452 | (qp & 0x3f);
453 }
454
455 static inline uint64_t tcg_opc_i5(int qp, uint64_t opc, int r1,
456 int r3, int r2)
457 {
458 return opc
459 | ((r3 & 0x7f) << 20)
460 | ((r2 & 0x7f) << 13)
461 | ((r1 & 0x7f) << 6)
462 | (qp & 0x3f);
463 }
464
465 static inline uint64_t tcg_opc_i7(int qp, uint64_t opc, int r1,
466 int r2, int r3)
467 {
468 return opc
469 | ((r3 & 0x7f) << 20)
470 | ((r2 & 0x7f) << 13)
471 | ((r1 & 0x7f) << 6)
472 | (qp & 0x3f);
473 }
474
475 static inline uint64_t tcg_opc_i10(int qp, uint64_t opc, int r1,
476 int r2, int r3, uint64_t count)
477 {
478 return opc
479 | ((count & 0x3f) << 27)
480 | ((r3 & 0x7f) << 20)
481 | ((r2 & 0x7f) << 13)
482 | ((r1 & 0x7f) << 6)
483 | (qp & 0x3f);
484 }
485
486 static inline uint64_t tcg_opc_i11(int qp, uint64_t opc, int r1,
487 int r3, uint64_t pos, uint64_t len)
488 {
489 return opc
490 | ((len & 0x3f) << 27)
491 | ((r3 & 0x7f) << 20)
492 | ((pos & 0x3f) << 14)
493 | ((r1 & 0x7f) << 6)
494 | (qp & 0x3f);
495 }
496
497 static inline uint64_t tcg_opc_i12(int qp, uint64_t opc, int r1,
498 int r2, uint64_t pos, uint64_t len)
499 {
500 return opc
501 | ((len & 0x3f) << 27)
502 | ((pos & 0x3f) << 20)
503 | ((r2 & 0x7f) << 13)
504 | ((r1 & 0x7f) << 6)
505 | (qp & 0x3f);
506 }
507
508 static inline uint64_t tcg_opc_i14(int qp, uint64_t opc, int r1, uint64_t imm,
509 int r3, uint64_t pos, uint64_t len)
510 {
511 return opc
512 | ((imm & 0x01) << 36)
513 | ((len & 0x3f) << 27)
514 | ((r3 & 0x7f) << 20)
515 | ((pos & 0x3f) << 14)
516 | ((r1 & 0x7f) << 6)
517 | (qp & 0x3f);
518 }
519
520 static inline uint64_t tcg_opc_i15(int qp, uint64_t opc, int r1, int r2,
521 int r3, uint64_t pos, uint64_t len)
522 {
523 return opc
524 | ((pos & 0x3f) << 31)
525 | ((len & 0x0f) << 27)
526 | ((r3 & 0x7f) << 20)
527 | ((r2 & 0x7f) << 13)
528 | ((r1 & 0x7f) << 6)
529 | (qp & 0x3f);
530 }
531
532 static inline uint64_t tcg_opc_i18(int qp, uint64_t opc, uint64_t imm)
533 {
534 return opc
535 | ((imm & 0x100000) << 16) /* i */
536 | ((imm & 0x0fffff) << 6) /* imm20a */
537 | (qp & 0x3f);
538 }
539
540 static inline uint64_t tcg_opc_i21(int qp, uint64_t opc, int b1,
541 int r2, uint64_t imm)
542 {
543 return opc
544 | ((imm & 0x1ff) << 24)
545 | ((r2 & 0x7f) << 13)
546 | ((b1 & 0x7) << 6)
547 | (qp & 0x3f);
548 }
549
550 static inline uint64_t tcg_opc_i22(int qp, uint64_t opc, int r1, int b2)
551 {
552 return opc
553 | ((b2 & 0x7) << 13)
554 | ((r1 & 0x7f) << 6)
555 | (qp & 0x3f);
556 }
557
558 static inline uint64_t tcg_opc_i26(int qp, uint64_t opc, int ar3, int r2)
559 {
560 return opc
561 | ((ar3 & 0x7f) << 20)
562 | ((r2 & 0x7f) << 13)
563 | (qp & 0x3f);
564 }
565
566 static inline uint64_t tcg_opc_i29(int qp, uint64_t opc, int r1, int r3)
567 {
568 return opc
569 | ((r3 & 0x7f) << 20)
570 | ((r1 & 0x7f) << 6)
571 | (qp & 0x3f);
572 }
573
574 static inline uint64_t tcg_opc_l2(uint64_t imm)
575 {
576 return (imm & 0x7fffffffffc00000ull) >> 22;
577 }
578
579 static inline uint64_t tcg_opc_l3(uint64_t imm)
580 {
581 return (imm & 0x07fffffffff00000ull) >> 18;
582 }
583
584 static inline uint64_t tcg_opc_m1(int qp, uint64_t opc, int r1, int r3)
585 {
586 return opc
587 | ((r3 & 0x7f) << 20)
588 | ((r1 & 0x7f) << 6)
589 | (qp & 0x3f);
590 }
591
592 static inline uint64_t tcg_opc_m3(int qp, uint64_t opc, int r1,
593 int r3, uint64_t imm)
594 {
595 return opc
596 | ((imm & 0x100) << 28) /* s */
597 | ((imm & 0x080) << 20) /* i */
598 | ((imm & 0x07f) << 13) /* imm7b */
599 | ((r3 & 0x7f) << 20)
600 | ((r1 & 0x7f) << 6)
601 | (qp & 0x3f);
602 }
603
604 static inline uint64_t tcg_opc_m4(int qp, uint64_t opc, int r2, int r3)
605 {
606 return opc
607 | ((r3 & 0x7f) << 20)
608 | ((r2 & 0x7f) << 13)
609 | (qp & 0x3f);
610 }
611
612 static inline uint64_t tcg_opc_m18(int qp, uint64_t opc, int f1, int r2)
613 {
614 return opc
615 | ((r2 & 0x7f) << 13)
616 | ((f1 & 0x7f) << 6)
617 | (qp & 0x3f);
618 }
619
620 static inline uint64_t tcg_opc_m19(int qp, uint64_t opc, int r1, int f2)
621 {
622 return opc
623 | ((f2 & 0x7f) << 13)
624 | ((r1 & 0x7f) << 6)
625 | (qp & 0x3f);
626 }
627
628 static inline uint64_t tcg_opc_m34(int qp, uint64_t opc, int r1,
629 int sof, int sol, int sor)
630 {
631 return opc
632 | ((sor & 0x0f) << 27)
633 | ((sol & 0x7f) << 20)
634 | ((sof & 0x7f) << 13)
635 | ((r1 & 0x7f) << 6)
636 | (qp & 0x3f);
637 }
638
639 static inline uint64_t tcg_opc_m48(int qp, uint64_t opc, uint64_t imm)
640 {
641 return opc
642 | ((imm & 0x100000) << 16) /* i */
643 | ((imm & 0x0fffff) << 6) /* imm20a */
644 | (qp & 0x3f);
645 }
646
647 static inline uint64_t tcg_opc_x2(int qp, uint64_t opc,
648 int r1, uint64_t imm)
649 {
650 return opc
651 | ((imm & 0x8000000000000000ull) >> 27) /* i */
652 | (imm & 0x0000000000200000ull) /* ic */
653 | ((imm & 0x00000000001f0000ull) << 6) /* imm5c */
654 | ((imm & 0x000000000000ff80ull) << 20) /* imm9d */
655 | ((imm & 0x000000000000007full) << 13) /* imm7b */
656 | ((r1 & 0x7f) << 6)
657 | (qp & 0x3f);
658 }
659
660 static inline uint64_t tcg_opc_x3(int qp, uint64_t opc, uint64_t imm)
661 {
662 return opc
663 | ((imm & 0x0800000000000000ull) >> 23) /* i */
664 | ((imm & 0x00000000000fffffull) << 13) /* imm20b */
665 | (qp & 0x3f);
666 }
667
668
669 /*
670 * Relocations
671 */
672
673 static inline void reloc_pcrel21b(void *pc, intptr_t target)
674 {
675 uint64_t imm;
676 int64_t disp;
677 int slot;
678
679 slot = (intptr_t)pc & 3;
680 pc = (void *)((intptr_t)pc & ~3);
681
682 disp = target - (intptr_t)pc;
683 imm = (uint64_t) disp >> 4;
684
685 switch(slot) {
686 case 0:
687 *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 8) & 0xfffffdc00003ffffull)
688 | ((imm & 0x100000) << 21) /* s */
689 | ((imm & 0x0fffff) << 18); /* imm20b */
690 break;
691 case 1:
692 *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xfffffffffffb8000ull)
693 | ((imm & 0x100000) >> 2) /* s */
694 | ((imm & 0x0fffe0) >> 5); /* imm20b */
695 *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x07ffffffffffffffull)
696 | ((imm & 0x00001f) << 59); /* imm20b */
697 break;
698 case 2:
699 *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fffffffffull)
700 | ((imm & 0x100000) << 39) /* s */
701 | ((imm & 0x0fffff) << 36); /* imm20b */
702 break;
703 }
704 }
705
706 static inline uint64_t get_reloc_pcrel21b (void *pc)
707 {
708 int64_t low, high;
709 int slot;
710
711 slot = (tcg_target_long) pc & 3;
712 pc = (void *)((tcg_target_long) pc & ~3);
713
714 low = (*(uint64_t *)(pc + 0));
715 high = (*(uint64_t *)(pc + 8));
716
717 switch(slot) {
718 case 0:
719 return ((low >> 21) & 0x100000) + /* s */
720 ((low >> 18) & 0x0fffff); /* imm20b */
721 case 1:
722 return ((high << 2) & 0x100000) + /* s */
723 ((high << 5) & 0x0fffe0) + /* imm20b */
724 ((low >> 59) & 0x00001f); /* imm20b */
725 case 2:
726 return ((high >> 39) & 0x100000) + /* s */
727 ((high >> 36) & 0x0fffff); /* imm20b */
728 default:
729 tcg_abort();
730 }
731 }
732
733 static inline void reloc_pcrel60b(void *pc, intptr_t target)
734 {
735 int64_t disp;
736 uint64_t imm;
737
738 disp = target - (intptr_t)pc;
739 imm = (uint64_t) disp >> 4;
740
741 *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fff800000ull)
742 | (imm & 0x0800000000000000ull) /* s */
743 | ((imm & 0x07fffff000000000ull) >> 36) /* imm39 */
744 | ((imm & 0x00000000000fffffull) << 36); /* imm20b */
745 *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x00003fffffffffffull)
746 | ((imm & 0x0000000ffff00000ull) << 28); /* imm39 */
747 }
748
749 static inline uint64_t get_reloc_pcrel60b (void *pc)
750 {
751 int64_t low, high;
752
753 low = (*(uint64_t *)(pc + 0));
754 high = (*(uint64_t *)(pc + 8));
755
756 return ((high) & 0x0800000000000000ull) + /* s */
757 ((high >> 36) & 0x00000000000fffffull) + /* imm20b */
758 ((high << 36) & 0x07fffff000000000ull) + /* imm39 */
759 ((low >> 28) & 0x0000000ffff00000ull); /* imm39 */
760 }
761
762
763 static void patch_reloc(uint8_t *code_ptr, int type,
764 intptr_t value, intptr_t addend)
765 {
766 value += addend;
767 switch (type) {
768 case R_IA64_PCREL21B:
769 reloc_pcrel21b(code_ptr, value);
770 break;
771 case R_IA64_PCREL60B:
772 reloc_pcrel60b(code_ptr, value);
773 default:
774 tcg_abort();
775 }
776 }
777
778 /*
779 * Constraints
780 */
781
782 /* parse target specific constraints */
783 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
784 {
785 const char *ct_str;
786
787 ct_str = *pct_str;
788 switch(ct_str[0]) {
789 case 'r':
790 ct->ct |= TCG_CT_REG;
791 tcg_regset_set(ct->u.regs, 0xffffffffffffffffull);
792 break;
793 case 'I':
794 ct->ct |= TCG_CT_CONST_S22;
795 break;
796 case 'S':
797 ct->ct |= TCG_CT_REG;
798 tcg_regset_set(ct->u.regs, 0xffffffffffffffffull);
799 #if defined(CONFIG_SOFTMMU)
800 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R56);
801 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R57);
802 #endif
803 break;
804 case 'Z':
805 /* We are cheating a bit here, using the fact that the register
806 r0 is also the register number 0. Hence there is no need
807 to check for const_args in each instruction. */
808 ct->ct |= TCG_CT_CONST_ZERO;
809 break;
810 default:
811 return -1;
812 }
813 ct_str++;
814 *pct_str = ct_str;
815 return 0;
816 }
817
818 /* test if a constant matches the constraint */
819 static inline int tcg_target_const_match(tcg_target_long val,
820 const TCGArgConstraint *arg_ct)
821 {
822 int ct;
823 ct = arg_ct->ct;
824 if (ct & TCG_CT_CONST)
825 return 1;
826 else if ((ct & TCG_CT_CONST_ZERO) && val == 0)
827 return 1;
828 else if ((ct & TCG_CT_CONST_S22) && val == ((int32_t)val << 10) >> 10)
829 return 1;
830 else
831 return 0;
832 }
833
834 /*
835 * Code generation
836 */
837
838 static uint8_t *tb_ret_addr;
839
840 static inline void tcg_out_bundle(TCGContext *s, int template,
841 uint64_t slot0, uint64_t slot1,
842 uint64_t slot2)
843 {
844 template &= 0x1f; /* 5 bits */
845 slot0 &= 0x1ffffffffffull; /* 41 bits */
846 slot1 &= 0x1ffffffffffull; /* 41 bits */
847 slot2 &= 0x1ffffffffffull; /* 41 bits */
848
849 *(uint64_t *)(s->code_ptr + 0) = (slot1 << 46) | (slot0 << 5) | template;
850 *(uint64_t *)(s->code_ptr + 8) = (slot2 << 23) | (slot1 >> 18);
851 s->code_ptr += 16;
852 }
853
854 static inline void tcg_out_mov(TCGContext *s, TCGType type,
855 TCGReg ret, TCGReg arg)
856 {
857 tcg_out_bundle(s, mmI,
858 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
859 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
860 tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, ret, 0, arg));
861 }
862
863 static inline void tcg_out_movi(TCGContext *s, TCGType type,
864 TCGReg reg, tcg_target_long arg)
865 {
866 tcg_out_bundle(s, mLX,
867 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
868 tcg_opc_l2 (arg),
869 tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, reg, arg));
870 }
871
872 static void tcg_out_br(TCGContext *s, int label_index)
873 {
874 TCGLabel *l = &s->labels[label_index];
875
876 /* We pay attention here to not modify the branch target by reading
877 the existing value and using it again. This ensure that caches and
878 memory are kept coherent during retranslation. */
879 tcg_out_bundle(s, mmB,
880 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
881 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
882 tcg_opc_b1 (TCG_REG_P0, OPC_BR_SPTK_MANY_B1,
883 get_reloc_pcrel21b(s->code_ptr + 2)));
884
885 if (l->has_value) {
886 reloc_pcrel21b((s->code_ptr - 16) + 2, l->u.value);
887 } else {
888 tcg_out_reloc(s, (s->code_ptr - 16) + 2,
889 R_IA64_PCREL21B, label_index, 0);
890 }
891 }
892
893 static inline void tcg_out_call(TCGContext *s, TCGArg addr)
894 {
895 tcg_out_bundle(s, MmI,
896 tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R2, addr),
897 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R3, 8, addr),
898 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
899 TCG_REG_B6, TCG_REG_R2, 0));
900 tcg_out_bundle(s, mmB,
901 tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R3),
902 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
903 tcg_opc_b5 (TCG_REG_P0, OPC_BR_CALL_SPTK_MANY_B5,
904 TCG_REG_B0, TCG_REG_B6));
905 }
906
907 static void tcg_out_exit_tb(TCGContext *s, tcg_target_long arg)
908 {
909 int64_t disp;
910 uint64_t imm;
911
912 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R8, arg);
913
914 disp = tb_ret_addr - s->code_ptr;
915 imm = (uint64_t)disp >> 4;
916
917 tcg_out_bundle(s, mLX,
918 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
919 tcg_opc_l3 (imm),
920 tcg_opc_x3 (TCG_REG_P0, OPC_BRL_SPTK_MANY_X3, imm));
921 }
922
923 static inline void tcg_out_goto_tb(TCGContext *s, TCGArg arg)
924 {
925 if (s->tb_jmp_offset) {
926 /* direct jump method */
927 tcg_abort();
928 } else {
929 /* indirect jump method */
930 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2,
931 (tcg_target_long)(s->tb_next + arg));
932 tcg_out_bundle(s, MmI,
933 tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1,
934 TCG_REG_R2, TCG_REG_R2),
935 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
936 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6,
937 TCG_REG_R2, 0));
938 tcg_out_bundle(s, mmB,
939 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
940 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
941 tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4,
942 TCG_REG_B6));
943 }
944 s->tb_next_offset[arg] = s->code_ptr - s->code_buf;
945 }
946
947 static inline void tcg_out_jmp(TCGContext *s, TCGArg addr)
948 {
949 tcg_out_bundle(s, mmI,
950 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
951 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
952 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6, addr, 0));
953 tcg_out_bundle(s, mmB,
954 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
955 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
956 tcg_opc_b4(TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6));
957 }
958
959 static inline void tcg_out_ld_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg,
960 TCGArg arg1, tcg_target_long arg2)
961 {
962 if (arg2 == ((int16_t)arg2 >> 2) << 2) {
963 tcg_out_bundle(s, MmI,
964 tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4,
965 TCG_REG_R2, arg2, arg1),
966 tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
967 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
968 } else {
969 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2);
970 tcg_out_bundle(s, MmI,
971 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1,
972 TCG_REG_R2, TCG_REG_R2, arg1),
973 tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
974 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
975 }
976 }
977
978 static inline void tcg_out_st_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg,
979 TCGArg arg1, tcg_target_long arg2)
980 {
981 if (arg2 == ((int16_t)arg2 >> 2) << 2) {
982 tcg_out_bundle(s, MmI,
983 tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4,
984 TCG_REG_R2, arg2, arg1),
985 tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
986 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
987 } else {
988 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2);
989 tcg_out_bundle(s, MmI,
990 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1,
991 TCG_REG_R2, TCG_REG_R2, arg1),
992 tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
993 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
994 }
995 }
996
997 static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
998 TCGReg arg1, intptr_t arg2)
999 {
1000 if (type == TCG_TYPE_I32) {
1001 tcg_out_ld_rel(s, OPC_LD4_M1, arg, arg1, arg2);
1002 } else {
1003 tcg_out_ld_rel(s, OPC_LD8_M1, arg, arg1, arg2);
1004 }
1005 }
1006
1007 static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
1008 TCGReg arg1, intptr_t arg2)
1009 {
1010 if (type == TCG_TYPE_I32) {
1011 tcg_out_st_rel(s, OPC_ST4_M4, arg, arg1, arg2);
1012 } else {
1013 tcg_out_st_rel(s, OPC_ST8_M4, arg, arg1, arg2);
1014 }
1015 }
1016
1017 static inline void tcg_out_alu(TCGContext *s, uint64_t opc_a1, TCGArg ret,
1018 TCGArg arg1, int const_arg1,
1019 TCGArg arg2, int const_arg2)
1020 {
1021 uint64_t opc1, opc2;
1022
1023 if (const_arg1 && arg1 != 0) {
1024 opc1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
1025 TCG_REG_R2, arg1, TCG_REG_R0);
1026 arg1 = TCG_REG_R2;
1027 } else {
1028 opc1 = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
1029 }
1030
1031 if (const_arg2 && arg2 != 0) {
1032 opc2 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
1033 TCG_REG_R3, arg2, TCG_REG_R0);
1034 arg2 = TCG_REG_R3;
1035 } else {
1036 opc2 = tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0);
1037 }
1038
1039 tcg_out_bundle(s, mII,
1040 opc1,
1041 opc2,
1042 tcg_opc_a1(TCG_REG_P0, opc_a1, ret, arg1, arg2));
1043 }
1044
1045 static inline void tcg_out_eqv(TCGContext *s, TCGArg ret,
1046 TCGArg arg1, int const_arg1,
1047 TCGArg arg2, int const_arg2)
1048 {
1049 tcg_out_bundle(s, mII,
1050 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1051 tcg_opc_a1 (TCG_REG_P0, OPC_XOR_A1, ret, arg1, arg2),
1052 tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
1053 }
1054
1055 static inline void tcg_out_nand(TCGContext *s, TCGArg ret,
1056 TCGArg arg1, int const_arg1,
1057 TCGArg arg2, int const_arg2)
1058 {
1059 tcg_out_bundle(s, mII,
1060 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1061 tcg_opc_a1 (TCG_REG_P0, OPC_AND_A1, ret, arg1, arg2),
1062 tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
1063 }
1064
1065 static inline void tcg_out_nor(TCGContext *s, TCGArg ret,
1066 TCGArg arg1, int const_arg1,
1067 TCGArg arg2, int const_arg2)
1068 {
1069 tcg_out_bundle(s, mII,
1070 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1071 tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, arg2),
1072 tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
1073 }
1074
1075 static inline void tcg_out_orc(TCGContext *s, TCGArg ret,
1076 TCGArg arg1, int const_arg1,
1077 TCGArg arg2, int const_arg2)
1078 {
1079 tcg_out_bundle(s, mII,
1080 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1081 tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, TCG_REG_R2, -1, arg2),
1082 tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, TCG_REG_R2));
1083 }
1084
1085 static inline void tcg_out_mul(TCGContext *s, TCGArg ret,
1086 TCGArg arg1, TCGArg arg2)
1087 {
1088 tcg_out_bundle(s, mmI,
1089 tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F6, arg1),
1090 tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F7, arg2),
1091 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1092 tcg_out_bundle(s, mmF,
1093 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1094 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1095 tcg_opc_f2 (TCG_REG_P0, OPC_XMA_L_F2, TCG_REG_F6, TCG_REG_F6,
1096 TCG_REG_F7, TCG_REG_F0));
1097 tcg_out_bundle(s, miI,
1098 tcg_opc_m19(TCG_REG_P0, OPC_GETF_SIG_M19, ret, TCG_REG_F6),
1099 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1100 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1101 }
1102
1103 static inline void tcg_out_sar_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1104 TCGArg arg2, int const_arg2)
1105 {
1106 if (const_arg2) {
1107 tcg_out_bundle(s, miI,
1108 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1109 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1110 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11,
1111 ret, arg1, arg2, 31 - arg2));
1112 } else {
1113 tcg_out_bundle(s, mII,
1114 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3,
1115 TCG_REG_R3, 0x1f, arg2),
1116 tcg_opc_i29(TCG_REG_P0, OPC_SXT4_I29, TCG_REG_R2, arg1),
1117 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret,
1118 TCG_REG_R2, TCG_REG_R3));
1119 }
1120 }
1121
1122 static inline void tcg_out_sar_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1123 TCGArg arg2, int const_arg2)
1124 {
1125 if (const_arg2) {
1126 tcg_out_bundle(s, miI,
1127 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1128 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1129 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11,
1130 ret, arg1, arg2, 63 - arg2));
1131 } else {
1132 tcg_out_bundle(s, miI,
1133 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1134 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1135 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret, arg1, arg2));
1136 }
1137 }
1138
1139 static inline void tcg_out_shl_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1140 TCGArg arg2, int const_arg2)
1141 {
1142 if (const_arg2) {
1143 tcg_out_bundle(s, miI,
1144 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1145 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1146 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret,
1147 arg1, 63 - arg2, 31 - arg2));
1148 } else {
1149 tcg_out_bundle(s, mII,
1150 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1151 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R2,
1152 0x1f, arg2),
1153 tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret,
1154 arg1, TCG_REG_R2));
1155 }
1156 }
1157
1158 static inline void tcg_out_shl_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1159 TCGArg arg2, int const_arg2)
1160 {
1161 if (const_arg2) {
1162 tcg_out_bundle(s, miI,
1163 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1164 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1165 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret,
1166 arg1, 63 - arg2, 63 - arg2));
1167 } else {
1168 tcg_out_bundle(s, miI,
1169 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1170 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1171 tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret,
1172 arg1, arg2));
1173 }
1174 }
1175
1176 static inline void tcg_out_shr_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1177 TCGArg arg2, int const_arg2)
1178 {
1179 if (const_arg2) {
1180 tcg_out_bundle(s, miI,
1181 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1182 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1183 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1184 arg1, arg2, 31 - arg2));
1185 } else {
1186 tcg_out_bundle(s, mII,
1187 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
1188 0x1f, arg2),
1189 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R2, arg1),
1190 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1191 TCG_REG_R2, TCG_REG_R3));
1192 }
1193 }
1194
1195 static inline void tcg_out_shr_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1196 TCGArg arg2, int const_arg2)
1197 {
1198 if (const_arg2) {
1199 tcg_out_bundle(s, miI,
1200 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1201 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1202 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1203 arg1, arg2, 63 - arg2));
1204 } else {
1205 tcg_out_bundle(s, miI,
1206 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1207 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1208 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1209 arg1, arg2));
1210 }
1211 }
1212
1213 static inline void tcg_out_rotl_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1214 TCGArg arg2, int const_arg2)
1215 {
1216 if (const_arg2) {
1217 tcg_out_bundle(s, mII,
1218 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1219 tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1220 TCG_REG_R2, arg1, arg1),
1221 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1222 TCG_REG_R2, 32 - arg2, 31));
1223 } else {
1224 tcg_out_bundle(s, miI,
1225 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1226 tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1227 TCG_REG_R2, arg1, arg1),
1228 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
1229 0x1f, arg2));
1230 tcg_out_bundle(s, mII,
1231 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1232 tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R3,
1233 0x20, TCG_REG_R3),
1234 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1235 TCG_REG_R2, TCG_REG_R3));
1236 }
1237 }
1238
1239 static inline void tcg_out_rotl_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1240 TCGArg arg2, int const_arg2)
1241 {
1242 if (const_arg2) {
1243 tcg_out_bundle(s, miI,
1244 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1245 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1246 tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1,
1247 arg1, 0x40 - arg2));
1248 } else {
1249 tcg_out_bundle(s, mII,
1250 tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2,
1251 0x40, arg2),
1252 tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R3,
1253 arg1, arg2),
1254 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R2,
1255 arg1, TCG_REG_R2));
1256 tcg_out_bundle(s, miI,
1257 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1258 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1259 tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret,
1260 TCG_REG_R2, TCG_REG_R3));
1261 }
1262 }
1263
1264 static inline void tcg_out_rotr_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1265 TCGArg arg2, int const_arg2)
1266 {
1267 if (const_arg2) {
1268 tcg_out_bundle(s, mII,
1269 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1270 tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1271 TCG_REG_R2, arg1, arg1),
1272 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1273 TCG_REG_R2, arg2, 31));
1274 } else {
1275 tcg_out_bundle(s, mII,
1276 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
1277 0x1f, arg2),
1278 tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1279 TCG_REG_R2, arg1, arg1),
1280 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1281 TCG_REG_R2, TCG_REG_R3));
1282 }
1283 }
1284
1285 static inline void tcg_out_rotr_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1286 TCGArg arg2, int const_arg2)
1287 {
1288 if (const_arg2) {
1289 tcg_out_bundle(s, miI,
1290 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1291 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1292 tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1,
1293 arg1, arg2));
1294 } else {
1295 tcg_out_bundle(s, mII,
1296 tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2,
1297 0x40, arg2),
1298 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R3,
1299 arg1, arg2),
1300 tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R2,
1301 arg1, TCG_REG_R2));
1302 tcg_out_bundle(s, miI,
1303 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1304 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1305 tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret,
1306 TCG_REG_R2, TCG_REG_R3));
1307 }
1308 }
1309
1310 static inline void tcg_out_ext(TCGContext *s, uint64_t opc_i29,
1311 TCGArg ret, TCGArg arg)
1312 {
1313 tcg_out_bundle(s, miI,
1314 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1315 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1316 tcg_opc_i29(TCG_REG_P0, opc_i29, ret, arg));
1317 }
1318
1319 static inline void tcg_out_bswap16(TCGContext *s, TCGArg ret, TCGArg arg)
1320 {
1321 tcg_out_bundle(s, mII,
1322 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1323 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 15, 15),
1324 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, ret, 0xb));
1325 }
1326
1327 static inline void tcg_out_bswap32(TCGContext *s, TCGArg ret, TCGArg arg)
1328 {
1329 tcg_out_bundle(s, mII,
1330 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1331 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 31, 31),
1332 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, ret, 0xb));
1333 }
1334
1335 static inline void tcg_out_bswap64(TCGContext *s, TCGArg ret, TCGArg arg)
1336 {
1337 tcg_out_bundle(s, miI,
1338 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1339 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1340 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, arg, 0xb));
1341 }
1342
1343 static inline void tcg_out_deposit(TCGContext *s, TCGArg ret, TCGArg a1,
1344 TCGArg a2, int const_a2, int pos, int len)
1345 {
1346 uint64_t i1 = 0, i2 = 0;
1347 int cpos = 63 - pos, lm1 = len - 1;
1348
1349 if (const_a2) {
1350 /* Truncate the value of a constant a2 to the width of the field. */
1351 int mask = (1u << len) - 1;
1352 a2 &= mask;
1353
1354 if (a2 == 0 || a2 == mask) {
1355 /* 1-bit signed constant inserted into register. */
1356 i2 = tcg_opc_i14(TCG_REG_P0, OPC_DEP_I14, ret, a2, a1, cpos, lm1);
1357 } else {
1358 /* Otherwise, load any constant into a temporary. Do this into
1359 the first I slot to help out with cross-unit delays. */
1360 i1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
1361 TCG_REG_R2, a2, TCG_REG_R0);
1362 a2 = TCG_REG_R2;
1363 }
1364 }
1365 if (i2 == 0) {
1366 i2 = tcg_opc_i15(TCG_REG_P0, OPC_DEP_I15, ret, a2, a1, cpos, lm1);
1367 }
1368 tcg_out_bundle(s, (i1 ? mII : miI),
1369 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1370 i1 ? i1 : tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1371 i2);
1372 }
1373
1374 static inline uint64_t tcg_opc_cmp_a(int qp, TCGCond cond, TCGArg arg1,
1375 TCGArg arg2, int cmp4)
1376 {
1377 uint64_t opc_eq_a6, opc_lt_a6, opc_ltu_a6;
1378
1379 if (cmp4) {
1380 opc_eq_a6 = OPC_CMP4_EQ_A6;
1381 opc_lt_a6 = OPC_CMP4_LT_A6;
1382 opc_ltu_a6 = OPC_CMP4_LTU_A6;
1383 } else {
1384 opc_eq_a6 = OPC_CMP_EQ_A6;
1385 opc_lt_a6 = OPC_CMP_LT_A6;
1386 opc_ltu_a6 = OPC_CMP_LTU_A6;
1387 }
1388
1389 switch (cond) {
1390 case TCG_COND_EQ:
1391 return tcg_opc_a6 (qp, opc_eq_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
1392 case TCG_COND_NE:
1393 return tcg_opc_a6 (qp, opc_eq_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
1394 case TCG_COND_LT:
1395 return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
1396 case TCG_COND_LTU:
1397 return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
1398 case TCG_COND_GE:
1399 return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
1400 case TCG_COND_GEU:
1401 return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
1402 case TCG_COND_LE:
1403 return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P7, TCG_REG_P6, arg2, arg1);
1404 case TCG_COND_LEU:
1405 return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg2, arg1);
1406 case TCG_COND_GT:
1407 return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P6, TCG_REG_P7, arg2, arg1);
1408 case TCG_COND_GTU:
1409 return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg2, arg1);
1410 default:
1411 tcg_abort();
1412 break;
1413 }
1414 }
1415
1416 static inline void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGArg arg1,
1417 int const_arg1, TCGArg arg2, int const_arg2,
1418 int label_index, int cmp4)
1419 {
1420 TCGLabel *l = &s->labels[label_index];
1421 uint64_t opc1, opc2;
1422
1423 if (const_arg1 && arg1 != 0) {
1424 opc1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R2,
1425 arg1, TCG_REG_R0);
1426 arg1 = TCG_REG_R2;
1427 } else {
1428 opc1 = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
1429 }
1430
1431 if (const_arg2 && arg2 != 0) {
1432 opc2 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R3,
1433 arg2, TCG_REG_R0);
1434 arg2 = TCG_REG_R3;
1435 } else {
1436 opc2 = tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0);
1437 }
1438
1439 tcg_out_bundle(s, mII,
1440 opc1,
1441 opc2,
1442 tcg_opc_cmp_a(TCG_REG_P0, cond, arg1, arg2, cmp4));
1443 tcg_out_bundle(s, mmB,
1444 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1445 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1446 tcg_opc_b1 (TCG_REG_P6, OPC_BR_DPTK_FEW_B1,
1447 get_reloc_pcrel21b(s->code_ptr + 2)));
1448
1449 if (l->has_value) {
1450 reloc_pcrel21b((s->code_ptr - 16) + 2, l->u.value);
1451 } else {
1452 tcg_out_reloc(s, (s->code_ptr - 16) + 2,
1453 R_IA64_PCREL21B, label_index, 0);
1454 }
1455 }
1456
1457 static inline void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGArg ret,
1458 TCGArg arg1, TCGArg arg2, int cmp4)
1459 {
1460 tcg_out_bundle(s, MmI,
1461 tcg_opc_cmp_a(TCG_REG_P0, cond, arg1, arg2, cmp4),
1462 tcg_opc_a5(TCG_REG_P6, OPC_ADDL_A5, ret, 1, TCG_REG_R0),
1463 tcg_opc_a5(TCG_REG_P7, OPC_ADDL_A5, ret, 0, TCG_REG_R0));
1464 }
1465
1466 static inline void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGArg ret,
1467 TCGArg c1, TCGArg c2,
1468 TCGArg v1, int const_v1,
1469 TCGArg v2, int const_v2, int cmp4)
1470 {
1471 uint64_t opc1, opc2;
1472
1473 if (const_v1) {
1474 opc1 = tcg_opc_a5(TCG_REG_P6, OPC_ADDL_A5, ret, v1, TCG_REG_R0);
1475 } else if (ret == v1) {
1476 opc1 = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
1477 } else {
1478 opc1 = tcg_opc_a4(TCG_REG_P6, OPC_ADDS_A4, ret, 0, v1);
1479 }
1480 if (const_v2) {
1481 opc2 = tcg_opc_a5(TCG_REG_P7, OPC_ADDL_A5, ret, v2, TCG_REG_R0);
1482 } else if (ret == v2) {
1483 opc2 = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
1484 } else {
1485 opc2 = tcg_opc_a4(TCG_REG_P7, OPC_ADDS_A4, ret, 0, v2);
1486 }
1487
1488 tcg_out_bundle(s, MmI,
1489 tcg_opc_cmp_a(TCG_REG_P0, cond, c1, c2, cmp4),
1490 opc1,
1491 opc2);
1492 }
1493
1494 #if defined(CONFIG_SOFTMMU)
1495 /* Load and compare a TLB entry, and return the result in (p6, p7).
1496 R2 is loaded with the address of the addend TLB entry.
1497 R57 is loaded with the address, zero extented on 32-bit targets. */
1498 static inline void tcg_out_qemu_tlb(TCGContext *s, TCGArg addr_reg,
1499 TCGMemOp s_bits, uint64_t offset_rw,
1500 uint64_t offset_addend)
1501 {
1502 tcg_out_bundle(s, mII,
1503 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1504 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, TCG_REG_R2,
1505 addr_reg, TARGET_PAGE_BITS, CPU_TLB_BITS - 1),
1506 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, TCG_REG_R2,
1507 TCG_REG_R2, 63 - CPU_TLB_ENTRY_BITS,
1508 63 - CPU_TLB_ENTRY_BITS));
1509 tcg_out_bundle(s, mII,
1510 tcg_opc_a5 (TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R2,
1511 offset_rw, TCG_REG_R2),
1512 #if TARGET_LONG_BITS == 32
1513 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R57, addr_reg),
1514 #else
1515 tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R57,
1516 0, addr_reg),
1517 #endif
1518 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1519 TCG_REG_R2, TCG_AREG0));
1520 tcg_out_bundle(s, mII,
1521 tcg_opc_m3 (TCG_REG_P0,
1522 (TARGET_LONG_BITS == 32
1523 ? OPC_LD4_M3 : OPC_LD8_M3), TCG_REG_R56,
1524 TCG_REG_R2, offset_addend - offset_rw),
1525 tcg_opc_i14(TCG_REG_P0, OPC_DEP_I14, TCG_REG_R3, 0,
1526 TCG_REG_R57, 63 - s_bits,
1527 TARGET_PAGE_BITS - s_bits - 1),
1528 tcg_opc_a6 (TCG_REG_P0, OPC_CMP_EQ_A6, TCG_REG_P6,
1529 TCG_REG_P7, TCG_REG_R3, TCG_REG_R56));
1530 }
1531
1532 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
1533 int mmu_idx) */
1534 static const void * const qemu_ld_helpers[4] = {
1535 helper_ldb_mmu,
1536 helper_ldw_mmu,
1537 helper_ldl_mmu,
1538 helper_ldq_mmu,
1539 };
1540
1541 static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
1542 TCGMemOp opc)
1543 {
1544 static const uint64_t opc_ld_m1[4] = {
1545 OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1
1546 };
1547 static const uint64_t opc_ext_i29[8] = {
1548 OPC_ZXT1_I29, OPC_ZXT2_I29, OPC_ZXT4_I29, 0,
1549 OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0
1550 };
1551 int addr_reg, data_reg, mem_index;
1552 TCGMemOp s_bits, bswap;
1553
1554 data_reg = *args++;
1555 addr_reg = *args++;
1556 mem_index = *args;
1557 s_bits = opc & MO_SIZE;
1558 bswap = opc & MO_BSWAP;
1559
1560 /* Read the TLB entry */
1561 tcg_out_qemu_tlb(s, addr_reg, s_bits,
1562 offsetof(CPUArchState, tlb_table[mem_index][0].addr_read),
1563 offsetof(CPUArchState, tlb_table[mem_index][0].addend));
1564
1565 /* P6 is the fast path, and P7 the slow path */
1566 tcg_out_bundle(s, mLX,
1567 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4,
1568 TCG_REG_R56, 0, TCG_AREG0),
1569 tcg_opc_l2 ((tcg_target_long) qemu_ld_helpers[s_bits]),
1570 tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2,
1571 (tcg_target_long) qemu_ld_helpers[s_bits]));
1572 tcg_out_bundle(s, MmI,
1573 tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3,
1574 TCG_REG_R2, 8),
1575 tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3,
1576 TCG_REG_R3, TCG_REG_R57),
1577 tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6,
1578 TCG_REG_R3, 0));
1579 if (bswap && s_bits == MO_16) {
1580 tcg_out_bundle(s, MmI,
1581 tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
1582 TCG_REG_R8, TCG_REG_R3),
1583 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
1584 tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1585 TCG_REG_R8, TCG_REG_R8, 15, 15));
1586 } else if (bswap && s_bits == MO_32) {
1587 tcg_out_bundle(s, MmI,
1588 tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
1589 TCG_REG_R8, TCG_REG_R3),
1590 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
1591 tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1592 TCG_REG_R8, TCG_REG_R8, 31, 31));
1593 } else {
1594 tcg_out_bundle(s, mmI,
1595 tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
1596 TCG_REG_R8, TCG_REG_R3),
1597 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
1598 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1599 }
1600 if (!bswap) {
1601 tcg_out_bundle(s, miB,
1602 tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58,
1603 mem_index, TCG_REG_R0),
1604 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1605 tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
1606 TCG_REG_B0, TCG_REG_B6));
1607 } else {
1608 tcg_out_bundle(s, miB,
1609 tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58,
1610 mem_index, TCG_REG_R0),
1611 tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1612 TCG_REG_R8, TCG_REG_R8, 0xb),
1613 tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
1614 TCG_REG_B0, TCG_REG_B6));
1615 }
1616
1617 if (s_bits == MO_64) {
1618 tcg_out_bundle(s, miI,
1619 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1620 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1621 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
1622 data_reg, 0, TCG_REG_R8));
1623 } else {
1624 tcg_out_bundle(s, miI,
1625 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1626 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1627 tcg_opc_i29(TCG_REG_P0, opc_ext_i29[opc & MO_SSIZE],
1628 data_reg, TCG_REG_R8));
1629 }
1630 }
1631
1632 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
1633 uintxx_t val, int mmu_idx) */
1634 static const void * const qemu_st_helpers[4] = {
1635 helper_stb_mmu,
1636 helper_stw_mmu,
1637 helper_stl_mmu,
1638 helper_stq_mmu,
1639 };
1640
1641 static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
1642 TCGMemOp opc)
1643 {
1644 static const uint64_t opc_st_m4[4] = {
1645 OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4
1646 };
1647 int addr_reg, data_reg, mem_index;
1648 TCGMemOp s_bits;
1649
1650 data_reg = *args++;
1651 addr_reg = *args++;
1652 mem_index = *args;
1653 s_bits = opc & MO_SIZE;
1654
1655 tcg_out_qemu_tlb(s, addr_reg, s_bits,
1656 offsetof(CPUArchState, tlb_table[mem_index][0].addr_write),
1657 offsetof(CPUArchState, tlb_table[mem_index][0].addend));
1658
1659 /* P6 is the fast path, and P7 the slow path */
1660 tcg_out_bundle(s, mLX,
1661 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4,
1662 TCG_REG_R56, 0, TCG_AREG0),
1663 tcg_opc_l2 ((tcg_target_long) qemu_st_helpers[s_bits]),
1664 tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2,
1665 (tcg_target_long) qemu_st_helpers[s_bits]));
1666 tcg_out_bundle(s, MmI,
1667 tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3,
1668 TCG_REG_R2, 8),
1669 tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3,
1670 TCG_REG_R3, TCG_REG_R57),
1671 tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6,
1672 TCG_REG_R3, 0));
1673
1674 switch (opc) {
1675 case MO_8:
1676 case MO_16:
1677 case MO_32:
1678 case MO_64:
1679 tcg_out_bundle(s, mii,
1680 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1681 TCG_REG_R1, TCG_REG_R2),
1682 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58,
1683 0, data_reg),
1684 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1685 break;
1686
1687 case MO_16 | MO_BSWAP:
1688 tcg_out_bundle(s, miI,
1689 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1690 TCG_REG_R1, TCG_REG_R2),
1691 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1692 tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1693 TCG_REG_R2, data_reg, 15, 15));
1694 tcg_out_bundle(s, miI,
1695 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58,
1696 0, data_reg),
1697 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1698 tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1699 TCG_REG_R2, TCG_REG_R2, 0xb));
1700 data_reg = TCG_REG_R2;
1701 break;
1702
1703 case MO_32 | MO_BSWAP:
1704 tcg_out_bundle(s, miI,
1705 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1706 TCG_REG_R1, TCG_REG_R2),
1707 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1708 tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1709 TCG_REG_R2, data_reg, 31, 31));
1710 tcg_out_bundle(s, miI,
1711 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58,
1712 0, data_reg),
1713 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1714 tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1715 TCG_REG_R2, TCG_REG_R2, 0xb));
1716 data_reg = TCG_REG_R2;
1717 break;
1718
1719 case MO_64 | MO_BSWAP:
1720 tcg_out_bundle(s, miI,
1721 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1722 TCG_REG_R1, TCG_REG_R2),
1723 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58,
1724 0, data_reg),
1725 tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1726 TCG_REG_R2, data_reg, 0xb));
1727 data_reg = TCG_REG_R2;
1728 break;
1729
1730 default:
1731 tcg_abort();
1732 }
1733
1734 tcg_out_bundle(s, miB,
1735 tcg_opc_m4 (TCG_REG_P6, opc_st_m4[s_bits],
1736 data_reg, TCG_REG_R3),
1737 tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R59,
1738 mem_index, TCG_REG_R0),
1739 tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
1740 TCG_REG_B0, TCG_REG_B6));
1741 }
1742
1743 #else /* !CONFIG_SOFTMMU */
1744
1745 static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
1746 TCGMemOp opc)
1747 {
1748 static uint64_t const opc_ld_m1[4] = {
1749 OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1
1750 };
1751 static uint64_t const opc_sxt_i29[4] = {
1752 OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0
1753 };
1754 int addr_reg, data_reg;
1755 TCGMemOp s_bits, bswap;
1756
1757 data_reg = *args++;
1758 addr_reg = *args++;
1759 s_bits = opc & MO_SIZE;
1760 bswap = opc & MO_BSWAP;
1761
1762 #if TARGET_LONG_BITS == 32
1763 if (GUEST_BASE != 0) {
1764 tcg_out_bundle(s, mII,
1765 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1766 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1767 TCG_REG_R3, addr_reg),
1768 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1769 TCG_GUEST_BASE_REG, TCG_REG_R3));
1770 } else {
1771 tcg_out_bundle(s, miI,
1772 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1773 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1774 TCG_REG_R2, addr_reg),
1775 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1776 }
1777
1778 if (!bswap) {
1779 if (!(opc & MO_SIGN)) {
1780 tcg_out_bundle(s, miI,
1781 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1782 data_reg, TCG_REG_R2),
1783 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1784 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1785 } else {
1786 tcg_out_bundle(s, mII,
1787 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1788 data_reg, TCG_REG_R2),
1789 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1790 tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits],
1791 data_reg, data_reg));
1792 }
1793 } else if (s_bits == MO_64) {
1794 tcg_out_bundle(s, mII,
1795 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1796 data_reg, TCG_REG_R2),
1797 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1798 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1799 data_reg, data_reg, 0xb));
1800 } else {
1801 if (s_bits == MO_16) {
1802 tcg_out_bundle(s, mII,
1803 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1804 data_reg, TCG_REG_R2),
1805 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1806 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1807 data_reg, data_reg, 15, 15));
1808 } else {
1809 tcg_out_bundle(s, mII,
1810 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1811 data_reg, TCG_REG_R2),
1812 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1813 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1814 data_reg, data_reg, 31, 31));
1815 }
1816 if (!(opc & MO_SIGN)) {
1817 tcg_out_bundle(s, miI,
1818 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1819 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1820 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1821 data_reg, data_reg, 0xb));
1822 } else {
1823 tcg_out_bundle(s, mII,
1824 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1825 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1826 data_reg, data_reg, 0xb),
1827 tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits],
1828 data_reg, data_reg));
1829 }
1830 }
1831 #else
1832 if (GUEST_BASE != 0) {
1833 tcg_out_bundle(s, MmI,
1834 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1835 TCG_GUEST_BASE_REG, addr_reg),
1836 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1837 data_reg, TCG_REG_R2),
1838 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1839 } else {
1840 tcg_out_bundle(s, mmI,
1841 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1842 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1843 data_reg, addr_reg),
1844 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1845 }
1846
1847 if (bswap && s_bits == MO_16) {
1848 tcg_out_bundle(s, mII,
1849 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1850 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1851 data_reg, data_reg, 15, 15),
1852 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1853 data_reg, data_reg, 0xb));
1854 } else if (bswap && s_bits == MO_32) {
1855 tcg_out_bundle(s, mII,
1856 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1857 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1858 data_reg, data_reg, 31, 31),
1859 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1860 data_reg, data_reg, 0xb));
1861 } else if (bswap && s_bits == MO_64) {
1862 tcg_out_bundle(s, miI,
1863 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1864 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1865 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1866 data_reg, data_reg, 0xb));
1867 }
1868 if (opc & MO_SIGN) {
1869 tcg_out_bundle(s, miI,
1870 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1871 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1872 tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits],
1873 data_reg, data_reg));
1874 }
1875 #endif
1876 }
1877
1878 static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
1879 TCGMemOp opc)
1880 {
1881 static uint64_t const opc_st_m4[4] = {
1882 OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4
1883 };
1884 int addr_reg, data_reg;
1885 #if TARGET_LONG_BITS == 64
1886 uint64_t add_guest_base;
1887 #endif
1888 TCGMemOp s_bits, bswap;
1889
1890 data_reg = *args++;
1891 addr_reg = *args++;
1892 s_bits = opc & MO_SIZE;
1893 bswap = opc & MO_BSWAP;
1894
1895 #if TARGET_LONG_BITS == 32
1896 if (GUEST_BASE != 0) {
1897 tcg_out_bundle(s, mII,
1898 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1899 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1900 TCG_REG_R3, addr_reg),
1901 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1902 TCG_GUEST_BASE_REG, TCG_REG_R3));
1903 } else {
1904 tcg_out_bundle(s, miI,
1905 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1906 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1907 TCG_REG_R2, addr_reg),
1908 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1909 }
1910
1911 if (bswap) {
1912 if (s_bits == MO_16) {
1913 tcg_out_bundle(s, mII,
1914 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1915 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1916 TCG_REG_R3, data_reg, 15, 15),
1917 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1918 TCG_REG_R3, TCG_REG_R3, 0xb));
1919 data_reg = TCG_REG_R3;
1920 } else if (s_bits == MO_32) {
1921 tcg_out_bundle(s, mII,
1922 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1923 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1924 TCG_REG_R3, data_reg, 31, 31),
1925 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1926 TCG_REG_R3, TCG_REG_R3, 0xb));
1927 data_reg = TCG_REG_R3;
1928 } else if (s_bits == MO_64) {
1929 tcg_out_bundle(s, miI,
1930 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1931 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1932 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1933 TCG_REG_R3, data_reg, 0xb));
1934 data_reg = TCG_REG_R3;
1935 }
1936 }
1937 tcg_out_bundle(s, mmI,
1938 tcg_opc_m4 (TCG_REG_P0, opc_st_m4[s_bits],
1939 data_reg, TCG_REG_R2),
1940 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1941 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1942 #else
1943 if (GUEST_BASE != 0) {
1944 add_guest_base = tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1945 TCG_GUEST_BASE_REG, addr_reg);
1946 addr_reg = TCG_REG_R2;
1947 } else {
1948 add_guest_base = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
1949 }
1950
1951 if (!bswap) {
1952 tcg_out_bundle(s, (GUEST_BASE ? MmI : mmI),
1953 add_guest_base,
1954 tcg_opc_m4 (TCG_REG_P0, opc_st_m4[s_bits],
1955 data_reg, addr_reg),
1956 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1957 } else {
1958 if (s_bits == MO_16) {
1959 tcg_out_bundle(s, mII,
1960 add_guest_base,
1961 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1962 TCG_REG_R3, data_reg, 15, 15),
1963 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1964 TCG_REG_R3, TCG_REG_R3, 0xb));
1965 data_reg = TCG_REG_R3;
1966 } else if (s_bits == MO_32) {
1967 tcg_out_bundle(s, mII,
1968 add_guest_base,
1969 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1970 TCG_REG_R3, data_reg, 31, 31),
1971 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1972 TCG_REG_R3, TCG_REG_R3, 0xb));
1973 data_reg = TCG_REG_R3;
1974 } else if (s_bits == MO_64) {
1975 tcg_out_bundle(s, miI,
1976 add_guest_base,
1977 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1978 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1979 TCG_REG_R3, data_reg, 0xb));
1980 data_reg = TCG_REG_R3;
1981 }
1982 tcg_out_bundle(s, miI,
1983 tcg_opc_m4 (TCG_REG_P0, opc_st_m4[s_bits],
1984 data_reg, addr_reg),
1985 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1986 tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1987 }
1988 #endif
1989 }
1990
1991 #endif
1992
1993 static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
1994 const TCGArg *args, const int *const_args)
1995 {
1996 switch(opc) {
1997 case INDEX_op_exit_tb:
1998 tcg_out_exit_tb(s, args[0]);
1999 break;
2000 case INDEX_op_br:
2001 tcg_out_br(s, args[0]);
2002 break;
2003 case INDEX_op_call:
2004 tcg_out_call(s, args[0]);
2005 break;
2006 case INDEX_op_goto_tb:
2007 tcg_out_goto_tb(s, args[0]);
2008 break;
2009
2010 case INDEX_op_movi_i32:
2011 tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
2012 break;
2013 case INDEX_op_movi_i64:
2014 tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
2015 break;
2016
2017 case INDEX_op_ld8u_i32:
2018 case INDEX_op_ld8u_i64:
2019 tcg_out_ld_rel(s, OPC_LD1_M1, args[0], args[1], args[2]);
2020 break;
2021 case INDEX_op_ld8s_i32:
2022 case INDEX_op_ld8s_i64:
2023 tcg_out_ld_rel(s, OPC_LD1_M1, args[0], args[1], args[2]);
2024 tcg_out_ext(s, OPC_SXT1_I29, args[0], args[0]);
2025 break;
2026 case INDEX_op_ld16u_i32:
2027 case INDEX_op_ld16u_i64:
2028 tcg_out_ld_rel(s, OPC_LD2_M1, args[0], args[1], args[2]);
2029 break;
2030 case INDEX_op_ld16s_i32:
2031 case INDEX_op_ld16s_i64:
2032 tcg_out_ld_rel(s, OPC_LD2_M1, args[0], args[1], args[2]);
2033 tcg_out_ext(s, OPC_SXT2_I29, args[0], args[0]);
2034 break;
2035 case INDEX_op_ld_i32:
2036 case INDEX_op_ld32u_i64:
2037 tcg_out_ld_rel(s, OPC_LD4_M1, args[0], args[1], args[2]);
2038 break;
2039 case INDEX_op_ld32s_i64:
2040 tcg_out_ld_rel(s, OPC_LD4_M1, args[0], args[1], args[2]);
2041 tcg_out_ext(s, OPC_SXT4_I29, args[0], args[0]);
2042 break;
2043 case INDEX_op_ld_i64:
2044 tcg_out_ld_rel(s, OPC_LD8_M1, args[0], args[1], args[2]);
2045 break;
2046 case INDEX_op_st8_i32:
2047 case INDEX_op_st8_i64:
2048 tcg_out_st_rel(s, OPC_ST1_M4, args[0], args[1], args[2]);
2049 break;
2050 case INDEX_op_st16_i32:
2051 case INDEX_op_st16_i64:
2052 tcg_out_st_rel(s, OPC_ST2_M4, args[0], args[1], args[2]);
2053 break;
2054 case INDEX_op_st_i32:
2055 case INDEX_op_st32_i64:
2056 tcg_out_st_rel(s, OPC_ST4_M4, args[0], args[1], args[2]);
2057 break;
2058 case INDEX_op_st_i64:
2059 tcg_out_st_rel(s, OPC_ST8_M4, args[0], args[1], args[2]);
2060 break;
2061
2062 case INDEX_op_add_i32:
2063 case INDEX_op_add_i64:
2064 tcg_out_alu(s, OPC_ADD_A1, args[0], args[1], const_args[1],
2065 args[2], const_args[2]);
2066 break;
2067 case INDEX_op_sub_i32:
2068 case INDEX_op_sub_i64:
2069 tcg_out_alu(s, OPC_SUB_A1, args[0], args[1], const_args[1],
2070 args[2], const_args[2]);
2071 break;
2072
2073 case INDEX_op_and_i32:
2074 case INDEX_op_and_i64:
2075 tcg_out_alu(s, OPC_AND_A1, args[0], args[1], const_args[1],
2076 args[2], const_args[2]);
2077 break;
2078 case INDEX_op_andc_i32:
2079 case INDEX_op_andc_i64:
2080 tcg_out_alu(s, OPC_ANDCM_A1, args[0], args[1], const_args[1],
2081 args[2], const_args[2]);
2082 break;
2083 case INDEX_op_eqv_i32:
2084 case INDEX_op_eqv_i64:
2085 tcg_out_eqv(s, args[0], args[1], const_args[1],
2086 args[2], const_args[2]);
2087 break;
2088 case INDEX_op_nand_i32:
2089 case INDEX_op_nand_i64:
2090 tcg_out_nand(s, args[0], args[1], const_args[1],
2091 args[2], const_args[2]);
2092 break;
2093 case INDEX_op_nor_i32:
2094 case INDEX_op_nor_i64:
2095 tcg_out_nor(s, args[0], args[1], const_args[1],
2096 args[2], const_args[2]);
2097 break;
2098 case INDEX_op_or_i32:
2099 case INDEX_op_or_i64:
2100 tcg_out_alu(s, OPC_OR_A1, args[0], args[1], const_args[1],
2101 args[2], const_args[2]);
2102 break;
2103 case INDEX_op_orc_i32:
2104 case INDEX_op_orc_i64:
2105 tcg_out_orc(s, args[0], args[1], const_args[1],
2106 args[2], const_args[2]);
2107 break;
2108 case INDEX_op_xor_i32:
2109 case INDEX_op_xor_i64:
2110 tcg_out_alu(s, OPC_XOR_A1, args[0], args[1], const_args[1],
2111 args[2], const_args[2]);
2112 break;
2113
2114 case INDEX_op_mul_i32:
2115 case INDEX_op_mul_i64:
2116 tcg_out_mul(s, args[0], args[1], args[2]);
2117 break;
2118
2119 case INDEX_op_sar_i32:
2120 tcg_out_sar_i32(s, args[0], args[1], args[2], const_args[2]);
2121 break;
2122 case INDEX_op_sar_i64:
2123 tcg_out_sar_i64(s, args[0], args[1], args[2], const_args[2]);
2124 break;
2125 case INDEX_op_shl_i32:
2126 tcg_out_shl_i32(s, args[0], args[1], args[2], const_args[2]);
2127 break;
2128 case INDEX_op_shl_i64:
2129 tcg_out_shl_i64(s, args[0], args[1], args[2], const_args[2]);
2130 break;
2131 case INDEX_op_shr_i32:
2132 tcg_out_shr_i32(s, args[0], args[1], args[2], const_args[2]);
2133 break;
2134 case INDEX_op_shr_i64:
2135 tcg_out_shr_i64(s, args[0], args[1], args[2], const_args[2]);
2136 break;
2137 case INDEX_op_rotl_i32:
2138 tcg_out_rotl_i32(s, args[0], args[1], args[2], const_args[2]);
2139 break;
2140 case INDEX_op_rotl_i64:
2141 tcg_out_rotl_i64(s, args[0], args[1], args[2], const_args[2]);
2142 break;
2143 case INDEX_op_rotr_i32:
2144 tcg_out_rotr_i32(s, args[0], args[1], args[2], const_args[2]);
2145 break;
2146 case INDEX_op_rotr_i64:
2147 tcg_out_rotr_i64(s, args[0], args[1], args[2], const_args[2]);
2148 break;
2149
2150 case INDEX_op_ext8s_i32:
2151 case INDEX_op_ext8s_i64:
2152 tcg_out_ext(s, OPC_SXT1_I29, args[0], args[1]);
2153 break;
2154 case INDEX_op_ext8u_i32:
2155 case INDEX_op_ext8u_i64:
2156 tcg_out_ext(s, OPC_ZXT1_I29, args[0], args[1]);
2157 break;
2158 case INDEX_op_ext16s_i32:
2159 case INDEX_op_ext16s_i64:
2160 tcg_out_ext(s, OPC_SXT2_I29, args[0], args[1]);
2161 break;
2162 case INDEX_op_ext16u_i32:
2163 case INDEX_op_ext16u_i64:
2164 tcg_out_ext(s, OPC_ZXT2_I29, args[0], args[1]);
2165 break;
2166 case INDEX_op_ext32s_i64:
2167 tcg_out_ext(s, OPC_SXT4_I29, args[0], args[1]);
2168 break;
2169 case INDEX_op_ext32u_i64:
2170 tcg_out_ext(s, OPC_ZXT4_I29, args[0], args[1]);
2171 break;
2172
2173 case INDEX_op_bswap16_i32:
2174 case INDEX_op_bswap16_i64:
2175 tcg_out_bswap16(s, args[0], args[1]);
2176 break;
2177 case INDEX_op_bswap32_i32:
2178 case INDEX_op_bswap32_i64:
2179 tcg_out_bswap32(s, args[0], args[1]);
2180 break;
2181 case INDEX_op_bswap64_i64:
2182 tcg_out_bswap64(s, args[0], args[1]);
2183 break;
2184
2185 case INDEX_op_deposit_i32:
2186 case INDEX_op_deposit_i64:
2187 tcg_out_deposit(s, args[0], args[1], args[2], const_args[2],
2188 args[3], args[4]);
2189 break;
2190
2191 case INDEX_op_brcond_i32:
2192 tcg_out_brcond(s, args[2], args[0], const_args[0],
2193 args[1], const_args[1], args[3], 1);
2194 break;
2195 case INDEX_op_brcond_i64:
2196 tcg_out_brcond(s, args[2], args[0], const_args[0],
2197 args[1], const_args[1], args[3], 0);
2198 break;
2199 case INDEX_op_setcond_i32:
2200 tcg_out_setcond(s, args[3], args[0], args[1], args[2], 1);
2201 break;
2202 case INDEX_op_setcond_i64:
2203 tcg_out_setcond(s, args[3], args[0], args[1], args[2], 0);
2204 break;
2205 case INDEX_op_movcond_i32:
2206 tcg_out_movcond(s, args[5], args[0], args[1], args[2],
2207 args[3], const_args[3], args[4], const_args[4], 1);
2208 break;
2209 case INDEX_op_movcond_i64:
2210 tcg_out_movcond(s, args[5], args[0], args[1], args[2],
2211 args[3], const_args[3], args[4], const_args[4], 0);
2212 break;
2213
2214 case INDEX_op_qemu_ld8u:
2215 tcg_out_qemu_ld(s, args, MO_UB);
2216 break;
2217 case INDEX_op_qemu_ld8s:
2218 tcg_out_qemu_ld(s, args, MO_SB);
2219 break;
2220 case INDEX_op_qemu_ld16u:
2221 tcg_out_qemu_ld(s, args, MO_TEUW);
2222 break;
2223 case INDEX_op_qemu_ld16s:
2224 tcg_out_qemu_ld(s, args, MO_TESW);
2225 break;
2226 case INDEX_op_qemu_ld32:
2227 case INDEX_op_qemu_ld32u:
2228 tcg_out_qemu_ld(s, args, MO_TEUL);
2229 break;
2230 case INDEX_op_qemu_ld32s:
2231 tcg_out_qemu_ld(s, args, MO_TESL);
2232 break;
2233 case INDEX_op_qemu_ld64:
2234 tcg_out_qemu_ld(s, args, MO_TEQ);
2235 break;
2236
2237 case INDEX_op_qemu_st8:
2238 tcg_out_qemu_st(s, args, MO_UB);
2239 break;
2240 case INDEX_op_qemu_st16:
2241 tcg_out_qemu_st(s, args, MO_TEUW);
2242 break;
2243 case INDEX_op_qemu_st32:
2244 tcg_out_qemu_st(s, args, MO_TEUL);
2245 break;
2246 case INDEX_op_qemu_st64:
2247 tcg_out_qemu_st(s, args, MO_TEQ);
2248 break;
2249
2250 default:
2251 tcg_abort();
2252 }
2253 }
2254
2255 static const TCGTargetOpDef ia64_op_defs[] = {
2256 { INDEX_op_br, { } },
2257 { INDEX_op_call, { "r" } },
2258 { INDEX_op_exit_tb, { } },
2259 { INDEX_op_goto_tb, { } },
2260
2261 { INDEX_op_mov_i32, { "r", "r" } },
2262 { INDEX_op_movi_i32, { "r" } },
2263
2264 { INDEX_op_ld8u_i32, { "r", "r" } },
2265 { INDEX_op_ld8s_i32, { "r", "r" } },
2266 { INDEX_op_ld16u_i32, { "r", "r" } },
2267 { INDEX_op_ld16s_i32, { "r", "r" } },
2268 { INDEX_op_ld_i32, { "r", "r" } },
2269 { INDEX_op_st8_i32, { "rZ", "r" } },
2270 { INDEX_op_st16_i32, { "rZ", "r" } },
2271 { INDEX_op_st_i32, { "rZ", "r" } },
2272
2273 { INDEX_op_add_i32, { "r", "rI", "rI" } },
2274 { INDEX_op_sub_i32, { "r", "rI", "rI" } },
2275
2276 { INDEX_op_and_i32, { "r", "rI", "rI" } },
2277 { INDEX_op_andc_i32, { "r", "rI", "rI" } },
2278 { INDEX_op_eqv_i32, { "r", "rZ", "rZ" } },
2279 { INDEX_op_nand_i32, { "r", "rZ", "rZ" } },
2280 { INDEX_op_nor_i32, { "r", "rZ", "rZ" } },
2281 { INDEX_op_or_i32, { "r", "rI", "rI" } },
2282 { INDEX_op_orc_i32, { "r", "rZ", "rZ" } },
2283 { INDEX_op_xor_i32, { "r", "rI", "rI" } },
2284
2285 { INDEX_op_mul_i32, { "r", "rZ", "rZ" } },
2286
2287 { INDEX_op_sar_i32, { "r", "rZ", "ri" } },
2288 { INDEX_op_shl_i32, { "r", "rZ", "ri" } },
2289 { INDEX_op_shr_i32, { "r", "rZ", "ri" } },
2290 { INDEX_op_rotl_i32, { "r", "rZ", "ri" } },
2291 { INDEX_op_rotr_i32, { "r", "rZ", "ri" } },
2292
2293 { INDEX_op_ext8s_i32, { "r", "rZ"} },
2294 { INDEX_op_ext8u_i32, { "r", "rZ"} },
2295 { INDEX_op_ext16s_i32, { "r", "rZ"} },
2296 { INDEX_op_ext16u_i32, { "r", "rZ"} },
2297
2298 { INDEX_op_bswap16_i32, { "r", "rZ" } },
2299 { INDEX_op_bswap32_i32, { "r", "rZ" } },
2300
2301 { INDEX_op_brcond_i32, { "rI", "rI" } },
2302 { INDEX_op_setcond_i32, { "r", "rZ", "rZ" } },
2303 { INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rI", "rI" } },
2304
2305 { INDEX_op_mov_i64, { "r", "r" } },
2306 { INDEX_op_movi_i64, { "r" } },
2307
2308 { INDEX_op_ld8u_i64, { "r", "r" } },
2309 { INDEX_op_ld8s_i64, { "r", "r" } },
2310 { INDEX_op_ld16u_i64, { "r", "r" } },
2311 { INDEX_op_ld16s_i64, { "r", "r" } },
2312 { INDEX_op_ld32u_i64, { "r", "r" } },
2313 { INDEX_op_ld32s_i64, { "r", "r" } },
2314 { INDEX_op_ld_i64, { "r", "r" } },
2315 { INDEX_op_st8_i64, { "rZ", "r" } },
2316 { INDEX_op_st16_i64, { "rZ", "r" } },
2317 { INDEX_op_st32_i64, { "rZ", "r" } },
2318 { INDEX_op_st_i64, { "rZ", "r" } },
2319
2320 { INDEX_op_add_i64, { "r", "rI", "rI" } },
2321 { INDEX_op_sub_i64, { "r", "rI", "rI" } },
2322
2323 { INDEX_op_and_i64, { "r", "rI", "rI" } },
2324 { INDEX_op_andc_i64, { "r", "rI", "rI" } },
2325 { INDEX_op_eqv_i64, { "r", "rZ", "rZ" } },
2326 { INDEX_op_nand_i64, { "r", "rZ", "rZ" } },
2327 { INDEX_op_nor_i64, { "r", "rZ", "rZ" } },
2328 { INDEX_op_or_i64, { "r", "rI", "rI" } },
2329 { INDEX_op_orc_i64, { "r", "rZ", "rZ" } },
2330 { INDEX_op_xor_i64, { "r", "rI", "rI" } },
2331
2332 { INDEX_op_mul_i64, { "r", "rZ", "rZ" } },
2333
2334 { INDEX_op_sar_i64, { "r", "rZ", "ri" } },
2335 { INDEX_op_shl_i64, { "r", "rZ", "ri" } },
2336 { INDEX_op_shr_i64, { "r", "rZ", "ri" } },
2337 { INDEX_op_rotl_i64, { "r", "rZ", "ri" } },
2338 { INDEX_op_rotr_i64, { "r", "rZ", "ri" } },
2339
2340 { INDEX_op_ext8s_i64, { "r", "rZ"} },
2341 { INDEX_op_ext8u_i64, { "r", "rZ"} },
2342 { INDEX_op_ext16s_i64, { "r", "rZ"} },
2343 { INDEX_op_ext16u_i64, { "r", "rZ"} },
2344 { INDEX_op_ext32s_i64, { "r", "rZ"} },
2345 { INDEX_op_ext32u_i64, { "r", "rZ"} },
2346
2347 { INDEX_op_bswap16_i64, { "r", "rZ" } },
2348 { INDEX_op_bswap32_i64, { "r", "rZ" } },
2349 { INDEX_op_bswap64_i64, { "r", "rZ" } },
2350
2351 { INDEX_op_brcond_i64, { "rI", "rI" } },
2352 { INDEX_op_setcond_i64, { "r", "rZ", "rZ" } },
2353 { INDEX_op_movcond_i64, { "r", "rZ", "rZ", "rI", "rI" } },
2354
2355 { INDEX_op_deposit_i32, { "r", "rZ", "ri" } },
2356 { INDEX_op_deposit_i64, { "r", "rZ", "ri" } },
2357
2358 { INDEX_op_qemu_ld8u, { "r", "r" } },
2359 { INDEX_op_qemu_ld8s, { "r", "r" } },
2360 { INDEX_op_qemu_ld16u, { "r", "r" } },
2361 { INDEX_op_qemu_ld16s, { "r", "r" } },
2362 { INDEX_op_qemu_ld32, { "r", "r" } },
2363 { INDEX_op_qemu_ld32u, { "r", "r" } },
2364 { INDEX_op_qemu_ld32s, { "r", "r" } },
2365 { INDEX_op_qemu_ld64, { "r", "r" } },
2366
2367 { INDEX_op_qemu_st8, { "SZ", "r" } },
2368 { INDEX_op_qemu_st16, { "SZ", "r" } },
2369 { INDEX_op_qemu_st32, { "SZ", "r" } },
2370 { INDEX_op_qemu_st64, { "SZ", "r" } },
2371
2372 { -1 },
2373 };
2374
2375 /* Generate global QEMU prologue and epilogue code */
2376 static void tcg_target_qemu_prologue(TCGContext *s)
2377 {
2378 int frame_size;
2379
2380 /* reserve some stack space */
2381 frame_size = TCG_STATIC_CALL_ARGS_SIZE +
2382 CPU_TEMP_BUF_NLONGS * sizeof(long);
2383 frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
2384 ~(TCG_TARGET_STACK_ALIGN - 1);
2385 tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE,
2386 CPU_TEMP_BUF_NLONGS * sizeof(long));
2387
2388 /* First emit adhoc function descriptor */
2389 *(uint64_t *)(s->code_ptr) = (uint64_t)s->code_ptr + 16; /* entry point */
2390 s->code_ptr += 16; /* skip GP */
2391
2392 /* prologue */
2393 tcg_out_bundle(s, miI,
2394 tcg_opc_m34(TCG_REG_P0, OPC_ALLOC_M34,
2395 TCG_REG_R34, 32, 24, 0),
2396 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
2397 TCG_AREG0, 0, TCG_REG_R32),
2398 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
2399 TCG_REG_B6, TCG_REG_R33, 0));
2400
2401 /* ??? If GUEST_BASE < 0x200000, we could load the register via
2402 an ADDL in the M slot of the next bundle. */
2403 if (GUEST_BASE != 0) {
2404 tcg_out_bundle(s, mlx,
2405 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
2406 tcg_opc_l2 (GUEST_BASE),
2407 tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2,
2408 TCG_GUEST_BASE_REG, GUEST_BASE));
2409 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2410 }
2411
2412 tcg_out_bundle(s, miB,
2413 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
2414 TCG_REG_R12, -frame_size, TCG_REG_R12),
2415 tcg_opc_i22(TCG_REG_P0, OPC_MOV_I22,
2416 TCG_REG_R32, TCG_REG_B0),
2417 tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6));
2418
2419 /* epilogue */
2420 tb_ret_addr = s->code_ptr;
2421 tcg_out_bundle(s, miI,
2422 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
2423 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
2424 TCG_REG_B0, TCG_REG_R32, 0),
2425 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
2426 TCG_REG_R12, frame_size, TCG_REG_R12));
2427 tcg_out_bundle(s, miB,
2428 tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
2429 tcg_opc_i26(TCG_REG_P0, OPC_MOV_I_I26,
2430 TCG_REG_PFS, TCG_REG_R34),
2431 tcg_opc_b4 (TCG_REG_P0, OPC_BR_RET_SPTK_MANY_B4,
2432 TCG_REG_B0));
2433 }
2434
2435 static void tcg_target_init(TCGContext *s)
2436 {
2437 tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I32],
2438 0xffffffffffffffffull);
2439 tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I64],
2440 0xffffffffffffffffull);
2441
2442 tcg_regset_clear(tcg_target_call_clobber_regs);
2443 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8);
2444 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9);
2445 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10);
2446 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11);
2447 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);
2448 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R15);
2449 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R16);
2450 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R17);
2451 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R18);
2452 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R19);
2453 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R20);
2454 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R21);
2455 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R22);
2456 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R23);
2457 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R24);
2458 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R25);
2459 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R26);
2460 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R27);
2461 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R28);
2462 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R29);
2463 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R30);
2464 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R31);
2465 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R56);
2466 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R57);
2467 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R58);
2468 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R59);
2469 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R60);
2470 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R61);
2471 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R62);
2472 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R63);
2473
2474 tcg_regset_clear(s->reserved_regs);
2475 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* zero register */
2476 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* global pointer */
2477 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* internal use */
2478 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R3); /* internal use */
2479 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R12); /* stack pointer */
2480 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
2481 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R32); /* return address */
2482 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R34); /* PFS */
2483
2484 /* The following 3 are not in use, are call-saved, but *not* saved
2485 by the prologue. Therefore we cannot use them without modifying
2486 the prologue. There doesn't seem to be any good reason to use
2487 these as opposed to the windowed registers. */
2488 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R4);
2489 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R5);
2490 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R6);
2491
2492 tcg_add_target_add_op_defs(ia64_op_defs);
2493 }
Qemu copy for testing