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tcg-ia64: Use SUB_A3 and ADDS_A4 for subtraction
[qemu.git] / tcg / ia64 / tcg-target.c
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2009-2010 Aurelien Jarno <aurelien@aurel32.net>
5 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 #include "tcg-be-null.h"
27
28 /*
29 * Register definitions
30 */
31
32 #ifndef NDEBUG
33 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
34 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
35 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
36 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
37 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
38 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
39 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
40 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
41 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
42 };
43 #endif
44
45 #ifdef CONFIG_USE_GUEST_BASE
46 #define TCG_GUEST_BASE_REG TCG_REG_R55
47 #else
48 #define TCG_GUEST_BASE_REG TCG_REG_R0
49 #endif
50 #ifndef GUEST_BASE
51 #define GUEST_BASE 0
52 #endif
53
54 /* Branch registers */
55 enum {
56 TCG_REG_B0 = 0,
57 TCG_REG_B1,
58 TCG_REG_B2,
59 TCG_REG_B3,
60 TCG_REG_B4,
61 TCG_REG_B5,
62 TCG_REG_B6,
63 TCG_REG_B7,
64 };
65
66 /* Floating point registers */
67 enum {
68 TCG_REG_F0 = 0,
69 TCG_REG_F1,
70 TCG_REG_F2,
71 TCG_REG_F3,
72 TCG_REG_F4,
73 TCG_REG_F5,
74 TCG_REG_F6,
75 TCG_REG_F7,
76 TCG_REG_F8,
77 TCG_REG_F9,
78 TCG_REG_F10,
79 TCG_REG_F11,
80 TCG_REG_F12,
81 TCG_REG_F13,
82 TCG_REG_F14,
83 TCG_REG_F15,
84 };
85
86 /* Predicate registers */
87 enum {
88 TCG_REG_P0 = 0,
89 TCG_REG_P1,
90 TCG_REG_P2,
91 TCG_REG_P3,
92 TCG_REG_P4,
93 TCG_REG_P5,
94 TCG_REG_P6,
95 TCG_REG_P7,
96 TCG_REG_P8,
97 TCG_REG_P9,
98 TCG_REG_P10,
99 TCG_REG_P11,
100 TCG_REG_P12,
101 TCG_REG_P13,
102 TCG_REG_P14,
103 TCG_REG_P15,
104 };
105
106 /* Application registers */
107 enum {
108 TCG_REG_PFS = 64,
109 };
110
111 static const int tcg_target_reg_alloc_order[] = {
112 TCG_REG_R35,
113 TCG_REG_R36,
114 TCG_REG_R37,
115 TCG_REG_R38,
116 TCG_REG_R39,
117 TCG_REG_R40,
118 TCG_REG_R41,
119 TCG_REG_R42,
120 TCG_REG_R43,
121 TCG_REG_R44,
122 TCG_REG_R45,
123 TCG_REG_R46,
124 TCG_REG_R47,
125 TCG_REG_R48,
126 TCG_REG_R49,
127 TCG_REG_R50,
128 TCG_REG_R51,
129 TCG_REG_R52,
130 TCG_REG_R53,
131 TCG_REG_R54,
132 TCG_REG_R55,
133 TCG_REG_R14,
134 TCG_REG_R15,
135 TCG_REG_R16,
136 TCG_REG_R17,
137 TCG_REG_R18,
138 TCG_REG_R19,
139 TCG_REG_R20,
140 TCG_REG_R21,
141 TCG_REG_R22,
142 TCG_REG_R23,
143 TCG_REG_R24,
144 TCG_REG_R25,
145 TCG_REG_R26,
146 TCG_REG_R27,
147 TCG_REG_R28,
148 TCG_REG_R29,
149 TCG_REG_R30,
150 TCG_REG_R31,
151 TCG_REG_R56,
152 TCG_REG_R57,
153 TCG_REG_R58,
154 TCG_REG_R59,
155 TCG_REG_R60,
156 TCG_REG_R61,
157 TCG_REG_R62,
158 TCG_REG_R63,
159 TCG_REG_R8,
160 TCG_REG_R9,
161 TCG_REG_R10,
162 TCG_REG_R11
163 };
164
165 static const int tcg_target_call_iarg_regs[8] = {
166 TCG_REG_R56,
167 TCG_REG_R57,
168 TCG_REG_R58,
169 TCG_REG_R59,
170 TCG_REG_R60,
171 TCG_REG_R61,
172 TCG_REG_R62,
173 TCG_REG_R63,
174 };
175
176 static const int tcg_target_call_oarg_regs[] = {
177 TCG_REG_R8
178 };
179
180 /*
181 * opcode formation
182 */
183
184 /* bundle templates: stops (double bar in the IA64 manual) are marked with
185 an uppercase letter. */
186 enum {
187 mii = 0x00,
188 miI = 0x01,
189 mIi = 0x02,
190 mII = 0x03,
191 mlx = 0x04,
192 mLX = 0x05,
193 mmi = 0x08,
194 mmI = 0x09,
195 Mmi = 0x0a,
196 MmI = 0x0b,
197 mfi = 0x0c,
198 mfI = 0x0d,
199 mmf = 0x0e,
200 mmF = 0x0f,
201 mib = 0x10,
202 miB = 0x11,
203 mbb = 0x12,
204 mbB = 0x13,
205 bbb = 0x16,
206 bbB = 0x17,
207 mmb = 0x18,
208 mmB = 0x19,
209 mfb = 0x1c,
210 mfB = 0x1d,
211 };
212
213 enum {
214 OPC_ADD_A1 = 0x10000000000ull,
215 OPC_AND_A1 = 0x10060000000ull,
216 OPC_AND_A3 = 0x10160000000ull,
217 OPC_ANDCM_A1 = 0x10068000000ull,
218 OPC_ANDCM_A3 = 0x10168000000ull,
219 OPC_ADDS_A4 = 0x10800000000ull,
220 OPC_ADDL_A5 = 0x12000000000ull,
221 OPC_ALLOC_M34 = 0x02c00000000ull,
222 OPC_BR_DPTK_FEW_B1 = 0x08400000000ull,
223 OPC_BR_SPTK_MANY_B1 = 0x08000001000ull,
224 OPC_BR_SPTK_MANY_B4 = 0x00100001000ull,
225 OPC_BR_CALL_SPTK_MANY_B5 = 0x02100001000ull,
226 OPC_BR_RET_SPTK_MANY_B4 = 0x00108001100ull,
227 OPC_BRL_SPTK_MANY_X3 = 0x18000001000ull,
228 OPC_BRL_CALL_SPTK_MANY_X4 = 0x1a000001000ull,
229 OPC_CMP_LT_A6 = 0x18000000000ull,
230 OPC_CMP_LTU_A6 = 0x1a000000000ull,
231 OPC_CMP_EQ_A6 = 0x1c000000000ull,
232 OPC_CMP4_LT_A6 = 0x18400000000ull,
233 OPC_CMP4_LTU_A6 = 0x1a400000000ull,
234 OPC_CMP4_EQ_A6 = 0x1c400000000ull,
235 OPC_DEP_I14 = 0x0ae00000000ull,
236 OPC_DEP_I15 = 0x08000000000ull,
237 OPC_DEP_Z_I12 = 0x0a600000000ull,
238 OPC_EXTR_I11 = 0x0a400002000ull,
239 OPC_EXTR_U_I11 = 0x0a400000000ull,
240 OPC_FCVT_FX_TRUNC_S1_F10 = 0x004d0000000ull,
241 OPC_FCVT_FXU_TRUNC_S1_F10 = 0x004d8000000ull,
242 OPC_FCVT_XF_F11 = 0x000e0000000ull,
243 OPC_FMA_S1_F1 = 0x10400000000ull,
244 OPC_FNMA_S1_F1 = 0x18400000000ull,
245 OPC_FRCPA_S1_F6 = 0x00600000000ull,
246 OPC_GETF_SIG_M19 = 0x08708000000ull,
247 OPC_LD1_M1 = 0x08000000000ull,
248 OPC_LD1_M3 = 0x0a000000000ull,
249 OPC_LD2_M1 = 0x08040000000ull,
250 OPC_LD2_M3 = 0x0a040000000ull,
251 OPC_LD4_M1 = 0x08080000000ull,
252 OPC_LD4_M3 = 0x0a080000000ull,
253 OPC_LD8_M1 = 0x080c0000000ull,
254 OPC_LD8_M3 = 0x0a0c0000000ull,
255 OPC_MUX1_I3 = 0x0eca0000000ull,
256 OPC_NOP_B9 = 0x04008000000ull,
257 OPC_NOP_F16 = 0x00008000000ull,
258 OPC_NOP_I18 = 0x00008000000ull,
259 OPC_NOP_M48 = 0x00008000000ull,
260 OPC_MOV_I21 = 0x00e00100000ull,
261 OPC_MOV_RET_I21 = 0x00e00500000ull,
262 OPC_MOV_I22 = 0x00188000000ull,
263 OPC_MOV_I_I26 = 0x00150000000ull,
264 OPC_MOVL_X2 = 0x0c000000000ull,
265 OPC_OR_A1 = 0x10070000000ull,
266 OPC_SETF_EXP_M18 = 0x0c748000000ull,
267 OPC_SETF_SIG_M18 = 0x0c708000000ull,
268 OPC_SHL_I7 = 0x0f240000000ull,
269 OPC_SHR_I5 = 0x0f220000000ull,
270 OPC_SHR_U_I5 = 0x0f200000000ull,
271 OPC_SHRP_I10 = 0x0ac00000000ull,
272 OPC_SXT1_I29 = 0x000a0000000ull,
273 OPC_SXT2_I29 = 0x000a8000000ull,
274 OPC_SXT4_I29 = 0x000b0000000ull,
275 OPC_ST1_M4 = 0x08c00000000ull,
276 OPC_ST2_M4 = 0x08c40000000ull,
277 OPC_ST4_M4 = 0x08c80000000ull,
278 OPC_ST8_M4 = 0x08cc0000000ull,
279 OPC_SUB_A1 = 0x10028000000ull,
280 OPC_SUB_A3 = 0x10128000000ull,
281 OPC_UNPACK4_L_I2 = 0x0f860000000ull,
282 OPC_XMA_L_F2 = 0x1d000000000ull,
283 OPC_XOR_A1 = 0x10078000000ull,
284 OPC_ZXT1_I29 = 0x00080000000ull,
285 OPC_ZXT2_I29 = 0x00088000000ull,
286 OPC_ZXT4_I29 = 0x00090000000ull,
287
288 INSN_NOP_M = OPC_NOP_M48, /* nop.m 0 */
289 INSN_NOP_I = OPC_NOP_I18, /* nop.i 0 */
290 };
291
292 static inline uint64_t tcg_opc_a1(int qp, uint64_t opc, int r1,
293 int r2, int r3)
294 {
295 return opc
296 | ((r3 & 0x7f) << 20)
297 | ((r2 & 0x7f) << 13)
298 | ((r1 & 0x7f) << 6)
299 | (qp & 0x3f);
300 }
301
302 static inline uint64_t tcg_opc_a3(int qp, uint64_t opc, int r1,
303 uint64_t imm, int r3)
304 {
305 return opc
306 | ((imm & 0x80) << 29) /* s */
307 | ((imm & 0x7f) << 13) /* imm7b */
308 | ((r3 & 0x7f) << 20)
309 | ((r1 & 0x7f) << 6)
310 | (qp & 0x3f);
311 }
312
313 static inline uint64_t tcg_opc_a4(int qp, uint64_t opc, int r1,
314 uint64_t imm, int r3)
315 {
316 return opc
317 | ((imm & 0x2000) << 23) /* s */
318 | ((imm & 0x1f80) << 20) /* imm6d */
319 | ((imm & 0x007f) << 13) /* imm7b */
320 | ((r3 & 0x7f) << 20)
321 | ((r1 & 0x7f) << 6)
322 | (qp & 0x3f);
323 }
324
325 static inline uint64_t tcg_opc_a5(int qp, uint64_t opc, int r1,
326 uint64_t imm, int r3)
327 {
328 return opc
329 | ((imm & 0x200000) << 15) /* s */
330 | ((imm & 0x1f0000) << 6) /* imm5c */
331 | ((imm & 0x00ff80) << 20) /* imm9d */
332 | ((imm & 0x00007f) << 13) /* imm7b */
333 | ((r3 & 0x03) << 20)
334 | ((r1 & 0x7f) << 6)
335 | (qp & 0x3f);
336 }
337
338 static inline uint64_t tcg_opc_a6(int qp, uint64_t opc, int p1,
339 int p2, int r2, int r3)
340 {
341 return opc
342 | ((p2 & 0x3f) << 27)
343 | ((r3 & 0x7f) << 20)
344 | ((r2 & 0x7f) << 13)
345 | ((p1 & 0x3f) << 6)
346 | (qp & 0x3f);
347 }
348
349 static inline uint64_t tcg_opc_b1(int qp, uint64_t opc, uint64_t imm)
350 {
351 return opc
352 | ((imm & 0x100000) << 16) /* s */
353 | ((imm & 0x0fffff) << 13) /* imm20b */
354 | (qp & 0x3f);
355 }
356
357 static inline uint64_t tcg_opc_b4(int qp, uint64_t opc, int b2)
358 {
359 return opc
360 | ((b2 & 0x7) << 13)
361 | (qp & 0x3f);
362 }
363
364 static inline uint64_t tcg_opc_b5(int qp, uint64_t opc, int b1, int b2)
365 {
366 return opc
367 | ((b2 & 0x7) << 13)
368 | ((b1 & 0x7) << 6)
369 | (qp & 0x3f);
370 }
371
372
373 static inline uint64_t tcg_opc_b9(int qp, uint64_t opc, uint64_t imm)
374 {
375 return opc
376 | ((imm & 0x100000) << 16) /* i */
377 | ((imm & 0x0fffff) << 6) /* imm20a */
378 | (qp & 0x3f);
379 }
380
381 static inline uint64_t tcg_opc_f1(int qp, uint64_t opc, int f1,
382 int f3, int f4, int f2)
383 {
384 return opc
385 | ((f4 & 0x7f) << 27)
386 | ((f3 & 0x7f) << 20)
387 | ((f2 & 0x7f) << 13)
388 | ((f1 & 0x7f) << 6)
389 | (qp & 0x3f);
390 }
391
392 static inline uint64_t tcg_opc_f2(int qp, uint64_t opc, int f1,
393 int f3, int f4, int f2)
394 {
395 return opc
396 | ((f4 & 0x7f) << 27)
397 | ((f3 & 0x7f) << 20)
398 | ((f2 & 0x7f) << 13)
399 | ((f1 & 0x7f) << 6)
400 | (qp & 0x3f);
401 }
402
403 static inline uint64_t tcg_opc_f6(int qp, uint64_t opc, int f1,
404 int p2, int f2, int f3)
405 {
406 return opc
407 | ((p2 & 0x3f) << 27)
408 | ((f3 & 0x7f) << 20)
409 | ((f2 & 0x7f) << 13)
410 | ((f1 & 0x7f) << 6)
411 | (qp & 0x3f);
412 }
413
414 static inline uint64_t tcg_opc_f10(int qp, uint64_t opc, int f1, int f2)
415 {
416 return opc
417 | ((f2 & 0x7f) << 13)
418 | ((f1 & 0x7f) << 6)
419 | (qp & 0x3f);
420 }
421
422 static inline uint64_t tcg_opc_f11(int qp, uint64_t opc, int f1, int f2)
423 {
424 return opc
425 | ((f2 & 0x7f) << 13)
426 | ((f1 & 0x7f) << 6)
427 | (qp & 0x3f);
428 }
429
430 static inline uint64_t tcg_opc_f16(int qp, uint64_t opc, uint64_t imm)
431 {
432 return opc
433 | ((imm & 0x100000) << 16) /* i */
434 | ((imm & 0x0fffff) << 6) /* imm20a */
435 | (qp & 0x3f);
436 }
437
438 static inline uint64_t tcg_opc_i2(int qp, uint64_t opc, int r1,
439 int r2, int r3)
440 {
441 return opc
442 | ((r3 & 0x7f) << 20)
443 | ((r2 & 0x7f) << 13)
444 | ((r1 & 0x7f) << 6)
445 | (qp & 0x3f);
446 }
447
448 static inline uint64_t tcg_opc_i3(int qp, uint64_t opc, int r1,
449 int r2, int mbtype)
450 {
451 return opc
452 | ((mbtype & 0x0f) << 20)
453 | ((r2 & 0x7f) << 13)
454 | ((r1 & 0x7f) << 6)
455 | (qp & 0x3f);
456 }
457
458 static inline uint64_t tcg_opc_i5(int qp, uint64_t opc, int r1,
459 int r3, int r2)
460 {
461 return opc
462 | ((r3 & 0x7f) << 20)
463 | ((r2 & 0x7f) << 13)
464 | ((r1 & 0x7f) << 6)
465 | (qp & 0x3f);
466 }
467
468 static inline uint64_t tcg_opc_i7(int qp, uint64_t opc, int r1,
469 int r2, int r3)
470 {
471 return opc
472 | ((r3 & 0x7f) << 20)
473 | ((r2 & 0x7f) << 13)
474 | ((r1 & 0x7f) << 6)
475 | (qp & 0x3f);
476 }
477
478 static inline uint64_t tcg_opc_i10(int qp, uint64_t opc, int r1,
479 int r2, int r3, uint64_t count)
480 {
481 return opc
482 | ((count & 0x3f) << 27)
483 | ((r3 & 0x7f) << 20)
484 | ((r2 & 0x7f) << 13)
485 | ((r1 & 0x7f) << 6)
486 | (qp & 0x3f);
487 }
488
489 static inline uint64_t tcg_opc_i11(int qp, uint64_t opc, int r1,
490 int r3, uint64_t pos, uint64_t len)
491 {
492 return opc
493 | ((len & 0x3f) << 27)
494 | ((r3 & 0x7f) << 20)
495 | ((pos & 0x3f) << 14)
496 | ((r1 & 0x7f) << 6)
497 | (qp & 0x3f);
498 }
499
500 static inline uint64_t tcg_opc_i12(int qp, uint64_t opc, int r1,
501 int r2, uint64_t pos, uint64_t len)
502 {
503 return opc
504 | ((len & 0x3f) << 27)
505 | ((pos & 0x3f) << 20)
506 | ((r2 & 0x7f) << 13)
507 | ((r1 & 0x7f) << 6)
508 | (qp & 0x3f);
509 }
510
511 static inline uint64_t tcg_opc_i14(int qp, uint64_t opc, int r1, uint64_t imm,
512 int r3, uint64_t pos, uint64_t len)
513 {
514 return opc
515 | ((imm & 0x01) << 36)
516 | ((len & 0x3f) << 27)
517 | ((r3 & 0x7f) << 20)
518 | ((pos & 0x3f) << 14)
519 | ((r1 & 0x7f) << 6)
520 | (qp & 0x3f);
521 }
522
523 static inline uint64_t tcg_opc_i15(int qp, uint64_t opc, int r1, int r2,
524 int r3, uint64_t pos, uint64_t len)
525 {
526 return opc
527 | ((pos & 0x3f) << 31)
528 | ((len & 0x0f) << 27)
529 | ((r3 & 0x7f) << 20)
530 | ((r2 & 0x7f) << 13)
531 | ((r1 & 0x7f) << 6)
532 | (qp & 0x3f);
533 }
534
535 static inline uint64_t tcg_opc_i18(int qp, uint64_t opc, uint64_t imm)
536 {
537 return opc
538 | ((imm & 0x100000) << 16) /* i */
539 | ((imm & 0x0fffff) << 6) /* imm20a */
540 | (qp & 0x3f);
541 }
542
543 static inline uint64_t tcg_opc_i21(int qp, uint64_t opc, int b1,
544 int r2, uint64_t imm)
545 {
546 return opc
547 | ((imm & 0x1ff) << 24)
548 | ((r2 & 0x7f) << 13)
549 | ((b1 & 0x7) << 6)
550 | (qp & 0x3f);
551 }
552
553 static inline uint64_t tcg_opc_i22(int qp, uint64_t opc, int r1, int b2)
554 {
555 return opc
556 | ((b2 & 0x7) << 13)
557 | ((r1 & 0x7f) << 6)
558 | (qp & 0x3f);
559 }
560
561 static inline uint64_t tcg_opc_i26(int qp, uint64_t opc, int ar3, int r2)
562 {
563 return opc
564 | ((ar3 & 0x7f) << 20)
565 | ((r2 & 0x7f) << 13)
566 | (qp & 0x3f);
567 }
568
569 static inline uint64_t tcg_opc_i29(int qp, uint64_t opc, int r1, int r3)
570 {
571 return opc
572 | ((r3 & 0x7f) << 20)
573 | ((r1 & 0x7f) << 6)
574 | (qp & 0x3f);
575 }
576
577 static inline uint64_t tcg_opc_l2(uint64_t imm)
578 {
579 return (imm & 0x7fffffffffc00000ull) >> 22;
580 }
581
582 static inline uint64_t tcg_opc_l3(uint64_t imm)
583 {
584 return (imm & 0x07fffffffff00000ull) >> 18;
585 }
586
587 #define tcg_opc_l4 tcg_opc_l3
588
589 static inline uint64_t tcg_opc_m1(int qp, uint64_t opc, int r1, int r3)
590 {
591 return opc
592 | ((r3 & 0x7f) << 20)
593 | ((r1 & 0x7f) << 6)
594 | (qp & 0x3f);
595 }
596
597 static inline uint64_t tcg_opc_m3(int qp, uint64_t opc, int r1,
598 int r3, uint64_t imm)
599 {
600 return opc
601 | ((imm & 0x100) << 28) /* s */
602 | ((imm & 0x080) << 20) /* i */
603 | ((imm & 0x07f) << 13) /* imm7b */
604 | ((r3 & 0x7f) << 20)
605 | ((r1 & 0x7f) << 6)
606 | (qp & 0x3f);
607 }
608
609 static inline uint64_t tcg_opc_m4(int qp, uint64_t opc, int r2, int r3)
610 {
611 return opc
612 | ((r3 & 0x7f) << 20)
613 | ((r2 & 0x7f) << 13)
614 | (qp & 0x3f);
615 }
616
617 static inline uint64_t tcg_opc_m18(int qp, uint64_t opc, int f1, int r2)
618 {
619 return opc
620 | ((r2 & 0x7f) << 13)
621 | ((f1 & 0x7f) << 6)
622 | (qp & 0x3f);
623 }
624
625 static inline uint64_t tcg_opc_m19(int qp, uint64_t opc, int r1, int f2)
626 {
627 return opc
628 | ((f2 & 0x7f) << 13)
629 | ((r1 & 0x7f) << 6)
630 | (qp & 0x3f);
631 }
632
633 static inline uint64_t tcg_opc_m34(int qp, uint64_t opc, int r1,
634 int sof, int sol, int sor)
635 {
636 return opc
637 | ((sor & 0x0f) << 27)
638 | ((sol & 0x7f) << 20)
639 | ((sof & 0x7f) << 13)
640 | ((r1 & 0x7f) << 6)
641 | (qp & 0x3f);
642 }
643
644 static inline uint64_t tcg_opc_m48(int qp, uint64_t opc, uint64_t imm)
645 {
646 return opc
647 | ((imm & 0x100000) << 16) /* i */
648 | ((imm & 0x0fffff) << 6) /* imm20a */
649 | (qp & 0x3f);
650 }
651
652 static inline uint64_t tcg_opc_x2(int qp, uint64_t opc,
653 int r1, uint64_t imm)
654 {
655 return opc
656 | ((imm & 0x8000000000000000ull) >> 27) /* i */
657 | (imm & 0x0000000000200000ull) /* ic */
658 | ((imm & 0x00000000001f0000ull) << 6) /* imm5c */
659 | ((imm & 0x000000000000ff80ull) << 20) /* imm9d */
660 | ((imm & 0x000000000000007full) << 13) /* imm7b */
661 | ((r1 & 0x7f) << 6)
662 | (qp & 0x3f);
663 }
664
665 static inline uint64_t tcg_opc_x3(int qp, uint64_t opc, uint64_t imm)
666 {
667 return opc
668 | ((imm & 0x0800000000000000ull) >> 23) /* i */
669 | ((imm & 0x00000000000fffffull) << 13) /* imm20b */
670 | (qp & 0x3f);
671 }
672
673 static inline uint64_t tcg_opc_x4(int qp, uint64_t opc, int b1, uint64_t imm)
674 {
675 return opc
676 | ((imm & 0x0800000000000000ull) >> 23) /* i */
677 | ((imm & 0x00000000000fffffull) << 13) /* imm20b */
678 | ((b1 & 0x7) << 6)
679 | (qp & 0x3f);
680 }
681
682
683 /*
684 * Relocations
685 */
686
687 static inline void reloc_pcrel21b(void *pc, intptr_t target)
688 {
689 uint64_t imm;
690 int64_t disp;
691 int slot;
692
693 slot = (intptr_t)pc & 3;
694 pc = (void *)((intptr_t)pc & ~3);
695
696 disp = target - (intptr_t)pc;
697 imm = (uint64_t) disp >> 4;
698
699 switch(slot) {
700 case 0:
701 *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 8) & 0xfffffdc00003ffffull)
702 | ((imm & 0x100000) << 21) /* s */
703 | ((imm & 0x0fffff) << 18); /* imm20b */
704 break;
705 case 1:
706 *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xfffffffffffb8000ull)
707 | ((imm & 0x100000) >> 2) /* s */
708 | ((imm & 0x0fffe0) >> 5); /* imm20b */
709 *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x07ffffffffffffffull)
710 | ((imm & 0x00001f) << 59); /* imm20b */
711 break;
712 case 2:
713 *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fffffffffull)
714 | ((imm & 0x100000) << 39) /* s */
715 | ((imm & 0x0fffff) << 36); /* imm20b */
716 break;
717 }
718 }
719
720 static inline uint64_t get_reloc_pcrel21b (void *pc)
721 {
722 int64_t low, high;
723 int slot;
724
725 slot = (tcg_target_long) pc & 3;
726 pc = (void *)((tcg_target_long) pc & ~3);
727
728 low = (*(uint64_t *)(pc + 0));
729 high = (*(uint64_t *)(pc + 8));
730
731 switch(slot) {
732 case 0:
733 return ((low >> 21) & 0x100000) + /* s */
734 ((low >> 18) & 0x0fffff); /* imm20b */
735 case 1:
736 return ((high << 2) & 0x100000) + /* s */
737 ((high << 5) & 0x0fffe0) + /* imm20b */
738 ((low >> 59) & 0x00001f); /* imm20b */
739 case 2:
740 return ((high >> 39) & 0x100000) + /* s */
741 ((high >> 36) & 0x0fffff); /* imm20b */
742 default:
743 tcg_abort();
744 }
745 }
746
747 static inline void reloc_pcrel60b(void *pc, intptr_t target)
748 {
749 int64_t disp;
750 uint64_t imm;
751
752 disp = target - (intptr_t)pc;
753 imm = (uint64_t) disp >> 4;
754
755 *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fff800000ull)
756 | (imm & 0x0800000000000000ull) /* s */
757 | ((imm & 0x07fffff000000000ull) >> 36) /* imm39 */
758 | ((imm & 0x00000000000fffffull) << 36); /* imm20b */
759 *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x00003fffffffffffull)
760 | ((imm & 0x0000000ffff00000ull) << 28); /* imm39 */
761 }
762
763 static inline uint64_t get_reloc_pcrel60b (void *pc)
764 {
765 int64_t low, high;
766
767 low = (*(uint64_t *)(pc + 0));
768 high = (*(uint64_t *)(pc + 8));
769
770 return ((high) & 0x0800000000000000ull) + /* s */
771 ((high >> 36) & 0x00000000000fffffull) + /* imm20b */
772 ((high << 36) & 0x07fffff000000000ull) + /* imm39 */
773 ((low >> 28) & 0x0000000ffff00000ull); /* imm39 */
774 }
775
776
777 static void patch_reloc(uint8_t *code_ptr, int type,
778 intptr_t value, intptr_t addend)
779 {
780 value += addend;
781 switch (type) {
782 case R_IA64_PCREL21B:
783 reloc_pcrel21b(code_ptr, value);
784 break;
785 case R_IA64_PCREL60B:
786 reloc_pcrel60b(code_ptr, value);
787 default:
788 tcg_abort();
789 }
790 }
791
792 /*
793 * Constraints
794 */
795
796 /* parse target specific constraints */
797 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
798 {
799 const char *ct_str;
800
801 ct_str = *pct_str;
802 switch(ct_str[0]) {
803 case 'r':
804 ct->ct |= TCG_CT_REG;
805 tcg_regset_set(ct->u.regs, 0xffffffffffffffffull);
806 break;
807 case 'I':
808 ct->ct |= TCG_CT_CONST_S22;
809 break;
810 case 'S':
811 ct->ct |= TCG_CT_REG;
812 tcg_regset_set(ct->u.regs, 0xffffffffffffffffull);
813 #if defined(CONFIG_SOFTMMU)
814 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R56);
815 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R57);
816 #endif
817 break;
818 case 'Z':
819 /* We are cheating a bit here, using the fact that the register
820 r0 is also the register number 0. Hence there is no need
821 to check for const_args in each instruction. */
822 ct->ct |= TCG_CT_CONST_ZERO;
823 break;
824 default:
825 return -1;
826 }
827 ct_str++;
828 *pct_str = ct_str;
829 return 0;
830 }
831
832 /* test if a constant matches the constraint */
833 static inline int tcg_target_const_match(tcg_target_long val,
834 const TCGArgConstraint *arg_ct)
835 {
836 int ct;
837 ct = arg_ct->ct;
838 if (ct & TCG_CT_CONST)
839 return 1;
840 else if ((ct & TCG_CT_CONST_ZERO) && val == 0)
841 return 1;
842 else if ((ct & TCG_CT_CONST_S22) && val == ((int32_t)val << 10) >> 10)
843 return 1;
844 else
845 return 0;
846 }
847
848 /*
849 * Code generation
850 */
851
852 static uint8_t *tb_ret_addr;
853
854 static inline void tcg_out_bundle(TCGContext *s, int template,
855 uint64_t slot0, uint64_t slot1,
856 uint64_t slot2)
857 {
858 template &= 0x1f; /* 5 bits */
859 slot0 &= 0x1ffffffffffull; /* 41 bits */
860 slot1 &= 0x1ffffffffffull; /* 41 bits */
861 slot2 &= 0x1ffffffffffull; /* 41 bits */
862
863 *(uint64_t *)(s->code_ptr + 0) = (slot1 << 46) | (slot0 << 5) | template;
864 *(uint64_t *)(s->code_ptr + 8) = (slot2 << 23) | (slot1 >> 18);
865 s->code_ptr += 16;
866 }
867
868 static inline void tcg_out_mov(TCGContext *s, TCGType type,
869 TCGReg ret, TCGReg arg)
870 {
871 tcg_out_bundle(s, mmI,
872 INSN_NOP_M,
873 INSN_NOP_M,
874 tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, ret, 0, arg));
875 }
876
877 static inline void tcg_out_movi(TCGContext *s, TCGType type,
878 TCGReg reg, tcg_target_long arg)
879 {
880 tcg_out_bundle(s, mLX,
881 INSN_NOP_M,
882 tcg_opc_l2 (arg),
883 tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, reg, arg));
884 }
885
886 static void tcg_out_br(TCGContext *s, int label_index)
887 {
888 TCGLabel *l = &s->labels[label_index];
889
890 /* We pay attention here to not modify the branch target by reading
891 the existing value and using it again. This ensure that caches and
892 memory are kept coherent during retranslation. */
893 tcg_out_bundle(s, mmB,
894 INSN_NOP_M,
895 INSN_NOP_M,
896 tcg_opc_b1 (TCG_REG_P0, OPC_BR_SPTK_MANY_B1,
897 get_reloc_pcrel21b(s->code_ptr + 2)));
898
899 if (l->has_value) {
900 reloc_pcrel21b((s->code_ptr - 16) + 2, l->u.value);
901 } else {
902 tcg_out_reloc(s, (s->code_ptr - 16) + 2,
903 R_IA64_PCREL21B, label_index, 0);
904 }
905 }
906
907 static inline void tcg_out_calli(TCGContext *s, uintptr_t addr)
908 {
909 /* Look through the function descriptor. */
910 uintptr_t disp, *desc = (uintptr_t *)addr;
911 tcg_out_bundle(s, mlx,
912 INSN_NOP_M,
913 tcg_opc_l2 (desc[1]),
914 tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, TCG_REG_R1, desc[1]));
915 disp = (desc[0] - (uintptr_t)s->code_ptr) >> 4;
916 tcg_out_bundle(s, mLX,
917 INSN_NOP_M,
918 tcg_opc_l4 (disp),
919 tcg_opc_x4 (TCG_REG_P0, OPC_BRL_CALL_SPTK_MANY_X4,
920 TCG_REG_B0, disp));
921 }
922
923 static inline void tcg_out_callr(TCGContext *s, TCGReg addr)
924 {
925 tcg_out_bundle(s, MmI,
926 tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R2, addr),
927 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R3, 8, addr),
928 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
929 TCG_REG_B6, TCG_REG_R2, 0));
930 tcg_out_bundle(s, mmB,
931 tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R3),
932 INSN_NOP_M,
933 tcg_opc_b5 (TCG_REG_P0, OPC_BR_CALL_SPTK_MANY_B5,
934 TCG_REG_B0, TCG_REG_B6));
935 }
936
937 static void tcg_out_exit_tb(TCGContext *s, tcg_target_long arg)
938 {
939 int64_t disp;
940 uint64_t imm;
941
942 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R8, arg);
943
944 disp = tb_ret_addr - s->code_ptr;
945 imm = (uint64_t)disp >> 4;
946
947 tcg_out_bundle(s, mLX,
948 INSN_NOP_M,
949 tcg_opc_l3 (imm),
950 tcg_opc_x3 (TCG_REG_P0, OPC_BRL_SPTK_MANY_X3, imm));
951 }
952
953 static inline void tcg_out_goto_tb(TCGContext *s, TCGArg arg)
954 {
955 if (s->tb_jmp_offset) {
956 /* direct jump method */
957 tcg_abort();
958 } else {
959 /* indirect jump method */
960 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2,
961 (tcg_target_long)(s->tb_next + arg));
962 tcg_out_bundle(s, MmI,
963 tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1,
964 TCG_REG_R2, TCG_REG_R2),
965 INSN_NOP_M,
966 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6,
967 TCG_REG_R2, 0));
968 tcg_out_bundle(s, mmB,
969 INSN_NOP_M,
970 INSN_NOP_M,
971 tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4,
972 TCG_REG_B6));
973 }
974 s->tb_next_offset[arg] = s->code_ptr - s->code_buf;
975 }
976
977 static inline void tcg_out_jmp(TCGContext *s, TCGArg addr)
978 {
979 tcg_out_bundle(s, mmI,
980 INSN_NOP_M,
981 INSN_NOP_M,
982 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6, addr, 0));
983 tcg_out_bundle(s, mmB,
984 INSN_NOP_M,
985 INSN_NOP_M,
986 tcg_opc_b4(TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6));
987 }
988
989 static inline void tcg_out_ld_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg,
990 TCGArg arg1, tcg_target_long arg2)
991 {
992 if (arg2 == ((int16_t)arg2 >> 2) << 2) {
993 tcg_out_bundle(s, MmI,
994 tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4,
995 TCG_REG_R2, arg2, arg1),
996 tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
997 INSN_NOP_I);
998 } else {
999 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2);
1000 tcg_out_bundle(s, MmI,
1001 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1,
1002 TCG_REG_R2, TCG_REG_R2, arg1),
1003 tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
1004 INSN_NOP_I);
1005 }
1006 }
1007
1008 static inline void tcg_out_st_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg,
1009 TCGArg arg1, tcg_target_long arg2)
1010 {
1011 if (arg2 == ((int16_t)arg2 >> 2) << 2) {
1012 tcg_out_bundle(s, MmI,
1013 tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4,
1014 TCG_REG_R2, arg2, arg1),
1015 tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
1016 INSN_NOP_I);
1017 } else {
1018 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2);
1019 tcg_out_bundle(s, MmI,
1020 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1,
1021 TCG_REG_R2, TCG_REG_R2, arg1),
1022 tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
1023 INSN_NOP_I);
1024 }
1025 }
1026
1027 static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
1028 TCGReg arg1, intptr_t arg2)
1029 {
1030 if (type == TCG_TYPE_I32) {
1031 tcg_out_ld_rel(s, OPC_LD4_M1, arg, arg1, arg2);
1032 } else {
1033 tcg_out_ld_rel(s, OPC_LD8_M1, arg, arg1, arg2);
1034 }
1035 }
1036
1037 static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
1038 TCGReg arg1, intptr_t arg2)
1039 {
1040 if (type == TCG_TYPE_I32) {
1041 tcg_out_st_rel(s, OPC_ST4_M4, arg, arg1, arg2);
1042 } else {
1043 tcg_out_st_rel(s, OPC_ST8_M4, arg, arg1, arg2);
1044 }
1045 }
1046
1047 static void tcg_out_alu(TCGContext *s, uint64_t opc_a1, TCGReg ret, TCGArg arg1,
1048 int const_arg1, TCGArg arg2, int const_arg2)
1049 {
1050 uint64_t opc1 = 0, opc2 = 0;
1051
1052 if (const_arg1 && arg1 != 0) {
1053 opc1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
1054 TCG_REG_R2, arg1, TCG_REG_R0);
1055 arg1 = TCG_REG_R2;
1056 }
1057
1058 if (const_arg2 && arg2 != 0) {
1059 opc2 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
1060 TCG_REG_R3, arg2, TCG_REG_R0);
1061 arg2 = TCG_REG_R3;
1062 }
1063
1064 tcg_out_bundle(s, (opc1 || opc2 ? mII : miI),
1065 opc1 ? opc1 : INSN_NOP_M,
1066 opc2 ? opc2 : INSN_NOP_I,
1067 tcg_opc_a1(TCG_REG_P0, opc_a1, ret, arg1, arg2));
1068 }
1069
1070 static inline void tcg_out_add(TCGContext *s, TCGReg ret, TCGReg arg1,
1071 TCGArg arg2, int const_arg2)
1072 {
1073 if (const_arg2 && arg2 == sextract64(arg2, 0, 14)) {
1074 tcg_out_bundle(s, mmI,
1075 INSN_NOP_M,
1076 INSN_NOP_M,
1077 tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, ret, arg2, arg1));
1078 } else {
1079 tcg_out_alu(s, OPC_ADD_A1, ret, arg1, 0, arg2, const_arg2);
1080 }
1081 }
1082
1083 static inline void tcg_out_sub(TCGContext *s, TCGReg ret, TCGArg arg1,
1084 int const_arg1, TCGArg arg2, int const_arg2)
1085 {
1086 if (const_arg1 && arg1 == (int8_t)arg1) {
1087 if (const_arg2) {
1088 tcg_out_movi(s, TCG_TYPE_I64, ret, arg1 - arg2);
1089 return;
1090 }
1091 tcg_out_bundle(s, mmI,
1092 INSN_NOP_M,
1093 INSN_NOP_M,
1094 tcg_opc_a3(TCG_REG_P0, OPC_SUB_A3, ret, arg1, arg2));
1095 } else if (const_arg2 && -arg2 == sextract64(-arg2, 0, 14)) {
1096 tcg_out_bundle(s, mmI,
1097 INSN_NOP_M,
1098 INSN_NOP_M,
1099 tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, ret, -arg2, arg1));
1100 } else {
1101 tcg_out_alu(s, OPC_SUB_A1, ret, arg1, const_arg1, arg2, const_arg2);
1102 }
1103 }
1104
1105 static inline void tcg_out_eqv(TCGContext *s, TCGArg ret,
1106 TCGArg arg1, int const_arg1,
1107 TCGArg arg2, int const_arg2)
1108 {
1109 tcg_out_bundle(s, mII,
1110 INSN_NOP_M,
1111 tcg_opc_a1 (TCG_REG_P0, OPC_XOR_A1, ret, arg1, arg2),
1112 tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
1113 }
1114
1115 static inline void tcg_out_nand(TCGContext *s, TCGArg ret,
1116 TCGArg arg1, int const_arg1,
1117 TCGArg arg2, int const_arg2)
1118 {
1119 tcg_out_bundle(s, mII,
1120 INSN_NOP_M,
1121 tcg_opc_a1 (TCG_REG_P0, OPC_AND_A1, ret, arg1, arg2),
1122 tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
1123 }
1124
1125 static inline void tcg_out_nor(TCGContext *s, TCGArg ret,
1126 TCGArg arg1, int const_arg1,
1127 TCGArg arg2, int const_arg2)
1128 {
1129 tcg_out_bundle(s, mII,
1130 INSN_NOP_M,
1131 tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, arg2),
1132 tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
1133 }
1134
1135 static inline void tcg_out_orc(TCGContext *s, TCGArg ret,
1136 TCGArg arg1, int const_arg1,
1137 TCGArg arg2, int const_arg2)
1138 {
1139 tcg_out_bundle(s, mII,
1140 INSN_NOP_M,
1141 tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, TCG_REG_R2, -1, arg2),
1142 tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, TCG_REG_R2));
1143 }
1144
1145 static inline void tcg_out_mul(TCGContext *s, TCGArg ret,
1146 TCGArg arg1, TCGArg arg2)
1147 {
1148 tcg_out_bundle(s, mmI,
1149 tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F6, arg1),
1150 tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F7, arg2),
1151 INSN_NOP_I);
1152 tcg_out_bundle(s, mmF,
1153 INSN_NOP_M,
1154 INSN_NOP_M,
1155 tcg_opc_f2 (TCG_REG_P0, OPC_XMA_L_F2, TCG_REG_F6, TCG_REG_F6,
1156 TCG_REG_F7, TCG_REG_F0));
1157 tcg_out_bundle(s, miI,
1158 tcg_opc_m19(TCG_REG_P0, OPC_GETF_SIG_M19, ret, TCG_REG_F6),
1159 INSN_NOP_I,
1160 INSN_NOP_I);
1161 }
1162
1163 static inline void tcg_out_sar_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1164 TCGArg arg2, int const_arg2)
1165 {
1166 if (const_arg2) {
1167 tcg_out_bundle(s, miI,
1168 INSN_NOP_M,
1169 INSN_NOP_I,
1170 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11,
1171 ret, arg1, arg2, 31 - arg2));
1172 } else {
1173 tcg_out_bundle(s, mII,
1174 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3,
1175 TCG_REG_R3, 0x1f, arg2),
1176 tcg_opc_i29(TCG_REG_P0, OPC_SXT4_I29, TCG_REG_R2, arg1),
1177 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret,
1178 TCG_REG_R2, TCG_REG_R3));
1179 }
1180 }
1181
1182 static inline void tcg_out_sar_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1183 TCGArg arg2, int const_arg2)
1184 {
1185 if (const_arg2) {
1186 tcg_out_bundle(s, miI,
1187 INSN_NOP_M,
1188 INSN_NOP_I,
1189 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11,
1190 ret, arg1, arg2, 63 - arg2));
1191 } else {
1192 tcg_out_bundle(s, miI,
1193 INSN_NOP_M,
1194 INSN_NOP_I,
1195 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret, arg1, arg2));
1196 }
1197 }
1198
1199 static inline void tcg_out_shl_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1200 TCGArg arg2, int const_arg2)
1201 {
1202 if (const_arg2) {
1203 tcg_out_bundle(s, miI,
1204 INSN_NOP_M,
1205 INSN_NOP_I,
1206 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret,
1207 arg1, 63 - arg2, 31 - arg2));
1208 } else {
1209 tcg_out_bundle(s, mII,
1210 INSN_NOP_M,
1211 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R2,
1212 0x1f, arg2),
1213 tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret,
1214 arg1, TCG_REG_R2));
1215 }
1216 }
1217
1218 static inline void tcg_out_shl_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1219 TCGArg arg2, int const_arg2)
1220 {
1221 if (const_arg2) {
1222 tcg_out_bundle(s, miI,
1223 INSN_NOP_M,
1224 INSN_NOP_I,
1225 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret,
1226 arg1, 63 - arg2, 63 - arg2));
1227 } else {
1228 tcg_out_bundle(s, miI,
1229 INSN_NOP_M,
1230 INSN_NOP_I,
1231 tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret,
1232 arg1, arg2));
1233 }
1234 }
1235
1236 static inline void tcg_out_shr_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1237 TCGArg arg2, int const_arg2)
1238 {
1239 if (const_arg2) {
1240 tcg_out_bundle(s, miI,
1241 INSN_NOP_M,
1242 INSN_NOP_I,
1243 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1244 arg1, arg2, 31 - arg2));
1245 } else {
1246 tcg_out_bundle(s, mII,
1247 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
1248 0x1f, arg2),
1249 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R2, arg1),
1250 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1251 TCG_REG_R2, TCG_REG_R3));
1252 }
1253 }
1254
1255 static inline void tcg_out_shr_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1256 TCGArg arg2, int const_arg2)
1257 {
1258 if (const_arg2) {
1259 tcg_out_bundle(s, miI,
1260 INSN_NOP_M,
1261 INSN_NOP_I,
1262 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1263 arg1, arg2, 63 - arg2));
1264 } else {
1265 tcg_out_bundle(s, miI,
1266 INSN_NOP_M,
1267 INSN_NOP_I,
1268 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1269 arg1, arg2));
1270 }
1271 }
1272
1273 static inline void tcg_out_rotl_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1274 TCGArg arg2, int const_arg2)
1275 {
1276 if (const_arg2) {
1277 tcg_out_bundle(s, mII,
1278 INSN_NOP_M,
1279 tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1280 TCG_REG_R2, arg1, arg1),
1281 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1282 TCG_REG_R2, 32 - arg2, 31));
1283 } else {
1284 tcg_out_bundle(s, miI,
1285 INSN_NOP_M,
1286 tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1287 TCG_REG_R2, arg1, arg1),
1288 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
1289 0x1f, arg2));
1290 tcg_out_bundle(s, mII,
1291 INSN_NOP_M,
1292 tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R3,
1293 0x20, TCG_REG_R3),
1294 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1295 TCG_REG_R2, TCG_REG_R3));
1296 }
1297 }
1298
1299 static inline void tcg_out_rotl_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1300 TCGArg arg2, int const_arg2)
1301 {
1302 if (const_arg2) {
1303 tcg_out_bundle(s, miI,
1304 INSN_NOP_M,
1305 INSN_NOP_I,
1306 tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1,
1307 arg1, 0x40 - arg2));
1308 } else {
1309 tcg_out_bundle(s, mII,
1310 tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2,
1311 0x40, arg2),
1312 tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R3,
1313 arg1, arg2),
1314 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R2,
1315 arg1, TCG_REG_R2));
1316 tcg_out_bundle(s, miI,
1317 INSN_NOP_M,
1318 INSN_NOP_I,
1319 tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret,
1320 TCG_REG_R2, TCG_REG_R3));
1321 }
1322 }
1323
1324 static inline void tcg_out_rotr_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1325 TCGArg arg2, int const_arg2)
1326 {
1327 if (const_arg2) {
1328 tcg_out_bundle(s, mII,
1329 INSN_NOP_M,
1330 tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1331 TCG_REG_R2, arg1, arg1),
1332 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1333 TCG_REG_R2, arg2, 31));
1334 } else {
1335 tcg_out_bundle(s, mII,
1336 tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
1337 0x1f, arg2),
1338 tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1339 TCG_REG_R2, arg1, arg1),
1340 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1341 TCG_REG_R2, TCG_REG_R3));
1342 }
1343 }
1344
1345 static inline void tcg_out_rotr_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1346 TCGArg arg2, int const_arg2)
1347 {
1348 if (const_arg2) {
1349 tcg_out_bundle(s, miI,
1350 INSN_NOP_M,
1351 INSN_NOP_I,
1352 tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1,
1353 arg1, arg2));
1354 } else {
1355 tcg_out_bundle(s, mII,
1356 tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2,
1357 0x40, arg2),
1358 tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R3,
1359 arg1, arg2),
1360 tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R2,
1361 arg1, TCG_REG_R2));
1362 tcg_out_bundle(s, miI,
1363 INSN_NOP_M,
1364 INSN_NOP_I,
1365 tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret,
1366 TCG_REG_R2, TCG_REG_R3));
1367 }
1368 }
1369
1370 static inline void tcg_out_ext(TCGContext *s, uint64_t opc_i29,
1371 TCGArg ret, TCGArg arg)
1372 {
1373 tcg_out_bundle(s, miI,
1374 INSN_NOP_M,
1375 INSN_NOP_I,
1376 tcg_opc_i29(TCG_REG_P0, opc_i29, ret, arg));
1377 }
1378
1379 static inline void tcg_out_bswap16(TCGContext *s, TCGArg ret, TCGArg arg)
1380 {
1381 tcg_out_bundle(s, mII,
1382 INSN_NOP_M,
1383 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 15, 15),
1384 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, ret, 0xb));
1385 }
1386
1387 static inline void tcg_out_bswap32(TCGContext *s, TCGArg ret, TCGArg arg)
1388 {
1389 tcg_out_bundle(s, mII,
1390 INSN_NOP_M,
1391 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 31, 31),
1392 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, ret, 0xb));
1393 }
1394
1395 static inline void tcg_out_bswap64(TCGContext *s, TCGArg ret, TCGArg arg)
1396 {
1397 tcg_out_bundle(s, miI,
1398 INSN_NOP_M,
1399 INSN_NOP_I,
1400 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, arg, 0xb));
1401 }
1402
1403 static inline void tcg_out_deposit(TCGContext *s, TCGArg ret, TCGArg a1,
1404 TCGArg a2, int const_a2, int pos, int len)
1405 {
1406 uint64_t i1 = 0, i2 = 0;
1407 int cpos = 63 - pos, lm1 = len - 1;
1408
1409 if (const_a2) {
1410 /* Truncate the value of a constant a2 to the width of the field. */
1411 int mask = (1u << len) - 1;
1412 a2 &= mask;
1413
1414 if (a2 == 0 || a2 == mask) {
1415 /* 1-bit signed constant inserted into register. */
1416 i2 = tcg_opc_i14(TCG_REG_P0, OPC_DEP_I14, ret, a2, a1, cpos, lm1);
1417 } else {
1418 /* Otherwise, load any constant into a temporary. Do this into
1419 the first I slot to help out with cross-unit delays. */
1420 i1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
1421 TCG_REG_R2, a2, TCG_REG_R0);
1422 a2 = TCG_REG_R2;
1423 }
1424 }
1425 if (i2 == 0) {
1426 i2 = tcg_opc_i15(TCG_REG_P0, OPC_DEP_I15, ret, a2, a1, cpos, lm1);
1427 }
1428 tcg_out_bundle(s, (i1 ? mII : miI),
1429 INSN_NOP_M,
1430 i1 ? i1 : INSN_NOP_I,
1431 i2);
1432 }
1433
1434 static inline uint64_t tcg_opc_cmp_a(int qp, TCGCond cond, TCGArg arg1,
1435 TCGArg arg2, int cmp4)
1436 {
1437 uint64_t opc_eq_a6, opc_lt_a6, opc_ltu_a6;
1438
1439 if (cmp4) {
1440 opc_eq_a6 = OPC_CMP4_EQ_A6;
1441 opc_lt_a6 = OPC_CMP4_LT_A6;
1442 opc_ltu_a6 = OPC_CMP4_LTU_A6;
1443 } else {
1444 opc_eq_a6 = OPC_CMP_EQ_A6;
1445 opc_lt_a6 = OPC_CMP_LT_A6;
1446 opc_ltu_a6 = OPC_CMP_LTU_A6;
1447 }
1448
1449 switch (cond) {
1450 case TCG_COND_EQ:
1451 return tcg_opc_a6 (qp, opc_eq_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
1452 case TCG_COND_NE:
1453 return tcg_opc_a6 (qp, opc_eq_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
1454 case TCG_COND_LT:
1455 return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
1456 case TCG_COND_LTU:
1457 return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
1458 case TCG_COND_GE:
1459 return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
1460 case TCG_COND_GEU:
1461 return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
1462 case TCG_COND_LE:
1463 return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P7, TCG_REG_P6, arg2, arg1);
1464 case TCG_COND_LEU:
1465 return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg2, arg1);
1466 case TCG_COND_GT:
1467 return tcg_opc_a6 (qp, opc_lt_a6, TCG_REG_P6, TCG_REG_P7, arg2, arg1);
1468 case TCG_COND_GTU:
1469 return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg2, arg1);
1470 default:
1471 tcg_abort();
1472 break;
1473 }
1474 }
1475
1476 static inline void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
1477 TCGReg arg2, int label_index, int cmp4)
1478 {
1479 TCGLabel *l = &s->labels[label_index];
1480
1481 tcg_out_bundle(s, miB,
1482 INSN_NOP_M,
1483 tcg_opc_cmp_a(TCG_REG_P0, cond, arg1, arg2, cmp4),
1484 tcg_opc_b1(TCG_REG_P6, OPC_BR_DPTK_FEW_B1,
1485 get_reloc_pcrel21b(s->code_ptr + 2)));
1486
1487 if (l->has_value) {
1488 reloc_pcrel21b((s->code_ptr - 16) + 2, l->u.value);
1489 } else {
1490 tcg_out_reloc(s, (s->code_ptr - 16) + 2,
1491 R_IA64_PCREL21B, label_index, 0);
1492 }
1493 }
1494
1495 static inline void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGArg ret,
1496 TCGArg arg1, TCGArg arg2, int cmp4)
1497 {
1498 tcg_out_bundle(s, MmI,
1499 tcg_opc_cmp_a(TCG_REG_P0, cond, arg1, arg2, cmp4),
1500 tcg_opc_a5(TCG_REG_P6, OPC_ADDL_A5, ret, 1, TCG_REG_R0),
1501 tcg_opc_a5(TCG_REG_P7, OPC_ADDL_A5, ret, 0, TCG_REG_R0));
1502 }
1503
1504 static inline void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGArg ret,
1505 TCGArg c1, TCGArg c2,
1506 TCGArg v1, int const_v1,
1507 TCGArg v2, int const_v2, int cmp4)
1508 {
1509 uint64_t opc1, opc2;
1510
1511 if (const_v1) {
1512 opc1 = tcg_opc_a5(TCG_REG_P6, OPC_ADDL_A5, ret, v1, TCG_REG_R0);
1513 } else if (ret == v1) {
1514 opc1 = INSN_NOP_M;
1515 } else {
1516 opc1 = tcg_opc_a4(TCG_REG_P6, OPC_ADDS_A4, ret, 0, v1);
1517 }
1518 if (const_v2) {
1519 opc2 = tcg_opc_a5(TCG_REG_P7, OPC_ADDL_A5, ret, v2, TCG_REG_R0);
1520 } else if (ret == v2) {
1521 opc2 = INSN_NOP_I;
1522 } else {
1523 opc2 = tcg_opc_a4(TCG_REG_P7, OPC_ADDS_A4, ret, 0, v2);
1524 }
1525
1526 tcg_out_bundle(s, MmI,
1527 tcg_opc_cmp_a(TCG_REG_P0, cond, c1, c2, cmp4),
1528 opc1,
1529 opc2);
1530 }
1531
1532 #if defined(CONFIG_SOFTMMU)
1533 /* Load and compare a TLB entry, and return the result in (p6, p7).
1534 R2 is loaded with the address of the addend TLB entry.
1535 R57 is loaded with the address, zero extented on 32-bit targets. */
1536 static inline void tcg_out_qemu_tlb(TCGContext *s, TCGArg addr_reg,
1537 TCGMemOp s_bits, uint64_t offset_rw,
1538 uint64_t offset_addend)
1539 {
1540 tcg_out_bundle(s, mII,
1541 INSN_NOP_M,
1542 tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, TCG_REG_R2,
1543 addr_reg, TARGET_PAGE_BITS, CPU_TLB_BITS - 1),
1544 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, TCG_REG_R2,
1545 TCG_REG_R2, 63 - CPU_TLB_ENTRY_BITS,
1546 63 - CPU_TLB_ENTRY_BITS));
1547 tcg_out_bundle(s, mII,
1548 tcg_opc_a5 (TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R2,
1549 offset_rw, TCG_REG_R2),
1550 #if TARGET_LONG_BITS == 32
1551 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R57, addr_reg),
1552 #else
1553 tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R57,
1554 0, addr_reg),
1555 #endif
1556 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1557 TCG_REG_R2, TCG_AREG0));
1558 tcg_out_bundle(s, mII,
1559 tcg_opc_m3 (TCG_REG_P0,
1560 (TARGET_LONG_BITS == 32
1561 ? OPC_LD4_M3 : OPC_LD8_M3), TCG_REG_R56,
1562 TCG_REG_R2, offset_addend - offset_rw),
1563 tcg_opc_i14(TCG_REG_P0, OPC_DEP_I14, TCG_REG_R3, 0,
1564 TCG_REG_R57, 63 - s_bits,
1565 TARGET_PAGE_BITS - s_bits - 1),
1566 tcg_opc_a6 (TCG_REG_P0, OPC_CMP_EQ_A6, TCG_REG_P6,
1567 TCG_REG_P7, TCG_REG_R3, TCG_REG_R56));
1568 }
1569
1570 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
1571 int mmu_idx) */
1572 static const void * const qemu_ld_helpers[4] = {
1573 helper_ldb_mmu,
1574 helper_ldw_mmu,
1575 helper_ldl_mmu,
1576 helper_ldq_mmu,
1577 };
1578
1579 static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
1580 TCGMemOp opc)
1581 {
1582 static const uint64_t opc_ld_m1[4] = {
1583 OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1
1584 };
1585 static const uint64_t opc_ext_i29[8] = {
1586 OPC_ZXT1_I29, OPC_ZXT2_I29, OPC_ZXT4_I29, 0,
1587 OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0
1588 };
1589 int addr_reg, data_reg, mem_index;
1590 TCGMemOp s_bits, bswap;
1591
1592 data_reg = *args++;
1593 addr_reg = *args++;
1594 mem_index = *args;
1595 s_bits = opc & MO_SIZE;
1596 bswap = opc & MO_BSWAP;
1597
1598 /* Read the TLB entry */
1599 tcg_out_qemu_tlb(s, addr_reg, s_bits,
1600 offsetof(CPUArchState, tlb_table[mem_index][0].addr_read),
1601 offsetof(CPUArchState, tlb_table[mem_index][0].addend));
1602
1603 /* P6 is the fast path, and P7 the slow path */
1604 tcg_out_bundle(s, mLX,
1605 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4,
1606 TCG_REG_R56, 0, TCG_AREG0),
1607 tcg_opc_l2 ((tcg_target_long) qemu_ld_helpers[s_bits]),
1608 tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2,
1609 (tcg_target_long) qemu_ld_helpers[s_bits]));
1610 tcg_out_bundle(s, MmI,
1611 tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3,
1612 TCG_REG_R2, 8),
1613 tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3,
1614 TCG_REG_R3, TCG_REG_R57),
1615 tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6,
1616 TCG_REG_R3, 0));
1617 if (bswap && s_bits == MO_16) {
1618 tcg_out_bundle(s, MmI,
1619 tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
1620 TCG_REG_R8, TCG_REG_R3),
1621 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
1622 tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1623 TCG_REG_R8, TCG_REG_R8, 15, 15));
1624 } else if (bswap && s_bits == MO_32) {
1625 tcg_out_bundle(s, MmI,
1626 tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
1627 TCG_REG_R8, TCG_REG_R3),
1628 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
1629 tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1630 TCG_REG_R8, TCG_REG_R8, 31, 31));
1631 } else {
1632 tcg_out_bundle(s, mmI,
1633 tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
1634 TCG_REG_R8, TCG_REG_R3),
1635 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
1636 INSN_NOP_I);
1637 }
1638 if (!bswap) {
1639 tcg_out_bundle(s, miB,
1640 tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58,
1641 mem_index, TCG_REG_R0),
1642 INSN_NOP_I,
1643 tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
1644 TCG_REG_B0, TCG_REG_B6));
1645 } else {
1646 tcg_out_bundle(s, miB,
1647 tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58,
1648 mem_index, TCG_REG_R0),
1649 tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1650 TCG_REG_R8, TCG_REG_R8, 0xb),
1651 tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
1652 TCG_REG_B0, TCG_REG_B6));
1653 }
1654
1655 if (s_bits == MO_64) {
1656 tcg_out_bundle(s, miI,
1657 INSN_NOP_M,
1658 INSN_NOP_I,
1659 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
1660 data_reg, 0, TCG_REG_R8));
1661 } else {
1662 tcg_out_bundle(s, miI,
1663 INSN_NOP_M,
1664 INSN_NOP_I,
1665 tcg_opc_i29(TCG_REG_P0, opc_ext_i29[opc & MO_SSIZE],
1666 data_reg, TCG_REG_R8));
1667 }
1668 }
1669
1670 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
1671 uintxx_t val, int mmu_idx) */
1672 static const void * const qemu_st_helpers[4] = {
1673 helper_stb_mmu,
1674 helper_stw_mmu,
1675 helper_stl_mmu,
1676 helper_stq_mmu,
1677 };
1678
1679 static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
1680 TCGMemOp opc)
1681 {
1682 static const uint64_t opc_st_m4[4] = {
1683 OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4
1684 };
1685 int addr_reg, data_reg, mem_index;
1686 TCGMemOp s_bits;
1687
1688 data_reg = *args++;
1689 addr_reg = *args++;
1690 mem_index = *args;
1691 s_bits = opc & MO_SIZE;
1692
1693 tcg_out_qemu_tlb(s, addr_reg, s_bits,
1694 offsetof(CPUArchState, tlb_table[mem_index][0].addr_write),
1695 offsetof(CPUArchState, tlb_table[mem_index][0].addend));
1696
1697 /* P6 is the fast path, and P7 the slow path */
1698 tcg_out_bundle(s, mLX,
1699 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4,
1700 TCG_REG_R56, 0, TCG_AREG0),
1701 tcg_opc_l2 ((tcg_target_long) qemu_st_helpers[s_bits]),
1702 tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2,
1703 (tcg_target_long) qemu_st_helpers[s_bits]));
1704 tcg_out_bundle(s, MmI,
1705 tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3,
1706 TCG_REG_R2, 8),
1707 tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3,
1708 TCG_REG_R3, TCG_REG_R57),
1709 tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6,
1710 TCG_REG_R3, 0));
1711
1712 switch (opc) {
1713 case MO_8:
1714 case MO_16:
1715 case MO_32:
1716 case MO_64:
1717 tcg_out_bundle(s, mii,
1718 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1719 TCG_REG_R1, TCG_REG_R2),
1720 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58,
1721 0, data_reg),
1722 INSN_NOP_I);
1723 break;
1724
1725 case MO_16 | MO_BSWAP:
1726 tcg_out_bundle(s, miI,
1727 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1728 TCG_REG_R1, TCG_REG_R2),
1729 INSN_NOP_I,
1730 tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1731 TCG_REG_R2, data_reg, 15, 15));
1732 tcg_out_bundle(s, miI,
1733 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58,
1734 0, data_reg),
1735 INSN_NOP_I,
1736 tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1737 TCG_REG_R2, TCG_REG_R2, 0xb));
1738 data_reg = TCG_REG_R2;
1739 break;
1740
1741 case MO_32 | MO_BSWAP:
1742 tcg_out_bundle(s, miI,
1743 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1744 TCG_REG_R1, TCG_REG_R2),
1745 INSN_NOP_I,
1746 tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1747 TCG_REG_R2, data_reg, 31, 31));
1748 tcg_out_bundle(s, miI,
1749 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58,
1750 0, data_reg),
1751 INSN_NOP_I,
1752 tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1753 TCG_REG_R2, TCG_REG_R2, 0xb));
1754 data_reg = TCG_REG_R2;
1755 break;
1756
1757 case MO_64 | MO_BSWAP:
1758 tcg_out_bundle(s, miI,
1759 tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1760 TCG_REG_R1, TCG_REG_R2),
1761 tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58,
1762 0, data_reg),
1763 tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1764 TCG_REG_R2, data_reg, 0xb));
1765 data_reg = TCG_REG_R2;
1766 break;
1767
1768 default:
1769 tcg_abort();
1770 }
1771
1772 tcg_out_bundle(s, miB,
1773 tcg_opc_m4 (TCG_REG_P6, opc_st_m4[s_bits],
1774 data_reg, TCG_REG_R3),
1775 tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R59,
1776 mem_index, TCG_REG_R0),
1777 tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
1778 TCG_REG_B0, TCG_REG_B6));
1779 }
1780
1781 #else /* !CONFIG_SOFTMMU */
1782
1783 static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
1784 TCGMemOp opc)
1785 {
1786 static uint64_t const opc_ld_m1[4] = {
1787 OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1
1788 };
1789 static uint64_t const opc_sxt_i29[4] = {
1790 OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0
1791 };
1792 int addr_reg, data_reg;
1793 TCGMemOp s_bits, bswap;
1794
1795 data_reg = *args++;
1796 addr_reg = *args++;
1797 s_bits = opc & MO_SIZE;
1798 bswap = opc & MO_BSWAP;
1799
1800 #if TARGET_LONG_BITS == 32
1801 if (GUEST_BASE != 0) {
1802 tcg_out_bundle(s, mII,
1803 INSN_NOP_M,
1804 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1805 TCG_REG_R3, addr_reg),
1806 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1807 TCG_GUEST_BASE_REG, TCG_REG_R3));
1808 } else {
1809 tcg_out_bundle(s, miI,
1810 INSN_NOP_M,
1811 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1812 TCG_REG_R2, addr_reg),
1813 INSN_NOP_I);
1814 }
1815
1816 if (!bswap) {
1817 if (!(opc & MO_SIGN)) {
1818 tcg_out_bundle(s, miI,
1819 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1820 data_reg, TCG_REG_R2),
1821 INSN_NOP_I,
1822 INSN_NOP_I);
1823 } else {
1824 tcg_out_bundle(s, mII,
1825 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1826 data_reg, TCG_REG_R2),
1827 INSN_NOP_I,
1828 tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits],
1829 data_reg, data_reg));
1830 }
1831 } else if (s_bits == MO_64) {
1832 tcg_out_bundle(s, mII,
1833 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1834 data_reg, TCG_REG_R2),
1835 INSN_NOP_I,
1836 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1837 data_reg, data_reg, 0xb));
1838 } else {
1839 if (s_bits == MO_16) {
1840 tcg_out_bundle(s, mII,
1841 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1842 data_reg, TCG_REG_R2),
1843 INSN_NOP_I,
1844 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1845 data_reg, data_reg, 15, 15));
1846 } else {
1847 tcg_out_bundle(s, mII,
1848 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1849 data_reg, TCG_REG_R2),
1850 INSN_NOP_I,
1851 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1852 data_reg, data_reg, 31, 31));
1853 }
1854 if (!(opc & MO_SIGN)) {
1855 tcg_out_bundle(s, miI,
1856 INSN_NOP_M,
1857 INSN_NOP_I,
1858 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1859 data_reg, data_reg, 0xb));
1860 } else {
1861 tcg_out_bundle(s, mII,
1862 INSN_NOP_M,
1863 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1864 data_reg, data_reg, 0xb),
1865 tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits],
1866 data_reg, data_reg));
1867 }
1868 }
1869 #else
1870 if (GUEST_BASE != 0) {
1871 tcg_out_bundle(s, MmI,
1872 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1873 TCG_GUEST_BASE_REG, addr_reg),
1874 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1875 data_reg, TCG_REG_R2),
1876 INSN_NOP_I);
1877 } else {
1878 tcg_out_bundle(s, mmI,
1879 INSN_NOP_M,
1880 tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1881 data_reg, addr_reg),
1882 INSN_NOP_I);
1883 }
1884
1885 if (bswap && s_bits == MO_16) {
1886 tcg_out_bundle(s, mII,
1887 INSN_NOP_M,
1888 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1889 data_reg, data_reg, 15, 15),
1890 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1891 data_reg, data_reg, 0xb));
1892 } else if (bswap && s_bits == MO_32) {
1893 tcg_out_bundle(s, mII,
1894 INSN_NOP_M,
1895 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1896 data_reg, data_reg, 31, 31),
1897 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1898 data_reg, data_reg, 0xb));
1899 } else if (bswap && s_bits == MO_64) {
1900 tcg_out_bundle(s, miI,
1901 INSN_NOP_M,
1902 INSN_NOP_I,
1903 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1904 data_reg, data_reg, 0xb));
1905 }
1906 if (opc & MO_SIGN) {
1907 tcg_out_bundle(s, miI,
1908 INSN_NOP_M,
1909 INSN_NOP_I,
1910 tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits],
1911 data_reg, data_reg));
1912 }
1913 #endif
1914 }
1915
1916 static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
1917 TCGMemOp opc)
1918 {
1919 static uint64_t const opc_st_m4[4] = {
1920 OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4
1921 };
1922 int addr_reg, data_reg;
1923 #if TARGET_LONG_BITS == 64
1924 uint64_t add_guest_base;
1925 #endif
1926 TCGMemOp s_bits, bswap;
1927
1928 data_reg = *args++;
1929 addr_reg = *args++;
1930 s_bits = opc & MO_SIZE;
1931 bswap = opc & MO_BSWAP;
1932
1933 #if TARGET_LONG_BITS == 32
1934 if (GUEST_BASE != 0) {
1935 tcg_out_bundle(s, mII,
1936 INSN_NOP_M,
1937 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1938 TCG_REG_R3, addr_reg),
1939 tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1940 TCG_GUEST_BASE_REG, TCG_REG_R3));
1941 } else {
1942 tcg_out_bundle(s, miI,
1943 INSN_NOP_M,
1944 tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1945 TCG_REG_R2, addr_reg),
1946 INSN_NOP_I);
1947 }
1948
1949 if (bswap) {
1950 if (s_bits == MO_16) {
1951 tcg_out_bundle(s, mII,
1952 INSN_NOP_M,
1953 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1954 TCG_REG_R3, data_reg, 15, 15),
1955 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1956 TCG_REG_R3, TCG_REG_R3, 0xb));
1957 data_reg = TCG_REG_R3;
1958 } else if (s_bits == MO_32) {
1959 tcg_out_bundle(s, mII,
1960 INSN_NOP_M,
1961 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1962 TCG_REG_R3, data_reg, 31, 31),
1963 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1964 TCG_REG_R3, TCG_REG_R3, 0xb));
1965 data_reg = TCG_REG_R3;
1966 } else if (s_bits == MO_64) {
1967 tcg_out_bundle(s, miI,
1968 INSN_NOP_M,
1969 INSN_NOP_I,
1970 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1971 TCG_REG_R3, data_reg, 0xb));
1972 data_reg = TCG_REG_R3;
1973 }
1974 }
1975 tcg_out_bundle(s, mmI,
1976 tcg_opc_m4 (TCG_REG_P0, opc_st_m4[s_bits],
1977 data_reg, TCG_REG_R2),
1978 INSN_NOP_M,
1979 INSN_NOP_I);
1980 #else
1981 if (GUEST_BASE != 0) {
1982 add_guest_base = tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1983 TCG_GUEST_BASE_REG, addr_reg);
1984 addr_reg = TCG_REG_R2;
1985 } else {
1986 add_guest_base = INSN_NOP_M;
1987 }
1988
1989 if (!bswap) {
1990 tcg_out_bundle(s, (GUEST_BASE ? MmI : mmI),
1991 add_guest_base,
1992 tcg_opc_m4 (TCG_REG_P0, opc_st_m4[s_bits],
1993 data_reg, addr_reg),
1994 INSN_NOP_I);
1995 } else {
1996 if (s_bits == MO_16) {
1997 tcg_out_bundle(s, mII,
1998 add_guest_base,
1999 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
2000 TCG_REG_R3, data_reg, 15, 15),
2001 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
2002 TCG_REG_R3, TCG_REG_R3, 0xb));
2003 data_reg = TCG_REG_R3;
2004 } else if (s_bits == MO_32) {
2005 tcg_out_bundle(s, mII,
2006 add_guest_base,
2007 tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
2008 TCG_REG_R3, data_reg, 31, 31),
2009 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
2010 TCG_REG_R3, TCG_REG_R3, 0xb));
2011 data_reg = TCG_REG_R3;
2012 } else if (s_bits == MO_64) {
2013 tcg_out_bundle(s, miI,
2014 add_guest_base,
2015 INSN_NOP_I,
2016 tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
2017 TCG_REG_R3, data_reg, 0xb));
2018 data_reg = TCG_REG_R3;
2019 }
2020 tcg_out_bundle(s, miI,
2021 tcg_opc_m4 (TCG_REG_P0, opc_st_m4[s_bits],
2022 data_reg, addr_reg),
2023 INSN_NOP_I,
2024 INSN_NOP_I);
2025 }
2026 #endif
2027 }
2028
2029 #endif
2030
2031 static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
2032 const TCGArg *args, const int *const_args)
2033 {
2034 switch(opc) {
2035 case INDEX_op_exit_tb:
2036 tcg_out_exit_tb(s, args[0]);
2037 break;
2038 case INDEX_op_br:
2039 tcg_out_br(s, args[0]);
2040 break;
2041 case INDEX_op_call:
2042 if (likely(const_args[0])) {
2043 tcg_out_calli(s, args[0]);
2044 } else {
2045 tcg_out_callr(s, args[0]);
2046 }
2047 break;
2048 case INDEX_op_goto_tb:
2049 tcg_out_goto_tb(s, args[0]);
2050 break;
2051
2052 case INDEX_op_movi_i32:
2053 tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
2054 break;
2055 case INDEX_op_movi_i64:
2056 tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
2057 break;
2058
2059 case INDEX_op_ld8u_i32:
2060 case INDEX_op_ld8u_i64:
2061 tcg_out_ld_rel(s, OPC_LD1_M1, args[0], args[1], args[2]);
2062 break;
2063 case INDEX_op_ld8s_i32:
2064 case INDEX_op_ld8s_i64:
2065 tcg_out_ld_rel(s, OPC_LD1_M1, args[0], args[1], args[2]);
2066 tcg_out_ext(s, OPC_SXT1_I29, args[0], args[0]);
2067 break;
2068 case INDEX_op_ld16u_i32:
2069 case INDEX_op_ld16u_i64:
2070 tcg_out_ld_rel(s, OPC_LD2_M1, args[0], args[1], args[2]);
2071 break;
2072 case INDEX_op_ld16s_i32:
2073 case INDEX_op_ld16s_i64:
2074 tcg_out_ld_rel(s, OPC_LD2_M1, args[0], args[1], args[2]);
2075 tcg_out_ext(s, OPC_SXT2_I29, args[0], args[0]);
2076 break;
2077 case INDEX_op_ld_i32:
2078 case INDEX_op_ld32u_i64:
2079 tcg_out_ld_rel(s, OPC_LD4_M1, args[0], args[1], args[2]);
2080 break;
2081 case INDEX_op_ld32s_i64:
2082 tcg_out_ld_rel(s, OPC_LD4_M1, args[0], args[1], args[2]);
2083 tcg_out_ext(s, OPC_SXT4_I29, args[0], args[0]);
2084 break;
2085 case INDEX_op_ld_i64:
2086 tcg_out_ld_rel(s, OPC_LD8_M1, args[0], args[1], args[2]);
2087 break;
2088 case INDEX_op_st8_i32:
2089 case INDEX_op_st8_i64:
2090 tcg_out_st_rel(s, OPC_ST1_M4, args[0], args[1], args[2]);
2091 break;
2092 case INDEX_op_st16_i32:
2093 case INDEX_op_st16_i64:
2094 tcg_out_st_rel(s, OPC_ST2_M4, args[0], args[1], args[2]);
2095 break;
2096 case INDEX_op_st_i32:
2097 case INDEX_op_st32_i64:
2098 tcg_out_st_rel(s, OPC_ST4_M4, args[0], args[1], args[2]);
2099 break;
2100 case INDEX_op_st_i64:
2101 tcg_out_st_rel(s, OPC_ST8_M4, args[0], args[1], args[2]);
2102 break;
2103
2104 case INDEX_op_add_i32:
2105 case INDEX_op_add_i64:
2106 tcg_out_add(s, args[0], args[1], args[2], const_args[2]);
2107 break;
2108 case INDEX_op_sub_i32:
2109 case INDEX_op_sub_i64:
2110 tcg_out_sub(s, args[0], args[1], const_args[1], args[2], const_args[2]);
2111 break;
2112
2113 case INDEX_op_and_i32:
2114 case INDEX_op_and_i64:
2115 tcg_out_alu(s, OPC_AND_A1, args[0], args[1], const_args[1],
2116 args[2], const_args[2]);
2117 break;
2118 case INDEX_op_andc_i32:
2119 case INDEX_op_andc_i64:
2120 tcg_out_alu(s, OPC_ANDCM_A1, args[0], args[1], const_args[1],
2121 args[2], const_args[2]);
2122 break;
2123 case INDEX_op_eqv_i32:
2124 case INDEX_op_eqv_i64:
2125 tcg_out_eqv(s, args[0], args[1], const_args[1],
2126 args[2], const_args[2]);
2127 break;
2128 case INDEX_op_nand_i32:
2129 case INDEX_op_nand_i64:
2130 tcg_out_nand(s, args[0], args[1], const_args[1],
2131 args[2], const_args[2]);
2132 break;
2133 case INDEX_op_nor_i32:
2134 case INDEX_op_nor_i64:
2135 tcg_out_nor(s, args[0], args[1], const_args[1],
2136 args[2], const_args[2]);
2137 break;
2138 case INDEX_op_or_i32:
2139 case INDEX_op_or_i64:
2140 tcg_out_alu(s, OPC_OR_A1, args[0], args[1], const_args[1],
2141 args[2], const_args[2]);
2142 break;
2143 case INDEX_op_orc_i32:
2144 case INDEX_op_orc_i64:
2145 tcg_out_orc(s, args[0], args[1], const_args[1],
2146 args[2], const_args[2]);
2147 break;
2148 case INDEX_op_xor_i32:
2149 case INDEX_op_xor_i64:
2150 tcg_out_alu(s, OPC_XOR_A1, args[0], args[1], const_args[1],
2151 args[2], const_args[2]);
2152 break;
2153
2154 case INDEX_op_mul_i32:
2155 case INDEX_op_mul_i64:
2156 tcg_out_mul(s, args[0], args[1], args[2]);
2157 break;
2158
2159 case INDEX_op_sar_i32:
2160 tcg_out_sar_i32(s, args[0], args[1], args[2], const_args[2]);
2161 break;
2162 case INDEX_op_sar_i64:
2163 tcg_out_sar_i64(s, args[0], args[1], args[2], const_args[2]);
2164 break;
2165 case INDEX_op_shl_i32:
2166 tcg_out_shl_i32(s, args[0], args[1], args[2], const_args[2]);
2167 break;
2168 case INDEX_op_shl_i64:
2169 tcg_out_shl_i64(s, args[0], args[1], args[2], const_args[2]);
2170 break;
2171 case INDEX_op_shr_i32:
2172 tcg_out_shr_i32(s, args[0], args[1], args[2], const_args[2]);
2173 break;
2174 case INDEX_op_shr_i64:
2175 tcg_out_shr_i64(s, args[0], args[1], args[2], const_args[2]);
2176 break;
2177 case INDEX_op_rotl_i32:
2178 tcg_out_rotl_i32(s, args[0], args[1], args[2], const_args[2]);
2179 break;
2180 case INDEX_op_rotl_i64:
2181 tcg_out_rotl_i64(s, args[0], args[1], args[2], const_args[2]);
2182 break;
2183 case INDEX_op_rotr_i32:
2184 tcg_out_rotr_i32(s, args[0], args[1], args[2], const_args[2]);
2185 break;
2186 case INDEX_op_rotr_i64:
2187 tcg_out_rotr_i64(s, args[0], args[1], args[2], const_args[2]);
2188 break;
2189
2190 case INDEX_op_ext8s_i32:
2191 case INDEX_op_ext8s_i64:
2192 tcg_out_ext(s, OPC_SXT1_I29, args[0], args[1]);
2193 break;
2194 case INDEX_op_ext8u_i32:
2195 case INDEX_op_ext8u_i64:
2196 tcg_out_ext(s, OPC_ZXT1_I29, args[0], args[1]);
2197 break;
2198 case INDEX_op_ext16s_i32:
2199 case INDEX_op_ext16s_i64:
2200 tcg_out_ext(s, OPC_SXT2_I29, args[0], args[1]);
2201 break;
2202 case INDEX_op_ext16u_i32:
2203 case INDEX_op_ext16u_i64:
2204 tcg_out_ext(s, OPC_ZXT2_I29, args[0], args[1]);
2205 break;
2206 case INDEX_op_ext32s_i64:
2207 tcg_out_ext(s, OPC_SXT4_I29, args[0], args[1]);
2208 break;
2209 case INDEX_op_ext32u_i64:
2210 tcg_out_ext(s, OPC_ZXT4_I29, args[0], args[1]);
2211 break;
2212
2213 case INDEX_op_bswap16_i32:
2214 case INDEX_op_bswap16_i64:
2215 tcg_out_bswap16(s, args[0], args[1]);
2216 break;
2217 case INDEX_op_bswap32_i32:
2218 case INDEX_op_bswap32_i64:
2219 tcg_out_bswap32(s, args[0], args[1]);
2220 break;
2221 case INDEX_op_bswap64_i64:
2222 tcg_out_bswap64(s, args[0], args[1]);
2223 break;
2224
2225 case INDEX_op_deposit_i32:
2226 case INDEX_op_deposit_i64:
2227 tcg_out_deposit(s, args[0], args[1], args[2], const_args[2],
2228 args[3], args[4]);
2229 break;
2230
2231 case INDEX_op_brcond_i32:
2232 tcg_out_brcond(s, args[2], args[0], args[1], args[3], 1);
2233 break;
2234 case INDEX_op_brcond_i64:
2235 tcg_out_brcond(s, args[2], args[0], args[1], args[3], 0);
2236 break;
2237 case INDEX_op_setcond_i32:
2238 tcg_out_setcond(s, args[3], args[0], args[1], args[2], 1);
2239 break;
2240 case INDEX_op_setcond_i64:
2241 tcg_out_setcond(s, args[3], args[0], args[1], args[2], 0);
2242 break;
2243 case INDEX_op_movcond_i32:
2244 tcg_out_movcond(s, args[5], args[0], args[1], args[2],
2245 args[3], const_args[3], args[4], const_args[4], 1);
2246 break;
2247 case INDEX_op_movcond_i64:
2248 tcg_out_movcond(s, args[5], args[0], args[1], args[2],
2249 args[3], const_args[3], args[4], const_args[4], 0);
2250 break;
2251
2252 case INDEX_op_qemu_ld8u:
2253 tcg_out_qemu_ld(s, args, MO_UB);
2254 break;
2255 case INDEX_op_qemu_ld8s:
2256 tcg_out_qemu_ld(s, args, MO_SB);
2257 break;
2258 case INDEX_op_qemu_ld16u:
2259 tcg_out_qemu_ld(s, args, MO_TEUW);
2260 break;
2261 case INDEX_op_qemu_ld16s:
2262 tcg_out_qemu_ld(s, args, MO_TESW);
2263 break;
2264 case INDEX_op_qemu_ld32:
2265 case INDEX_op_qemu_ld32u:
2266 tcg_out_qemu_ld(s, args, MO_TEUL);
2267 break;
2268 case INDEX_op_qemu_ld32s:
2269 tcg_out_qemu_ld(s, args, MO_TESL);
2270 break;
2271 case INDEX_op_qemu_ld64:
2272 tcg_out_qemu_ld(s, args, MO_TEQ);
2273 break;
2274
2275 case INDEX_op_qemu_st8:
2276 tcg_out_qemu_st(s, args, MO_UB);
2277 break;
2278 case INDEX_op_qemu_st16:
2279 tcg_out_qemu_st(s, args, MO_TEUW);
2280 break;
2281 case INDEX_op_qemu_st32:
2282 tcg_out_qemu_st(s, args, MO_TEUL);
2283 break;
2284 case INDEX_op_qemu_st64:
2285 tcg_out_qemu_st(s, args, MO_TEQ);
2286 break;
2287
2288 default:
2289 tcg_abort();
2290 }
2291 }
2292
2293 static const TCGTargetOpDef ia64_op_defs[] = {
2294 { INDEX_op_br, { } },
2295 { INDEX_op_call, { "ri" } },
2296 { INDEX_op_exit_tb, { } },
2297 { INDEX_op_goto_tb, { } },
2298
2299 { INDEX_op_mov_i32, { "r", "r" } },
2300 { INDEX_op_movi_i32, { "r" } },
2301
2302 { INDEX_op_ld8u_i32, { "r", "r" } },
2303 { INDEX_op_ld8s_i32, { "r", "r" } },
2304 { INDEX_op_ld16u_i32, { "r", "r" } },
2305 { INDEX_op_ld16s_i32, { "r", "r" } },
2306 { INDEX_op_ld_i32, { "r", "r" } },
2307 { INDEX_op_st8_i32, { "rZ", "r" } },
2308 { INDEX_op_st16_i32, { "rZ", "r" } },
2309 { INDEX_op_st_i32, { "rZ", "r" } },
2310
2311 { INDEX_op_add_i32, { "r", "rZ", "rI" } },
2312 { INDEX_op_sub_i32, { "r", "rI", "rI" } },
2313
2314 { INDEX_op_and_i32, { "r", "rI", "rI" } },
2315 { INDEX_op_andc_i32, { "r", "rI", "rI" } },
2316 { INDEX_op_eqv_i32, { "r", "rZ", "rZ" } },
2317 { INDEX_op_nand_i32, { "r", "rZ", "rZ" } },
2318 { INDEX_op_nor_i32, { "r", "rZ", "rZ" } },
2319 { INDEX_op_or_i32, { "r", "rI", "rI" } },
2320 { INDEX_op_orc_i32, { "r", "rZ", "rZ" } },
2321 { INDEX_op_xor_i32, { "r", "rI", "rI" } },
2322
2323 { INDEX_op_mul_i32, { "r", "rZ", "rZ" } },
2324
2325 { INDEX_op_sar_i32, { "r", "rZ", "ri" } },
2326 { INDEX_op_shl_i32, { "r", "rZ", "ri" } },
2327 { INDEX_op_shr_i32, { "r", "rZ", "ri" } },
2328 { INDEX_op_rotl_i32, { "r", "rZ", "ri" } },
2329 { INDEX_op_rotr_i32, { "r", "rZ", "ri" } },
2330
2331 { INDEX_op_ext8s_i32, { "r", "rZ"} },
2332 { INDEX_op_ext8u_i32, { "r", "rZ"} },
2333 { INDEX_op_ext16s_i32, { "r", "rZ"} },
2334 { INDEX_op_ext16u_i32, { "r", "rZ"} },
2335
2336 { INDEX_op_bswap16_i32, { "r", "rZ" } },
2337 { INDEX_op_bswap32_i32, { "r", "rZ" } },
2338
2339 { INDEX_op_brcond_i32, { "rZ", "rZ" } },
2340 { INDEX_op_setcond_i32, { "r", "rZ", "rZ" } },
2341 { INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rI", "rI" } },
2342
2343 { INDEX_op_mov_i64, { "r", "r" } },
2344 { INDEX_op_movi_i64, { "r" } },
2345
2346 { INDEX_op_ld8u_i64, { "r", "r" } },
2347 { INDEX_op_ld8s_i64, { "r", "r" } },
2348 { INDEX_op_ld16u_i64, { "r", "r" } },
2349 { INDEX_op_ld16s_i64, { "r", "r" } },
2350 { INDEX_op_ld32u_i64, { "r", "r" } },
2351 { INDEX_op_ld32s_i64, { "r", "r" } },
2352 { INDEX_op_ld_i64, { "r", "r" } },
2353 { INDEX_op_st8_i64, { "rZ", "r" } },
2354 { INDEX_op_st16_i64, { "rZ", "r" } },
2355 { INDEX_op_st32_i64, { "rZ", "r" } },
2356 { INDEX_op_st_i64, { "rZ", "r" } },
2357
2358 { INDEX_op_add_i64, { "r", "rZ", "rI" } },
2359 { INDEX_op_sub_i64, { "r", "rI", "rI" } },
2360
2361 { INDEX_op_and_i64, { "r", "rI", "rI" } },
2362 { INDEX_op_andc_i64, { "r", "rI", "rI" } },
2363 { INDEX_op_eqv_i64, { "r", "rZ", "rZ" } },
2364 { INDEX_op_nand_i64, { "r", "rZ", "rZ" } },
2365 { INDEX_op_nor_i64, { "r", "rZ", "rZ" } },
2366 { INDEX_op_or_i64, { "r", "rI", "rI" } },
2367 { INDEX_op_orc_i64, { "r", "rZ", "rZ" } },
2368 { INDEX_op_xor_i64, { "r", "rI", "rI" } },
2369
2370 { INDEX_op_mul_i64, { "r", "rZ", "rZ" } },
2371
2372 { INDEX_op_sar_i64, { "r", "rZ", "ri" } },
2373 { INDEX_op_shl_i64, { "r", "rZ", "ri" } },
2374 { INDEX_op_shr_i64, { "r", "rZ", "ri" } },
2375 { INDEX_op_rotl_i64, { "r", "rZ", "ri" } },
2376 { INDEX_op_rotr_i64, { "r", "rZ", "ri" } },
2377
2378 { INDEX_op_ext8s_i64, { "r", "rZ"} },
2379 { INDEX_op_ext8u_i64, { "r", "rZ"} },
2380 { INDEX_op_ext16s_i64, { "r", "rZ"} },
2381 { INDEX_op_ext16u_i64, { "r", "rZ"} },
2382 { INDEX_op_ext32s_i64, { "r", "rZ"} },
2383 { INDEX_op_ext32u_i64, { "r", "rZ"} },
2384
2385 { INDEX_op_bswap16_i64, { "r", "rZ" } },
2386 { INDEX_op_bswap32_i64, { "r", "rZ" } },
2387 { INDEX_op_bswap64_i64, { "r", "rZ" } },
2388
2389 { INDEX_op_brcond_i64, { "rZ", "rZ" } },
2390 { INDEX_op_setcond_i64, { "r", "rZ", "rZ" } },
2391 { INDEX_op_movcond_i64, { "r", "rZ", "rZ", "rI", "rI" } },
2392
2393 { INDEX_op_deposit_i32, { "r", "rZ", "ri" } },
2394 { INDEX_op_deposit_i64, { "r", "rZ", "ri" } },
2395
2396 { INDEX_op_qemu_ld8u, { "r", "r" } },
2397 { INDEX_op_qemu_ld8s, { "r", "r" } },
2398 { INDEX_op_qemu_ld16u, { "r", "r" } },
2399 { INDEX_op_qemu_ld16s, { "r", "r" } },
2400 { INDEX_op_qemu_ld32, { "r", "r" } },
2401 { INDEX_op_qemu_ld32u, { "r", "r" } },
2402 { INDEX_op_qemu_ld32s, { "r", "r" } },
2403 { INDEX_op_qemu_ld64, { "r", "r" } },
2404
2405 { INDEX_op_qemu_st8, { "SZ", "r" } },
2406 { INDEX_op_qemu_st16, { "SZ", "r" } },
2407 { INDEX_op_qemu_st32, { "SZ", "r" } },
2408 { INDEX_op_qemu_st64, { "SZ", "r" } },
2409
2410 { -1 },
2411 };
2412
2413 /* Generate global QEMU prologue and epilogue code */
2414 static void tcg_target_qemu_prologue(TCGContext *s)
2415 {
2416 int frame_size;
2417
2418 /* reserve some stack space */
2419 frame_size = TCG_STATIC_CALL_ARGS_SIZE +
2420 CPU_TEMP_BUF_NLONGS * sizeof(long);
2421 frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
2422 ~(TCG_TARGET_STACK_ALIGN - 1);
2423 tcg_set_frame(s, TCG_REG_CALL_STACK, TCG_STATIC_CALL_ARGS_SIZE,
2424 CPU_TEMP_BUF_NLONGS * sizeof(long));
2425
2426 /* First emit adhoc function descriptor */
2427 *(uint64_t *)(s->code_ptr) = (uint64_t)s->code_ptr + 16; /* entry point */
2428 s->code_ptr += 16; /* skip GP */
2429
2430 /* prologue */
2431 tcg_out_bundle(s, miI,
2432 tcg_opc_m34(TCG_REG_P0, OPC_ALLOC_M34,
2433 TCG_REG_R34, 32, 24, 0),
2434 INSN_NOP_I,
2435 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
2436 TCG_REG_B6, TCG_REG_R33, 0));
2437
2438 /* ??? If GUEST_BASE < 0x200000, we could load the register via
2439 an ADDL in the M slot of the next bundle. */
2440 if (GUEST_BASE != 0) {
2441 tcg_out_bundle(s, mlx,
2442 INSN_NOP_M,
2443 tcg_opc_l2 (GUEST_BASE),
2444 tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2,
2445 TCG_GUEST_BASE_REG, GUEST_BASE));
2446 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2447 }
2448
2449 tcg_out_bundle(s, miB,
2450 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
2451 TCG_REG_R12, -frame_size, TCG_REG_R12),
2452 tcg_opc_i22(TCG_REG_P0, OPC_MOV_I22,
2453 TCG_REG_R33, TCG_REG_B0),
2454 tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6));
2455
2456 /* epilogue */
2457 tb_ret_addr = s->code_ptr;
2458 tcg_out_bundle(s, miI,
2459 INSN_NOP_M,
2460 tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
2461 TCG_REG_B0, TCG_REG_R33, 0),
2462 tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
2463 TCG_REG_R12, frame_size, TCG_REG_R12));
2464 tcg_out_bundle(s, miB,
2465 INSN_NOP_M,
2466 tcg_opc_i26(TCG_REG_P0, OPC_MOV_I_I26,
2467 TCG_REG_PFS, TCG_REG_R34),
2468 tcg_opc_b4 (TCG_REG_P0, OPC_BR_RET_SPTK_MANY_B4,
2469 TCG_REG_B0));
2470 }
2471
2472 static void tcg_target_init(TCGContext *s)
2473 {
2474 tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I32],
2475 0xffffffffffffffffull);
2476 tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I64],
2477 0xffffffffffffffffull);
2478
2479 tcg_regset_clear(tcg_target_call_clobber_regs);
2480 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8);
2481 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9);
2482 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10);
2483 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11);
2484 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);
2485 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R15);
2486 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R16);
2487 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R17);
2488 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R18);
2489 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R19);
2490 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R20);
2491 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R21);
2492 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R22);
2493 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R23);
2494 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R24);
2495 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R25);
2496 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R26);
2497 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R27);
2498 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R28);
2499 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R29);
2500 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R30);
2501 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R31);
2502 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R56);
2503 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R57);
2504 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R58);
2505 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R59);
2506 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R60);
2507 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R61);
2508 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R62);
2509 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R63);
2510
2511 tcg_regset_clear(s->reserved_regs);
2512 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* zero register */
2513 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* global pointer */
2514 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* internal use */
2515 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R3); /* internal use */
2516 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R12); /* stack pointer */
2517 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
2518 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R33); /* return address */
2519 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R34); /* PFS */
2520
2521 /* The following 4 are not in use, are call-saved, but *not* saved
2522 by the prologue. Therefore we cannot use them without modifying
2523 the prologue. There doesn't seem to be any good reason to use
2524 these as opposed to the windowed registers. */
2525 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R4);
2526 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R5);
2527 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R6);
2528 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R7);
2529
2530 tcg_add_target_add_op_defs(ia64_op_defs);
2531 }
Qemu copy for testing