tcg/ia64/tcg-target.h

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2009-2010 Aurelien Jarno <aurelien@aurel32.net>
   5  * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #define TCG_TARGET_IA64 1
  26
  27 /* We only map the first 64 registers */
  28 #define TCG_TARGET_NB_REGS 64
  29 typedef enum {
  30     TCG_REG_R0 = 0,
  31     TCG_REG_R1,
  32     TCG_REG_R2,
  33     TCG_REG_R3,
  34     TCG_REG_R4,
  35     TCG_REG_R5,
  36     TCG_REG_R6,
  37     TCG_REG_R7,
  38     TCG_REG_R8,
  39     TCG_REG_R9,
  40     TCG_REG_R10,
  41     TCG_REG_R11,
  42     TCG_REG_R12,
  43     TCG_REG_R13,
  44     TCG_REG_R14,
  45     TCG_REG_R15,
  46     TCG_REG_R16,
  47     TCG_REG_R17,
  48     TCG_REG_R18,
  49     TCG_REG_R19,
  50     TCG_REG_R20,
  51     TCG_REG_R21,
  52     TCG_REG_R22,
  53     TCG_REG_R23,
  54     TCG_REG_R24,
  55     TCG_REG_R25,
  56     TCG_REG_R26,
  57     TCG_REG_R27,
  58     TCG_REG_R28,
  59     TCG_REG_R29,
  60     TCG_REG_R30,
  61     TCG_REG_R31,
  62     TCG_REG_R32,
  63     TCG_REG_R33,
  64     TCG_REG_R34,
  65     TCG_REG_R35,
  66     TCG_REG_R36,
  67     TCG_REG_R37,
  68     TCG_REG_R38,
  69     TCG_REG_R39,
  70     TCG_REG_R40,
  71     TCG_REG_R41,
  72     TCG_REG_R42,
  73     TCG_REG_R43,
  74     TCG_REG_R44,
  75     TCG_REG_R45,
  76     TCG_REG_R46,
  77     TCG_REG_R47,
  78     TCG_REG_R48,
  79     TCG_REG_R49,
  80     TCG_REG_R50,
  81     TCG_REG_R51,
  82     TCG_REG_R52,
  83     TCG_REG_R53,
  84     TCG_REG_R54,
  85     TCG_REG_R55,
  86     TCG_REG_R56,
  87     TCG_REG_R57,
  88     TCG_REG_R58,
  89     TCG_REG_R59,
  90     TCG_REG_R60,
  91     TCG_REG_R61,
  92     TCG_REG_R62,
  93     TCG_REG_R63,
  94 } TCGReg;
  95
  96 #define TCG_CT_CONST_ZERO 0x100
  97 #define TCG_CT_CONST_S22 0x200
  98
  99 /* used for function call generation */
 100 #define TCG_REG_CALL_STACK TCG_REG_R12
 101 #define TCG_TARGET_STACK_ALIGN 16
 102 #define TCG_TARGET_CALL_STACK_OFFSET 16
 103
 104 /* optional instructions */
 105 #define TCG_TARGET_HAS_div_i32          0
 106 #define TCG_TARGET_HAS_div_i64          0
 107 #define TCG_TARGET_HAS_andc_i32         1
 108 #define TCG_TARGET_HAS_andc_i64         1
 109 #define TCG_TARGET_HAS_bswap16_i32      1
 110 #define TCG_TARGET_HAS_bswap16_i64      1
 111 #define TCG_TARGET_HAS_bswap32_i32      1
 112 #define TCG_TARGET_HAS_bswap32_i64      1
 113 #define TCG_TARGET_HAS_bswap64_i64      1
 114 #define TCG_TARGET_HAS_eqv_i32          1
 115 #define TCG_TARGET_HAS_eqv_i64          1
 116 #define TCG_TARGET_HAS_ext8s_i32        1
 117 #define TCG_TARGET_HAS_ext16s_i32       1
 118 #define TCG_TARGET_HAS_ext8s_i64        1
 119 #define TCG_TARGET_HAS_ext16s_i64       1
 120 #define TCG_TARGET_HAS_ext32s_i64       1
 121 #define TCG_TARGET_HAS_ext8u_i32        1
 122 #define TCG_TARGET_HAS_ext16u_i32       1
 123 #define TCG_TARGET_HAS_ext8u_i64        1
 124 #define TCG_TARGET_HAS_ext16u_i64       1
 125 #define TCG_TARGET_HAS_ext32u_i64       1
 126 #define TCG_TARGET_HAS_nand_i32         1
 127 #define TCG_TARGET_HAS_nand_i64         1
 128 #define TCG_TARGET_HAS_nor_i32          1
 129 #define TCG_TARGET_HAS_nor_i64          1
 130 #define TCG_TARGET_HAS_orc_i32          1
 131 #define TCG_TARGET_HAS_orc_i64          1
 132 #define TCG_TARGET_HAS_rot_i32          1
 133 #define TCG_TARGET_HAS_rot_i64          1
 134 #define TCG_TARGET_HAS_deposit_i32      0
 135 #define TCG_TARGET_HAS_deposit_i64      0
 136
 137 /* optional instructions automatically implemented */
 138 #define TCG_TARGET_HAS_neg_i32          0 /* sub r1, r0, r3 */
 139 #define TCG_TARGET_HAS_neg_i64          0 /* sub r1, r0, r3 */
 140 #define TCG_TARGET_HAS_not_i32          0 /* xor r1, -1, r3 */
 141 #define TCG_TARGET_HAS_not_i64          0 /* xor r1, -1, r3 */
 142
 143 #define TCG_AREG0 TCG_REG_R7
 144
 145 /* Guest base is supported */
 146 #define TCG_TARGET_HAS_GUEST_BASE
 147
 148 static inline void flush_icache_range(tcg_target_ulong start,
 149                                       tcg_target_ulong stop)
 150 {
 151     start = start & ~(32UL - 1UL);
 152     stop = (stop + (32UL - 1UL)) & ~(32UL - 1UL);
 153
 154     for (; start < stop; start += 32UL) {
 155         asm volatile ("fc.i %0" :: "r" (start));
 156     }
 157     asm volatile (";;sync.i;;srlz.i;;");
 158 }