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tci: Use 32-bit signed offsets to loads/stores
[qemu.git] / tci.c
1 /*
2 * Tiny Code Interpreter for QEMU
3 *
4 * Copyright (c) 2009, 2011 Stefan Weil
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "config.h"
21
22 /* Defining NDEBUG disables assertions (which makes the code faster). */
23 #if !defined(CONFIG_DEBUG_TCG) && !defined(NDEBUG)
24 # define NDEBUG
25 #endif
26
27 #include "qemu-common.h"
28 #include "exec/exec-all.h" /* MAX_OPC_PARAM_IARGS */
29 #include "tcg-op.h"
30
31 /* Marker for missing code. */
32 #define TODO() \
33 do { \
34 fprintf(stderr, "TODO %s:%u: %s()\n", \
35 __FILE__, __LINE__, __func__); \
36 tcg_abort(); \
37 } while (0)
38
39 #if MAX_OPC_PARAM_IARGS != 5
40 # error Fix needed, number of supported input arguments changed!
41 #endif
42 #if TCG_TARGET_REG_BITS == 32
43 typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong,
44 tcg_target_ulong, tcg_target_ulong,
45 tcg_target_ulong, tcg_target_ulong,
46 tcg_target_ulong, tcg_target_ulong,
47 tcg_target_ulong, tcg_target_ulong);
48 #else
49 typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong,
50 tcg_target_ulong, tcg_target_ulong,
51 tcg_target_ulong);
52 #endif
53
54 /* TCI can optionally use a global register variable for env. */
55 #if !defined(AREG0)
56 CPUArchState *env;
57 #endif
58
59 /* Targets which don't use GETPC also don't need tci_tb_ptr
60 which makes them a little faster. */
61 #if defined(GETPC)
62 uintptr_t tci_tb_ptr;
63 #endif
64
65 static tcg_target_ulong tci_reg[TCG_TARGET_NB_REGS];
66
67 static tcg_target_ulong tci_read_reg(TCGReg index)
68 {
69 assert(index < ARRAY_SIZE(tci_reg));
70 return tci_reg[index];
71 }
72
73 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
74 static int8_t tci_read_reg8s(TCGReg index)
75 {
76 return (int8_t)tci_read_reg(index);
77 }
78 #endif
79
80 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
81 static int16_t tci_read_reg16s(TCGReg index)
82 {
83 return (int16_t)tci_read_reg(index);
84 }
85 #endif
86
87 #if TCG_TARGET_REG_BITS == 64
88 static int32_t tci_read_reg32s(TCGReg index)
89 {
90 return (int32_t)tci_read_reg(index);
91 }
92 #endif
93
94 static uint8_t tci_read_reg8(TCGReg index)
95 {
96 return (uint8_t)tci_read_reg(index);
97 }
98
99 static uint16_t tci_read_reg16(TCGReg index)
100 {
101 return (uint16_t)tci_read_reg(index);
102 }
103
104 static uint32_t tci_read_reg32(TCGReg index)
105 {
106 return (uint32_t)tci_read_reg(index);
107 }
108
109 #if TCG_TARGET_REG_BITS == 64
110 static uint64_t tci_read_reg64(TCGReg index)
111 {
112 return tci_read_reg(index);
113 }
114 #endif
115
116 static void tci_write_reg(TCGReg index, tcg_target_ulong value)
117 {
118 assert(index < ARRAY_SIZE(tci_reg));
119 assert(index != TCG_AREG0);
120 tci_reg[index] = value;
121 }
122
123 static void tci_write_reg8s(TCGReg index, int8_t value)
124 {
125 tci_write_reg(index, value);
126 }
127
128 static void tci_write_reg16s(TCGReg index, int16_t value)
129 {
130 tci_write_reg(index, value);
131 }
132
133 #if TCG_TARGET_REG_BITS == 64
134 static void tci_write_reg32s(TCGReg index, int32_t value)
135 {
136 tci_write_reg(index, value);
137 }
138 #endif
139
140 static void tci_write_reg8(TCGReg index, uint8_t value)
141 {
142 tci_write_reg(index, value);
143 }
144
145 static void tci_write_reg16(TCGReg index, uint16_t value)
146 {
147 tci_write_reg(index, value);
148 }
149
150 static void tci_write_reg32(TCGReg index, uint32_t value)
151 {
152 tci_write_reg(index, value);
153 }
154
155 #if TCG_TARGET_REG_BITS == 32
156 static void tci_write_reg64(uint32_t high_index, uint32_t low_index,
157 uint64_t value)
158 {
159 tci_write_reg(low_index, value);
160 tci_write_reg(high_index, value >> 32);
161 }
162 #elif TCG_TARGET_REG_BITS == 64
163 static void tci_write_reg64(TCGReg index, uint64_t value)
164 {
165 tci_write_reg(index, value);
166 }
167 #endif
168
169 #if TCG_TARGET_REG_BITS == 32
170 /* Create a 64 bit value from two 32 bit values. */
171 static uint64_t tci_uint64(uint32_t high, uint32_t low)
172 {
173 return ((uint64_t)high << 32) + low;
174 }
175 #endif
176
177 /* Read constant (native size) from bytecode. */
178 static tcg_target_ulong tci_read_i(uint8_t **tb_ptr)
179 {
180 tcg_target_ulong value = *(tcg_target_ulong *)(*tb_ptr);
181 *tb_ptr += sizeof(value);
182 return value;
183 }
184
185 /* Read unsigned constant (32 bit) from bytecode. */
186 static uint32_t tci_read_i32(uint8_t **tb_ptr)
187 {
188 uint32_t value = *(uint32_t *)(*tb_ptr);
189 *tb_ptr += sizeof(value);
190 return value;
191 }
192
193 /* Read signed constant (32 bit) from bytecode. */
194 static int32_t tci_read_s32(uint8_t **tb_ptr)
195 {
196 int32_t value = *(int32_t *)(*tb_ptr);
197 *tb_ptr += sizeof(value);
198 return value;
199 }
200
201 #if TCG_TARGET_REG_BITS == 64
202 /* Read constant (64 bit) from bytecode. */
203 static uint64_t tci_read_i64(uint8_t **tb_ptr)
204 {
205 uint64_t value = *(uint64_t *)(*tb_ptr);
206 *tb_ptr += sizeof(value);
207 return value;
208 }
209 #endif
210
211 /* Read indexed register (native size) from bytecode. */
212 static tcg_target_ulong tci_read_r(uint8_t **tb_ptr)
213 {
214 tcg_target_ulong value = tci_read_reg(**tb_ptr);
215 *tb_ptr += 1;
216 return value;
217 }
218
219 /* Read indexed register (8 bit) from bytecode. */
220 static uint8_t tci_read_r8(uint8_t **tb_ptr)
221 {
222 uint8_t value = tci_read_reg8(**tb_ptr);
223 *tb_ptr += 1;
224 return value;
225 }
226
227 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
228 /* Read indexed register (8 bit signed) from bytecode. */
229 static int8_t tci_read_r8s(uint8_t **tb_ptr)
230 {
231 int8_t value = tci_read_reg8s(**tb_ptr);
232 *tb_ptr += 1;
233 return value;
234 }
235 #endif
236
237 /* Read indexed register (16 bit) from bytecode. */
238 static uint16_t tci_read_r16(uint8_t **tb_ptr)
239 {
240 uint16_t value = tci_read_reg16(**tb_ptr);
241 *tb_ptr += 1;
242 return value;
243 }
244
245 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
246 /* Read indexed register (16 bit signed) from bytecode. */
247 static int16_t tci_read_r16s(uint8_t **tb_ptr)
248 {
249 int16_t value = tci_read_reg16s(**tb_ptr);
250 *tb_ptr += 1;
251 return value;
252 }
253 #endif
254
255 /* Read indexed register (32 bit) from bytecode. */
256 static uint32_t tci_read_r32(uint8_t **tb_ptr)
257 {
258 uint32_t value = tci_read_reg32(**tb_ptr);
259 *tb_ptr += 1;
260 return value;
261 }
262
263 #if TCG_TARGET_REG_BITS == 32
264 /* Read two indexed registers (2 * 32 bit) from bytecode. */
265 static uint64_t tci_read_r64(uint8_t **tb_ptr)
266 {
267 uint32_t low = tci_read_r32(tb_ptr);
268 return tci_uint64(tci_read_r32(tb_ptr), low);
269 }
270 #elif TCG_TARGET_REG_BITS == 64
271 /* Read indexed register (32 bit signed) from bytecode. */
272 static int32_t tci_read_r32s(uint8_t **tb_ptr)
273 {
274 int32_t value = tci_read_reg32s(**tb_ptr);
275 *tb_ptr += 1;
276 return value;
277 }
278
279 /* Read indexed register (64 bit) from bytecode. */
280 static uint64_t tci_read_r64(uint8_t **tb_ptr)
281 {
282 uint64_t value = tci_read_reg64(**tb_ptr);
283 *tb_ptr += 1;
284 return value;
285 }
286 #endif
287
288 /* Read indexed register(s) with target address from bytecode. */
289 static target_ulong tci_read_ulong(uint8_t **tb_ptr)
290 {
291 target_ulong taddr = tci_read_r(tb_ptr);
292 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
293 taddr += (uint64_t)tci_read_r(tb_ptr) << 32;
294 #endif
295 return taddr;
296 }
297
298 /* Read indexed register or constant (native size) from bytecode. */
299 static tcg_target_ulong tci_read_ri(uint8_t **tb_ptr)
300 {
301 tcg_target_ulong value;
302 TCGReg r = **tb_ptr;
303 *tb_ptr += 1;
304 if (r == TCG_CONST) {
305 value = tci_read_i(tb_ptr);
306 } else {
307 value = tci_read_reg(r);
308 }
309 return value;
310 }
311
312 /* Read indexed register or constant (32 bit) from bytecode. */
313 static uint32_t tci_read_ri32(uint8_t **tb_ptr)
314 {
315 uint32_t value;
316 TCGReg r = **tb_ptr;
317 *tb_ptr += 1;
318 if (r == TCG_CONST) {
319 value = tci_read_i32(tb_ptr);
320 } else {
321 value = tci_read_reg32(r);
322 }
323 return value;
324 }
325
326 #if TCG_TARGET_REG_BITS == 32
327 /* Read two indexed registers or constants (2 * 32 bit) from bytecode. */
328 static uint64_t tci_read_ri64(uint8_t **tb_ptr)
329 {
330 uint32_t low = tci_read_ri32(tb_ptr);
331 return tci_uint64(tci_read_ri32(tb_ptr), low);
332 }
333 #elif TCG_TARGET_REG_BITS == 64
334 /* Read indexed register or constant (64 bit) from bytecode. */
335 static uint64_t tci_read_ri64(uint8_t **tb_ptr)
336 {
337 uint64_t value;
338 TCGReg r = **tb_ptr;
339 *tb_ptr += 1;
340 if (r == TCG_CONST) {
341 value = tci_read_i64(tb_ptr);
342 } else {
343 value = tci_read_reg64(r);
344 }
345 return value;
346 }
347 #endif
348
349 static tcg_target_ulong tci_read_label(uint8_t **tb_ptr)
350 {
351 tcg_target_ulong label = tci_read_i(tb_ptr);
352 assert(label != 0);
353 return label;
354 }
355
356 static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition)
357 {
358 bool result = false;
359 int32_t i0 = u0;
360 int32_t i1 = u1;
361 switch (condition) {
362 case TCG_COND_EQ:
363 result = (u0 == u1);
364 break;
365 case TCG_COND_NE:
366 result = (u0 != u1);
367 break;
368 case TCG_COND_LT:
369 result = (i0 < i1);
370 break;
371 case TCG_COND_GE:
372 result = (i0 >= i1);
373 break;
374 case TCG_COND_LE:
375 result = (i0 <= i1);
376 break;
377 case TCG_COND_GT:
378 result = (i0 > i1);
379 break;
380 case TCG_COND_LTU:
381 result = (u0 < u1);
382 break;
383 case TCG_COND_GEU:
384 result = (u0 >= u1);
385 break;
386 case TCG_COND_LEU:
387 result = (u0 <= u1);
388 break;
389 case TCG_COND_GTU:
390 result = (u0 > u1);
391 break;
392 default:
393 TODO();
394 }
395 return result;
396 }
397
398 static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition)
399 {
400 bool result = false;
401 int64_t i0 = u0;
402 int64_t i1 = u1;
403 switch (condition) {
404 case TCG_COND_EQ:
405 result = (u0 == u1);
406 break;
407 case TCG_COND_NE:
408 result = (u0 != u1);
409 break;
410 case TCG_COND_LT:
411 result = (i0 < i1);
412 break;
413 case TCG_COND_GE:
414 result = (i0 >= i1);
415 break;
416 case TCG_COND_LE:
417 result = (i0 <= i1);
418 break;
419 case TCG_COND_GT:
420 result = (i0 > i1);
421 break;
422 case TCG_COND_LTU:
423 result = (u0 < u1);
424 break;
425 case TCG_COND_GEU:
426 result = (u0 >= u1);
427 break;
428 case TCG_COND_LEU:
429 result = (u0 <= u1);
430 break;
431 case TCG_COND_GTU:
432 result = (u0 > u1);
433 break;
434 default:
435 TODO();
436 }
437 return result;
438 }
439
440 /* Interpret pseudo code in tb. */
441 tcg_target_ulong tcg_qemu_tb_exec(CPUArchState *cpustate, uint8_t *tb_ptr)
442 {
443 tcg_target_ulong next_tb = 0;
444
445 env = cpustate;
446 tci_reg[TCG_AREG0] = (tcg_target_ulong)env;
447 assert(tb_ptr);
448
449 for (;;) {
450 #if defined(GETPC)
451 tci_tb_ptr = (uintptr_t)tb_ptr;
452 #endif
453 TCGOpcode opc = tb_ptr[0];
454 #if !defined(NDEBUG)
455 uint8_t op_size = tb_ptr[1];
456 uint8_t *old_code_ptr = tb_ptr;
457 #endif
458 tcg_target_ulong t0;
459 tcg_target_ulong t1;
460 tcg_target_ulong t2;
461 tcg_target_ulong label;
462 TCGCond condition;
463 target_ulong taddr;
464 #ifndef CONFIG_SOFTMMU
465 tcg_target_ulong host_addr;
466 #endif
467 uint8_t tmp8;
468 uint16_t tmp16;
469 uint32_t tmp32;
470 uint64_t tmp64;
471 #if TCG_TARGET_REG_BITS == 32
472 uint64_t v64;
473 #endif
474
475 /* Skip opcode and size entry. */
476 tb_ptr += 2;
477
478 switch (opc) {
479 case INDEX_op_end:
480 case INDEX_op_nop:
481 break;
482 case INDEX_op_nop1:
483 case INDEX_op_nop2:
484 case INDEX_op_nop3:
485 case INDEX_op_nopn:
486 case INDEX_op_discard:
487 TODO();
488 break;
489 case INDEX_op_set_label:
490 TODO();
491 break;
492 case INDEX_op_call:
493 t0 = tci_read_ri(&tb_ptr);
494 #if TCG_TARGET_REG_BITS == 32
495 tmp64 = ((helper_function)t0)(tci_read_reg(TCG_REG_R0),
496 tci_read_reg(TCG_REG_R1),
497 tci_read_reg(TCG_REG_R2),
498 tci_read_reg(TCG_REG_R3),
499 tci_read_reg(TCG_REG_R5),
500 tci_read_reg(TCG_REG_R6),
501 tci_read_reg(TCG_REG_R7),
502 tci_read_reg(TCG_REG_R8),
503 tci_read_reg(TCG_REG_R9),
504 tci_read_reg(TCG_REG_R10));
505 tci_write_reg(TCG_REG_R0, tmp64);
506 tci_write_reg(TCG_REG_R1, tmp64 >> 32);
507 #else
508 tmp64 = ((helper_function)t0)(tci_read_reg(TCG_REG_R0),
509 tci_read_reg(TCG_REG_R1),
510 tci_read_reg(TCG_REG_R2),
511 tci_read_reg(TCG_REG_R3),
512 tci_read_reg(TCG_REG_R5));
513 tci_write_reg(TCG_REG_R0, tmp64);
514 #endif
515 break;
516 case INDEX_op_br:
517 label = tci_read_label(&tb_ptr);
518 assert(tb_ptr == old_code_ptr + op_size);
519 tb_ptr = (uint8_t *)label;
520 continue;
521 case INDEX_op_setcond_i32:
522 t0 = *tb_ptr++;
523 t1 = tci_read_r32(&tb_ptr);
524 t2 = tci_read_ri32(&tb_ptr);
525 condition = *tb_ptr++;
526 tci_write_reg32(t0, tci_compare32(t1, t2, condition));
527 break;
528 #if TCG_TARGET_REG_BITS == 32
529 case INDEX_op_setcond2_i32:
530 t0 = *tb_ptr++;
531 tmp64 = tci_read_r64(&tb_ptr);
532 v64 = tci_read_ri64(&tb_ptr);
533 condition = *tb_ptr++;
534 tci_write_reg32(t0, tci_compare64(tmp64, v64, condition));
535 break;
536 #elif TCG_TARGET_REG_BITS == 64
537 case INDEX_op_setcond_i64:
538 t0 = *tb_ptr++;
539 t1 = tci_read_r64(&tb_ptr);
540 t2 = tci_read_ri64(&tb_ptr);
541 condition = *tb_ptr++;
542 tci_write_reg64(t0, tci_compare64(t1, t2, condition));
543 break;
544 #endif
545 case INDEX_op_mov_i32:
546 t0 = *tb_ptr++;
547 t1 = tci_read_r32(&tb_ptr);
548 tci_write_reg32(t0, t1);
549 break;
550 case INDEX_op_movi_i32:
551 t0 = *tb_ptr++;
552 t1 = tci_read_i32(&tb_ptr);
553 tci_write_reg32(t0, t1);
554 break;
555
556 /* Load/store operations (32 bit). */
557
558 case INDEX_op_ld8u_i32:
559 t0 = *tb_ptr++;
560 t1 = tci_read_r(&tb_ptr);
561 t2 = tci_read_s32(&tb_ptr);
562 tci_write_reg8(t0, *(uint8_t *)(t1 + t2));
563 break;
564 case INDEX_op_ld8s_i32:
565 case INDEX_op_ld16u_i32:
566 TODO();
567 break;
568 case INDEX_op_ld16s_i32:
569 TODO();
570 break;
571 case INDEX_op_ld_i32:
572 t0 = *tb_ptr++;
573 t1 = tci_read_r(&tb_ptr);
574 t2 = tci_read_s32(&tb_ptr);
575 tci_write_reg32(t0, *(uint32_t *)(t1 + t2));
576 break;
577 case INDEX_op_st8_i32:
578 t0 = tci_read_r8(&tb_ptr);
579 t1 = tci_read_r(&tb_ptr);
580 t2 = tci_read_s32(&tb_ptr);
581 *(uint8_t *)(t1 + t2) = t0;
582 break;
583 case INDEX_op_st16_i32:
584 t0 = tci_read_r16(&tb_ptr);
585 t1 = tci_read_r(&tb_ptr);
586 t2 = tci_read_s32(&tb_ptr);
587 *(uint16_t *)(t1 + t2) = t0;
588 break;
589 case INDEX_op_st_i32:
590 t0 = tci_read_r32(&tb_ptr);
591 t1 = tci_read_r(&tb_ptr);
592 t2 = tci_read_s32(&tb_ptr);
593 *(uint32_t *)(t1 + t2) = t0;
594 break;
595
596 /* Arithmetic operations (32 bit). */
597
598 case INDEX_op_add_i32:
599 t0 = *tb_ptr++;
600 t1 = tci_read_ri32(&tb_ptr);
601 t2 = tci_read_ri32(&tb_ptr);
602 tci_write_reg32(t0, t1 + t2);
603 break;
604 case INDEX_op_sub_i32:
605 t0 = *tb_ptr++;
606 t1 = tci_read_ri32(&tb_ptr);
607 t2 = tci_read_ri32(&tb_ptr);
608 tci_write_reg32(t0, t1 - t2);
609 break;
610 case INDEX_op_mul_i32:
611 t0 = *tb_ptr++;
612 t1 = tci_read_ri32(&tb_ptr);
613 t2 = tci_read_ri32(&tb_ptr);
614 tci_write_reg32(t0, t1 * t2);
615 break;
616 #if TCG_TARGET_HAS_div_i32
617 case INDEX_op_div_i32:
618 t0 = *tb_ptr++;
619 t1 = tci_read_ri32(&tb_ptr);
620 t2 = tci_read_ri32(&tb_ptr);
621 tci_write_reg32(t0, (int32_t)t1 / (int32_t)t2);
622 break;
623 case INDEX_op_divu_i32:
624 t0 = *tb_ptr++;
625 t1 = tci_read_ri32(&tb_ptr);
626 t2 = tci_read_ri32(&tb_ptr);
627 tci_write_reg32(t0, t1 / t2);
628 break;
629 case INDEX_op_rem_i32:
630 t0 = *tb_ptr++;
631 t1 = tci_read_ri32(&tb_ptr);
632 t2 = tci_read_ri32(&tb_ptr);
633 tci_write_reg32(t0, (int32_t)t1 % (int32_t)t2);
634 break;
635 case INDEX_op_remu_i32:
636 t0 = *tb_ptr++;
637 t1 = tci_read_ri32(&tb_ptr);
638 t2 = tci_read_ri32(&tb_ptr);
639 tci_write_reg32(t0, t1 % t2);
640 break;
641 #elif TCG_TARGET_HAS_div2_i32
642 case INDEX_op_div2_i32:
643 case INDEX_op_divu2_i32:
644 TODO();
645 break;
646 #endif
647 case INDEX_op_and_i32:
648 t0 = *tb_ptr++;
649 t1 = tci_read_ri32(&tb_ptr);
650 t2 = tci_read_ri32(&tb_ptr);
651 tci_write_reg32(t0, t1 & t2);
652 break;
653 case INDEX_op_or_i32:
654 t0 = *tb_ptr++;
655 t1 = tci_read_ri32(&tb_ptr);
656 t2 = tci_read_ri32(&tb_ptr);
657 tci_write_reg32(t0, t1 | t2);
658 break;
659 case INDEX_op_xor_i32:
660 t0 = *tb_ptr++;
661 t1 = tci_read_ri32(&tb_ptr);
662 t2 = tci_read_ri32(&tb_ptr);
663 tci_write_reg32(t0, t1 ^ t2);
664 break;
665
666 /* Shift/rotate operations (32 bit). */
667
668 case INDEX_op_shl_i32:
669 t0 = *tb_ptr++;
670 t1 = tci_read_ri32(&tb_ptr);
671 t2 = tci_read_ri32(&tb_ptr);
672 tci_write_reg32(t0, t1 << t2);
673 break;
674 case INDEX_op_shr_i32:
675 t0 = *tb_ptr++;
676 t1 = tci_read_ri32(&tb_ptr);
677 t2 = tci_read_ri32(&tb_ptr);
678 tci_write_reg32(t0, t1 >> t2);
679 break;
680 case INDEX_op_sar_i32:
681 t0 = *tb_ptr++;
682 t1 = tci_read_ri32(&tb_ptr);
683 t2 = tci_read_ri32(&tb_ptr);
684 tci_write_reg32(t0, ((int32_t)t1 >> t2));
685 break;
686 #if TCG_TARGET_HAS_rot_i32
687 case INDEX_op_rotl_i32:
688 t0 = *tb_ptr++;
689 t1 = tci_read_ri32(&tb_ptr);
690 t2 = tci_read_ri32(&tb_ptr);
691 tci_write_reg32(t0, (t1 << t2) | (t1 >> (32 - t2)));
692 break;
693 case INDEX_op_rotr_i32:
694 t0 = *tb_ptr++;
695 t1 = tci_read_ri32(&tb_ptr);
696 t2 = tci_read_ri32(&tb_ptr);
697 tci_write_reg32(t0, (t1 >> t2) | (t1 << (32 - t2)));
698 break;
699 #endif
700 #if TCG_TARGET_HAS_deposit_i32
701 case INDEX_op_deposit_i32:
702 t0 = *tb_ptr++;
703 t1 = tci_read_r32(&tb_ptr);
704 t2 = tci_read_r32(&tb_ptr);
705 tmp16 = *tb_ptr++;
706 tmp8 = *tb_ptr++;
707 tmp32 = (((1 << tmp8) - 1) << tmp16);
708 tci_write_reg32(t0, (t1 & ~tmp32) | ((t2 << tmp16) & tmp32));
709 break;
710 #endif
711 case INDEX_op_brcond_i32:
712 t0 = tci_read_r32(&tb_ptr);
713 t1 = tci_read_ri32(&tb_ptr);
714 condition = *tb_ptr++;
715 label = tci_read_label(&tb_ptr);
716 if (tci_compare32(t0, t1, condition)) {
717 assert(tb_ptr == old_code_ptr + op_size);
718 tb_ptr = (uint8_t *)label;
719 continue;
720 }
721 break;
722 #if TCG_TARGET_REG_BITS == 32
723 case INDEX_op_add2_i32:
724 t0 = *tb_ptr++;
725 t1 = *tb_ptr++;
726 tmp64 = tci_read_r64(&tb_ptr);
727 tmp64 += tci_read_r64(&tb_ptr);
728 tci_write_reg64(t1, t0, tmp64);
729 break;
730 case INDEX_op_sub2_i32:
731 t0 = *tb_ptr++;
732 t1 = *tb_ptr++;
733 tmp64 = tci_read_r64(&tb_ptr);
734 tmp64 -= tci_read_r64(&tb_ptr);
735 tci_write_reg64(t1, t0, tmp64);
736 break;
737 case INDEX_op_brcond2_i32:
738 tmp64 = tci_read_r64(&tb_ptr);
739 v64 = tci_read_ri64(&tb_ptr);
740 condition = *tb_ptr++;
741 label = tci_read_label(&tb_ptr);
742 if (tci_compare64(tmp64, v64, condition)) {
743 assert(tb_ptr == old_code_ptr + op_size);
744 tb_ptr = (uint8_t *)label;
745 continue;
746 }
747 break;
748 case INDEX_op_mulu2_i32:
749 t0 = *tb_ptr++;
750 t1 = *tb_ptr++;
751 t2 = tci_read_r32(&tb_ptr);
752 tmp64 = tci_read_r32(&tb_ptr);
753 tci_write_reg64(t1, t0, t2 * tmp64);
754 break;
755 #endif /* TCG_TARGET_REG_BITS == 32 */
756 #if TCG_TARGET_HAS_ext8s_i32
757 case INDEX_op_ext8s_i32:
758 t0 = *tb_ptr++;
759 t1 = tci_read_r8s(&tb_ptr);
760 tci_write_reg32(t0, t1);
761 break;
762 #endif
763 #if TCG_TARGET_HAS_ext16s_i32
764 case INDEX_op_ext16s_i32:
765 t0 = *tb_ptr++;
766 t1 = tci_read_r16s(&tb_ptr);
767 tci_write_reg32(t0, t1);
768 break;
769 #endif
770 #if TCG_TARGET_HAS_ext8u_i32
771 case INDEX_op_ext8u_i32:
772 t0 = *tb_ptr++;
773 t1 = tci_read_r8(&tb_ptr);
774 tci_write_reg32(t0, t1);
775 break;
776 #endif
777 #if TCG_TARGET_HAS_ext16u_i32
778 case INDEX_op_ext16u_i32:
779 t0 = *tb_ptr++;
780 t1 = tci_read_r16(&tb_ptr);
781 tci_write_reg32(t0, t1);
782 break;
783 #endif
784 #if TCG_TARGET_HAS_bswap16_i32
785 case INDEX_op_bswap16_i32:
786 t0 = *tb_ptr++;
787 t1 = tci_read_r16(&tb_ptr);
788 tci_write_reg32(t0, bswap16(t1));
789 break;
790 #endif
791 #if TCG_TARGET_HAS_bswap32_i32
792 case INDEX_op_bswap32_i32:
793 t0 = *tb_ptr++;
794 t1 = tci_read_r32(&tb_ptr);
795 tci_write_reg32(t0, bswap32(t1));
796 break;
797 #endif
798 #if TCG_TARGET_HAS_not_i32
799 case INDEX_op_not_i32:
800 t0 = *tb_ptr++;
801 t1 = tci_read_r32(&tb_ptr);
802 tci_write_reg32(t0, ~t1);
803 break;
804 #endif
805 #if TCG_TARGET_HAS_neg_i32
806 case INDEX_op_neg_i32:
807 t0 = *tb_ptr++;
808 t1 = tci_read_r32(&tb_ptr);
809 tci_write_reg32(t0, -t1);
810 break;
811 #endif
812 #if TCG_TARGET_REG_BITS == 64
813 case INDEX_op_mov_i64:
814 t0 = *tb_ptr++;
815 t1 = tci_read_r64(&tb_ptr);
816 tci_write_reg64(t0, t1);
817 break;
818 case INDEX_op_movi_i64:
819 t0 = *tb_ptr++;
820 t1 = tci_read_i64(&tb_ptr);
821 tci_write_reg64(t0, t1);
822 break;
823
824 /* Load/store operations (64 bit). */
825
826 case INDEX_op_ld8u_i64:
827 t0 = *tb_ptr++;
828 t1 = tci_read_r(&tb_ptr);
829 t2 = tci_read_s32(&tb_ptr);
830 tci_write_reg8(t0, *(uint8_t *)(t1 + t2));
831 break;
832 case INDEX_op_ld8s_i64:
833 case INDEX_op_ld16u_i64:
834 case INDEX_op_ld16s_i64:
835 TODO();
836 break;
837 case INDEX_op_ld32u_i64:
838 t0 = *tb_ptr++;
839 t1 = tci_read_r(&tb_ptr);
840 t2 = tci_read_s32(&tb_ptr);
841 tci_write_reg32(t0, *(uint32_t *)(t1 + t2));
842 break;
843 case INDEX_op_ld32s_i64:
844 t0 = *tb_ptr++;
845 t1 = tci_read_r(&tb_ptr);
846 t2 = tci_read_s32(&tb_ptr);
847 tci_write_reg32s(t0, *(int32_t *)(t1 + t2));
848 break;
849 case INDEX_op_ld_i64:
850 t0 = *tb_ptr++;
851 t1 = tci_read_r(&tb_ptr);
852 t2 = tci_read_s32(&tb_ptr);
853 tci_write_reg64(t0, *(uint64_t *)(t1 + t2));
854 break;
855 case INDEX_op_st8_i64:
856 t0 = tci_read_r8(&tb_ptr);
857 t1 = tci_read_r(&tb_ptr);
858 t2 = tci_read_s32(&tb_ptr);
859 *(uint8_t *)(t1 + t2) = t0;
860 break;
861 case INDEX_op_st16_i64:
862 t0 = tci_read_r16(&tb_ptr);
863 t1 = tci_read_r(&tb_ptr);
864 t2 = tci_read_s32(&tb_ptr);
865 *(uint16_t *)(t1 + t2) = t0;
866 break;
867 case INDEX_op_st32_i64:
868 t0 = tci_read_r32(&tb_ptr);
869 t1 = tci_read_r(&tb_ptr);
870 t2 = tci_read_s32(&tb_ptr);
871 *(uint32_t *)(t1 + t2) = t0;
872 break;
873 case INDEX_op_st_i64:
874 t0 = tci_read_r64(&tb_ptr);
875 t1 = tci_read_r(&tb_ptr);
876 t2 = tci_read_s32(&tb_ptr);
877 *(uint64_t *)(t1 + t2) = t0;
878 break;
879
880 /* Arithmetic operations (64 bit). */
881
882 case INDEX_op_add_i64:
883 t0 = *tb_ptr++;
884 t1 = tci_read_ri64(&tb_ptr);
885 t2 = tci_read_ri64(&tb_ptr);
886 tci_write_reg64(t0, t1 + t2);
887 break;
888 case INDEX_op_sub_i64:
889 t0 = *tb_ptr++;
890 t1 = tci_read_ri64(&tb_ptr);
891 t2 = tci_read_ri64(&tb_ptr);
892 tci_write_reg64(t0, t1 - t2);
893 break;
894 case INDEX_op_mul_i64:
895 t0 = *tb_ptr++;
896 t1 = tci_read_ri64(&tb_ptr);
897 t2 = tci_read_ri64(&tb_ptr);
898 tci_write_reg64(t0, t1 * t2);
899 break;
900 #if TCG_TARGET_HAS_div_i64
901 case INDEX_op_div_i64:
902 case INDEX_op_divu_i64:
903 case INDEX_op_rem_i64:
904 case INDEX_op_remu_i64:
905 TODO();
906 break;
907 #elif TCG_TARGET_HAS_div2_i64
908 case INDEX_op_div2_i64:
909 case INDEX_op_divu2_i64:
910 TODO();
911 break;
912 #endif
913 case INDEX_op_and_i64:
914 t0 = *tb_ptr++;
915 t1 = tci_read_ri64(&tb_ptr);
916 t2 = tci_read_ri64(&tb_ptr);
917 tci_write_reg64(t0, t1 & t2);
918 break;
919 case INDEX_op_or_i64:
920 t0 = *tb_ptr++;
921 t1 = tci_read_ri64(&tb_ptr);
922 t2 = tci_read_ri64(&tb_ptr);
923 tci_write_reg64(t0, t1 | t2);
924 break;
925 case INDEX_op_xor_i64:
926 t0 = *tb_ptr++;
927 t1 = tci_read_ri64(&tb_ptr);
928 t2 = tci_read_ri64(&tb_ptr);
929 tci_write_reg64(t0, t1 ^ t2);
930 break;
931
932 /* Shift/rotate operations (64 bit). */
933
934 case INDEX_op_shl_i64:
935 t0 = *tb_ptr++;
936 t1 = tci_read_ri64(&tb_ptr);
937 t2 = tci_read_ri64(&tb_ptr);
938 tci_write_reg64(t0, t1 << t2);
939 break;
940 case INDEX_op_shr_i64:
941 t0 = *tb_ptr++;
942 t1 = tci_read_ri64(&tb_ptr);
943 t2 = tci_read_ri64(&tb_ptr);
944 tci_write_reg64(t0, t1 >> t2);
945 break;
946 case INDEX_op_sar_i64:
947 t0 = *tb_ptr++;
948 t1 = tci_read_ri64(&tb_ptr);
949 t2 = tci_read_ri64(&tb_ptr);
950 tci_write_reg64(t0, ((int64_t)t1 >> t2));
951 break;
952 #if TCG_TARGET_HAS_rot_i64
953 case INDEX_op_rotl_i64:
954 case INDEX_op_rotr_i64:
955 TODO();
956 break;
957 #endif
958 #if TCG_TARGET_HAS_deposit_i64
959 case INDEX_op_deposit_i64:
960 t0 = *tb_ptr++;
961 t1 = tci_read_r64(&tb_ptr);
962 t2 = tci_read_r64(&tb_ptr);
963 tmp16 = *tb_ptr++;
964 tmp8 = *tb_ptr++;
965 tmp64 = (((1ULL << tmp8) - 1) << tmp16);
966 tci_write_reg64(t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp64));
967 break;
968 #endif
969 case INDEX_op_brcond_i64:
970 t0 = tci_read_r64(&tb_ptr);
971 t1 = tci_read_ri64(&tb_ptr);
972 condition = *tb_ptr++;
973 label = tci_read_label(&tb_ptr);
974 if (tci_compare64(t0, t1, condition)) {
975 assert(tb_ptr == old_code_ptr + op_size);
976 tb_ptr = (uint8_t *)label;
977 continue;
978 }
979 break;
980 #if TCG_TARGET_HAS_ext8u_i64
981 case INDEX_op_ext8u_i64:
982 t0 = *tb_ptr++;
983 t1 = tci_read_r8(&tb_ptr);
984 tci_write_reg64(t0, t1);
985 break;
986 #endif
987 #if TCG_TARGET_HAS_ext8s_i64
988 case INDEX_op_ext8s_i64:
989 t0 = *tb_ptr++;
990 t1 = tci_read_r8s(&tb_ptr);
991 tci_write_reg64(t0, t1);
992 break;
993 #endif
994 #if TCG_TARGET_HAS_ext16s_i64
995 case INDEX_op_ext16s_i64:
996 t0 = *tb_ptr++;
997 t1 = tci_read_r16s(&tb_ptr);
998 tci_write_reg64(t0, t1);
999 break;
1000 #endif
1001 #if TCG_TARGET_HAS_ext16u_i64
1002 case INDEX_op_ext16u_i64:
1003 t0 = *tb_ptr++;
1004 t1 = tci_read_r16(&tb_ptr);
1005 tci_write_reg64(t0, t1);
1006 break;
1007 #endif
1008 #if TCG_TARGET_HAS_ext32s_i64
1009 case INDEX_op_ext32s_i64:
1010 t0 = *tb_ptr++;
1011 t1 = tci_read_r32s(&tb_ptr);
1012 tci_write_reg64(t0, t1);
1013 break;
1014 #endif
1015 #if TCG_TARGET_HAS_ext32u_i64
1016 case INDEX_op_ext32u_i64:
1017 t0 = *tb_ptr++;
1018 t1 = tci_read_r32(&tb_ptr);
1019 tci_write_reg64(t0, t1);
1020 break;
1021 #endif
1022 #if TCG_TARGET_HAS_bswap16_i64
1023 case INDEX_op_bswap16_i64:
1024 TODO();
1025 t0 = *tb_ptr++;
1026 t1 = tci_read_r16(&tb_ptr);
1027 tci_write_reg64(t0, bswap16(t1));
1028 break;
1029 #endif
1030 #if TCG_TARGET_HAS_bswap32_i64
1031 case INDEX_op_bswap32_i64:
1032 t0 = *tb_ptr++;
1033 t1 = tci_read_r32(&tb_ptr);
1034 tci_write_reg64(t0, bswap32(t1));
1035 break;
1036 #endif
1037 #if TCG_TARGET_HAS_bswap64_i64
1038 case INDEX_op_bswap64_i64:
1039 t0 = *tb_ptr++;
1040 t1 = tci_read_r64(&tb_ptr);
1041 tci_write_reg64(t0, bswap64(t1));
1042 break;
1043 #endif
1044 #if TCG_TARGET_HAS_not_i64
1045 case INDEX_op_not_i64:
1046 t0 = *tb_ptr++;
1047 t1 = tci_read_r64(&tb_ptr);
1048 tci_write_reg64(t0, ~t1);
1049 break;
1050 #endif
1051 #if TCG_TARGET_HAS_neg_i64
1052 case INDEX_op_neg_i64:
1053 t0 = *tb_ptr++;
1054 t1 = tci_read_r64(&tb_ptr);
1055 tci_write_reg64(t0, -t1);
1056 break;
1057 #endif
1058 #endif /* TCG_TARGET_REG_BITS == 64 */
1059
1060 /* QEMU specific operations. */
1061
1062 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
1063 case INDEX_op_debug_insn_start:
1064 TODO();
1065 break;
1066 #else
1067 case INDEX_op_debug_insn_start:
1068 TODO();
1069 break;
1070 #endif
1071 case INDEX_op_exit_tb:
1072 next_tb = *(uint64_t *)tb_ptr;
1073 goto exit;
1074 break;
1075 case INDEX_op_goto_tb:
1076 t0 = tci_read_i32(&tb_ptr);
1077 assert(tb_ptr == old_code_ptr + op_size);
1078 tb_ptr += (int32_t)t0;
1079 continue;
1080 case INDEX_op_qemu_ld8u:
1081 t0 = *tb_ptr++;
1082 taddr = tci_read_ulong(&tb_ptr);
1083 #ifdef CONFIG_SOFTMMU
1084 tmp8 = helper_ldb_mmu(env, taddr, tci_read_i(&tb_ptr));
1085 #else
1086 host_addr = (tcg_target_ulong)taddr;
1087 assert(taddr == host_addr);
1088 tmp8 = *(uint8_t *)(host_addr + GUEST_BASE);
1089 #endif
1090 tci_write_reg8(t0, tmp8);
1091 break;
1092 case INDEX_op_qemu_ld8s:
1093 t0 = *tb_ptr++;
1094 taddr = tci_read_ulong(&tb_ptr);
1095 #ifdef CONFIG_SOFTMMU
1096 tmp8 = helper_ldb_mmu(env, taddr, tci_read_i(&tb_ptr));
1097 #else
1098 host_addr = (tcg_target_ulong)taddr;
1099 assert(taddr == host_addr);
1100 tmp8 = *(uint8_t *)(host_addr + GUEST_BASE);
1101 #endif
1102 tci_write_reg8s(t0, tmp8);
1103 break;
1104 case INDEX_op_qemu_ld16u:
1105 t0 = *tb_ptr++;
1106 taddr = tci_read_ulong(&tb_ptr);
1107 #ifdef CONFIG_SOFTMMU
1108 tmp16 = helper_ldw_mmu(env, taddr, tci_read_i(&tb_ptr));
1109 #else
1110 host_addr = (tcg_target_ulong)taddr;
1111 assert(taddr == host_addr);
1112 tmp16 = tswap16(*(uint16_t *)(host_addr + GUEST_BASE));
1113 #endif
1114 tci_write_reg16(t0, tmp16);
1115 break;
1116 case INDEX_op_qemu_ld16s:
1117 t0 = *tb_ptr++;
1118 taddr = tci_read_ulong(&tb_ptr);
1119 #ifdef CONFIG_SOFTMMU
1120 tmp16 = helper_ldw_mmu(env, taddr, tci_read_i(&tb_ptr));
1121 #else
1122 host_addr = (tcg_target_ulong)taddr;
1123 assert(taddr == host_addr);
1124 tmp16 = tswap16(*(uint16_t *)(host_addr + GUEST_BASE));
1125 #endif
1126 tci_write_reg16s(t0, tmp16);
1127 break;
1128 #if TCG_TARGET_REG_BITS == 64
1129 case INDEX_op_qemu_ld32u:
1130 t0 = *tb_ptr++;
1131 taddr = tci_read_ulong(&tb_ptr);
1132 #ifdef CONFIG_SOFTMMU
1133 tmp32 = helper_ldl_mmu(env, taddr, tci_read_i(&tb_ptr));
1134 #else
1135 host_addr = (tcg_target_ulong)taddr;
1136 assert(taddr == host_addr);
1137 tmp32 = tswap32(*(uint32_t *)(host_addr + GUEST_BASE));
1138 #endif
1139 tci_write_reg32(t0, tmp32);
1140 break;
1141 case INDEX_op_qemu_ld32s:
1142 t0 = *tb_ptr++;
1143 taddr = tci_read_ulong(&tb_ptr);
1144 #ifdef CONFIG_SOFTMMU
1145 tmp32 = helper_ldl_mmu(env, taddr, tci_read_i(&tb_ptr));
1146 #else
1147 host_addr = (tcg_target_ulong)taddr;
1148 assert(taddr == host_addr);
1149 tmp32 = tswap32(*(uint32_t *)(host_addr + GUEST_BASE));
1150 #endif
1151 tci_write_reg32s(t0, tmp32);
1152 break;
1153 #endif /* TCG_TARGET_REG_BITS == 64 */
1154 case INDEX_op_qemu_ld32:
1155 t0 = *tb_ptr++;
1156 taddr = tci_read_ulong(&tb_ptr);
1157 #ifdef CONFIG_SOFTMMU
1158 tmp32 = helper_ldl_mmu(env, taddr, tci_read_i(&tb_ptr));
1159 #else
1160 host_addr = (tcg_target_ulong)taddr;
1161 assert(taddr == host_addr);
1162 tmp32 = tswap32(*(uint32_t *)(host_addr + GUEST_BASE));
1163 #endif
1164 tci_write_reg32(t0, tmp32);
1165 break;
1166 case INDEX_op_qemu_ld64:
1167 t0 = *tb_ptr++;
1168 #if TCG_TARGET_REG_BITS == 32
1169 t1 = *tb_ptr++;
1170 #endif
1171 taddr = tci_read_ulong(&tb_ptr);
1172 #ifdef CONFIG_SOFTMMU
1173 tmp64 = helper_ldq_mmu(env, taddr, tci_read_i(&tb_ptr));
1174 #else
1175 host_addr = (tcg_target_ulong)taddr;
1176 assert(taddr == host_addr);
1177 tmp64 = tswap64(*(uint64_t *)(host_addr + GUEST_BASE));
1178 #endif
1179 tci_write_reg(t0, tmp64);
1180 #if TCG_TARGET_REG_BITS == 32
1181 tci_write_reg(t1, tmp64 >> 32);
1182 #endif
1183 break;
1184 case INDEX_op_qemu_st8:
1185 t0 = tci_read_r8(&tb_ptr);
1186 taddr = tci_read_ulong(&tb_ptr);
1187 #ifdef CONFIG_SOFTMMU
1188 t2 = tci_read_i(&tb_ptr);
1189 helper_stb_mmu(env, taddr, t0, t2);
1190 #else
1191 host_addr = (tcg_target_ulong)taddr;
1192 assert(taddr == host_addr);
1193 *(uint8_t *)(host_addr + GUEST_BASE) = t0;
1194 #endif
1195 break;
1196 case INDEX_op_qemu_st16:
1197 t0 = tci_read_r16(&tb_ptr);
1198 taddr = tci_read_ulong(&tb_ptr);
1199 #ifdef CONFIG_SOFTMMU
1200 t2 = tci_read_i(&tb_ptr);
1201 helper_stw_mmu(env, taddr, t0, t2);
1202 #else
1203 host_addr = (tcg_target_ulong)taddr;
1204 assert(taddr == host_addr);
1205 *(uint16_t *)(host_addr + GUEST_BASE) = tswap16(t0);
1206 #endif
1207 break;
1208 case INDEX_op_qemu_st32:
1209 t0 = tci_read_r32(&tb_ptr);
1210 taddr = tci_read_ulong(&tb_ptr);
1211 #ifdef CONFIG_SOFTMMU
1212 t2 = tci_read_i(&tb_ptr);
1213 helper_stl_mmu(env, taddr, t0, t2);
1214 #else
1215 host_addr = (tcg_target_ulong)taddr;
1216 assert(taddr == host_addr);
1217 *(uint32_t *)(host_addr + GUEST_BASE) = tswap32(t0);
1218 #endif
1219 break;
1220 case INDEX_op_qemu_st64:
1221 tmp64 = tci_read_r64(&tb_ptr);
1222 taddr = tci_read_ulong(&tb_ptr);
1223 #ifdef CONFIG_SOFTMMU
1224 t2 = tci_read_i(&tb_ptr);
1225 helper_stq_mmu(env, taddr, tmp64, t2);
1226 #else
1227 host_addr = (tcg_target_ulong)taddr;
1228 assert(taddr == host_addr);
1229 *(uint64_t *)(host_addr + GUEST_BASE) = tswap64(tmp64);
1230 #endif
1231 break;
1232 default:
1233 TODO();
1234 break;
1235 }
1236 assert(tb_ptr == old_code_ptr + op_size);
1237 }
1238 exit:
1239 return next_tb;
1240 }
Qemu copy for testing