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added nop test for exception
[qemu.git] / vl.c
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include <stdlib.h>
25 #include <stdio.h>
26 #include <stdarg.h>
27 #include <string.h>
28 #include <getopt.h>
29 #include <inttypes.h>
30 #include <unistd.h>
31 #include <sys/mman.h>
32 #include <fcntl.h>
33 #include <signal.h>
34 #include <time.h>
35 #include <sys/time.h>
36 #include <malloc.h>
37 #include <termios.h>
38 #include <sys/poll.h>
39 #include <errno.h>
40 #include <sys/wait.h>
41
42 #include <sys/ioctl.h>
43 #include <sys/socket.h>
44 #include <linux/if.h>
45 #include <linux/if_tun.h>
46
47 #include "cpu-i386.h"
48 #include "disas.h"
49 #include "thunk.h"
50
51 #include "vl.h"
52
53 #define DEBUG_LOGFILE "/tmp/vl.log"
54 #define DEFAULT_NETWORK_SCRIPT "/etc/vl-ifup"
55
56 //#define DEBUG_UNUSED_IOPORT
57 //#define DEBUG_IRQ_LATENCY
58
59 #define PHYS_RAM_BASE 0xac000000
60 #define PHYS_RAM_MAX_SIZE (256 * 1024 * 1024)
61
62 #define KERNEL_LOAD_ADDR 0x00100000
63 #define INITRD_LOAD_ADDR 0x00400000
64 #define KERNEL_PARAMS_ADDR 0x00090000
65
66 #define MAX_DISKS 2
67
68 /* from plex86 (BSD license) */
69 struct __attribute__ ((packed)) linux_params {
70 // For 0x00..0x3f, see 'struct screen_info' in linux/include/linux/tty.h.
71 // I just padded out the VESA parts, rather than define them.
72
73 /* 0x000 */ uint8_t orig_x;
74 /* 0x001 */ uint8_t orig_y;
75 /* 0x002 */ uint16_t ext_mem_k;
76 /* 0x004 */ uint16_t orig_video_page;
77 /* 0x006 */ uint8_t orig_video_mode;
78 /* 0x007 */ uint8_t orig_video_cols;
79 /* 0x008 */ uint16_t unused1;
80 /* 0x00a */ uint16_t orig_video_ega_bx;
81 /* 0x00c */ uint16_t unused2;
82 /* 0x00e */ uint8_t orig_video_lines;
83 /* 0x00f */ uint8_t orig_video_isVGA;
84 /* 0x010 */ uint16_t orig_video_points;
85 /* 0x012 */ uint8_t pad0[0x20 - 0x12]; // VESA info.
86 /* 0x020 */ uint16_t cl_magic; // Commandline magic number (0xA33F)
87 /* 0x022 */ uint16_t cl_offset; // Commandline offset. Address of commandline
88 // is calculated as 0x90000 + cl_offset, bu
89 // only if cl_magic == 0xA33F.
90 /* 0x024 */ uint8_t pad1[0x40 - 0x24]; // VESA info.
91
92 /* 0x040 */ uint8_t apm_bios_info[20]; // struct apm_bios_info
93 /* 0x054 */ uint8_t pad2[0x80 - 0x54];
94
95 // Following 2 from 'struct drive_info_struct' in drivers/block/cciss.h.
96 // Might be truncated?
97 /* 0x080 */ uint8_t hd0_info[16]; // hd0-disk-parameter from intvector 0x41
98 /* 0x090 */ uint8_t hd1_info[16]; // hd1-disk-parameter from intvector 0x46
99
100 // System description table truncated to 16 bytes
101 // From 'struct sys_desc_table_struct' in linux/arch/i386/kernel/setup.c.
102 /* 0x0a0 */ uint16_t sys_description_len;
103 /* 0x0a2 */ uint8_t sys_description_table[14];
104 // [0] machine id
105 // [1] machine submodel id
106 // [2] BIOS revision
107 // [3] bit1: MCA bus
108
109 /* 0x0b0 */ uint8_t pad3[0x1e0 - 0xb0];
110 /* 0x1e0 */ uint32_t alt_mem_k;
111 /* 0x1e4 */ uint8_t pad4[4];
112 /* 0x1e8 */ uint8_t e820map_entries;
113 /* 0x1e9 */ uint8_t eddbuf_entries; // EDD_NR
114 /* 0x1ea */ uint8_t pad5[0x1f1 - 0x1ea];
115 /* 0x1f1 */ uint8_t setup_sects; // size of setup.S, number of sectors
116 /* 0x1f2 */ uint16_t mount_root_rdonly; // MOUNT_ROOT_RDONLY (if !=0)
117 /* 0x1f4 */ uint16_t sys_size; // size of compressed kernel-part in the
118 // (b)zImage-file (in 16 byte units, rounded up)
119 /* 0x1f6 */ uint16_t swap_dev; // (unused AFAIK)
120 /* 0x1f8 */ uint16_t ramdisk_flags;
121 /* 0x1fa */ uint16_t vga_mode; // (old one)
122 /* 0x1fc */ uint16_t orig_root_dev; // (high=Major, low=minor)
123 /* 0x1fe */ uint8_t pad6[1];
124 /* 0x1ff */ uint8_t aux_device_info;
125 /* 0x200 */ uint16_t jump_setup; // Jump to start of setup code,
126 // aka "reserved" field.
127 /* 0x202 */ uint8_t setup_signature[4]; // Signature for SETUP-header, ="HdrS"
128 /* 0x206 */ uint16_t header_format_version; // Version number of header format;
129 /* 0x208 */ uint8_t setup_S_temp0[8]; // Used by setup.S for communication with
130 // boot loaders, look there.
131 /* 0x210 */ uint8_t loader_type;
132 // 0 for old one.
133 // else 0xTV:
134 // T=0: LILO
135 // T=1: Loadlin
136 // T=2: bootsect-loader
137 // T=3: SYSLINUX
138 // T=4: ETHERBOOT
139 // V=version
140 /* 0x211 */ uint8_t loadflags;
141 // bit0 = 1: kernel is loaded high (bzImage)
142 // bit7 = 1: Heap and pointer (see below) set by boot
143 // loader.
144 /* 0x212 */ uint16_t setup_S_temp1;
145 /* 0x214 */ uint32_t kernel_start;
146 /* 0x218 */ uint32_t initrd_start;
147 /* 0x21c */ uint32_t initrd_size;
148 /* 0x220 */ uint8_t setup_S_temp2[4];
149 /* 0x224 */ uint16_t setup_S_heap_end_pointer;
150 /* 0x226 */ uint8_t pad7[0x2d0 - 0x226];
151
152 /* 0x2d0 : Int 15, ax=e820 memory map. */
153 // (linux/include/asm-i386/e820.h, 'struct e820entry')
154 #define E820MAX 32
155 #define E820_RAM 1
156 #define E820_RESERVED 2
157 #define E820_ACPI 3 /* usable as RAM once ACPI tables have been read */
158 #define E820_NVS 4
159 struct {
160 uint64_t addr;
161 uint64_t size;
162 uint32_t type;
163 } e820map[E820MAX];
164
165 /* 0x550 */ uint8_t pad8[0x600 - 0x550];
166
167 // BIOS Enhanced Disk Drive Services.
168 // (From linux/include/asm-i386/edd.h, 'struct edd_info')
169 // Each 'struct edd_info is 78 bytes, times a max of 6 structs in array.
170 /* 0x600 */ uint8_t eddbuf[0x7d4 - 0x600];
171
172 /* 0x7d4 */ uint8_t pad9[0x800 - 0x7d4];
173 /* 0x800 */ uint8_t commandline[0x800];
174
175 /* 0x1000 */
176 uint64_t gdt_table[256];
177 uint64_t idt_table[48];
178 };
179
180 #define KERNEL_CS 0x10
181 #define KERNEL_DS 0x18
182
183 typedef void (IOPortWriteFunc)(CPUX86State *env, uint32_t address, uint32_t data);
184 typedef uint32_t (IOPortReadFunc)(CPUX86State *env, uint32_t address);
185
186 #define MAX_IOPORTS 4096
187
188 char phys_ram_file[1024];
189 CPUX86State *global_env;
190 CPUX86State *cpu_single_env;
191 FILE *logfile = NULL;
192 int loglevel;
193 IOPortReadFunc *ioport_read_table[3][MAX_IOPORTS];
194 IOPortWriteFunc *ioport_write_table[3][MAX_IOPORTS];
195 BlockDriverState *bs_table[MAX_DISKS];
196
197 /***********************************************************/
198 /* x86 io ports */
199
200 uint32_t default_ioport_readb(CPUX86State *env, uint32_t address)
201 {
202 #ifdef DEBUG_UNUSED_IOPORT
203 fprintf(stderr, "inb: port=0x%04x\n", address);
204 #endif
205 return 0xff;
206 }
207
208 void default_ioport_writeb(CPUX86State *env, uint32_t address, uint32_t data)
209 {
210 #ifdef DEBUG_UNUSED_IOPORT
211 fprintf(stderr, "outb: port=0x%04x data=0x%02x\n", address, data);
212 #endif
213 }
214
215 /* default is to make two byte accesses */
216 uint32_t default_ioport_readw(CPUX86State *env, uint32_t address)
217 {
218 uint32_t data;
219 data = ioport_read_table[0][address](env, address);
220 data |= ioport_read_table[0][address + 1](env, address + 1) << 8;
221 return data;
222 }
223
224 void default_ioport_writew(CPUX86State *env, uint32_t address, uint32_t data)
225 {
226 ioport_write_table[0][address](env, address, data & 0xff);
227 ioport_write_table[0][address + 1](env, address + 1, (data >> 8) & 0xff);
228 }
229
230 uint32_t default_ioport_readl(CPUX86State *env, uint32_t address)
231 {
232 #ifdef DEBUG_UNUSED_IOPORT
233 fprintf(stderr, "inl: port=0x%04x\n", address);
234 #endif
235 return 0xffffffff;
236 }
237
238 void default_ioport_writel(CPUX86State *env, uint32_t address, uint32_t data)
239 {
240 #ifdef DEBUG_UNUSED_IOPORT
241 fprintf(stderr, "outl: port=0x%04x data=0x%02x\n", address, data);
242 #endif
243 }
244
245 void init_ioports(void)
246 {
247 int i;
248
249 for(i = 0; i < MAX_IOPORTS; i++) {
250 ioport_read_table[0][i] = default_ioport_readb;
251 ioport_write_table[0][i] = default_ioport_writeb;
252 ioport_read_table[1][i] = default_ioport_readw;
253 ioport_write_table[1][i] = default_ioport_writew;
254 ioport_read_table[2][i] = default_ioport_readl;
255 ioport_write_table[2][i] = default_ioport_writel;
256 }
257 }
258
259 /* size is the word size in byte */
260 int register_ioport_read(int start, int length, IOPortReadFunc *func, int size)
261 {
262 int i, bsize;
263
264 if (size == 1)
265 bsize = 0;
266 else if (size == 2)
267 bsize = 1;
268 else if (size == 4)
269 bsize = 2;
270 else
271 return -1;
272 for(i = start; i < start + length; i += size)
273 ioport_read_table[bsize][i] = func;
274 return 0;
275 }
276
277 /* size is the word size in byte */
278 int register_ioport_write(int start, int length, IOPortWriteFunc *func, int size)
279 {
280 int i, bsize;
281
282 if (size == 1)
283 bsize = 0;
284 else if (size == 2)
285 bsize = 1;
286 else if (size == 4)
287 bsize = 2;
288 else
289 return -1;
290 for(i = start; i < start + length; i += size)
291 ioport_write_table[bsize][i] = func;
292 return 0;
293 }
294
295 void pstrcpy(char *buf, int buf_size, const char *str)
296 {
297 int c;
298 char *q = buf;
299
300 if (buf_size <= 0)
301 return;
302
303 for(;;) {
304 c = *str++;
305 if (c == 0 || q >= buf + buf_size - 1)
306 break;
307 *q++ = c;
308 }
309 *q = '\0';
310 }
311
312 /* strcat and truncate. */
313 char *pstrcat(char *buf, int buf_size, const char *s)
314 {
315 int len;
316 len = strlen(buf);
317 if (len < buf_size)
318 pstrcpy(buf + len, buf_size - len, s);
319 return buf;
320 }
321
322 int load_kernel(const char *filename, uint8_t *addr)
323 {
324 int fd, size, setup_sects;
325 uint8_t bootsect[512];
326
327 fd = open(filename, O_RDONLY);
328 if (fd < 0)
329 return -1;
330 if (read(fd, bootsect, 512) != 512)
331 goto fail;
332 setup_sects = bootsect[0x1F1];
333 if (!setup_sects)
334 setup_sects = 4;
335 /* skip 16 bit setup code */
336 lseek(fd, (setup_sects + 1) * 512, SEEK_SET);
337 size = read(fd, addr, 16 * 1024 * 1024);
338 if (size < 0)
339 goto fail;
340 close(fd);
341 return size;
342 fail:
343 close(fd);
344 return -1;
345 }
346
347 /* return the size or -1 if error */
348 int load_image(const char *filename, uint8_t *addr)
349 {
350 int fd, size;
351 fd = open(filename, O_RDONLY);
352 if (fd < 0)
353 return -1;
354 size = lseek(fd, 0, SEEK_END);
355 lseek(fd, 0, SEEK_SET);
356 if (read(fd, addr, size) != size) {
357 close(fd);
358 return -1;
359 }
360 close(fd);
361 return size;
362 }
363
364 void cpu_x86_outb(CPUX86State *env, int addr, int val)
365 {
366 ioport_write_table[0][addr & (MAX_IOPORTS - 1)](env, addr, val);
367 }
368
369 void cpu_x86_outw(CPUX86State *env, int addr, int val)
370 {
371 ioport_write_table[1][addr & (MAX_IOPORTS - 1)](env, addr, val);
372 }
373
374 void cpu_x86_outl(CPUX86State *env, int addr, int val)
375 {
376 ioport_write_table[2][addr & (MAX_IOPORTS - 1)](env, addr, val);
377 }
378
379 int cpu_x86_inb(CPUX86State *env, int addr)
380 {
381 return ioport_read_table[0][addr & (MAX_IOPORTS - 1)](env, addr);
382 }
383
384 int cpu_x86_inw(CPUX86State *env, int addr)
385 {
386 return ioport_read_table[1][addr & (MAX_IOPORTS - 1)](env, addr);
387 }
388
389 int cpu_x86_inl(CPUX86State *env, int addr)
390 {
391 return ioport_read_table[2][addr & (MAX_IOPORTS - 1)](env, addr);
392 }
393
394 /***********************************************************/
395 void ioport80_write(CPUX86State *env, uint32_t addr, uint32_t data)
396 {
397 }
398
399 void hw_error(const char *fmt, ...)
400 {
401 va_list ap;
402
403 va_start(ap, fmt);
404 fprintf(stderr, "qemu: hardware error: ");
405 vfprintf(stderr, fmt, ap);
406 fprintf(stderr, "\n");
407 #ifdef TARGET_I386
408 cpu_x86_dump_state(global_env, stderr, X86_DUMP_FPU | X86_DUMP_CCOP);
409 #endif
410 va_end(ap);
411 abort();
412 }
413
414 /***********************************************************/
415 /* vga emulation */
416 static uint8_t vga_index;
417 static uint8_t vga_regs[256];
418 static int last_cursor_pos;
419
420 void update_console_messages(void)
421 {
422 int c, i, cursor_pos, eol;
423
424 cursor_pos = vga_regs[0x0f] | (vga_regs[0x0e] << 8);
425 eol = 0;
426 for(i = last_cursor_pos; i < cursor_pos; i++) {
427 c = phys_ram_base[0xb8000 + (i) * 2];
428 if (c >= ' ') {
429 putchar(c);
430 eol = 0;
431 } else {
432 if (!eol)
433 putchar('\n');
434 eol = 1;
435 }
436 }
437 fflush(stdout);
438 last_cursor_pos = cursor_pos;
439 }
440
441 /* just to see first Linux console messages, we intercept cursor position */
442 void vga_ioport_write(CPUX86State *env, uint32_t addr, uint32_t data)
443 {
444 switch(addr) {
445 case 0x3d4:
446 vga_index = data;
447 break;
448 case 0x3d5:
449 vga_regs[vga_index] = data;
450 if (vga_index == 0x0f)
451 update_console_messages();
452 break;
453 }
454
455 }
456
457 /***********************************************************/
458 /* cmos emulation */
459
460 #define RTC_SECONDS 0
461 #define RTC_SECONDS_ALARM 1
462 #define RTC_MINUTES 2
463 #define RTC_MINUTES_ALARM 3
464 #define RTC_HOURS 4
465 #define RTC_HOURS_ALARM 5
466 #define RTC_ALARM_DONT_CARE 0xC0
467
468 #define RTC_DAY_OF_WEEK 6
469 #define RTC_DAY_OF_MONTH 7
470 #define RTC_MONTH 8
471 #define RTC_YEAR 9
472
473 #define RTC_REG_A 10
474 #define RTC_REG_B 11
475 #define RTC_REG_C 12
476 #define RTC_REG_D 13
477
478 /* PC cmos mappings */
479 #define REG_EQUIPMENT_BYTE 0x14
480
481 uint8_t cmos_data[128];
482 uint8_t cmos_index;
483
484 void cmos_ioport_write(CPUX86State *env, uint32_t addr, uint32_t data)
485 {
486 if (addr == 0x70) {
487 cmos_index = data & 0x7f;
488 }
489 }
490
491 uint32_t cmos_ioport_read(CPUX86State *env, uint32_t addr)
492 {
493 int ret;
494
495 if (addr == 0x70) {
496 return 0xff;
497 } else {
498 /* toggle update-in-progress bit for Linux (same hack as
499 plex86) */
500 ret = cmos_data[cmos_index];
501 if (cmos_index == RTC_REG_A)
502 cmos_data[RTC_REG_A] ^= 0x80;
503 else if (cmos_index == RTC_REG_C)
504 cmos_data[RTC_REG_C] = 0x00;
505 return ret;
506 }
507 }
508
509
510 static inline int to_bcd(int a)
511 {
512 return ((a / 10) << 4) | (a % 10);
513 }
514
515 void cmos_init(void)
516 {
517 struct tm *tm;
518 time_t ti;
519
520 ti = time(NULL);
521 tm = gmtime(&ti);
522 cmos_data[RTC_SECONDS] = to_bcd(tm->tm_sec);
523 cmos_data[RTC_MINUTES] = to_bcd(tm->tm_min);
524 cmos_data[RTC_HOURS] = to_bcd(tm->tm_hour);
525 cmos_data[RTC_DAY_OF_WEEK] = to_bcd(tm->tm_wday);
526 cmos_data[RTC_DAY_OF_MONTH] = to_bcd(tm->tm_mday);
527 cmos_data[RTC_MONTH] = to_bcd(tm->tm_mon + 1);
528 cmos_data[RTC_YEAR] = to_bcd(tm->tm_year % 100);
529
530 cmos_data[RTC_REG_A] = 0x26;
531 cmos_data[RTC_REG_B] = 0x02;
532 cmos_data[RTC_REG_C] = 0x00;
533 cmos_data[RTC_REG_D] = 0x80;
534
535 cmos_data[REG_EQUIPMENT_BYTE] = 0x02; /* FPU is there */
536
537 register_ioport_write(0x70, 2, cmos_ioport_write, 1);
538 register_ioport_read(0x70, 2, cmos_ioport_read, 1);
539 }
540
541 /***********************************************************/
542 /* 8259 pic emulation */
543
544 //#define DEBUG_PIC
545
546 typedef struct PicState {
547 uint8_t last_irr; /* edge detection */
548 uint8_t irr; /* interrupt request register */
549 uint8_t imr; /* interrupt mask register */
550 uint8_t isr; /* interrupt service register */
551 uint8_t priority_add; /* used to compute irq priority */
552 uint8_t irq_base;
553 uint8_t read_reg_select;
554 uint8_t special_mask;
555 uint8_t init_state;
556 uint8_t auto_eoi;
557 uint8_t rotate_on_autoeoi;
558 uint8_t init4; /* true if 4 byte init */
559 } PicState;
560
561 /* 0 is master pic, 1 is slave pic */
562 PicState pics[2];
563 int pic_irq_requested;
564
565 /* set irq level. If an edge is detected, then the IRR is set to 1 */
566 static inline void pic_set_irq1(PicState *s, int irq, int level)
567 {
568 int mask;
569 mask = 1 << irq;
570 if (level) {
571 if ((s->last_irr & mask) == 0)
572 s->irr |= mask;
573 s->last_irr |= mask;
574 } else {
575 s->last_irr &= ~mask;
576 }
577 }
578
579 static inline int get_priority(PicState *s, int mask)
580 {
581 int priority;
582 if (mask == 0)
583 return -1;
584 priority = 7;
585 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
586 priority--;
587 return priority;
588 }
589
590 /* return the pic wanted interrupt. return -1 if none */
591 static int pic_get_irq(PicState *s)
592 {
593 int mask, cur_priority, priority;
594
595 mask = s->irr & ~s->imr;
596 priority = get_priority(s, mask);
597 if (priority < 0)
598 return -1;
599 /* compute current priority */
600 cur_priority = get_priority(s, s->isr);
601 if (priority > cur_priority) {
602 /* higher priority found: an irq should be generated */
603 return priority;
604 } else {
605 return -1;
606 }
607 }
608
609 /* raise irq to CPU if necessary. must be called every time the active
610 irq may change */
611 static void pic_update_irq(void)
612 {
613 int irq2, irq;
614
615 /* first look at slave pic */
616 irq2 = pic_get_irq(&pics[1]);
617 if (irq2 >= 0) {
618 /* if irq request by slave pic, signal master PIC */
619 pic_set_irq1(&pics[0], 2, 1);
620 pic_set_irq1(&pics[0], 2, 0);
621 }
622 /* look at requested irq */
623 irq = pic_get_irq(&pics[0]);
624 if (irq >= 0) {
625 if (irq == 2) {
626 /* from slave pic */
627 pic_irq_requested = 8 + irq2;
628 } else {
629 /* from master pic */
630 pic_irq_requested = irq;
631 }
632 cpu_x86_interrupt(global_env, CPU_INTERRUPT_HARD);
633 }
634 }
635
636 #ifdef DEBUG_IRQ_LATENCY
637 int64_t irq_time[16];
638 int64_t cpu_get_ticks(void);
639 #endif
640 #ifdef DEBUG_PIC
641 int irq_level[16];
642 #endif
643
644 void pic_set_irq(int irq, int level)
645 {
646 #ifdef DEBUG_PIC
647 if (level != irq_level[irq]) {
648 printf("pic_set_irq: irq=%d level=%d\n", irq, level);
649 irq_level[irq] = level;
650 }
651 #endif
652 #ifdef DEBUG_IRQ_LATENCY
653 if (level) {
654 irq_time[irq] = cpu_get_ticks();
655 }
656 #endif
657 pic_set_irq1(&pics[irq >> 3], irq & 7, level);
658 pic_update_irq();
659 }
660
661 int cpu_x86_get_pic_interrupt(CPUX86State *env)
662 {
663 int irq, irq2, intno;
664
665 /* signal the pic that the irq was acked by the CPU */
666 irq = pic_irq_requested;
667 #ifdef DEBUG_IRQ_LATENCY
668 printf("IRQ%d latency=%Ld\n", irq, cpu_get_ticks() - irq_time[irq]);
669 #endif
670 #ifdef DEBUG_PIC
671 printf("pic_interrupt: irq=%d\n", irq);
672 #endif
673
674 if (irq >= 8) {
675 irq2 = irq & 7;
676 pics[1].isr |= (1 << irq2);
677 pics[1].irr &= ~(1 << irq2);
678 irq = 2;
679 intno = pics[1].irq_base + irq2;
680 } else {
681 intno = pics[0].irq_base + irq;
682 }
683 pics[0].isr |= (1 << irq);
684 pics[0].irr &= ~(1 << irq);
685 return intno;
686 }
687
688 void pic_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
689 {
690 PicState *s;
691 int priority;
692
693 #ifdef DEBUG_PIC
694 printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
695 #endif
696 s = &pics[addr >> 7];
697 addr &= 1;
698 if (addr == 0) {
699 if (val & 0x10) {
700 /* init */
701 memset(s, 0, sizeof(PicState));
702 s->init_state = 1;
703 s->init4 = val & 1;
704 if (val & 0x02)
705 hw_error("single mode not supported");
706 if (val & 0x08)
707 hw_error("level sensitive irq not supported");
708 } else if (val & 0x08) {
709 if (val & 0x02)
710 s->read_reg_select = val & 1;
711 if (val & 0x40)
712 s->special_mask = (val >> 5) & 1;
713 } else {
714 switch(val) {
715 case 0x00:
716 case 0x80:
717 s->rotate_on_autoeoi = val >> 7;
718 break;
719 case 0x20: /* end of interrupt */
720 case 0xa0:
721 priority = get_priority(s, s->isr);
722 if (priority >= 0) {
723 s->isr &= ~(1 << ((priority + s->priority_add) & 7));
724 }
725 if (val == 0xa0)
726 s->priority_add = (s->priority_add + 1) & 7;
727 break;
728 case 0x60 ... 0x67:
729 priority = val & 7;
730 s->isr &= ~(1 << priority);
731 break;
732 case 0xc0 ... 0xc7:
733 s->priority_add = (val + 1) & 7;
734 break;
735 case 0xe0 ... 0xe7:
736 priority = val & 7;
737 s->isr &= ~(1 << priority);
738 s->priority_add = (priority + 1) & 7;
739 break;
740 }
741 }
742 } else {
743 switch(s->init_state) {
744 case 0:
745 /* normal mode */
746 s->imr = val;
747 pic_update_irq();
748 break;
749 case 1:
750 s->irq_base = val & 0xf8;
751 s->init_state = 2;
752 break;
753 case 2:
754 if (s->init4) {
755 s->init_state = 3;
756 } else {
757 s->init_state = 0;
758 }
759 break;
760 case 3:
761 s->auto_eoi = (val >> 1) & 1;
762 s->init_state = 0;
763 break;
764 }
765 }
766 }
767
768 uint32_t pic_ioport_read(CPUX86State *env, uint32_t addr1)
769 {
770 PicState *s;
771 unsigned int addr;
772 int ret;
773
774 addr = addr1;
775 s = &pics[addr >> 7];
776 addr &= 1;
777 if (addr == 0) {
778 if (s->read_reg_select)
779 ret = s->isr;
780 else
781 ret = s->irr;
782 } else {
783 ret = s->imr;
784 }
785 #ifdef DEBUG_PIC
786 printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
787 #endif
788 return ret;
789 }
790
791 void pic_init(void)
792 {
793 register_ioport_write(0x20, 2, pic_ioport_write, 1);
794 register_ioport_read(0x20, 2, pic_ioport_read, 1);
795 register_ioport_write(0xa0, 2, pic_ioport_write, 1);
796 register_ioport_read(0xa0, 2, pic_ioport_read, 1);
797 }
798
799 /***********************************************************/
800 /* 8253 PIT emulation */
801
802 #define PIT_FREQ 1193182
803
804 #define RW_STATE_LSB 0
805 #define RW_STATE_MSB 1
806 #define RW_STATE_WORD0 2
807 #define RW_STATE_WORD1 3
808 #define RW_STATE_LATCHED_WORD0 4
809 #define RW_STATE_LATCHED_WORD1 5
810
811 typedef struct PITChannelState {
812 int count; /* can be 65536 */
813 uint16_t latched_count;
814 uint8_t rw_state;
815 uint8_t mode;
816 uint8_t bcd; /* not supported */
817 uint8_t gate; /* timer start */
818 int64_t count_load_time;
819 int64_t count_last_edge_check_time;
820 } PITChannelState;
821
822 PITChannelState pit_channels[3];
823 int speaker_data_on;
824 int pit_min_timer_count = 0;
825
826 int64_t ticks_per_sec;
827
828 int64_t get_clock(void)
829 {
830 struct timeval tv;
831 gettimeofday(&tv, NULL);
832 return tv.tv_sec * 1000000LL + tv.tv_usec;
833 }
834
835 int64_t cpu_get_ticks(void)
836 {
837 int64_t val;
838 asm("rdtsc" : "=A" (val));
839 return val;
840 }
841
842 void cpu_calibrate_ticks(void)
843 {
844 int64_t usec, ticks;
845
846 usec = get_clock();
847 ticks = cpu_get_ticks();
848 usleep(50 * 1000);
849 usec = get_clock() - usec;
850 ticks = cpu_get_ticks() - ticks;
851 ticks_per_sec = (ticks * 1000000LL + (usec >> 1)) / usec;
852 }
853
854 /* compute with 96 bit intermediate result: (a*b)/c */
855 static uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c)
856 {
857 union {
858 uint64_t ll;
859 struct {
860 #ifdef WORDS_BIGENDIAN
861 uint32_t high, low;
862 #else
863 uint32_t low, high;
864 #endif
865 } l;
866 } u, res;
867 uint64_t rl, rh;
868
869 u.ll = a;
870 rl = (uint64_t)u.l.low * (uint64_t)b;
871 rh = (uint64_t)u.l.high * (uint64_t)b;
872 rh += (rl >> 32);
873 res.l.high = rh / c;
874 res.l.low = (((rh % c) << 32) + (rl & 0xffffffff)) / c;
875 return res.ll;
876 }
877
878 static int pit_get_count(PITChannelState *s)
879 {
880 uint64_t d;
881 int counter;
882
883 d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec);
884 switch(s->mode) {
885 case 0:
886 case 1:
887 case 4:
888 case 5:
889 counter = (s->count - d) & 0xffff;
890 break;
891 default:
892 counter = s->count - (d % s->count);
893 break;
894 }
895 return counter;
896 }
897
898 /* get pit output bit */
899 static int pit_get_out(PITChannelState *s)
900 {
901 uint64_t d;
902 int out;
903
904 d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec);
905 switch(s->mode) {
906 default:
907 case 0:
908 out = (d >= s->count);
909 break;
910 case 1:
911 out = (d < s->count);
912 break;
913 case 2:
914 if ((d % s->count) == 0 && d != 0)
915 out = 1;
916 else
917 out = 0;
918 break;
919 case 3:
920 out = (d % s->count) < (s->count >> 1);
921 break;
922 case 4:
923 case 5:
924 out = (d == s->count);
925 break;
926 }
927 return out;
928 }
929
930 /* get the number of 0 to 1 transitions we had since we call this
931 function */
932 /* XXX: maybe better to use ticks precision to avoid getting edges
933 twice if checks are done at very small intervals */
934 static int pit_get_out_edges(PITChannelState *s)
935 {
936 uint64_t d1, d2;
937 int64_t ticks;
938 int ret, v;
939
940 ticks = cpu_get_ticks();
941 d1 = muldiv64(s->count_last_edge_check_time - s->count_load_time,
942 PIT_FREQ, ticks_per_sec);
943 d2 = muldiv64(ticks - s->count_load_time,
944 PIT_FREQ, ticks_per_sec);
945 s->count_last_edge_check_time = ticks;
946 switch(s->mode) {
947 default:
948 case 0:
949 if (d1 < s->count && d2 >= s->count)
950 ret = 1;
951 else
952 ret = 0;
953 break;
954 case 1:
955 ret = 0;
956 break;
957 case 2:
958 d1 /= s->count;
959 d2 /= s->count;
960 ret = d2 - d1;
961 break;
962 case 3:
963 v = s->count - (s->count >> 1);
964 d1 = (d1 + v) / s->count;
965 d2 = (d2 + v) / s->count;
966 ret = d2 - d1;
967 break;
968 case 4:
969 case 5:
970 if (d1 < s->count && d2 >= s->count)
971 ret = 1;
972 else
973 ret = 0;
974 break;
975 }
976 return ret;
977 }
978
979 static inline void pit_load_count(PITChannelState *s, int val)
980 {
981 if (val == 0)
982 val = 0x10000;
983 s->count_load_time = cpu_get_ticks();
984 s->count_last_edge_check_time = s->count_load_time;
985 s->count = val;
986 if (s == &pit_channels[0] && val <= pit_min_timer_count) {
987 fprintf(stderr,
988 "\nWARNING: vl: on your system, accurate timer emulation is impossible if its frequency is more than %d Hz. If using a 2.5.xx Linux kernel, you must patch asm/param.h to change HZ from 1000 to 100.\n\n",
989 PIT_FREQ / pit_min_timer_count);
990 }
991 }
992
993 void pit_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
994 {
995 int channel, access;
996 PITChannelState *s;
997
998 addr &= 3;
999 if (addr == 3) {
1000 channel = val >> 6;
1001 if (channel == 3)
1002 return;
1003 s = &pit_channels[channel];
1004 access = (val >> 4) & 3;
1005 switch(access) {
1006 case 0:
1007 s->latched_count = pit_get_count(s);
1008 s->rw_state = RW_STATE_LATCHED_WORD0;
1009 break;
1010 default:
1011 s->mode = (val >> 1) & 7;
1012 s->bcd = val & 1;
1013 s->rw_state = access - 1 + RW_STATE_LSB;
1014 break;
1015 }
1016 } else {
1017 s = &pit_channels[addr];
1018 switch(s->rw_state) {
1019 case RW_STATE_LSB:
1020 pit_load_count(s, val);
1021 break;
1022 case RW_STATE_MSB:
1023 pit_load_count(s, val << 8);
1024 break;
1025 case RW_STATE_WORD0:
1026 case RW_STATE_WORD1:
1027 if (s->rw_state & 1) {
1028 pit_load_count(s, (s->latched_count & 0xff) | (val << 8));
1029 } else {
1030 s->latched_count = val;
1031 }
1032 s->rw_state ^= 1;
1033 break;
1034 }
1035 }
1036 }
1037
1038 uint32_t pit_ioport_read(CPUX86State *env, uint32_t addr)
1039 {
1040 int ret, count;
1041 PITChannelState *s;
1042
1043 addr &= 3;
1044 s = &pit_channels[addr];
1045 switch(s->rw_state) {
1046 case RW_STATE_LSB:
1047 case RW_STATE_MSB:
1048 case RW_STATE_WORD0:
1049 case RW_STATE_WORD1:
1050 count = pit_get_count(s);
1051 if (s->rw_state & 1)
1052 ret = (count >> 8) & 0xff;
1053 else
1054 ret = count & 0xff;
1055 if (s->rw_state & 2)
1056 s->rw_state ^= 1;
1057 break;
1058 default:
1059 case RW_STATE_LATCHED_WORD0:
1060 case RW_STATE_LATCHED_WORD1:
1061 if (s->rw_state & 1)
1062 ret = s->latched_count >> 8;
1063 else
1064 ret = s->latched_count & 0xff;
1065 s->rw_state ^= 1;
1066 break;
1067 }
1068 return ret;
1069 }
1070
1071 void speaker_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1072 {
1073 speaker_data_on = (val >> 1) & 1;
1074 pit_channels[2].gate = val & 1;
1075 }
1076
1077 uint32_t speaker_ioport_read(CPUX86State *env, uint32_t addr)
1078 {
1079 int out;
1080 out = pit_get_out(&pit_channels[2]);
1081 return (speaker_data_on << 1) | pit_channels[2].gate | (out << 5);
1082 }
1083
1084 void pit_init(void)
1085 {
1086 PITChannelState *s;
1087 int i;
1088
1089 cpu_calibrate_ticks();
1090
1091 for(i = 0;i < 3; i++) {
1092 s = &pit_channels[i];
1093 s->mode = 3;
1094 s->gate = (i != 2);
1095 pit_load_count(s, 0);
1096 }
1097
1098 register_ioport_write(0x40, 4, pit_ioport_write, 1);
1099 register_ioport_read(0x40, 3, pit_ioport_read, 1);
1100
1101 register_ioport_read(0x61, 1, speaker_ioport_read, 1);
1102 register_ioport_write(0x61, 1, speaker_ioport_write, 1);
1103 }
1104
1105 /***********************************************************/
1106 /* serial port emulation */
1107
1108 #define UART_IRQ 4
1109
1110 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
1111
1112 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
1113 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
1114 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
1115 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
1116
1117 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
1118 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
1119
1120 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
1121 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
1122 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
1123 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
1124
1125 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
1126 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
1127 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
1128 #define UART_LSR_FE 0x08 /* Frame error indicator */
1129 #define UART_LSR_PE 0x04 /* Parity error indicator */
1130 #define UART_LSR_OE 0x02 /* Overrun error indicator */
1131 #define UART_LSR_DR 0x01 /* Receiver data ready */
1132
1133 typedef struct SerialState {
1134 uint8_t divider;
1135 uint8_t rbr; /* receive register */
1136 uint8_t ier;
1137 uint8_t iir; /* read only */
1138 uint8_t lcr;
1139 uint8_t mcr;
1140 uint8_t lsr; /* read only */
1141 uint8_t msr;
1142 uint8_t scr;
1143 } SerialState;
1144
1145 SerialState serial_ports[1];
1146
1147 void serial_update_irq(void)
1148 {
1149 SerialState *s = &serial_ports[0];
1150
1151 if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
1152 s->iir = UART_IIR_RDI;
1153 } else if ((s->lsr & UART_LSR_THRE) && (s->ier & UART_IER_THRI)) {
1154 s->iir = UART_IIR_THRI;
1155 } else {
1156 s->iir = UART_IIR_NO_INT;
1157 }
1158 if (s->iir != UART_IIR_NO_INT) {
1159 pic_set_irq(UART_IRQ, 1);
1160 } else {
1161 pic_set_irq(UART_IRQ, 0);
1162 }
1163 }
1164
1165 void serial_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1166 {
1167 SerialState *s = &serial_ports[0];
1168 unsigned char ch;
1169 int ret;
1170
1171 addr &= 7;
1172 switch(addr) {
1173 default:
1174 case 0:
1175 if (s->lcr & UART_LCR_DLAB) {
1176 s->divider = (s->divider & 0xff00) | val;
1177 } else {
1178 s->lsr &= ~UART_LSR_THRE;
1179 serial_update_irq();
1180
1181 ch = val;
1182 do {
1183 ret = write(1, &ch, 1);
1184 } while (ret != 1);
1185 s->lsr |= UART_LSR_THRE;
1186 s->lsr |= UART_LSR_TEMT;
1187 serial_update_irq();
1188 }
1189 break;
1190 case 1:
1191 if (s->lcr & UART_LCR_DLAB) {
1192 s->divider = (s->divider & 0x00ff) | (val << 8);
1193 } else {
1194 s->ier = val;
1195 serial_update_irq();
1196 }
1197 break;
1198 case 2:
1199 break;
1200 case 3:
1201 s->lcr = val;
1202 break;
1203 case 4:
1204 s->mcr = val;
1205 break;
1206 case 5:
1207 break;
1208 case 6:
1209 s->msr = val;
1210 break;
1211 case 7:
1212 s->scr = val;
1213 break;
1214 }
1215 }
1216
1217 uint32_t serial_ioport_read(CPUX86State *env, uint32_t addr)
1218 {
1219 SerialState *s = &serial_ports[0];
1220 uint32_t ret;
1221
1222 addr &= 7;
1223 switch(addr) {
1224 default:
1225 case 0:
1226 if (s->lcr & UART_LCR_DLAB) {
1227 ret = s->divider & 0xff;
1228 } else {
1229 ret = s->rbr;
1230 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
1231 serial_update_irq();
1232 }
1233 break;
1234 case 1:
1235 if (s->lcr & UART_LCR_DLAB) {
1236 ret = (s->divider >> 8) & 0xff;
1237 } else {
1238 ret = s->ier;
1239 }
1240 break;
1241 case 2:
1242 ret = s->iir;
1243 break;
1244 case 3:
1245 ret = s->lcr;
1246 break;
1247 case 4:
1248 ret = s->mcr;
1249 break;
1250 case 5:
1251 ret = s->lsr;
1252 break;
1253 case 6:
1254 ret = s->msr;
1255 break;
1256 case 7:
1257 ret = s->scr;
1258 break;
1259 }
1260 return ret;
1261 }
1262
1263 #define TERM_ESCAPE 0x01 /* ctrl-a is used for escape */
1264 static int term_got_escape;
1265
1266 void term_print_help(void)
1267 {
1268 printf("\n"
1269 "C-a h print this help\n"
1270 "C-a x exit emulatior\n"
1271 "C-a s save disk data back to file (if -snapshot)\n"
1272 "C-a b send break (magic sysrq)\n"
1273 "C-a C-a send C-a\n"
1274 );
1275 }
1276
1277 /* called when a char is received */
1278 void serial_received_byte(SerialState *s, int ch)
1279 {
1280 if (term_got_escape) {
1281 term_got_escape = 0;
1282 switch(ch) {
1283 case 'h':
1284 term_print_help();
1285 break;
1286 case 'x':
1287 exit(0);
1288 break;
1289 case 's':
1290 {
1291 int i;
1292 for (i = 0; i < MAX_DISKS; i++) {
1293 if (bs_table[i])
1294 bdrv_commit(bs_table[i]);
1295 }
1296 }
1297 break;
1298 case 'b':
1299 /* send break */
1300 s->rbr = 0;
1301 s->lsr |= UART_LSR_BI | UART_LSR_DR;
1302 serial_update_irq();
1303 break;
1304 case TERM_ESCAPE:
1305 goto send_char;
1306 }
1307 } else if (ch == TERM_ESCAPE) {
1308 term_got_escape = 1;
1309 } else {
1310 send_char:
1311 s->rbr = ch;
1312 s->lsr |= UART_LSR_DR;
1313 serial_update_irq();
1314 }
1315 }
1316
1317 /* init terminal so that we can grab keys */
1318 static struct termios oldtty;
1319
1320 static void term_exit(void)
1321 {
1322 tcsetattr (0, TCSANOW, &oldtty);
1323 }
1324
1325 static void term_init(void)
1326 {
1327 struct termios tty;
1328
1329 tcgetattr (0, &tty);
1330 oldtty = tty;
1331
1332 tty.c_iflag &= ~(IGNBRK|BRKINT|PARMRK|ISTRIP
1333 |INLCR|IGNCR|ICRNL|IXON);
1334 tty.c_oflag |= OPOST;
1335 tty.c_lflag &= ~(ECHO|ECHONL|ICANON|IEXTEN|ISIG);
1336 tty.c_cflag &= ~(CSIZE|PARENB);
1337 tty.c_cflag |= CS8;
1338 tty.c_cc[VMIN] = 1;
1339 tty.c_cc[VTIME] = 0;
1340
1341 tcsetattr (0, TCSANOW, &tty);
1342
1343 atexit(term_exit);
1344
1345 fcntl(0, F_SETFL, O_NONBLOCK);
1346 }
1347
1348 void serial_init(void)
1349 {
1350 SerialState *s = &serial_ports[0];
1351
1352 s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
1353
1354 register_ioport_write(0x3f8, 8, serial_ioport_write, 1);
1355 register_ioport_read(0x3f8, 8, serial_ioport_read, 1);
1356
1357 term_init();
1358 }
1359
1360 /***********************************************************/
1361 /* ne2000 emulation */
1362
1363 //#define DEBUG_NE2000
1364
1365 #define NE2000_IOPORT 0x300
1366 #define NE2000_IRQ 9
1367
1368 #define MAX_ETH_FRAME_SIZE 1514
1369
1370 #define E8390_CMD 0x00 /* The command register (for all pages) */
1371 /* Page 0 register offsets. */
1372 #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */
1373 #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */
1374 #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
1375 #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */
1376 #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */
1377 #define EN0_TSR 0x04 /* Transmit status reg RD */
1378 #define EN0_TPSR 0x04 /* Transmit starting page WR */
1379 #define EN0_NCR 0x05 /* Number of collision reg RD */
1380 #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */
1381 #define EN0_FIFO 0x06 /* FIFO RD */
1382 #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
1383 #define EN0_ISR 0x07 /* Interrupt status reg RD WR */
1384 #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */
1385 #define EN0_RSARLO 0x08 /* Remote start address reg 0 */
1386 #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
1387 #define EN0_RSARHI 0x09 /* Remote start address reg 1 */
1388 #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
1389 #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
1390 #define EN0_RSR 0x0c /* rx status reg RD */
1391 #define EN0_RXCR 0x0c /* RX configuration reg WR */
1392 #define EN0_TXCR 0x0d /* TX configuration reg WR */
1393 #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */
1394 #define EN0_DCFG 0x0e /* Data configuration reg WR */
1395 #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */
1396 #define EN0_IMR 0x0f /* Interrupt mask reg WR */
1397 #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */
1398
1399 #define EN1_PHYS 0x11
1400 #define EN1_CURPAG 0x17
1401 #define EN1_MULT 0x18
1402
1403 /* Register accessed at EN_CMD, the 8390 base addr. */
1404 #define E8390_STOP 0x01 /* Stop and reset the chip */
1405 #define E8390_START 0x02 /* Start the chip, clear reset */
1406 #define E8390_TRANS 0x04 /* Transmit a frame */
1407 #define E8390_RREAD 0x08 /* Remote read */
1408 #define E8390_RWRITE 0x10 /* Remote write */
1409 #define E8390_NODMA 0x20 /* Remote DMA */
1410 #define E8390_PAGE0 0x00 /* Select page chip registers */
1411 #define E8390_PAGE1 0x40 /* using the two high-order bits */
1412 #define E8390_PAGE2 0x80 /* Page 3 is invalid. */
1413
1414 /* Bits in EN0_ISR - Interrupt status register */
1415 #define ENISR_RX 0x01 /* Receiver, no error */
1416 #define ENISR_TX 0x02 /* Transmitter, no error */
1417 #define ENISR_RX_ERR 0x04 /* Receiver, with error */
1418 #define ENISR_TX_ERR 0x08 /* Transmitter, with error */
1419 #define ENISR_OVER 0x10 /* Receiver overwrote the ring */
1420 #define ENISR_COUNTERS 0x20 /* Counters need emptying */
1421 #define ENISR_RDC 0x40 /* remote dma complete */
1422 #define ENISR_RESET 0x80 /* Reset completed */
1423 #define ENISR_ALL 0x3f /* Interrupts we will enable */
1424
1425 /* Bits in received packet status byte and EN0_RSR*/
1426 #define ENRSR_RXOK 0x01 /* Received a good packet */
1427 #define ENRSR_CRC 0x02 /* CRC error */
1428 #define ENRSR_FAE 0x04 /* frame alignment error */
1429 #define ENRSR_FO 0x08 /* FIFO overrun */
1430 #define ENRSR_MPA 0x10 /* missed pkt */
1431 #define ENRSR_PHY 0x20 /* physical/multicast address */
1432 #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
1433 #define ENRSR_DEF 0x80 /* deferring */
1434
1435 /* Transmitted packet status, EN0_TSR. */
1436 #define ENTSR_PTX 0x01 /* Packet transmitted without error */
1437 #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
1438 #define ENTSR_COL 0x04 /* The transmit collided at least once. */
1439 #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
1440 #define ENTSR_CRS 0x10 /* The carrier sense was lost. */
1441 #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
1442 #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
1443 #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
1444
1445 #define NE2000_MEM_SIZE 32768
1446
1447 typedef struct NE2000State {
1448 uint8_t cmd;
1449 uint32_t start;
1450 uint32_t stop;
1451 uint8_t boundary;
1452 uint8_t tsr;
1453 uint8_t tpsr;
1454 uint16_t tcnt;
1455 uint16_t rcnt;
1456 uint32_t rsar;
1457 uint8_t isr;
1458 uint8_t dcfg;
1459 uint8_t imr;
1460 uint8_t phys[6]; /* mac address */
1461 uint8_t curpag;
1462 uint8_t mult[8]; /* multicast mask array */
1463 uint8_t mem[NE2000_MEM_SIZE];
1464 } NE2000State;
1465
1466 NE2000State ne2000_state;
1467 int net_fd = -1;
1468 char network_script[1024];
1469
1470 void ne2000_reset(void)
1471 {
1472 NE2000State *s = &ne2000_state;
1473 int i;
1474
1475 s->isr = ENISR_RESET;
1476 s->mem[0] = 0x52;
1477 s->mem[1] = 0x54;
1478 s->mem[2] = 0x00;
1479 s->mem[3] = 0x12;
1480 s->mem[4] = 0x34;
1481 s->mem[5] = 0x56;
1482 s->mem[14] = 0x57;
1483 s->mem[15] = 0x57;
1484
1485 /* duplicate prom data */
1486 for(i = 15;i >= 0; i--) {
1487 s->mem[2 * i] = s->mem[i];
1488 s->mem[2 * i + 1] = s->mem[i];
1489 }
1490 }
1491
1492 void ne2000_update_irq(NE2000State *s)
1493 {
1494 int isr;
1495 isr = s->isr & s->imr;
1496 if (isr)
1497 pic_set_irq(NE2000_IRQ, 1);
1498 else
1499 pic_set_irq(NE2000_IRQ, 0);
1500 }
1501
1502 int net_init(void)
1503 {
1504 struct ifreq ifr;
1505 int fd, ret, pid, status;
1506
1507 fd = open("/dev/net/tun", O_RDWR);
1508 if (fd < 0) {
1509 fprintf(stderr, "warning: could not open /dev/net/tun: no virtual network emulation\n");
1510 return -1;
1511 }
1512 memset(&ifr, 0, sizeof(ifr));
1513 ifr.ifr_flags = IFF_TAP | IFF_NO_PI;
1514 pstrcpy(ifr.ifr_name, IFNAMSIZ, "tun%d");
1515 ret = ioctl(fd, TUNSETIFF, (void *) &ifr);
1516 if (ret != 0) {
1517 fprintf(stderr, "warning: could not configure /dev/net/tun: no virtual network emulation\n");
1518 close(fd);
1519 return -1;
1520 }
1521 printf("Connected to host network interface: %s\n", ifr.ifr_name);
1522 fcntl(fd, F_SETFL, O_NONBLOCK);
1523 net_fd = fd;
1524
1525 /* try to launch network init script */
1526 pid = fork();
1527 if (pid >= 0) {
1528 if (pid == 0) {
1529 execl(network_script, network_script, ifr.ifr_name, NULL);
1530 exit(1);
1531 }
1532 while (waitpid(pid, &status, 0) != pid);
1533 if (!WIFEXITED(status) ||
1534 WEXITSTATUS(status) != 0) {
1535 fprintf(stderr, "%s: could not launch network script for '%s'\n",
1536 network_script, ifr.ifr_name);
1537 }
1538 }
1539 return 0;
1540 }
1541
1542 void net_send_packet(NE2000State *s, const uint8_t *buf, int size)
1543 {
1544 #ifdef DEBUG_NE2000
1545 printf("NE2000: sending packet size=%d\n", size);
1546 #endif
1547 write(net_fd, buf, size);
1548 }
1549
1550 /* return true if the NE2000 can receive more data */
1551 int ne2000_can_receive(NE2000State *s)
1552 {
1553 int avail, index, boundary;
1554
1555 if (s->cmd & E8390_STOP)
1556 return 0;
1557 index = s->curpag << 8;
1558 boundary = s->boundary << 8;
1559 if (index < boundary)
1560 avail = boundary - index;
1561 else
1562 avail = (s->stop - s->start) - (index - boundary);
1563 if (avail < (MAX_ETH_FRAME_SIZE + 4))
1564 return 0;
1565 return 1;
1566 }
1567
1568 void ne2000_receive(NE2000State *s, uint8_t *buf, int size)
1569 {
1570 uint8_t *p;
1571 int total_len, next, avail, len, index;
1572
1573 #if defined(DEBUG_NE2000)
1574 printf("NE2000: received len=%d\n", size);
1575 #endif
1576
1577 index = s->curpag << 8;
1578 /* 4 bytes for header */
1579 total_len = size + 4;
1580 /* address for next packet (4 bytes for CRC) */
1581 next = index + ((total_len + 4 + 255) & ~0xff);
1582 if (next >= s->stop)
1583 next -= (s->stop - s->start);
1584 /* prepare packet header */
1585 p = s->mem + index;
1586 p[0] = ENRSR_RXOK; /* receive status */
1587 p[1] = next >> 8;
1588 p[2] = total_len;
1589 p[3] = total_len >> 8;
1590 index += 4;
1591
1592 /* write packet data */
1593 while (size > 0) {
1594 avail = s->stop - index;
1595 len = size;
1596 if (len > avail)
1597 len = avail;
1598 memcpy(s->mem + index, buf, len);
1599 buf += len;
1600 index += len;
1601 if (index == s->stop)
1602 index = s->start;
1603 size -= len;
1604 }
1605 s->curpag = next >> 8;
1606
1607 /* now we can signal we have receive something */
1608 s->isr |= ENISR_RX;
1609 ne2000_update_irq(s);
1610 }
1611
1612 void ne2000_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1613 {
1614 NE2000State *s = &ne2000_state;
1615 int offset, page;
1616
1617 addr &= 0xf;
1618 #ifdef DEBUG_NE2000
1619 printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
1620 #endif
1621 if (addr == E8390_CMD) {
1622 /* control register */
1623 s->cmd = val;
1624 if (val & E8390_START) {
1625 /* test specific case: zero length transfert */
1626 if ((val & (E8390_RREAD | E8390_RWRITE)) &&
1627 s->rcnt == 0) {
1628 s->isr |= ENISR_RDC;
1629 ne2000_update_irq(s);
1630 }
1631 if (val & E8390_TRANS) {
1632 net_send_packet(s, s->mem + (s->tpsr << 8), s->tcnt);
1633 /* signal end of transfert */
1634 s->tsr = ENTSR_PTX;
1635 s->isr |= ENISR_TX;
1636 ne2000_update_irq(s);
1637 }
1638 }
1639 } else {
1640 page = s->cmd >> 6;
1641 offset = addr | (page << 4);
1642 switch(offset) {
1643 case EN0_STARTPG:
1644 s->start = val << 8;
1645 break;
1646 case EN0_STOPPG:
1647 s->stop = val << 8;
1648 break;
1649 case EN0_BOUNDARY:
1650 s->boundary = val;
1651 break;
1652 case EN0_IMR:
1653 s->imr = val;
1654 ne2000_update_irq(s);
1655 break;
1656 case EN0_TPSR:
1657 s->tpsr = val;
1658 break;
1659 case EN0_TCNTLO:
1660 s->tcnt = (s->tcnt & 0xff00) | val;
1661 break;
1662 case EN0_TCNTHI:
1663 s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
1664 break;
1665 case EN0_RSARLO:
1666 s->rsar = (s->rsar & 0xff00) | val;
1667 break;
1668 case EN0_RSARHI:
1669 s->rsar = (s->rsar & 0x00ff) | (val << 8);
1670 break;
1671 case EN0_RCNTLO:
1672 s->rcnt = (s->rcnt & 0xff00) | val;
1673 break;
1674 case EN0_RCNTHI:
1675 s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
1676 break;
1677 case EN0_DCFG:
1678 s->dcfg = val;
1679 break;
1680 case EN0_ISR:
1681 s->isr &= ~val;
1682 ne2000_update_irq(s);
1683 break;
1684 case EN1_PHYS ... EN1_PHYS + 5:
1685 s->phys[offset - EN1_PHYS] = val;
1686 break;
1687 case EN1_CURPAG:
1688 s->curpag = val;
1689 break;
1690 case EN1_MULT ... EN1_MULT + 7:
1691 s->mult[offset - EN1_MULT] = val;
1692 break;
1693 }
1694 }
1695 }
1696
1697 uint32_t ne2000_ioport_read(CPUX86State *env, uint32_t addr)
1698 {
1699 NE2000State *s = &ne2000_state;
1700 int offset, page, ret;
1701
1702 addr &= 0xf;
1703 if (addr == E8390_CMD) {
1704 ret = s->cmd;
1705 } else {
1706 page = s->cmd >> 6;
1707 offset = addr | (page << 4);
1708 switch(offset) {
1709 case EN0_TSR:
1710 ret = s->tsr;
1711 break;
1712 case EN0_BOUNDARY:
1713 ret = s->boundary;
1714 break;
1715 case EN0_ISR:
1716 ret = s->isr;
1717 break;
1718 case EN1_PHYS ... EN1_PHYS + 5:
1719 ret = s->phys[offset - EN1_PHYS];
1720 break;
1721 case EN1_CURPAG:
1722 ret = s->curpag;
1723 break;
1724 case EN1_MULT ... EN1_MULT + 7:
1725 ret = s->mult[offset - EN1_MULT];
1726 break;
1727 default:
1728 ret = 0x00;
1729 break;
1730 }
1731 }
1732 #ifdef DEBUG_NE2000
1733 printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
1734 #endif
1735 return ret;
1736 }
1737
1738 void ne2000_asic_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1739 {
1740 NE2000State *s = &ne2000_state;
1741 uint8_t *p;
1742
1743 #ifdef DEBUG_NE2000
1744 printf("NE2000: asic write val=0x%04x\n", val);
1745 #endif
1746 p = s->mem + s->rsar;
1747 if (s->dcfg & 0x01) {
1748 /* 16 bit access */
1749 p[0] = val;
1750 p[1] = val >> 8;
1751 s->rsar += 2;
1752 s->rcnt -= 2;
1753 } else {
1754 /* 8 bit access */
1755 p[0] = val;
1756 s->rsar++;
1757 s->rcnt--;
1758 }
1759 /* wrap */
1760 if (s->rsar == s->stop)
1761 s->rsar = s->start;
1762 if (s->rcnt == 0) {
1763 /* signal end of transfert */
1764 s->isr |= ENISR_RDC;
1765 ne2000_update_irq(s);
1766 }
1767 }
1768
1769 uint32_t ne2000_asic_ioport_read(CPUX86State *env, uint32_t addr)
1770 {
1771 NE2000State *s = &ne2000_state;
1772 uint8_t *p;
1773 int ret;
1774
1775 p = s->mem + s->rsar;
1776 if (s->dcfg & 0x01) {
1777 /* 16 bit access */
1778 ret = p[0] | (p[1] << 8);
1779 s->rsar += 2;
1780 s->rcnt -= 2;
1781 } else {
1782 /* 8 bit access */
1783 ret = p[0];
1784 s->rsar++;
1785 s->rcnt--;
1786 }
1787 /* wrap */
1788 if (s->rsar == s->stop)
1789 s->rsar = s->start;
1790 if (s->rcnt == 0) {
1791 /* signal end of transfert */
1792 s->isr |= ENISR_RDC;
1793 ne2000_update_irq(s);
1794 }
1795 #ifdef DEBUG_NE2000
1796 printf("NE2000: asic read val=0x%04x\n", ret);
1797 #endif
1798 return ret;
1799 }
1800
1801 void ne2000_reset_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
1802 {
1803 /* nothing to do (end of reset pulse) */
1804 }
1805
1806 uint32_t ne2000_reset_ioport_read(CPUX86State *env, uint32_t addr)
1807 {
1808 ne2000_reset();
1809 return 0;
1810 }
1811
1812 void ne2000_init(void)
1813 {
1814 register_ioport_write(NE2000_IOPORT, 16, ne2000_ioport_write, 1);
1815 register_ioport_read(NE2000_IOPORT, 16, ne2000_ioport_read, 1);
1816
1817 register_ioport_write(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_write, 1);
1818 register_ioport_read(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_read, 1);
1819 register_ioport_write(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_write, 2);
1820 register_ioport_read(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_read, 2);
1821
1822 register_ioport_write(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_write, 1);
1823 register_ioport_read(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_read, 1);
1824 ne2000_reset();
1825 }
1826
1827 /***********************************************************/
1828 /* ide emulation */
1829
1830 //#define DEBUG_IDE
1831
1832 /* Bits of HD_STATUS */
1833 #define ERR_STAT 0x01
1834 #define INDEX_STAT 0x02
1835 #define ECC_STAT 0x04 /* Corrected error */
1836 #define DRQ_STAT 0x08
1837 #define SEEK_STAT 0x10
1838 #define SRV_STAT 0x10
1839 #define WRERR_STAT 0x20
1840 #define READY_STAT 0x40
1841 #define BUSY_STAT 0x80
1842
1843 /* Bits for HD_ERROR */
1844 #define MARK_ERR 0x01 /* Bad address mark */
1845 #define TRK0_ERR 0x02 /* couldn't find track 0 */
1846 #define ABRT_ERR 0x04 /* Command aborted */
1847 #define MCR_ERR 0x08 /* media change request */
1848 #define ID_ERR 0x10 /* ID field not found */
1849 #define MC_ERR 0x20 /* media changed */
1850 #define ECC_ERR 0x40 /* Uncorrectable ECC error */
1851 #define BBD_ERR 0x80 /* pre-EIDE meaning: block marked bad */
1852 #define ICRC_ERR 0x80 /* new meaning: CRC error during transfer */
1853
1854 /* Bits of HD_NSECTOR */
1855 #define CD 0x01
1856 #define IO 0x02
1857 #define REL 0x04
1858 #define TAG_MASK 0xf8
1859
1860 #define IDE_CMD_RESET 0x04
1861 #define IDE_CMD_DISABLE_IRQ 0x02
1862
1863 /* ATA/ATAPI Commands pre T13 Spec */
1864 #define WIN_NOP 0x00
1865 /*
1866 * 0x01->0x02 Reserved
1867 */
1868 #define CFA_REQ_EXT_ERROR_CODE 0x03 /* CFA Request Extended Error Code */
1869 /*
1870 * 0x04->0x07 Reserved
1871 */
1872 #define WIN_SRST 0x08 /* ATAPI soft reset command */
1873 #define WIN_DEVICE_RESET 0x08
1874 /*
1875 * 0x09->0x0F Reserved
1876 */
1877 #define WIN_RECAL 0x10
1878 #define WIN_RESTORE WIN_RECAL
1879 /*
1880 * 0x10->0x1F Reserved
1881 */
1882 #define WIN_READ 0x20 /* 28-Bit */
1883 #define WIN_READ_ONCE 0x21 /* 28-Bit without retries */
1884 #define WIN_READ_LONG 0x22 /* 28-Bit */
1885 #define WIN_READ_LONG_ONCE 0x23 /* 28-Bit without retries */
1886 #define WIN_READ_EXT 0x24 /* 48-Bit */
1887 #define WIN_READDMA_EXT 0x25 /* 48-Bit */
1888 #define WIN_READDMA_QUEUED_EXT 0x26 /* 48-Bit */
1889 #define WIN_READ_NATIVE_MAX_EXT 0x27 /* 48-Bit */
1890 /*
1891 * 0x28
1892 */
1893 #define WIN_MULTREAD_EXT 0x29 /* 48-Bit */
1894 /*
1895 * 0x2A->0x2F Reserved
1896 */
1897 #define WIN_WRITE 0x30 /* 28-Bit */
1898 #define WIN_WRITE_ONCE 0x31 /* 28-Bit without retries */
1899 #define WIN_WRITE_LONG 0x32 /* 28-Bit */
1900 #define WIN_WRITE_LONG_ONCE 0x33 /* 28-Bit without retries */
1901 #define WIN_WRITE_EXT 0x34 /* 48-Bit */
1902 #define WIN_WRITEDMA_EXT 0x35 /* 48-Bit */
1903 #define WIN_WRITEDMA_QUEUED_EXT 0x36 /* 48-Bit */
1904 #define WIN_SET_MAX_EXT 0x37 /* 48-Bit */
1905 #define CFA_WRITE_SECT_WO_ERASE 0x38 /* CFA Write Sectors without erase */
1906 #define WIN_MULTWRITE_EXT 0x39 /* 48-Bit */
1907 /*
1908 * 0x3A->0x3B Reserved
1909 */
1910 #define WIN_WRITE_VERIFY 0x3C /* 28-Bit */
1911 /*
1912 * 0x3D->0x3F Reserved
1913 */
1914 #define WIN_VERIFY 0x40 /* 28-Bit - Read Verify Sectors */
1915 #define WIN_VERIFY_ONCE 0x41 /* 28-Bit - without retries */
1916 #define WIN_VERIFY_EXT 0x42 /* 48-Bit */
1917 /*
1918 * 0x43->0x4F Reserved
1919 */
1920 #define WIN_FORMAT 0x50
1921 /*
1922 * 0x51->0x5F Reserved
1923 */
1924 #define WIN_INIT 0x60
1925 /*
1926 * 0x61->0x5F Reserved
1927 */
1928 #define WIN_SEEK 0x70 /* 0x70-0x7F Reserved */
1929 #define CFA_TRANSLATE_SECTOR 0x87 /* CFA Translate Sector */
1930 #define WIN_DIAGNOSE 0x90
1931 #define WIN_SPECIFY 0x91 /* set drive geometry translation */
1932 #define WIN_DOWNLOAD_MICROCODE 0x92
1933 #define WIN_STANDBYNOW2 0x94
1934 #define WIN_STANDBY2 0x96
1935 #define WIN_SETIDLE2 0x97
1936 #define WIN_CHECKPOWERMODE2 0x98
1937 #define WIN_SLEEPNOW2 0x99
1938 /*
1939 * 0x9A VENDOR
1940 */
1941 #define WIN_PACKETCMD 0xA0 /* Send a packet command. */
1942 #define WIN_PIDENTIFY 0xA1 /* identify ATAPI device */
1943 #define WIN_QUEUED_SERVICE 0xA2
1944 #define WIN_SMART 0xB0 /* self-monitoring and reporting */
1945 #define CFA_ERASE_SECTORS 0xC0
1946 #define WIN_MULTREAD 0xC4 /* read sectors using multiple mode*/
1947 #define WIN_MULTWRITE 0xC5 /* write sectors using multiple mode */
1948 #define WIN_SETMULT 0xC6 /* enable/disable multiple mode */
1949 #define WIN_READDMA_QUEUED 0xC7 /* read sectors using Queued DMA transfers */
1950 #define WIN_READDMA 0xC8 /* read sectors using DMA transfers */
1951 #define WIN_READDMA_ONCE 0xC9 /* 28-Bit - without retries */
1952 #define WIN_WRITEDMA 0xCA /* write sectors using DMA transfers */
1953 #define WIN_WRITEDMA_ONCE 0xCB /* 28-Bit - without retries */
1954 #define WIN_WRITEDMA_QUEUED 0xCC /* write sectors using Queued DMA transfers */
1955 #define CFA_WRITE_MULTI_WO_ERASE 0xCD /* CFA Write multiple without erase */
1956 #define WIN_GETMEDIASTATUS 0xDA
1957 #define WIN_ACKMEDIACHANGE 0xDB /* ATA-1, ATA-2 vendor */
1958 #define WIN_POSTBOOT 0xDC
1959 #define WIN_PREBOOT 0xDD
1960 #define WIN_DOORLOCK 0xDE /* lock door on removable drives */
1961 #define WIN_DOORUNLOCK 0xDF /* unlock door on removable drives */
1962 #define WIN_STANDBYNOW1 0xE0
1963 #define WIN_IDLEIMMEDIATE 0xE1 /* force drive to become "ready" */
1964 #define WIN_STANDBY 0xE2 /* Set device in Standby Mode */
1965 #define WIN_SETIDLE1 0xE3
1966 #define WIN_READ_BUFFER 0xE4 /* force read only 1 sector */
1967 #define WIN_CHECKPOWERMODE1 0xE5
1968 #define WIN_SLEEPNOW1 0xE6
1969 #define WIN_FLUSH_CACHE 0xE7
1970 #define WIN_WRITE_BUFFER 0xE8 /* force write only 1 sector */
1971 #define WIN_WRITE_SAME 0xE9 /* read ata-2 to use */
1972 /* SET_FEATURES 0x22 or 0xDD */
1973 #define WIN_FLUSH_CACHE_EXT 0xEA /* 48-Bit */
1974 #define WIN_IDENTIFY 0xEC /* ask drive to identify itself */
1975 #define WIN_MEDIAEJECT 0xED
1976 #define WIN_IDENTIFY_DMA 0xEE /* same as WIN_IDENTIFY, but DMA */
1977 #define WIN_SETFEATURES 0xEF /* set special drive features */
1978 #define EXABYTE_ENABLE_NEST 0xF0
1979 #define WIN_SECURITY_SET_PASS 0xF1
1980 #define WIN_SECURITY_UNLOCK 0xF2
1981 #define WIN_SECURITY_ERASE_PREPARE 0xF3
1982 #define WIN_SECURITY_ERASE_UNIT 0xF4
1983 #define WIN_SECURITY_FREEZE_LOCK 0xF5
1984 #define WIN_SECURITY_DISABLE 0xF6
1985 #define WIN_READ_NATIVE_MAX 0xF8 /* return the native maximum address */
1986 #define WIN_SET_MAX 0xF9
1987 #define DISABLE_SEAGATE 0xFB
1988
1989 /* set to 1 set disable mult support */
1990 #define MAX_MULT_SECTORS 8
1991
1992 struct IDEState;
1993
1994 typedef void EndTransferFunc(struct IDEState *);
1995
1996 typedef struct IDEState {
1997 /* ide config */
1998 int cylinders, heads, sectors;
1999 int64_t nb_sectors;
2000 int mult_sectors;
2001 int irq;
2002 /* ide regs */
2003 uint8_t feature;
2004 uint8_t error;
2005 uint16_t nsector; /* 0 is 256 to ease computations */
2006 uint8_t sector;
2007 uint8_t lcyl;
2008 uint8_t hcyl;
2009 uint8_t select;
2010 uint8_t status;
2011 /* 0x3f6 command, only meaningful for drive 0 */
2012 uint8_t cmd;
2013 /* depends on bit 4 in select, only meaningful for drive 0 */
2014 struct IDEState *cur_drive;
2015 BlockDriverState *bs;
2016 int req_nb_sectors; /* number of sectors per interrupt */
2017 EndTransferFunc *end_transfer_func;
2018 uint8_t *data_ptr;
2019 uint8_t *data_end;
2020 uint8_t io_buffer[MAX_MULT_SECTORS*512 + 4];
2021 } IDEState;
2022
2023 IDEState ide_state[MAX_DISKS];
2024
2025 static void padstr(char *str, const char *src, int len)
2026 {
2027 int i, v;
2028 for(i = 0; i < len; i++) {
2029 if (*src)
2030 v = *src++;
2031 else
2032 v = ' ';
2033 *(char *)((long)str ^ 1) = v;
2034 str++;
2035 }
2036 }
2037
2038 static void ide_identify(IDEState *s)
2039 {
2040 uint16_t *p;
2041 unsigned int oldsize;
2042
2043 memset(s->io_buffer, 0, 512);
2044 p = (uint16_t *)s->io_buffer;
2045 stw(p + 0, 0x0040);
2046 stw(p + 1, s->cylinders);
2047 stw(p + 3, s->heads);
2048 stw(p + 4, 512 * s->sectors); /* sectors */
2049 stw(p + 5, 512); /* sector size */
2050 stw(p + 6, s->sectors);
2051 stw(p + 20, 3); /* buffer type */
2052 stw(p + 21, 512); /* cache size in sectors */
2053 stw(p + 22, 4); /* ecc bytes */
2054 padstr((uint8_t *)(p + 27), "QEMU HARDDISK", 40);
2055 #if MAX_MULT_SECTORS > 1
2056 stw(p + 47, MAX_MULT_SECTORS);
2057 #endif
2058 stw(p + 48, 1); /* dword I/O */
2059 stw(p + 49, 1 << 9); /* LBA supported, no DMA */
2060 stw(p + 51, 0x200); /* PIO transfer cycle */
2061 stw(p + 52, 0x200); /* DMA transfer cycle */
2062 stw(p + 54, s->cylinders);
2063 stw(p + 55, s->heads);
2064 stw(p + 56, s->sectors);
2065 oldsize = s->cylinders * s->heads * s->sectors;
2066 stw(p + 57, oldsize);
2067 stw(p + 58, oldsize >> 16);
2068 if (s->mult_sectors)
2069 stw(p + 59, 0x100 | s->mult_sectors);
2070 stw(p + 60, s->nb_sectors);
2071 stw(p + 61, s->nb_sectors >> 16);
2072 stw(p + 80, (1 << 1) | (1 << 2));
2073 stw(p + 82, (1 << 14));
2074 stw(p + 83, (1 << 14));
2075 stw(p + 84, (1 << 14));
2076 stw(p + 85, (1 << 14));
2077 stw(p + 86, 0);
2078 stw(p + 87, (1 << 14));
2079 }
2080
2081 static inline void ide_abort_command(IDEState *s)
2082 {
2083 s->status = READY_STAT | ERR_STAT;
2084 s->error = ABRT_ERR;
2085 }
2086
2087 static inline void ide_set_irq(IDEState *s)
2088 {
2089 if (!(ide_state[0].cmd & IDE_CMD_DISABLE_IRQ)) {
2090 pic_set_irq(s->irq, 1);
2091 }
2092 }
2093
2094 /* prepare data transfer and tell what to do after */
2095 static void ide_transfer_start(IDEState *s, int size,
2096 EndTransferFunc *end_transfer_func)
2097 {
2098 s->end_transfer_func = end_transfer_func;
2099 s->data_ptr = s->io_buffer;
2100 s->data_end = s->io_buffer + size;
2101 s->status |= DRQ_STAT;
2102 }
2103
2104 static void ide_transfer_stop(IDEState *s)
2105 {
2106 s->end_transfer_func = ide_transfer_stop;
2107 s->data_ptr = s->io_buffer;
2108 s->data_end = s->io_buffer;
2109 s->status &= ~DRQ_STAT;
2110 }
2111
2112 static int64_t ide_get_sector(IDEState *s)
2113 {
2114 int64_t sector_num;
2115 if (s->select & 0x40) {
2116 /* lba */
2117 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
2118 (s->lcyl << 8) | s->sector;
2119 } else {
2120 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
2121 (s->select & 0x0f) * s->sectors +
2122 (s->sector - 1);
2123 }
2124 return sector_num;
2125 }
2126
2127 static void ide_set_sector(IDEState *s, int64_t sector_num)
2128 {
2129 unsigned int cyl, r;
2130 if (s->select & 0x40) {
2131 s->select = (s->select & 0xf0) | (sector_num >> 24);
2132 s->hcyl = (sector_num >> 16);
2133 s->lcyl = (sector_num >> 8);
2134 s->sector = (sector_num);
2135 } else {
2136 cyl = sector_num / (s->heads * s->sectors);
2137 r = sector_num % (s->heads * s->sectors);
2138 s->hcyl = cyl >> 8;
2139 s->lcyl = cyl;
2140 s->select = (s->select & 0xf0) | (r / s->sectors);
2141 s->sector = (r % s->sectors) + 1;
2142 }
2143 }
2144
2145 static void ide_sector_read(IDEState *s)
2146 {
2147 int64_t sector_num;
2148 int ret, n;
2149
2150 s->status = READY_STAT | SEEK_STAT;
2151 sector_num = ide_get_sector(s);
2152 n = s->nsector;
2153 if (n == 0) {
2154 /* no more sector to read from disk */
2155 ide_transfer_stop(s);
2156 } else {
2157 #if defined(DEBUG_IDE)
2158 printf("read sector=%Ld\n", sector_num);
2159 #endif
2160 if (n > s->req_nb_sectors)
2161 n = s->req_nb_sectors;
2162 ret = bdrv_read(s->bs, sector_num, s->io_buffer, n);
2163 ide_transfer_start(s, 512 * n, ide_sector_read);
2164 ide_set_irq(s);
2165 ide_set_sector(s, sector_num + n);
2166 s->nsector -= n;
2167 }
2168 }
2169
2170 static void ide_sector_write(IDEState *s)
2171 {
2172 int64_t sector_num;
2173 int ret, n, n1;
2174
2175 s->status = READY_STAT | SEEK_STAT;
2176 sector_num = ide_get_sector(s);
2177 #if defined(DEBUG_IDE)
2178 printf("write sector=%Ld\n", sector_num);
2179 #endif
2180 n = s->nsector;
2181 if (n > s->req_nb_sectors)
2182 n = s->req_nb_sectors;
2183 ret = bdrv_write(s->bs, sector_num, s->io_buffer, n);
2184 s->nsector -= n;
2185 if (s->nsector == 0) {
2186 /* no more sector to write */
2187 ide_transfer_stop(s);
2188 } else {
2189 n1 = s->nsector;
2190 if (n1 > s->req_nb_sectors)
2191 n1 = s->req_nb_sectors;
2192 ide_transfer_start(s, 512 * n1, ide_sector_write);
2193 }
2194 ide_set_sector(s, sector_num + n);
2195 ide_set_irq(s);
2196 }
2197
2198 void ide_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
2199 {
2200 IDEState *s = ide_state[0].cur_drive;
2201 int unit, n;
2202
2203 addr &= 7;
2204 #ifdef DEBUG_IDE
2205 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
2206 #endif
2207 switch(addr) {
2208 case 0:
2209 break;
2210 case 1:
2211 s->feature = val;
2212 break;
2213 case 2:
2214 if (val == 0)
2215 val = 256;
2216 s->nsector = val;
2217 break;
2218 case 3:
2219 s->sector = val;
2220 break;
2221 case 4:
2222 s->lcyl = val;
2223 break;
2224 case 5:
2225 s->hcyl = val;
2226 break;
2227 case 6:
2228 /* select drive */
2229 unit = (val >> 4) & 1;
2230 s = &ide_state[unit];
2231 ide_state[0].cur_drive = s;
2232 s->select = val;
2233 break;
2234 default:
2235 case 7:
2236 /* command */
2237 #if defined(DEBUG_IDE)
2238 printf("ide: CMD=%02x\n", val);
2239 #endif
2240 switch(val) {
2241 case WIN_PIDENTIFY:
2242 case WIN_IDENTIFY:
2243 if (s->bs) {
2244 ide_identify(s);
2245 s->status = READY_STAT;
2246 ide_transfer_start(s, 512, ide_transfer_stop);
2247 } else {
2248 ide_abort_command(s);
2249 }
2250 ide_set_irq(s);
2251 break;
2252 case WIN_SPECIFY:
2253 case WIN_RECAL:
2254 s->status = READY_STAT;
2255 ide_set_irq(s);
2256 break;
2257 case WIN_SETMULT:
2258 if (s->nsector > MAX_MULT_SECTORS ||
2259 s->nsector == 0 ||
2260 (s->nsector & (s->nsector - 1)) != 0) {
2261 ide_abort_command(s);
2262 } else {
2263 s->mult_sectors = s->nsector;
2264 s->status = READY_STAT;
2265 }
2266 ide_set_irq(s);
2267 break;
2268 case WIN_READ:
2269 case WIN_READ_ONCE:
2270 s->req_nb_sectors = 1;
2271 ide_sector_read(s);
2272 break;
2273 case WIN_WRITE:
2274 case WIN_WRITE_ONCE:
2275 s->status = SEEK_STAT;
2276 s->req_nb_sectors = 1;
2277 ide_transfer_start(s, 512, ide_sector_write);
2278 break;
2279 case WIN_MULTREAD:
2280 if (!s->mult_sectors)
2281 goto abort_cmd;
2282 s->req_nb_sectors = s->mult_sectors;
2283 ide_sector_read(s);
2284 break;
2285 case WIN_MULTWRITE:
2286 if (!s->mult_sectors)
2287 goto abort_cmd;
2288 s->status = SEEK_STAT;
2289 s->req_nb_sectors = s->mult_sectors;
2290 n = s->nsector;
2291 if (n > s->req_nb_sectors)
2292 n = s->req_nb_sectors;
2293 ide_transfer_start(s, 512 * n, ide_sector_write);
2294 break;
2295 case WIN_READ_NATIVE_MAX:
2296 ide_set_sector(s, s->nb_sectors - 1);
2297 s->status = READY_STAT;
2298 ide_set_irq(s);
2299 break;
2300 default:
2301 abort_cmd:
2302 ide_abort_command(s);
2303 ide_set_irq(s);
2304 break;
2305 }
2306 }
2307 }
2308
2309 uint32_t ide_ioport_read(CPUX86State *env, uint32_t addr)
2310 {
2311 IDEState *s = ide_state[0].cur_drive;
2312 int ret;
2313
2314 addr &= 7;
2315 switch(addr) {
2316 case 0:
2317 ret = 0xff;
2318 break;
2319 case 1:
2320 ret = s->error;
2321 break;
2322 case 2:
2323 ret = s->nsector & 0xff;
2324 break;
2325 case 3:
2326 ret = s->sector;
2327 break;
2328 case 4:
2329 ret = s->lcyl;
2330 break;
2331 case 5:
2332 ret = s->hcyl;
2333 break;
2334 case 6:
2335 ret = s->select;
2336 break;
2337 default:
2338 case 7:
2339 ret = s->status;
2340 pic_set_irq(s->irq, 0);
2341 break;
2342 }
2343 #ifdef DEBUG_IDE
2344 printf("ide: read addr=0x%x val=%02x\n", addr, ret);
2345 #endif
2346 return ret;
2347 }
2348
2349 uint32_t ide_status_read(CPUX86State *env, uint32_t addr)
2350 {
2351 IDEState *s = ide_state[0].cur_drive;
2352 int ret;
2353 ret = s->status;
2354 #ifdef DEBUG_IDE
2355 printf("ide: read addr=0x%x val=%02x\n", addr, ret);
2356 #endif
2357 return ret;
2358 }
2359
2360 void ide_cmd_write(CPUX86State *env, uint32_t addr, uint32_t val)
2361 {
2362 IDEState *s = &ide_state[0];
2363 /* common for both drives */
2364 s->cmd = val;
2365 }
2366
2367 void ide_data_writew(CPUX86State *env, uint32_t addr, uint32_t val)
2368 {
2369 IDEState *s = ide_state[0].cur_drive;
2370 uint8_t *p;
2371
2372 p = s->data_ptr;
2373 *(uint16_t *)p = tswap16(val);
2374 p += 2;
2375 s->data_ptr = p;
2376 if (p >= s->data_end)
2377 s->end_transfer_func(s);
2378 }
2379
2380 uint32_t ide_data_readw(CPUX86State *env, uint32_t addr)
2381 {
2382 IDEState *s = ide_state[0].cur_drive;
2383 uint8_t *p;
2384 int ret;
2385
2386 p = s->data_ptr;
2387 ret = tswap16(*(uint16_t *)p);
2388 p += 2;
2389 s->data_ptr = p;
2390 if (p >= s->data_end)
2391 s->end_transfer_func(s);
2392 return ret;
2393 }
2394
2395 void ide_data_writel(CPUX86State *env, uint32_t addr, uint32_t val)
2396 {
2397 IDEState *s = ide_state[0].cur_drive;
2398 uint8_t *p;
2399
2400 p = s->data_ptr;
2401 *(uint32_t *)p = tswap32(val);
2402 p += 4;
2403 s->data_ptr = p;
2404 if (p >= s->data_end)
2405 s->end_transfer_func(s);
2406 }
2407
2408 uint32_t ide_data_readl(CPUX86State *env, uint32_t addr)
2409 {
2410 IDEState *s = ide_state[0].cur_drive;
2411 uint8_t *p;
2412 int ret;
2413
2414 p = s->data_ptr;
2415 ret = tswap32(*(uint32_t *)p);
2416 p += 4;
2417 s->data_ptr = p;
2418 if (p >= s->data_end)
2419 s->end_transfer_func(s);
2420 return ret;
2421 }
2422
2423 void ide_reset(IDEState *s)
2424 {
2425 s->mult_sectors = MAX_MULT_SECTORS;
2426 s->status = READY_STAT;
2427 s->cur_drive = s;
2428 s->select = 0xa0;
2429 }
2430
2431 void ide_init(void)
2432 {
2433 IDEState *s;
2434 int i, cylinders;
2435 int64_t nb_sectors;
2436
2437 for(i = 0; i < MAX_DISKS; i++) {
2438 s = &ide_state[i];
2439 s->bs = bs_table[i];
2440 if (s->bs) {
2441 bdrv_get_geometry(s->bs, &nb_sectors);
2442 cylinders = nb_sectors / (16 * 63);
2443 if (cylinders > 16383)
2444 cylinders = 16383;
2445 else if (cylinders < 2)
2446 cylinders = 2;
2447 s->cylinders = cylinders;
2448 s->heads = 16;
2449 s->sectors = 63;
2450 s->nb_sectors = nb_sectors;
2451 }
2452 s->irq = 14;
2453 ide_reset(s);
2454 }
2455 register_ioport_write(0x1f0, 8, ide_ioport_write, 1);
2456 register_ioport_read(0x1f0, 8, ide_ioport_read, 1);
2457 register_ioport_read(0x3f6, 1, ide_status_read, 1);
2458 register_ioport_write(0x3f6, 1, ide_cmd_write, 1);
2459
2460 /* data ports */
2461 register_ioport_write(0x1f0, 2, ide_data_writew, 2);
2462 register_ioport_read(0x1f0, 2, ide_data_readw, 2);
2463 register_ioport_write(0x1f0, 4, ide_data_writel, 4);
2464 register_ioport_read(0x1f0, 4, ide_data_readl, 4);
2465 }
2466
2467 /***********************************************************/
2468 /* simulate reset (stop qemu) */
2469
2470 int reset_requested;
2471
2472 uint32_t kbd_read_status(CPUX86State *env, uint32_t addr)
2473 {
2474 return 0;
2475 }
2476
2477 void kbd_write_command(CPUX86State *env, uint32_t addr, uint32_t val)
2478 {
2479 switch(val) {
2480 case 0xfe:
2481 reset_requested = 1;
2482 cpu_x86_interrupt(global_env, CPU_INTERRUPT_EXIT);
2483 break;
2484 default:
2485 break;
2486 }
2487 }
2488
2489 void kbd_init(void)
2490 {
2491 register_ioport_read(0x64, 1, kbd_read_status, 1);
2492 register_ioport_write(0x64, 1, kbd_write_command, 1);
2493 }
2494
2495 /***********************************************************/
2496 /* cpu signal handler */
2497 static void host_segv_handler(int host_signum, siginfo_t *info,
2498 void *puc)
2499 {
2500 if (cpu_signal_handler(host_signum, info, puc))
2501 return;
2502 term_exit();
2503 abort();
2504 }
2505
2506 static int timer_irq_pending;
2507 static int timer_irq_count;
2508
2509 static void host_alarm_handler(int host_signum, siginfo_t *info,
2510 void *puc)
2511 {
2512 /* NOTE: since usually the OS asks a 100 Hz clock, there can be
2513 some drift between cpu_get_ticks() and the interrupt time. So
2514 we queue some interrupts to avoid missing some */
2515 timer_irq_count += pit_get_out_edges(&pit_channels[0]);
2516 if (timer_irq_count) {
2517 if (timer_irq_count > 2)
2518 timer_irq_count = 2;
2519 timer_irq_count--;
2520 /* just exit from the cpu to have a chance to handle timers */
2521 cpu_x86_interrupt(global_env, CPU_INTERRUPT_EXIT);
2522 timer_irq_pending = 1;
2523 }
2524 }
2525
2526 unsigned long mmap_addr = PHYS_RAM_BASE;
2527
2528 void *get_mmap_addr(unsigned long size)
2529 {
2530 unsigned long addr;
2531 addr = mmap_addr;
2532 mmap_addr += ((size + 4095) & ~4095) + 4096;
2533 return (void *)addr;
2534 }
2535
2536 /* main execution loop */
2537
2538 CPUState *cpu_gdbstub_get_env(void *opaque)
2539 {
2540 return global_env;
2541 }
2542
2543 void main_loop(void *opaque)
2544 {
2545 struct pollfd ufds[2], *pf, *serial_ufd, *net_ufd, *gdb_ufd;
2546 int ret, n, timeout;
2547 uint8_t ch;
2548 CPUState *env = global_env;
2549
2550 for(;;) {
2551
2552 ret = cpu_x86_exec(env);
2553 if (reset_requested)
2554 break;
2555
2556 /* if hlt instruction, we wait until the next IRQ */
2557 if (ret == EXCP_HLT)
2558 timeout = 10;
2559 else
2560 timeout = 0;
2561 /* poll any events */
2562 serial_ufd = NULL;
2563 pf = ufds;
2564 if (!(serial_ports[0].lsr & UART_LSR_DR)) {
2565 serial_ufd = pf;
2566 pf->fd = 0;
2567 pf->events = POLLIN;
2568 pf++;
2569 }
2570 net_ufd = NULL;
2571 if (net_fd > 0 && ne2000_can_receive(&ne2000_state)) {
2572 net_ufd = pf;
2573 pf->fd = net_fd;
2574 pf->events = POLLIN;
2575 pf++;
2576 }
2577 gdb_ufd = NULL;
2578 if (gdbstub_fd > 0) {
2579 gdb_ufd = pf;
2580 pf->fd = gdbstub_fd;
2581 pf->events = POLLIN;
2582 pf++;
2583 }
2584
2585 ret = poll(ufds, pf - ufds, timeout);
2586 if (ret > 0) {
2587 if (serial_ufd && (serial_ufd->revents & POLLIN)) {
2588 n = read(0, &ch, 1);
2589 if (n == 1) {
2590 serial_received_byte(&serial_ports[0], ch);
2591 }
2592 }
2593 if (net_ufd && (net_ufd->revents & POLLIN)) {
2594 uint8_t buf[MAX_ETH_FRAME_SIZE];
2595
2596 n = read(net_fd, buf, MAX_ETH_FRAME_SIZE);
2597 if (n > 0) {
2598 if (n < 60) {
2599 memset(buf + n, 0, 60 - n);
2600 n = 60;
2601 }
2602 ne2000_receive(&ne2000_state, buf, n);
2603 }
2604 }
2605 if (gdb_ufd && (gdb_ufd->revents & POLLIN)) {
2606 uint8_t buf[1];
2607 /* stop emulation if requested by gdb */
2608 n = read(gdbstub_fd, buf, 1);
2609 if (n == 1)
2610 break;
2611 }
2612 }
2613
2614 /* timer IRQ */
2615 if (timer_irq_pending) {
2616 pic_set_irq(0, 1);
2617 pic_set_irq(0, 0);
2618 timer_irq_pending = 0;
2619 }
2620 }
2621 }
2622
2623 void help(void)
2624 {
2625 printf("Virtual Linux version " QEMU_VERSION ", Copyright (c) 2003 Fabrice Bellard\n"
2626 "usage: vl [options] bzImage [kernel parameters...]\n"
2627 "\n"
2628 "'bzImage' is a Linux kernel image (PAGE_OFFSET must be defined\n"
2629 "to 0x90000000 in asm/page.h and arch/i386/vmlinux.lds)\n"
2630 "\n"
2631 "General options:\n"
2632 "-initrd file use 'file' as initial ram disk\n"
2633 "-hda file use 'file' as hard disk 0 image\n"
2634 "-hdb file use 'file' as hard disk 1 image\n"
2635 "-snapshot write to temporary files instead of disk image files\n"
2636 "-m megs set virtual RAM size to megs MB\n"
2637 "-n script set network init script [default=%s]\n"
2638 "\n"
2639 "Debug options:\n"
2640 "-s wait gdb connection to port %d\n"
2641 "-p port change gdb connection port\n"
2642 "-d output log in /tmp/vl.log\n"
2643 "\n"
2644 "During emulation, use C-a h to get terminal commands:\n",
2645 DEFAULT_NETWORK_SCRIPT, DEFAULT_GDBSTUB_PORT);
2646 term_print_help();
2647 exit(1);
2648 }
2649
2650 struct option long_options[] = {
2651 { "initrd", 1, NULL, 0, },
2652 { "hda", 1, NULL, 0, },
2653 { "hdb", 1, NULL, 0, },
2654 { "snapshot", 0, NULL, 0, },
2655 { NULL, 0, NULL, 0 },
2656 };
2657
2658 int main(int argc, char **argv)
2659 {
2660 int c, ret, initrd_size, i, use_gdbstub, gdbstub_port, long_index;
2661 int snapshot;
2662 struct linux_params *params;
2663 struct sigaction act;
2664 struct itimerval itv;
2665 CPUX86State *env;
2666 const char *tmpdir, *initrd_filename;
2667 const char *hd_filename[MAX_DISKS];
2668
2669 /* we never want that malloc() uses mmap() */
2670 mallopt(M_MMAP_THRESHOLD, 4096 * 1024);
2671 initrd_filename = NULL;
2672 for(i = 0; i < MAX_DISKS; i++)
2673 hd_filename[i] = NULL;
2674 phys_ram_size = 32 * 1024 * 1024;
2675 pstrcpy(network_script, sizeof(network_script), DEFAULT_NETWORK_SCRIPT);
2676 use_gdbstub = 0;
2677 gdbstub_port = DEFAULT_GDBSTUB_PORT;
2678 snapshot = 0;
2679 for(;;) {
2680 c = getopt_long_only(argc, argv, "hm:dn:sp:", long_options, &long_index);
2681 if (c == -1)
2682 break;
2683 switch(c) {
2684 case 0:
2685 switch(long_index) {
2686 case 0:
2687 initrd_filename = optarg;
2688 break;
2689 case 1:
2690 hd_filename[0] = optarg;
2691 break;
2692 case 2:
2693 hd_filename[1] = optarg;
2694 break;
2695 case 3:
2696 snapshot = 1;
2697 break;
2698 }
2699 break;
2700 case 'h':
2701 help();
2702 break;
2703 case 'm':
2704 phys_ram_size = atoi(optarg) * 1024 * 1024;
2705 if (phys_ram_size <= 0)
2706 help();
2707 if (phys_ram_size > PHYS_RAM_MAX_SIZE) {
2708 fprintf(stderr, "vl: at most %d MB RAM can be simulated\n",
2709 PHYS_RAM_MAX_SIZE / (1024 * 1024));
2710 exit(1);
2711 }
2712 break;
2713 case 'd':
2714 loglevel = 1;
2715 break;
2716 case 'n':
2717 pstrcpy(network_script, sizeof(network_script), optarg);
2718 break;
2719 case 's':
2720 use_gdbstub = 1;
2721 break;
2722 case 'p':
2723 gdbstub_port = atoi(optarg);
2724 break;
2725 }
2726 }
2727 if (optind >= argc)
2728 help();
2729
2730 /* init debug */
2731 setvbuf(stdout, NULL, _IOLBF, 0);
2732 if (loglevel) {
2733 logfile = fopen(DEBUG_LOGFILE, "w");
2734 if (!logfile) {
2735 perror(DEBUG_LOGFILE);
2736 _exit(1);
2737 }
2738 setvbuf(logfile, NULL, _IOLBF, 0);
2739 }
2740
2741 /* init network tun interface */
2742 net_init();
2743
2744 /* init the memory */
2745 tmpdir = getenv("VLTMPDIR");
2746 if (!tmpdir)
2747 tmpdir = "/tmp";
2748 snprintf(phys_ram_file, sizeof(phys_ram_file), "%s/vlXXXXXX", tmpdir);
2749 if (mkstemp(phys_ram_file) < 0) {
2750 fprintf(stderr, "Could not create temporary memory file '%s'\n",
2751 phys_ram_file);
2752 exit(1);
2753 }
2754 phys_ram_fd = open(phys_ram_file, O_CREAT | O_TRUNC | O_RDWR, 0600);
2755 if (phys_ram_fd < 0) {
2756 fprintf(stderr, "Could not open temporary memory file '%s'\n",
2757 phys_ram_file);
2758 exit(1);
2759 }
2760 ftruncate(phys_ram_fd, phys_ram_size);
2761 unlink(phys_ram_file);
2762 phys_ram_base = mmap(get_mmap_addr(phys_ram_size), phys_ram_size,
2763 PROT_WRITE | PROT_READ, MAP_SHARED | MAP_FIXED,
2764 phys_ram_fd, 0);
2765 if (phys_ram_base == MAP_FAILED) {
2766 fprintf(stderr, "Could not map physical memory\n");
2767 exit(1);
2768 }
2769
2770 /* open the virtual block devices */
2771 for(i = 0; i < MAX_DISKS; i++) {
2772 if (hd_filename[i]) {
2773 bs_table[i] = bdrv_open(hd_filename[i], snapshot);
2774 if (!bs_table[i]) {
2775 fprintf(stderr, "vl: could not open hard disk image '%s\n",
2776 hd_filename[i]);
2777 exit(1);
2778 }
2779 }
2780 }
2781
2782 /* now we can load the kernel */
2783 ret = load_kernel(argv[optind], phys_ram_base + KERNEL_LOAD_ADDR);
2784 if (ret < 0) {
2785 fprintf(stderr, "vl: could not load kernel '%s'\n", argv[optind]);
2786 exit(1);
2787 }
2788
2789 /* load initrd */
2790 initrd_size = 0;
2791 if (initrd_filename) {
2792 initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
2793 if (initrd_size < 0) {
2794 fprintf(stderr, "vl: could not load initial ram disk '%s'\n",
2795 initrd_filename);
2796 exit(1);
2797 }
2798 }
2799
2800 /* init kernel params */
2801 params = (void *)(phys_ram_base + KERNEL_PARAMS_ADDR);
2802 memset(params, 0, sizeof(struct linux_params));
2803 params->mount_root_rdonly = 0;
2804 params->cl_magic = 0xA33F;
2805 params->cl_offset = params->commandline - (uint8_t *)params;
2806 params->alt_mem_k = (phys_ram_size / 1024) - 1024;
2807 for(i = optind + 1; i < argc; i++) {
2808 if (i != optind + 1)
2809 pstrcat(params->commandline, sizeof(params->commandline), " ");
2810 pstrcat(params->commandline, sizeof(params->commandline), argv[i]);
2811 }
2812 params->loader_type = 0x01;
2813 if (initrd_size > 0) {
2814 params->initrd_start = INITRD_LOAD_ADDR;
2815 params->initrd_size = initrd_size;
2816 }
2817 params->orig_video_lines = 25;
2818 params->orig_video_cols = 80;
2819
2820 /* init basic PC hardware */
2821 init_ioports();
2822 register_ioport_write(0x80, 1, ioport80_write, 1);
2823
2824 register_ioport_write(0x3d4, 2, vga_ioport_write, 1);
2825
2826 cmos_init();
2827 pic_init();
2828 pit_init();
2829 serial_init();
2830 ne2000_init();
2831 ide_init();
2832 kbd_init();
2833
2834 /* setup cpu signal handlers for MMU / self modifying code handling */
2835 sigfillset(&act.sa_mask);
2836 act.sa_flags = SA_SIGINFO;
2837 act.sa_sigaction = host_segv_handler;
2838 sigaction(SIGSEGV, &act, NULL);
2839 sigaction(SIGBUS, &act, NULL);
2840
2841 act.sa_sigaction = host_alarm_handler;
2842 sigaction(SIGALRM, &act, NULL);
2843
2844 /* init CPU state */
2845 env = cpu_init();
2846 global_env = env;
2847 cpu_single_env = env;
2848
2849 /* setup basic memory access */
2850 env->cr[0] = 0x00000033;
2851 cpu_x86_init_mmu(env);
2852
2853 memset(params->idt_table, 0, sizeof(params->idt_table));
2854
2855 params->gdt_table[2] = 0x00cf9a000000ffffLL; /* KERNEL_CS */
2856 params->gdt_table[3] = 0x00cf92000000ffffLL; /* KERNEL_DS */
2857
2858 env->idt.base = (void *)params->idt_table;
2859 env->idt.limit = sizeof(params->idt_table) - 1;
2860 env->gdt.base = (void *)params->gdt_table;
2861 env->gdt.limit = sizeof(params->gdt_table) - 1;
2862
2863 cpu_x86_load_seg(env, R_CS, KERNEL_CS);
2864 cpu_x86_load_seg(env, R_DS, KERNEL_DS);
2865 cpu_x86_load_seg(env, R_ES, KERNEL_DS);
2866 cpu_x86_load_seg(env, R_SS, KERNEL_DS);
2867 cpu_x86_load_seg(env, R_FS, KERNEL_DS);
2868 cpu_x86_load_seg(env, R_GS, KERNEL_DS);
2869
2870 env->eip = KERNEL_LOAD_ADDR;
2871 env->regs[R_ESI] = KERNEL_PARAMS_ADDR;
2872 env->eflags = 0x2;
2873
2874 itv.it_interval.tv_sec = 0;
2875 itv.it_interval.tv_usec = 1000;
2876 itv.it_value.tv_sec = 0;
2877 itv.it_value.tv_usec = 10 * 1000;
2878 setitimer(ITIMER_REAL, &itv, NULL);
2879 /* we probe the tick duration of the kernel to inform the user if
2880 the emulated kernel requested a too high timer frequency */
2881 getitimer(ITIMER_REAL, &itv);
2882 pit_min_timer_count = ((uint64_t)itv.it_interval.tv_usec * PIT_FREQ) /
2883 1000000;
2884
2885 if (use_gdbstub) {
2886 cpu_gdbstub(NULL, main_loop, gdbstub_port);
2887 } else {
2888 main_loop(NULL);
2889 }
2890 return 0;
2891 }
Qemu copy for testing