#include "config.h"
#include "cpu.h"
-#include "exec-all.h"
-#include "memory.h"
+#include "exec/exec-all.h"
+#include "exec/memory.h"
+#include "exec/address-spaces.h"
-#include "cputlb.h"
+#include "exec/cputlb.h"
-#define WANT_EXEC_OBSOLETE
-#include "exec-obsolete.h"
+#include "exec/memory-internal.h"
//#define DEBUG_TLB
//#define DEBUG_TLB_CHECK
*/
void tlb_flush(CPUArchState *env, int flush_global)
{
+ CPUState *cpu = ENV_GET_CPU(env);
int i;
#if defined(DEBUG_TLB)
#endif
/* must reset current TB so that interrupts cannot modify the
links while we are modifying them */
- env->current_tb = NULL;
+ cpu->current_tb = NULL;
for (i = 0; i < CPU_TLB_SIZE; i++) {
int mmu_idx;
void tlb_flush_page(CPUArchState *env, target_ulong addr)
{
+ CPUState *cpu = ENV_GET_CPU(env);
int i;
int mmu_idx;
}
/* must reset current TB so that interrupts cannot modify the
links while we are modifying them */
- env->current_tb = NULL;
+ cpu->current_tb = NULL;
addr &= TARGET_PAGE_MASK;
i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
}
}
-static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry)
+static inline ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr)
{
ram_addr_t ram_addr;
- void *p;
- if (tlb_is_dirty_ram(tlb_entry)) {
- p = (void *)(uintptr_t)((tlb_entry->addr_write & TARGET_PAGE_MASK)
- + tlb_entry->addend);
- ram_addr = qemu_ram_addr_from_host_nofail(p);
- if (!cpu_physical_memory_is_dirty(ram_addr)) {
- tlb_entry->addr_write |= TLB_NOTDIRTY;
- }
+ if (qemu_ram_addr_from_host(ptr, &ram_addr) == NULL) {
+ fprintf(stderr, "Bad ram pointer %p\n", ptr);
+ abort();
}
+ return ram_addr;
}
void cpu_tlb_reset_dirty_all(ram_addr_t start1, ram_addr_t length)
{
+ CPUState *cpu;
CPUArchState *env;
- for (env = first_cpu; env != NULL; env = env->next_cpu) {
+ CPU_FOREACH(cpu) {
int mmu_idx;
+ env = cpu->env_ptr;
for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
unsigned int i;
is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
supplied size is only used by tlb_flush_page. */
void tlb_set_page(CPUArchState *env, target_ulong vaddr,
- target_phys_addr_t paddr, int prot,
+ hwaddr paddr, int prot,
int mmu_idx, target_ulong size)
{
MemoryRegionSection *section;
target_ulong code_address;
uintptr_t addend;
CPUTLBEntry *te;
- target_phys_addr_t iotlb;
+ hwaddr iotlb, xlat, sz;
assert(size >= TARGET_PAGE_SIZE);
if (size != TARGET_PAGE_SIZE) {
tlb_add_large_page(env, vaddr, size);
}
- section = phys_page_find(paddr >> TARGET_PAGE_BITS);
+
+ sz = size;
+ section = address_space_translate_for_iotlb(&address_space_memory, paddr,
+ &xlat, &sz);
+ assert(sz >= TARGET_PAGE_SIZE);
+
#if defined(DEBUG_TLB)
printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx
- " prot=%x idx=%d pd=0x%08lx\n",
- vaddr, paddr, prot, mmu_idx, pd);
+ " prot=%x idx=%d\n",
+ vaddr, paddr, prot, mmu_idx);
#endif
address = vaddr;
- if (!(memory_region_is_ram(section->mr) ||
- memory_region_is_romd(section->mr))) {
- /* IO memory case (romd handled later) */
+ if (!memory_region_is_ram(section->mr) && !memory_region_is_romd(section->mr)) {
+ /* IO memory case */
address |= TLB_MMIO;
- }
- if (memory_region_is_ram(section->mr) ||
- memory_region_is_romd(section->mr)) {
- addend = (uintptr_t)memory_region_get_ram_ptr(section->mr)
- + memory_region_section_addr(section, paddr);
- } else {
addend = 0;
+ } else {
+ /* TLB_MMIO for rom/romd handled below */
+ addend = (uintptr_t)memory_region_get_ram_ptr(section->mr) + xlat;
}
code_address = address;
- iotlb = memory_region_section_get_iotlb(env, section, vaddr, paddr, prot,
- &address);
+ iotlb = memory_region_section_get_iotlb(env, section, vaddr, paddr, xlat,
+ prot, &address);
index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
env->iotlb[mmu_idx][index] = iotlb - vaddr;
/* Write access calls the I/O callback. */
te->addr_write = address | TLB_MMIO;
} else if (memory_region_is_ram(section->mr)
- && !cpu_physical_memory_is_dirty(
- section->mr->ram_addr
- + memory_region_section_addr(section, paddr))) {
+ && !cpu_physical_memory_is_dirty(section->mr->ram_addr + xlat)) {
te->addr_write = address | TLB_NOTDIRTY;
} else {
te->addr_write = address;
pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK;
mr = iotlb_to_region(pd);
if (memory_region_is_unassigned(mr)) {
-#if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_SPARC)
- cpu_unassigned_access(env1, addr, 0, 1, 0, 4);
-#else
- cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x"
- TARGET_FMT_lx "\n", addr);
-#endif
+ CPUState *cpu = ENV_GET_CPU(env1);
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (cc->do_unassigned_access) {
+ cc->do_unassigned_access(cpu, addr, false, true, 0, 4);
+ } else {
+ cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x"
+ TARGET_FMT_lx "\n", addr);
+ }
}
p = (void *)((uintptr_t)addr + env1->tlb_table[mmu_idx][page_index].addend);
return qemu_ram_addr_from_host_nofail(p);
#define SOFTMMU_CODE_ACCESS
#define SHIFT 0
-#include "softmmu_template.h"
+#include "exec/softmmu_template.h"
#define SHIFT 1
-#include "softmmu_template.h"
+#include "exec/softmmu_template.h"
#define SHIFT 2
-#include "softmmu_template.h"
+#include "exec/softmmu_template.h"
#define SHIFT 3
-#include "softmmu_template.h"
+#include "exec/softmmu_template.h"
#undef env
projects / qemu.git / blobdiff