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2ef2b01e A |
1 | /** @file\r |
2 | \r | |
d6ebcab7 | 3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r |
2ef2b01e | 4 | \r |
d6ebcab7 | 5 | This program and the accompanying materials\r |
2ef2b01e A |
6 | are licensed and made available under the terms and conditions of the BSD License\r |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #include "CpuDxe.h"\r | |
16 | \r | |
8a4d81e6 A |
17 | BOOLEAN mInterruptState = FALSE;\r |
18 | \r | |
f659880b A |
19 | \r |
20 | /**\r | |
21 | This function flushes the range of addresses from Start to Start+Length \r | |
22 | from the processor's data cache. If Start is not aligned to a cache line \r | |
23 | boundary, then the bytes before Start to the preceding cache line boundary \r | |
24 | are also flushed. If Start+Length is not aligned to a cache line boundary, \r | |
25 | then the bytes past Start+Length to the end of the next cache line boundary \r | |
26 | are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be \r | |
27 | supported. If the data cache is fully coherent with all DMA operations, then \r | |
28 | this function can just return EFI_SUCCESS. If the processor does not support \r | |
29 | flushing a range of the data cache, then the entire data cache can be flushed.\r | |
30 | \r | |
31 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
32 | @param Start The beginning physical address to flush from the processor's data\r | |
33 | cache.\r | |
34 | @param Length The number of bytes to flush from the processor's data cache. This\r | |
35 | function may flush more bytes than Length specifies depending upon\r | |
36 | the granularity of the flush operation that the processor supports.\r | |
37 | @param FlushType Specifies the type of flush operation to perform.\r | |
38 | \r | |
39 | @retval EFI_SUCCESS The address range from Start to Start+Length was flushed from\r | |
40 | the processor's data cache.\r | |
41 | @retval EFI_UNSUPPORTEDT The processor does not support the cache flush type specified\r | |
42 | by FlushType.\r | |
43 | @retval EFI_DEVICE_ERROR The address range from Start to Start+Length could not be flushed\r | |
44 | from the processor's data cache.\r | |
45 | \r | |
46 | **/\r | |
2ef2b01e A |
47 | EFI_STATUS\r |
48 | EFIAPI\r | |
49 | CpuFlushCpuDataCache (\r | |
50 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
51 | IN EFI_PHYSICAL_ADDRESS Start,\r | |
52 | IN UINT64 Length,\r | |
53 | IN EFI_CPU_FLUSH_TYPE FlushType\r | |
54 | )\r | |
55 | {\r | |
f659880b | 56 | \r |
2ef2b01e A |
57 | switch (FlushType) {\r |
58 | case EfiCpuFlushTypeWriteBack:\r | |
8a4d81e6 | 59 | WriteBackDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);\r |
2ef2b01e A |
60 | break;\r |
61 | case EfiCpuFlushTypeInvalidate:\r | |
8a4d81e6 | 62 | InvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);\r |
2ef2b01e A |
63 | break;\r |
64 | case EfiCpuFlushTypeWriteBackInvalidate:\r | |
8a4d81e6 | 65 | WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);\r |
2ef2b01e A |
66 | break;\r |
67 | default:\r | |
68 | return EFI_INVALID_PARAMETER;\r | |
69 | }\r | |
70 | \r | |
71 | return EFI_SUCCESS;\r | |
72 | }\r | |
73 | \r | |
f659880b A |
74 | \r |
75 | /**\r | |
76 | This function enables interrupt processing by the processor. \r | |
77 | \r | |
78 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
79 | \r | |
80 | @retval EFI_SUCCESS Interrupts are enabled on the processor.\r | |
81 | @retval EFI_DEVICE_ERROR Interrupts could not be enabled on the processor.\r | |
82 | \r | |
83 | **/\r | |
2ef2b01e A |
84 | EFI_STATUS\r |
85 | EFIAPI\r | |
86 | CpuEnableInterrupt (\r | |
87 | IN EFI_CPU_ARCH_PROTOCOL *This\r | |
88 | )\r | |
89 | {\r | |
d213712d | 90 | ArmEnableInterrupts ();\r |
8a4d81e6 A |
91 | \r |
92 | mInterruptState = TRUE;\r | |
2ef2b01e A |
93 | return EFI_SUCCESS;\r |
94 | }\r | |
95 | \r | |
96 | \r | |
f659880b A |
97 | /**\r |
98 | This function disables interrupt processing by the processor.\r | |
99 | \r | |
100 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
101 | \r | |
102 | @retval EFI_SUCCESS Interrupts are disabled on the processor.\r | |
103 | @retval EFI_DEVICE_ERROR Interrupts could not be disabled on the processor.\r | |
104 | \r | |
105 | **/\r | |
2ef2b01e A |
106 | EFI_STATUS\r |
107 | EFIAPI\r | |
108 | CpuDisableInterrupt (\r | |
109 | IN EFI_CPU_ARCH_PROTOCOL *This\r | |
110 | )\r | |
111 | {\r | |
d213712d | 112 | ArmDisableInterrupts ();\r |
8a4d81e6 A |
113 | \r |
114 | mInterruptState = FALSE;\r | |
2ef2b01e A |
115 | return EFI_SUCCESS;\r |
116 | }\r | |
117 | \r | |
f659880b A |
118 | \r |
119 | /**\r | |
120 | This function retrieves the processor's current interrupt state a returns it in \r | |
121 | State. If interrupts are currently enabled, then TRUE is returned. If interrupts \r | |
122 | are currently disabled, then FALSE is returned.\r | |
123 | \r | |
124 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
125 | @param State A pointer to the processor's current interrupt state. Set to TRUE if\r | |
126 | interrupts are enabled and FALSE if interrupts are disabled.\r | |
127 | \r | |
128 | @retval EFI_SUCCESS The processor's current interrupt state was returned in State.\r | |
129 | @retval EFI_INVALID_PARAMETER State is NULL.\r | |
130 | \r | |
131 | **/\r | |
2ef2b01e A |
132 | EFI_STATUS\r |
133 | EFIAPI\r | |
134 | CpuGetInterruptState (\r | |
135 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
136 | OUT BOOLEAN *State\r | |
137 | )\r | |
138 | {\r | |
139 | if (State == NULL) {\r | |
140 | return EFI_INVALID_PARAMETER;\r | |
141 | }\r | |
142 | \r | |
8a4d81e6 | 143 | *State = mInterruptState;\r |
2ef2b01e A |
144 | return EFI_SUCCESS;\r |
145 | }\r | |
146 | \r | |
f659880b A |
147 | \r |
148 | /**\r | |
149 | This function generates an INIT on the processor. If this function succeeds, then the\r | |
150 | processor will be reset, and control will not be returned to the caller. If InitType is \r | |
151 | not supported by this processor, or the processor cannot programmatically generate an \r | |
152 | INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error \r | |
153 | occurs attempting to generate an INIT, then EFI_DEVICE_ERROR is returned.\r | |
154 | \r | |
155 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
156 | @param InitType The type of processor INIT to perform.\r | |
157 | \r | |
158 | @retval EFI_SUCCESS The processor INIT was performed. This return code should never be seen.\r | |
159 | @retval EFI_UNSUPPORTED The processor INIT operation specified by InitType is not supported\r | |
160 | by this processor.\r | |
161 | @retval EFI_DEVICE_ERROR The processor INIT failed.\r | |
162 | \r | |
163 | **/\r | |
2ef2b01e A |
164 | EFI_STATUS\r |
165 | EFIAPI\r | |
166 | CpuInit (\r | |
167 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
168 | IN EFI_CPU_INIT_TYPE InitType\r | |
169 | )\r | |
170 | {\r | |
171 | return EFI_UNSUPPORTED;\r | |
172 | }\r | |
173 | \r | |
174 | EFI_STATUS\r | |
175 | EFIAPI\r | |
176 | CpuRegisterInterruptHandler (\r | |
177 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
178 | IN EFI_EXCEPTION_TYPE InterruptType,\r | |
179 | IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r | |
180 | )\r | |
181 | {\r | |
8a4d81e6 | 182 | return RegisterInterruptHandler (InterruptType, InterruptHandler);\r |
2ef2b01e A |
183 | }\r |
184 | \r | |
185 | EFI_STATUS\r | |
186 | EFIAPI\r | |
187 | CpuGetTimerValue (\r | |
188 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
189 | IN UINT32 TimerIndex,\r | |
190 | OUT UINT64 *TimerValue,\r | |
191 | OUT UINT64 *TimerPeriod OPTIONAL\r | |
192 | )\r | |
193 | {\r | |
194 | return EFI_UNSUPPORTED;\r | |
195 | }\r | |
196 | \r | |
2ef2b01e A |
197 | \r |
198 | //\r | |
199 | // Globals used to initialize the protocol\r | |
200 | //\r | |
201 | EFI_HANDLE mCpuHandle = NULL;\r | |
202 | EFI_CPU_ARCH_PROTOCOL mCpu = {\r | |
203 | CpuFlushCpuDataCache,\r | |
204 | CpuEnableInterrupt,\r | |
205 | CpuDisableInterrupt,\r | |
206 | CpuGetInterruptState,\r | |
207 | CpuInit,\r | |
208 | CpuRegisterInterruptHandler,\r | |
209 | CpuGetTimerValue,\r | |
210 | CpuSetMemoryAttributes,\r | |
211 | 0, // NumberOfTimers\r | |
212 | 4, // DmaBufferAlignment\r | |
213 | };\r | |
214 | \r | |
215 | EFI_STATUS\r | |
216 | CpuDxeInitialize (\r | |
217 | IN EFI_HANDLE ImageHandle,\r | |
218 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
219 | )\r | |
f659880b A |
220 | {\r |
221 | EFI_STATUS Status;\r | |
222 | \r | |
8a4d81e6 | 223 | InitializeExceptions (&mCpu); \r |
f659880b A |
224 | \r |
225 | \r | |
226 | Status = gBS->InstallMultipleProtocolInterfaces (\r | |
227 | &mCpuHandle, \r | |
228 | &gEfiCpuArchProtocolGuid, &mCpu, \r | |
229 | &gVirtualUncachedPagesProtocolGuid, &gVirtualUncachedPages,\r | |
230 | NULL\r | |
231 | );\r | |
232 | \r | |
233 | //\r | |
234 | // Make sure GCD and MMU settings match. This API calls gDS->SetMemorySpaceAttributes ()\r | |
235 | // and that calls EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes, so this code needs to go\r | |
236 | // after the protocol is installed\r | |
237 | //\r | |
238 | SyncCacheConfig (&mCpu);\r | |
239 | \r | |
240 | return Status;\r | |
2ef2b01e A |
241 | }\r |
242 | \r |