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aeb61534 A |
1 | /*++\r |
2 | \r | |
d6ebcab7 HT |
3 | Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>\r |
4 | Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>\r | |
aeb61534 | 5 | \r |
d6ebcab7 | 6 | This program and the accompanying materials \r |
aeb61534 A |
7 | are licensed and made available under the terms and conditions of the BSD License \r |
8 | which accompanies this distribution. The full text of the license may be found at \r | |
9 | http://opensource.org/licenses/bsd-license.php \r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
13 | \r | |
14 | \r | |
15 | --*/\r | |
16 | \r | |
17 | #include "CpuDxe.h"\r | |
18 | \r | |
f659880b | 19 | \r |
aeb61534 A |
20 | //\r |
21 | // Translation/page table definitions\r | |
22 | //\r | |
23 | \r | |
24 | // First Level Descriptors\r | |
25 | typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR;\r | |
26 | \r | |
27 | // memory space covered by a first level descriptor\r | |
28 | #define ARM_PAGE_DESC_ENTRY_MVA_SIZE 0x00100000 // 1MB\r | |
29 | \r | |
30 | // number of first level descriptors to cover entire 32-bit memory space\r | |
31 | #define FIRST_LEVEL_ENTRY_COUNT (0xFFFFFFFF / ARM_PAGE_DESC_ENTRY_MVA_SIZE + 1)\r | |
32 | \r | |
33 | \r | |
34 | // page table 1st level descriptor entries\r | |
35 | #define ARM_PAGE_DESC_BASE_MASK 0xFFFFFC00\r | |
36 | #define ARM_PAGE_DESC_BASE_SHFIT 10\r | |
37 | #define ARM_PAGE_DESC_DOMAIN_MASK 0x000001E0\r | |
38 | #define ARM_PAGE_DESC_DOMAIN_SHIFT 5\r | |
39 | #define ARM_PAGE_DESC_NS 0x00000008\r | |
40 | \r | |
41 | #define ARM_FIRST_LEVEL_DESC_ALIGN 0x00004000 // 16KB\r | |
42 | \r | |
43 | // section 1st level desriptor entries\r | |
44 | #define ARM_SECTION_BASE_MASK 0xFFF00000\r | |
45 | #define ARM_SECTION_BASE_SHIFT 20\r | |
46 | #define ARM_SECTION_NS 0x00080000\r | |
47 | #define ARM_SECTION_nG 0x00020000\r | |
48 | #define ARM_SECTION_S 0x00010000\r | |
49 | #define ARM_SECTION_AP2 0x00008000\r | |
50 | #define ARM_SECTION_TEX_MASK 0x00007000\r | |
51 | #define ARM_SECTION_TEX_SHIFT 12\r | |
52 | #define ARM_SECTION_AP10_MASK 0x00000C00\r | |
53 | #define ARM_SECTION_AP10_SHIFT 10\r | |
54 | #define ARM_SECTION_DOMAIN_MASK 0x000001E0\r | |
55 | #define ARM_SECTION_DOMAIN_SHIFT 5\r | |
56 | #define ARM_SECTION_XN 0x00000010\r | |
57 | #define ARM_SECTION_C 0x00000008\r | |
58 | #define ARM_SECTION_B 0x00000004\r | |
59 | \r | |
60 | // section level AP[2:0] definitions\r | |
61 | #define ARM_SECTION_AP_NO_ACCESS 0 // AP[2:0] = 0\r | |
62 | #define ARM_SECTION_AP_READ_WRITE ARM_SECTION_AP10_MASK // AP[2:0] = 011\r | |
63 | #define ARM_SECTION_AP_READ_ONLY (ARM_SECTION_AP2 | ARM_SECTION_AP10_MASK) // AP[2:0] = 111\r | |
64 | \r | |
65 | // common 1st level descriptor fields\r | |
66 | #define ARM_DESC_TYPE_MASK 0x00000003\r | |
67 | \r | |
68 | // descriptor type values\r | |
69 | #define ARM_DESC_TYPE_FAULT 0x0\r | |
70 | #define ARM_DESC_TYPE_PAGE_TABLE 0x1\r | |
71 | #define ARM_DESC_TYPE_SECTION 0x2\r | |
72 | \r | |
73 | \r | |
74 | // Second Level Descriptors\r | |
75 | typedef UINT32 ARM_PAGE_TABLE_ENTRY;\r | |
76 | \r | |
77 | // small page 2nd level descriptor entries\r | |
78 | #define ARM_SMALL_PAGE_BASE_MASK 0xFFFFF000\r | |
79 | #define ARM_SMALL_PAGE_INDEX_MASK 0x000FF000\r | |
80 | #define ARM_SMALL_PAGE_BASE_SHIFT 12\r | |
81 | #define ARM_SMALL_PAGE_TEX_MASK 0x000001C0\r | |
82 | #define ARM_SMALL_PAGE_TEX_SHIFT 6\r | |
83 | #define ARM_SMALL_PAGE_XN 0x00000001\r | |
84 | \r | |
85 | // large page 2nd level descriptor entries\r | |
86 | #define ARM_LARGE_PAGE_BASE_MASK 0xFFFF0000\r | |
87 | #define ARM_LARGE_PAGE_BASE_SHIFT 16\r | |
88 | #define ARM_LARGE_PAGE_TEX_MASK 0x00007000\r | |
89 | #define ARM_LARGE_PAGE_TEX_SHIFT 12\r | |
90 | #define ARM_LARGE_PAGE_XN 0x00008000\r | |
91 | \r | |
92 | // common 2nd level desriptor fields\r | |
93 | #define ARM_PAGE_nG 0x00000800\r | |
94 | #define ARM_PAGE_S 0x00000400\r | |
95 | #define ARM_PAGE_AP2 0x00000200\r | |
96 | #define ARM_PAGE_AP10_MASK 0x00000030\r | |
97 | #define ARM_PAGE_AP10_SHIFT 4\r | |
98 | #define ARM_PAGE_C 0x00000008\r | |
99 | #define ARM_PAGE_B 0x00000004\r | |
100 | #define ARM_PAGE_DESC_TYPE_MASK 0x00000003\r | |
101 | \r | |
102 | // descriptor type values\r | |
103 | #define ARM_PAGE_TYPE_FAULT 0x0\r | |
104 | #define ARM_PAGE_TYPE_LARGE 0x1\r | |
105 | #define ARM_PAGE_TYPE_SMALL 0x2\r | |
106 | #define ARM_PAGE_TYPE_SMALL_XN 0x3\r | |
107 | \r | |
bb02cb80 | 108 | #define SMALL_PAGE_TABLE_ENTRY_COUNT (ARM_PAGE_DESC_ENTRY_MVA_SIZE / SIZE_4KB)\r |
aeb61534 A |
109 | \r |
110 | \r | |
111 | // Translation Table Base 0 fields\r | |
112 | #define ARM_TTBR0_BASE_MASK 0xFFFFC000\r | |
113 | #define ARM_TTBR0_BASE_SHIFT 14\r | |
114 | #define ARM_TTRB0_NOS 0x00000020\r | |
115 | \r | |
116 | // define the combination of interesting attributes: cacheability and access permissions\r | |
117 | #define ARM_SECTION_CACHEABILITY_MASK ( ARM_SECTION_TEX_MASK | ARM_SECTION_C | ARM_SECTION_B )\r | |
118 | #define ARM_SECTION_RW_PERMISSIONS_MASK ( ARM_SECTION_AP2 | ARM_SECTION_AP10_MASK )\r | |
119 | #define ARM_DESCRIPTOR_ATTRIBUTES ( ARM_SECTION_CACHEABILITY_MASK | ARM_SECTION_RW_PERMISSIONS_MASK | ARM_SECTION_XN )\r | |
120 | \r | |
121 | // cacheability values for section entries\r | |
122 | #define ARM_SECTION_STRONGLY_ORDERED 0\r | |
123 | #define ARM_SECTION_SHAREABLE_DEVICE ARM_SECTION_B\r | |
124 | #define ARM_SECTION_WRITE_THROUGH ARM_SECTION_C\r | |
125 | #define ARM_SECTION_WRITE_BACK_NWA ( ARM_SECTION_C| ARM_SECTION_B )\r | |
126 | #define ARM_SECTION_NORMAL_UNCACHEABLE ( 0x1 << ARM_SECTION_TEX_SHIFT )\r | |
127 | #define ARM_SECTION_WRITE_BACK ( ( 0x1 << ARM_SECTION_TEX_SHIFT ) | ARM_SECTION_C | ARM_SECTION_B )\r | |
128 | #define ARM_SECTION_NONSHAREABLE_DEVICE ( 0x2 << ARM_SECTION_TEX_SHIFT )\r | |
129 | \r | |
130 | // permissions values for section entries\r | |
131 | #define ARM_SECTION_NO_ACCESS 0\r | |
132 | #define ARM_SECTION_PRIV_ACCESS_ONLY ( 0x1 << ARM_SECTION_AP10_SHIFT)\r | |
133 | #define ARM_SECTION_USER_READ_ONLY ( 0x2 << ARM_SECTION_AP10_SHIFT)\r | |
134 | #define ARM_SECTION_FULL_ACCESS ( 0x3 << ARM_SECTION_AP10_SHIFT)\r | |
135 | #define ARM_SECTION_PRIV_READ_ONLY ( ARM_SECTION_AP2 | (0x1 << ARM_SECTION_AP10_SHIFT) )\r | |
136 | #define ARM_SECTION_READ_ONLY_DEP ( ARM_SECTION_AP2 | (0x2 << ARM_SECTION_AP10_SHIFT) )\r | |
137 | #define ARM_SECTION_READ_ONLY ( ARM_SECTION_AP2 | (0x3 << ARM_SECTION_AP10_SHIFT) )\r | |
138 | \r | |
139 | \r | |
140 | \r | |
141 | EFI_STATUS \r | |
142 | SectionToGcdAttributes (\r | |
143 | IN UINT32 SectionAttributes,\r | |
144 | OUT UINT64 *GcdAttributes\r | |
145 | )\r | |
146 | {\r | |
147 | *GcdAttributes = 0;\r | |
148 | \r | |
149 | // determine cacheability attributes\r | |
150 | switch(SectionAttributes & ARM_SECTION_CACHEABILITY_MASK) {\r | |
151 | case ARM_SECTION_STRONGLY_ORDERED:\r | |
152 | *GcdAttributes |= EFI_MEMORY_UC;\r | |
153 | break;\r | |
154 | case ARM_SECTION_SHAREABLE_DEVICE:\r | |
155 | *GcdAttributes |= EFI_MEMORY_UC;\r | |
156 | break;\r | |
157 | case ARM_SECTION_WRITE_THROUGH:\r | |
158 | *GcdAttributes |= EFI_MEMORY_WT;\r | |
159 | break;\r | |
160 | case ARM_SECTION_WRITE_BACK_NWA:\r | |
161 | *GcdAttributes |= EFI_MEMORY_WB;\r | |
162 | break;\r | |
163 | case ARM_SECTION_NORMAL_UNCACHEABLE:\r | |
164 | *GcdAttributes |= EFI_MEMORY_WC;\r | |
165 | break;\r | |
166 | case ARM_SECTION_WRITE_BACK:\r | |
167 | *GcdAttributes |= EFI_MEMORY_WB;\r | |
168 | break;\r | |
169 | case ARM_SECTION_NONSHAREABLE_DEVICE:\r | |
170 | *GcdAttributes |= EFI_MEMORY_UC;\r | |
171 | break;\r | |
172 | default:\r | |
173 | return EFI_UNSUPPORTED;\r | |
aeb61534 A |
174 | }\r |
175 | \r | |
176 | // determine protection attributes\r | |
177 | switch(SectionAttributes & ARM_SECTION_RW_PERMISSIONS_MASK) {\r | |
178 | case ARM_SECTION_NO_ACCESS: // no read, no write\r | |
f659880b | 179 | //*GcdAttributes |= EFI_MEMORY_WP | EFI_MEMORY_RP;\r |
aeb61534 A |
180 | break;\r |
181 | \r | |
182 | case ARM_SECTION_PRIV_ACCESS_ONLY:\r | |
183 | case ARM_SECTION_FULL_ACCESS:\r | |
184 | // normal read/write access, do not add additional attributes\r | |
185 | break;\r | |
186 | \r | |
187 | // read only cases map to write-protect\r | |
188 | case ARM_SECTION_PRIV_READ_ONLY:\r | |
189 | case ARM_SECTION_READ_ONLY_DEP:\r | |
190 | case ARM_SECTION_READ_ONLY:\r | |
191 | *GcdAttributes |= EFI_MEMORY_WP;\r | |
192 | break;\r | |
193 | \r | |
194 | default:\r | |
195 | return EFI_UNSUPPORTED;\r | |
aeb61534 A |
196 | }\r |
197 | \r | |
198 | // now process eXectue Never attribute\r | |
199 | if ((SectionAttributes & ARM_SECTION_XN) != 0 ) {\r | |
200 | *GcdAttributes |= EFI_MEMORY_XP;\r | |
201 | }\r | |
202 | \r | |
203 | return EFI_SUCCESS;\r | |
204 | }\r | |
205 | \r | |
f659880b A |
206 | /**\r |
207 | Searches memory descriptors covered by given memory range.\r | |
208 | \r | |
209 | This function searches into the Gcd Memory Space for descriptors\r | |
210 | (from StartIndex to EndIndex) that contains the memory range\r | |
211 | specified by BaseAddress and Length.\r | |
212 | \r | |
213 | @param MemorySpaceMap Gcd Memory Space Map as array.\r | |
214 | @param NumberOfDescriptors Number of descriptors in map.\r | |
215 | @param BaseAddress BaseAddress for the requested range.\r | |
216 | @param Length Length for the requested range.\r | |
217 | @param StartIndex Start index into the Gcd Memory Space Map.\r | |
218 | @param EndIndex End index into the Gcd Memory Space Map.\r | |
219 | \r | |
220 | @retval EFI_SUCCESS Search successfully.\r | |
221 | @retval EFI_NOT_FOUND The requested descriptors does not exist.\r | |
222 | \r | |
223 | **/\r | |
224 | EFI_STATUS\r | |
225 | SearchGcdMemorySpaces (\r | |
226 | IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,\r | |
227 | IN UINTN NumberOfDescriptors,\r | |
228 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
229 | IN UINT64 Length,\r | |
230 | OUT UINTN *StartIndex,\r | |
231 | OUT UINTN *EndIndex\r | |
232 | )\r | |
233 | {\r | |
234 | UINTN Index;\r | |
235 | \r | |
236 | *StartIndex = 0;\r | |
237 | *EndIndex = 0;\r | |
238 | for (Index = 0; Index < NumberOfDescriptors; Index++) {\r | |
239 | if (BaseAddress >= MemorySpaceMap[Index].BaseAddress &&\r | |
240 | BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r | |
241 | *StartIndex = Index;\r | |
242 | }\r | |
243 | if (BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress &&\r | |
244 | BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r | |
245 | *EndIndex = Index;\r | |
246 | return EFI_SUCCESS;\r | |
247 | }\r | |
248 | }\r | |
249 | return EFI_NOT_FOUND;\r | |
250 | }\r | |
251 | \r | |
252 | \r | |
253 | /**\r | |
254 | Sets the attributes for a specified range in Gcd Memory Space Map.\r | |
255 | \r | |
256 | This function sets the attributes for a specified range in\r | |
257 | Gcd Memory Space Map.\r | |
258 | \r | |
259 | @param MemorySpaceMap Gcd Memory Space Map as array\r | |
260 | @param NumberOfDescriptors Number of descriptors in map\r | |
261 | @param BaseAddress BaseAddress for the range\r | |
262 | @param Length Length for the range\r | |
263 | @param Attributes Attributes to set\r | |
264 | \r | |
265 | @retval EFI_SUCCESS Memory attributes set successfully\r | |
266 | @retval EFI_NOT_FOUND The specified range does not exist in Gcd Memory Space\r | |
267 | \r | |
268 | **/\r | |
269 | EFI_STATUS\r | |
270 | SetGcdMemorySpaceAttributes (\r | |
271 | IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,\r | |
272 | IN UINTN NumberOfDescriptors,\r | |
273 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
274 | IN UINT64 Length,\r | |
275 | IN UINT64 Attributes\r | |
276 | )\r | |
277 | {\r | |
278 | EFI_STATUS Status;\r | |
279 | UINTN Index;\r | |
280 | UINTN StartIndex;\r | |
281 | UINTN EndIndex;\r | |
282 | EFI_PHYSICAL_ADDRESS RegionStart;\r | |
283 | UINT64 RegionLength;\r | |
284 | \r | |
285 | //\r | |
286 | // Get all memory descriptors covered by the memory range\r | |
287 | //\r | |
288 | Status = SearchGcdMemorySpaces (\r | |
289 | MemorySpaceMap,\r | |
290 | NumberOfDescriptors,\r | |
291 | BaseAddress,\r | |
292 | Length,\r | |
293 | &StartIndex,\r | |
294 | &EndIndex\r | |
295 | );\r | |
296 | if (EFI_ERROR (Status)) {\r | |
297 | return Status;\r | |
298 | }\r | |
299 | \r | |
300 | //\r | |
301 | // Go through all related descriptors and set attributes accordingly\r | |
302 | //\r | |
303 | for (Index = StartIndex; Index <= EndIndex; Index++) {\r | |
304 | if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {\r | |
305 | continue;\r | |
306 | }\r | |
307 | //\r | |
308 | // Calculate the start and end address of the overlapping range\r | |
309 | //\r | |
310 | if (BaseAddress >= MemorySpaceMap[Index].BaseAddress) {\r | |
311 | RegionStart = BaseAddress;\r | |
312 | } else {\r | |
313 | RegionStart = MemorySpaceMap[Index].BaseAddress;\r | |
314 | }\r | |
315 | if (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r | |
316 | RegionLength = BaseAddress + Length - RegionStart;\r | |
317 | } else {\r | |
318 | RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;\r | |
319 | }\r | |
320 | //\r | |
321 | // Set memory attributes according to MTRR attribute and the original attribute of descriptor\r | |
322 | //\r | |
323 | gDS->SetMemorySpaceAttributes (\r | |
324 | RegionStart,\r | |
325 | RegionLength,\r | |
326 | (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (MemorySpaceMap[Index].Capabilities & Attributes)\r | |
327 | );\r | |
328 | }\r | |
329 | \r | |
330 | return EFI_SUCCESS;\r | |
331 | }\r | |
aeb61534 A |
332 | \r |
333 | \r | |
334 | EFI_STATUS\r | |
335 | SyncCacheConfig (\r | |
336 | IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol\r | |
337 | )\r | |
338 | {\r | |
f659880b A |
339 | EFI_STATUS Status;\r |
340 | UINT32 i;\r | |
341 | UINT32 Descriptor;\r | |
342 | UINT32 SectionAttributes;\r | |
343 | EFI_PHYSICAL_ADDRESS NextRegionBase;\r | |
344 | UINT64 NextRegionLength;\r | |
345 | UINT64 GcdAttributes;\r | |
346 | UINT32 NextRegionAttributes = 0;\r | |
aeb61534 | 347 | volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r |
f659880b A |
348 | UINTN NumberOfDescriptors;\r |
349 | EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;\r | |
aeb61534 A |
350 | \r |
351 | \r | |
225290eb | 352 | DEBUG ((EFI_D_PAGE, "SyncCacheConfig()\n"));\r |
f659880b | 353 | \r |
aeb61534 A |
354 | // This code assumes MMU is enabled and filed with section translations\r |
355 | ASSERT (ArmMmuEnabled ());\r | |
356 | \r | |
f659880b A |
357 | //\r |
358 | // Get the memory space map from GCD\r | |
359 | //\r | |
360 | MemorySpaceMap = NULL;\r | |
361 | Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);\r | |
362 | ASSERT_EFI_ERROR (Status);\r | |
363 | \r | |
aeb61534 A |
364 | \r |
365 | // The GCD implementation maintains its own copy of the state of memory space attributes. GCD needs\r | |
366 | // to know what the initial memory space attributes are. The CPU Arch. Protocol does not provide a\r | |
367 | // GetMemoryAttributes function for GCD to get this so we must resort to calling GCD (as if we were\r | |
368 | // a client) to update its copy of the attributes. This is bad architecture and should be replaced\r | |
369 | // with a way for GCD to query the CPU Arch. driver of the existing memory space attributes instead.\r | |
370 | \r | |
371 | // obtain page table base\r | |
372 | FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)(ArmGetTranslationTableBaseAddress ());\r | |
373 | \r | |
374 | \r | |
375 | // iterate through each 1MB descriptor\r | |
376 | NextRegionBase = NextRegionLength = 0;\r | |
377 | for (i=0; i< FIRST_LEVEL_ENTRY_COUNT; i++) {\r | |
378 | \r | |
f659880b A |
379 | // obtain existing descriptor and make sure it contains a valid Base Address even if it is a fault section\r |
380 | Descriptor = FirstLevelTable[i] | (ARM_SECTION_BASE_MASK & (i << ARM_SECTION_BASE_SHIFT));\r | |
aeb61534 A |
381 | \r |
382 | // extract attributes (cacheability and permissions)\r | |
383 | SectionAttributes = Descriptor & 0xDEC;\r | |
384 | \r | |
385 | // do we already have an existing region (or are we about to finish)?\r | |
386 | // Skip the first entry, and make sure we close on the last entry\r | |
387 | if ( (NextRegionLength > 0) || (i == (FIRST_LEVEL_ENTRY_COUNT-1)) ) {\r | |
388 | // attributes are changing, update attributes in GCD\r | |
389 | if (SectionAttributes != NextRegionAttributes) {\r | |
390 | \r | |
391 | // convert section entry attributes to GCD bitmask\r | |
392 | Status = SectionToGcdAttributes (NextRegionAttributes, &GcdAttributes);\r | |
f659880b | 393 | ASSERT_EFI_ERROR (Status);\r |
aeb61534 A |
394 | \r |
395 | // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)\r | |
f659880b A |
396 | SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);\r |
397 | \r | |
aeb61534 A |
398 | \r |
399 | // start on a new region\r | |
400 | NextRegionLength = 0;\r | |
401 | NextRegionBase = Descriptor & ARM_SECTION_BASE_MASK;\r | |
402 | }\r | |
403 | }\r | |
404 | \r | |
405 | // starting a new region?\r | |
406 | if (NextRegionLength == 0) {\r | |
407 | NextRegionAttributes = SectionAttributes;\r | |
408 | }\r | |
409 | \r | |
410 | NextRegionLength += ARM_PAGE_DESC_ENTRY_MVA_SIZE;\r | |
411 | \r | |
412 | } // section entry loop\r | |
413 | \r | |
414 | return EFI_SUCCESS;\r | |
415 | }\r | |
416 | \r | |
417 | \r | |
418 | \r | |
419 | EFI_STATUS\r | |
420 | UpdatePageEntries (\r | |
421 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
422 | IN UINT64 Length,\r | |
423 | IN UINT64 Attributes,\r | |
424 | IN EFI_PHYSICAL_ADDRESS VirtualMask\r | |
425 | )\r | |
426 | {\r | |
427 | EFI_STATUS Status;\r | |
428 | UINT32 EntryValue;\r | |
429 | UINT32 EntryMask;\r | |
430 | UINT32 FirstLevelIdx;\r | |
431 | UINT32 Offset;\r | |
432 | UINT32 NumPageEntries;\r | |
433 | UINT32 Descriptor;\r | |
434 | UINT32 p;\r | |
435 | UINT32 PageTableIndex;\r | |
436 | UINT32 PageTableEntry;\r | |
bb02cb80 | 437 | UINT32 CurrentPageTableEntry;\r |
438 | VOID *Mva;\r | |
aeb61534 A |
439 | \r |
440 | volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r | |
441 | volatile ARM_PAGE_TABLE_ENTRY *PageTable;\r | |
442 | \r | |
920cb926 A |
443 | Status = EFI_SUCCESS;\r |
444 | \r | |
aeb61534 A |
445 | // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)\r |
446 | // EntryValue: values at bit positions specified by EntryMask\r | |
d4f167a9 A |
447 | EntryMask = ARM_PAGE_DESC_TYPE_MASK;\r |
448 | EntryValue = ARM_PAGE_TYPE_SMALL;\r | |
aeb61534 A |
449 | // Although the PI spec is unclear on this the GCD guarantees that only\r |
450 | // one Attribute bit is set at a time, so we can safely use a switch statement\r | |
451 | switch (Attributes) {\r | |
452 | case EFI_MEMORY_UC:\r | |
453 | // modify cacheability attributes\r | |
d4f167a9 | 454 | EntryMask |= ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r |
aeb61534 | 455 | // map to strongly ordered\r |
d4f167a9 | 456 | EntryValue |= 0; // TEX[2:0] = 0, C=0, B=0\r |
aeb61534 A |
457 | break;\r |
458 | \r | |
459 | case EFI_MEMORY_WC:\r | |
460 | // modify cacheability attributes\r | |
d4f167a9 | 461 | EntryMask |= ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r |
aeb61534 | 462 | // map to normal non-cachable\r |
d4f167a9 | 463 | EntryValue |= (0x1 << ARM_SMALL_PAGE_TEX_SHIFT); // TEX [2:0]= 001 = 0x2, B=0, C=0\r |
aeb61534 A |
464 | break;\r |
465 | \r | |
466 | case EFI_MEMORY_WT:\r | |
467 | // modify cacheability attributes\r | |
d4f167a9 | 468 | EntryMask |= ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r |
aeb61534 | 469 | // write through with no-allocate\r |
d4f167a9 | 470 | EntryValue |= ARM_PAGE_C; // TEX [2:0] = 0, C=1, B=0\r |
aeb61534 A |
471 | break;\r |
472 | \r | |
473 | case EFI_MEMORY_WB:\r | |
474 | // modify cacheability attributes\r | |
d4f167a9 | 475 | EntryMask |= ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;\r |
aeb61534 | 476 | // write back (with allocate)\r |
d4f167a9 | 477 | EntryValue |= (0x1 << ARM_SMALL_PAGE_TEX_SHIFT) | ARM_PAGE_C | ARM_PAGE_B; // TEX [2:0] = 001, C=1, B=1\r |
aeb61534 A |
478 | break;\r |
479 | \r | |
480 | case EFI_MEMORY_WP:\r | |
481 | case EFI_MEMORY_XP:\r | |
482 | case EFI_MEMORY_UCE:\r | |
483 | // cannot be implemented UEFI definition unclear for ARM\r | |
484 | // Cause a page fault if these ranges are accessed.\r | |
d4f167a9 | 485 | EntryValue = ARM_PAGE_TYPE_FAULT;\r |
225290eb | 486 | DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting page %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));\r |
aeb61534 A |
487 | break;\r |
488 | \r | |
489 | default:\r | |
490 | return EFI_UNSUPPORTED;\r | |
aeb61534 A |
491 | }\r |
492 | \r | |
493 | // obtain page table base\r | |
494 | FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTranslationTableBaseAddress ();\r | |
495 | \r | |
496 | // calculate number of 4KB page table entries to change\r | |
bb02cb80 | 497 | NumPageEntries = Length/SIZE_4KB;\r |
aeb61534 A |
498 | \r |
499 | // iterate for the number of 4KB pages to change\r | |
500 | Offset = 0;\r | |
501 | for(p=0; p<NumPageEntries; p++) {\r | |
502 | // calculate index into first level translation table for page table value\r | |
503 | \r | |
504 | FirstLevelIdx = ((BaseAddress + Offset) & ARM_SECTION_BASE_MASK) >> ARM_SECTION_BASE_SHIFT;\r | |
505 | ASSERT (FirstLevelIdx < FIRST_LEVEL_ENTRY_COUNT);\r | |
506 | \r | |
507 | // read the descriptor from the first level page table\r | |
508 | Descriptor = FirstLevelTable[FirstLevelIdx];\r | |
509 | \r | |
510 | // does this descriptor need to be converted from section entry to 4K pages?\r | |
f659880b | 511 | if ((Descriptor & ARM_DESC_TYPE_MASK) != ARM_DESC_TYPE_PAGE_TABLE ) {\r |
aeb61534 A |
512 | Status = ConvertSectionToPages (FirstLevelIdx << ARM_SECTION_BASE_SHIFT);\r |
513 | if (EFI_ERROR(Status)) {\r | |
514 | // exit for loop\r | |
515 | break; \r | |
516 | } \r | |
517 | \r | |
518 | // re-read descriptor\r | |
519 | Descriptor = FirstLevelTable[FirstLevelIdx];\r | |
520 | }\r | |
521 | \r | |
522 | // obtain page table base address\r | |
523 | PageTable = (ARM_PAGE_TABLE_ENTRY *)(Descriptor & ARM_SMALL_PAGE_BASE_MASK);\r | |
524 | \r | |
525 | // calculate index into the page table\r | |
526 | PageTableIndex = ((BaseAddress + Offset) & ARM_SMALL_PAGE_INDEX_MASK) >> ARM_SMALL_PAGE_BASE_SHIFT;\r | |
f659880b | 527 | ASSERT (PageTableIndex < SMALL_PAGE_TABLE_ENTRY_COUNT);\r |
aeb61534 A |
528 | \r |
529 | // get the entry\r | |
bb02cb80 | 530 | CurrentPageTableEntry = PageTable[PageTableIndex];\r |
aeb61534 A |
531 | \r |
532 | // mask off appropriate fields\r | |
bb02cb80 | 533 | PageTableEntry = CurrentPageTableEntry & ~EntryMask;\r |
aeb61534 A |
534 | \r |
535 | // mask in new attributes and/or permissions\r | |
536 | PageTableEntry |= EntryValue;\r | |
537 | \r | |
538 | if (VirtualMask != 0) {\r | |
539 | // Make this virtual address point at a physical page\r | |
540 | PageTableEntry &= ~VirtualMask;\r | |
541 | }\r | |
aeb61534 | 542 | \r |
bb02cb80 | 543 | if (CurrentPageTableEntry != PageTableEntry) {\r |
544 | Mva = (VOID *)(UINTN)((((UINTN)FirstLevelIdx) << ARM_SECTION_BASE_SHIFT) + (PageTableIndex << ARM_SMALL_PAGE_BASE_SHIFT));\r | |
545 | if ((CurrentPageTableEntry & ARM_PAGE_C) == ARM_PAGE_C) {\r | |
546 | // The current section mapping is cacheable so Clean/Invalidate the MVA of the page\r | |
547 | // Note assumes switch(Attributes), not ARMv7 possibilities\r | |
548 | WriteBackInvalidateDataCacheRange (Mva, SIZE_4KB);\r | |
549 | }\r | |
550 | \r | |
551 | // Only need to update if we are changing the entry \r | |
552 | PageTable[PageTableIndex] = PageTableEntry; \r | |
553 | ArmUpdateTranslationTableEntry ((VOID *)&PageTable[PageTableIndex], Mva);\r | |
554 | }\r | |
aeb61534 A |
555 | \r |
556 | Status = EFI_SUCCESS;\r | |
bb02cb80 | 557 | Offset += SIZE_4KB;\r |
aeb61534 A |
558 | \r |
559 | } // end first level translation table loop\r | |
560 | \r | |
561 | return Status;\r | |
562 | }\r | |
563 | \r | |
564 | \r | |
565 | \r | |
566 | EFI_STATUS\r | |
567 | UpdateSectionEntries (\r | |
568 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
569 | IN UINT64 Length,\r | |
570 | IN UINT64 Attributes,\r | |
571 | IN EFI_PHYSICAL_ADDRESS VirtualMask\r | |
572 | )\r | |
573 | {\r | |
574 | EFI_STATUS Status = EFI_SUCCESS;\r | |
575 | UINT32 EntryMask;\r | |
576 | UINT32 EntryValue;\r | |
577 | UINT32 FirstLevelIdx;\r | |
578 | UINT32 NumSections;\r | |
579 | UINT32 i;\r | |
bb02cb80 | 580 | UINT32 CurrentDescriptor;\r |
aeb61534 | 581 | UINT32 Descriptor;\r |
bb02cb80 | 582 | VOID *Mva;\r |
aeb61534 A |
583 | volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r |
584 | \r | |
585 | // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)\r | |
586 | // EntryValue: values at bit positions specified by EntryMask\r | |
587 | \r | |
f659880b A |
588 | // Make sure we handle a section range that is unmapped \r |
589 | EntryMask = ARM_DESC_TYPE_MASK;\r | |
590 | EntryValue = ARM_DESC_TYPE_SECTION;\r | |
591 | \r | |
aeb61534 A |
592 | // Although the PI spec is unclear on this the GCD guarantees that only\r |
593 | // one Attribute bit is set at a time, so we can safely use a switch statement\r | |
594 | switch(Attributes) {\r | |
595 | case EFI_MEMORY_UC:\r | |
596 | // modify cacheability attributes\r | |
bb02cb80 | 597 | EntryMask |= ARM_SECTION_CACHEABILITY_MASK;\r |
aeb61534 | 598 | // map to strongly ordered\r |
f659880b | 599 | EntryValue |= 0; // TEX[2:0] = 0, C=0, B=0\r |
aeb61534 A |
600 | break;\r |
601 | \r | |
602 | case EFI_MEMORY_WC:\r | |
603 | // modify cacheability attributes\r | |
bb02cb80 | 604 | EntryMask |= ARM_SECTION_CACHEABILITY_MASK;\r |
aeb61534 | 605 | // map to normal non-cachable\r |
f659880b | 606 | EntryValue |= (0x1 << ARM_SECTION_TEX_SHIFT); // TEX [2:0]= 001 = 0x2, B=0, C=0\r |
aeb61534 A |
607 | break;\r |
608 | \r | |
609 | case EFI_MEMORY_WT:\r | |
610 | // modify cacheability attributes\r | |
bb02cb80 | 611 | EntryMask |= ARM_SECTION_CACHEABILITY_MASK;\r |
aeb61534 | 612 | // write through with no-allocate\r |
f659880b | 613 | EntryValue |= ARM_SECTION_C; // TEX [2:0] = 0, C=1, B=0\r |
aeb61534 A |
614 | break;\r |
615 | \r | |
616 | case EFI_MEMORY_WB:\r | |
617 | // modify cacheability attributes\r | |
bb02cb80 | 618 | EntryMask |= ARM_SECTION_CACHEABILITY_MASK;\r |
aeb61534 | 619 | // write back (with allocate)\r |
f659880b | 620 | EntryValue |= (0x1 << ARM_SECTION_TEX_SHIFT) | ARM_SECTION_C | ARM_SECTION_B; // TEX [2:0] = 001, C=1, B=1\r |
aeb61534 A |
621 | break;\r |
622 | \r | |
623 | case EFI_MEMORY_WP:\r | |
624 | case EFI_MEMORY_XP:\r | |
625 | case EFI_MEMORY_RP:\r | |
626 | case EFI_MEMORY_UCE:\r | |
627 | // cannot be implemented UEFI definition unclear for ARM\r | |
628 | // Cause a page fault if these ranges are accessed.\r | |
f659880b | 629 | EntryValue = ARM_DESC_TYPE_FAULT;\r |
225290eb | 630 | DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting section %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));\r |
aeb61534 A |
631 | break;\r |
632 | \r | |
633 | \r | |
634 | default:\r | |
635 | return EFI_UNSUPPORTED;\r | |
aeb61534 A |
636 | }\r |
637 | \r | |
638 | // obtain page table base\r | |
639 | FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTranslationTableBaseAddress ();\r | |
640 | \r | |
641 | // calculate index into first level translation table for start of modification\r | |
642 | FirstLevelIdx = (BaseAddress & ARM_SECTION_BASE_MASK) >> ARM_SECTION_BASE_SHIFT;\r | |
643 | ASSERT (FirstLevelIdx < FIRST_LEVEL_ENTRY_COUNT);\r | |
644 | \r | |
645 | // calculate number of 1MB first level entries this applies to\r | |
646 | NumSections = Length / ARM_PAGE_DESC_ENTRY_MVA_SIZE;\r | |
647 | \r | |
648 | // iterate through each descriptor\r | |
649 | for(i=0; i<NumSections; i++) {\r | |
bb02cb80 | 650 | CurrentDescriptor = FirstLevelTable[FirstLevelIdx + i];\r |
aeb61534 A |
651 | \r |
652 | // has this descriptor already been coverted to pages?\r | |
bb02cb80 | 653 | if ((CurrentDescriptor & ARM_DESC_TYPE_MASK) != ARM_DESC_TYPE_PAGE_TABLE ) {\r |
aeb61534 A |
654 | // forward this 1MB range to page table function instead\r |
655 | Status = UpdatePageEntries ((FirstLevelIdx + i) << ARM_SECTION_BASE_SHIFT, ARM_PAGE_DESC_ENTRY_MVA_SIZE, Attributes, VirtualMask);\r | |
656 | } else {\r | |
657 | // still a section entry\r | |
658 | \r | |
659 | // mask off appropriate fields\r | |
bb02cb80 | 660 | Descriptor = CurrentDescriptor & ~EntryMask;\r |
aeb61534 A |
661 | \r |
662 | // mask in new attributes and/or permissions\r | |
663 | Descriptor |= EntryValue;\r | |
664 | if (VirtualMask != 0) {\r | |
665 | Descriptor &= ~VirtualMask;\r | |
666 | }\r | |
667 | \r | |
bb02cb80 | 668 | if (CurrentDescriptor != Descriptor) {\r |
669 | Mva = (VOID *)(UINTN)(((UINTN)FirstLevelTable) << ARM_SECTION_BASE_SHIFT);\r | |
670 | if ((CurrentDescriptor & ARM_SECTION_C) == ARM_SECTION_C) {\r | |
671 | // The current section mapping is cacheable so Clean/Invalidate the MVA of the section\r | |
672 | // Note assumes switch(Attributes), not ARMv7 possabilities\r | |
673 | WriteBackInvalidateDataCacheRange (Mva, SIZE_1MB);\r | |
674 | }\r | |
675 | \r | |
676 | // Only need to update if we are changing the descriptor \r | |
677 | FirstLevelTable[FirstLevelIdx + i] = Descriptor;\r | |
678 | ArmUpdateTranslationTableEntry ((VOID *)&FirstLevelTable[FirstLevelIdx + i], Mva);\r | |
679 | }\r | |
aeb61534 A |
680 | \r |
681 | Status = EFI_SUCCESS;\r | |
682 | }\r | |
683 | }\r | |
684 | \r | |
685 | return Status;\r | |
686 | }\r | |
687 | \r | |
688 | EFI_STATUS \r | |
689 | ConvertSectionToPages (\r | |
690 | IN EFI_PHYSICAL_ADDRESS BaseAddress\r | |
691 | )\r | |
692 | {\r | |
693 | EFI_STATUS Status;\r | |
694 | EFI_PHYSICAL_ADDRESS PageTableAddr;\r | |
695 | UINT32 FirstLevelIdx;\r | |
696 | UINT32 SectionDescriptor;\r | |
697 | UINT32 PageTableDescriptor;\r | |
698 | UINT32 PageDescriptor;\r | |
699 | UINT32 i;\r | |
700 | \r | |
701 | volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;\r | |
702 | volatile ARM_PAGE_TABLE_ENTRY *PageTable;\r | |
703 | \r | |
225290eb | 704 | DEBUG ((EFI_D_PAGE, "Converting section at 0x%x to pages\n", (UINTN)BaseAddress));\r |
aeb61534 A |
705 | \r |
706 | // obtain page table base\r | |
707 | FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTranslationTableBaseAddress ();\r | |
708 | \r | |
709 | // calculate index into first level translation table for start of modification\r | |
710 | FirstLevelIdx = (BaseAddress & ARM_SECTION_BASE_MASK) >> ARM_SECTION_BASE_SHIFT;\r | |
f659880b | 711 | ASSERT (FirstLevelIdx < FIRST_LEVEL_ENTRY_COUNT);\r |
aeb61534 A |
712 | \r |
713 | // get section attributes and convert to page attributes\r | |
714 | SectionDescriptor = FirstLevelTable[FirstLevelIdx];\r | |
715 | PageDescriptor = ARM_PAGE_TYPE_SMALL;\r | |
716 | PageDescriptor |= ((SectionDescriptor & ARM_SECTION_TEX_MASK) >> ARM_SECTION_TEX_SHIFT) << ARM_SMALL_PAGE_TEX_SHIFT;\r | |
717 | if ((SectionDescriptor & ARM_SECTION_B) != 0) {\r | |
718 | PageDescriptor |= ARM_PAGE_B;\r | |
719 | }\r | |
720 | if ((SectionDescriptor & ARM_SECTION_C) != 0) {\r | |
721 | PageDescriptor |= ARM_PAGE_C;\r | |
722 | }\r | |
723 | PageDescriptor |= ((SectionDescriptor & ARM_SECTION_AP10_MASK) >> ARM_SECTION_AP10_SHIFT) << ARM_PAGE_AP10_SHIFT;\r | |
724 | if ((SectionDescriptor & ARM_SECTION_AP2) != 0) {\r | |
725 | PageDescriptor |= ARM_PAGE_AP2;\r | |
726 | }\r | |
727 | if ((SectionDescriptor & ARM_SECTION_XN) != 0) {\r | |
728 | PageDescriptor |= ARM_PAGE_TYPE_SMALL_XN;\r | |
729 | }\r | |
730 | if ((SectionDescriptor & ARM_SECTION_nG) != 0) {\r | |
731 | PageDescriptor |= ARM_PAGE_nG;\r | |
732 | }\r | |
733 | if ((SectionDescriptor & ARM_SECTION_S) != 0) {\r | |
734 | PageDescriptor |= ARM_PAGE_S;\r | |
735 | }\r | |
736 | \r | |
737 | // allocate a page table for the 4KB entries (we use up a full page even though we only need 1KB)\r | |
738 | Status = gBS->AllocatePages (AllocateAnyPages, EfiBootServicesData, 1, &PageTableAddr);\r | |
739 | if (EFI_ERROR(Status)) {\r | |
740 | return Status;\r | |
741 | }\r | |
742 | \r | |
743 | PageTable = (volatile ARM_PAGE_TABLE_ENTRY *)(UINTN)PageTableAddr;\r | |
744 | \r | |
745 | // write the page table entries out\r | |
bb02cb80 | 746 | for (i=0; i<(ARM_PAGE_DESC_ENTRY_MVA_SIZE/SIZE_4KB); i++) {\r |
aeb61534 A |
747 | PageTable[i] = ((BaseAddress + (i << 12)) & ARM_SMALL_PAGE_BASE_MASK) | PageDescriptor;\r |
748 | }\r | |
749 | \r | |
750 | // flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r | |
bb02cb80 | 751 | WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)PageTableAddr, SIZE_4KB);\r |
aeb61534 A |
752 | \r |
753 | // formulate page table entry, Domain=0, NS=0\r | |
754 | PageTableDescriptor = (((UINTN)PageTableAddr) & ARM_PAGE_DESC_BASE_MASK) | ARM_DESC_TYPE_PAGE_TABLE;\r | |
755 | \r | |
756 | // write the page table entry out, repalcing section entry\r | |
757 | FirstLevelTable[FirstLevelIdx] = PageTableDescriptor;\r | |
758 | \r | |
759 | return EFI_SUCCESS;\r | |
760 | }\r | |
761 | \r | |
762 | \r | |
763 | \r | |
764 | EFI_STATUS\r | |
765 | SetMemoryAttributes (\r | |
766 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
767 | IN UINT64 Length,\r | |
768 | IN UINT64 Attributes,\r | |
769 | IN EFI_PHYSICAL_ADDRESS VirtualMask\r | |
770 | )\r | |
771 | {\r | |
772 | EFI_STATUS Status;\r | |
773 | \r | |
774 | if(((BaseAddress & 0xFFFFF) == 0) && ((Length & 0xFFFFF) == 0)) {\r | |
775 | // is the base and length a multiple of 1 MB?\r | |
225290eb | 776 | DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU section 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));\r |
aeb61534 A |
777 | Status = UpdateSectionEntries (BaseAddress, Length, Attributes, VirtualMask);\r |
778 | } else {\r | |
779 | // base and/or length is not a multiple of 1 MB\r | |
225290eb | 780 | DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU page 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes));\r |
aeb61534 A |
781 | Status = UpdatePageEntries (BaseAddress, Length, Attributes, VirtualMask);\r |
782 | }\r | |
783 | \r | |
784 | // flush d-cache so descriptors make it back to uncached memory for subsequent table walks\r | |
785 | // flush and invalidate pages\r | |
786 | ArmCleanInvalidateDataCache ();\r | |
787 | \r | |
788 | ArmInvalidateInstructionCache ();\r | |
789 | \r | |
790 | // invalidate all TLB entries so changes are synced\r | |
791 | ArmInvalidateTlb (); \r | |
792 | \r | |
793 | return Status;\r | |
794 | }\r | |
795 | \r | |
796 | \r | |
797 | /**\r | |
798 | This function modifies the attributes for the memory region specified by BaseAddress and\r | |
799 | Length from their current attributes to the attributes specified by Attributes.\r | |
800 | \r | |
801 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
802 | @param BaseAddress The physical address that is the start address of a memory region.\r | |
803 | @param Length The size in bytes of the memory region.\r | |
804 | @param Attributes The bit mask of attributes to set for the memory region.\r | |
805 | \r | |
806 | @retval EFI_SUCCESS The attributes were set for the memory region.\r | |
807 | @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r | |
808 | BaseAddress and Length cannot be modified.\r | |
809 | @retval EFI_INVALID_PARAMETER Length is zero.\r | |
810 | @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r | |
811 | the memory resource range.\r | |
812 | @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r | |
813 | resource range specified by BaseAddress and Length.\r | |
814 | The bit mask of attributes is not support for the memory resource\r | |
815 | range specified by BaseAddress and Length.\r | |
816 | \r | |
817 | **/\r | |
818 | EFI_STATUS\r | |
819 | EFIAPI\r | |
820 | CpuSetMemoryAttributes (\r | |
821 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
822 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
823 | IN UINT64 Length,\r | |
824 | IN UINT64 Attributes\r | |
825 | )\r | |
826 | {\r | |
225290eb | 827 | DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx)\n", BaseAddress, Length, Attributes));\r |
bb02cb80 | 828 | if ( ((BaseAddress & (SIZE_4KB-1)) != 0) || ((Length & (SIZE_4KB-1)) != 0)){\r |
829 | // minimum granularity is SIZE_4KB (4KB on ARM)\r | |
830 | DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(%lx, %lx, %lx): minimum ganularity is SIZE_4KB\n", BaseAddress, Length, Attributes));\r | |
aeb61534 A |
831 | return EFI_UNSUPPORTED;\r |
832 | }\r | |
833 | \r | |
834 | return SetMemoryAttributes (BaseAddress, Length, Attributes, 0);\r | |
835 | }\r | |
836 | \r | |
837 | \r | |
838 | \r | |
839 | //\r | |
840 | // Add a new protocol to support \r | |
841 | //\r | |
842 | \r | |
843 | EFI_STATUS\r | |
844 | EFIAPI\r | |
845 | CpuConvertPagesToUncachedVirtualAddress (\r | |
846 | IN VIRTUAL_UNCACHED_PAGES_PROTOCOL *This,\r | |
847 | IN EFI_PHYSICAL_ADDRESS Address,\r | |
848 | IN UINTN Length,\r | |
849 | IN EFI_PHYSICAL_ADDRESS VirtualMask,\r | |
850 | OUT UINT64 *Attributes OPTIONAL\r | |
851 | )\r | |
852 | {\r | |
853 | EFI_STATUS Status;\r | |
854 | EFI_GCD_MEMORY_SPACE_DESCRIPTOR GcdDescriptor;\r | |
855 | \r | |
856 | \r | |
857 | if (Attributes != NULL) {\r | |
858 | Status = gDS->GetMemorySpaceDescriptor (Address, &GcdDescriptor);\r | |
859 | if (!EFI_ERROR (Status)) {\r | |
860 | *Attributes = GcdDescriptor.Attributes;\r | |
861 | }\r | |
862 | }\r | |
225290eb | 863 | \r |
aeb61534 A |
864 | //\r |
865 | // Make this address range page fault if accessed. If it is a DMA buffer than this would \r | |
866 | // be the PCI address. Code should always use the CPU address, and we will or in VirtualMask\r | |
867 | // to that address. \r | |
868 | //\r | |
f659880b | 869 | Status = SetMemoryAttributes (Address, Length, EFI_MEMORY_WP, 0);\r |
aeb61534 A |
870 | if (!EFI_ERROR (Status)) {\r |
871 | Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_UC, VirtualMask);\r | |
872 | }\r | |
873 | \r | |
6f72e28d | 874 | DEBUG ((DEBUG_INFO | DEBUG_LOAD, "ConvertPagesToUncachedVirtualAddress()\n Unmapped 0x%08lx Mapped 0x%08lx 0x%x bytes\n", Address, Address | VirtualMask, Length));\r |
875 | \r | |
aeb61534 A |
876 | return Status;\r |
877 | }\r | |
878 | \r | |
879 | \r | |
880 | EFI_STATUS\r | |
881 | EFIAPI\r | |
6f72e28d | 882 | CpuReconvertPages (\r |
aeb61534 A |
883 | IN VIRTUAL_UNCACHED_PAGES_PROTOCOL *This,\r |
884 | IN EFI_PHYSICAL_ADDRESS Address,\r | |
885 | IN UINTN Length,\r | |
886 | IN EFI_PHYSICAL_ADDRESS VirtualMask,\r | |
887 | IN UINT64 Attributes\r | |
888 | )\r | |
889 | {\r | |
890 | EFI_STATUS Status;\r | |
6f72e28d | 891 | \r |
892 | DEBUG ((DEBUG_INFO | DEBUG_LOAD, "CpuReconvertPages(%lx, %x, %lx, %lx)\n", Address, Length, VirtualMask, Attributes));\r | |
893 | \r | |
894 | //\r | |
aeb61534 A |
895 | // Unmap the alaised Address\r |
896 | //\r | |
f659880b | 897 | Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_WP, 0);\r |
aeb61534 A |
898 | if (!EFI_ERROR (Status)) {\r |
899 | //\r | |
900 | // Restore atttributes\r | |
901 | //\r | |
902 | Status = SetMemoryAttributes (Address, Length, Attributes, 0);\r | |
903 | }\r | |
904 | \r | |
905 | return Status;\r | |
906 | }\r | |
907 | \r | |
908 | \r | |
909 | VIRTUAL_UNCACHED_PAGES_PROTOCOL gVirtualUncachedPages = {\r | |
910 | CpuConvertPagesToUncachedVirtualAddress,\r | |
6f72e28d | 911 | CpuReconvertPages\r |
aeb61534 A |
912 | };\r |
913 | \r | |
914 | \r | |
915 | \r | |
916 | \r |