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2ef2b01e A |
1 | /** @file\r |
2 | \r | |
d6ebcab7 | 3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r |
7aec2926 | 4 | Copyright (c) 2011-2015, ARM Ltd. All rights reserved.<BR>\r |
2ef2b01e | 5 | \r |
d6ebcab7 | 6 | This program and the accompanying materials\r |
2ef2b01e A |
7 | are licensed and made available under the terms and conditions of the BSD License\r |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
5dea9bd6 | 16 | #ifndef __ARM_V7_H__\r |
17 | #define __ARM_V7_H__\r | |
2ef2b01e | 18 | \r |
11c20f4e | 19 | #include <Chipset/ArmV7Mmu.h>\r |
25402f5d | 20 | #include <Chipset/ArmArchTimer.h>\r |
11c20f4e | 21 | \r |
111339d2 | 22 | // ARM Interrupt ID in Exception Table\r |
23 | #define ARM_ARCH_EXCEPTION_IRQ EXCEPT_ARM_IRQ\r | |
24 | \r | |
27331bff OM |
25 | // ID_PFR1 - ARM Processor Feature Register 1 definitions\r |
26 | #define ARM_PFR1_SEC (0xFUL << 4)\r | |
27 | #define ARM_PFR1_TIMER (0xFUL << 16)\r | |
28 | #define ARM_PFR1_GIC (0xFUL << 28)\r | |
29 | \r | |
2ef2b01e A |
30 | // Domain Access Control Register\r |
31 | #define DOMAIN_ACCESS_CONTROL_MASK(a) (3UL << (2 * (a)))\r | |
32 | #define DOMAIN_ACCESS_CONTROL_NONE(a) (0UL << (2 * (a)))\r | |
33 | #define DOMAIN_ACCESS_CONTROL_CLIENT(a) (1UL << (2 * (a)))\r | |
34 | #define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))\r | |
35 | #define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a)))\r | |
36 | \r | |
063ad84e | 37 | // CPSR - Coprocessor Status Register definitions\r |
38 | #define CPSR_MODE_USER 0x10\r | |
39 | #define CPSR_MODE_FIQ 0x11\r | |
40 | #define CPSR_MODE_IRQ 0x12\r | |
41 | #define CPSR_MODE_SVC 0x13\r | |
42 | #define CPSR_MODE_ABORT 0x17\r | |
43 | #define CPSR_MODE_HYP 0x1A\r | |
44 | #define CPSR_MODE_UNDEFINED 0x1B\r | |
45 | #define CPSR_MODE_SYSTEM 0x1F\r | |
46 | #define CPSR_MODE_MASK 0x1F\r | |
47 | #define CPSR_ASYNC_ABORT (1 << 8)\r | |
48 | #define CPSR_IRQ (1 << 7)\r | |
49 | #define CPSR_FIQ (1 << 6)\r | |
50 | \r | |
51 | \r | |
11c20f4e | 52 | // CPACR - Coprocessor Access Control Register definitions\r |
1bfda055 | 53 | #define CPACR_CP_DENIED(cp) 0x00\r |
54 | #define CPACR_CP_PRIV(cp) ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)\r | |
55 | #define CPACR_CP_FULL(cp) ((0x3 << ((cp) << 1)) & 0x0FFFFFFF)\r | |
56 | #define CPACR_ASEDIS (1 << 31)\r | |
57 | #define CPACR_D32DIS (1 << 30)\r | |
58 | #define CPACR_CP_FULL_ACCESS 0x0FFFFFFF\r | |
59 | \r | |
11c20f4e | 60 | // NSACR - Non-Secure Access Control Register definitions\r |
1bfda055 | 61 | #define NSACR_CP(cp) ((1 << (cp)) & 0x3FFF)\r |
62 | #define NSACR_NSD32DIS (1 << 14)\r | |
63 | #define NSACR_NSASEDIS (1 << 15)\r | |
64 | #define NSACR_PLE (1 << 16)\r | |
65 | #define NSACR_TL (1 << 17)\r | |
66 | #define NSACR_NS_SMP (1 << 18)\r | |
67 | #define NSACR_RFR (1 << 19)\r | |
68 | \r | |
11c20f4e | 69 | // SCR - Secure Configuration Register definitions\r |
1bfda055 | 70 | #define SCR_NS (1 << 0)\r |
71 | #define SCR_IRQ (1 << 1)\r | |
72 | #define SCR_FIQ (1 << 2)\r | |
73 | #define SCR_EA (1 << 3)\r | |
74 | #define SCR_FW (1 << 4)\r | |
75 | #define SCR_AW (1 << 5)\r | |
76 | \r | |
bd6b9799 | 77 | // MIDR - Main ID Register definitions\r |
7aec2926 | 78 | #define ARM_CPU_TYPE_SHIFT 4\r |
bd6b9799 | 79 | #define ARM_CPU_TYPE_MASK 0xFFF\r |
b7dd4dbd OM |
80 | #define ARM_CPU_TYPE_AEMv8 0xD0F\r |
81 | #define ARM_CPU_TYPE_A53 0xD03\r | |
82 | #define ARM_CPU_TYPE_A57 0xD07\r | |
bd6b9799 | 83 | #define ARM_CPU_TYPE_A15 0xC0F\r |
7aec2926 | 84 | #define ARM_CPU_TYPE_A12 0xC0D\r |
bd6b9799 | 85 | #define ARM_CPU_TYPE_A9 0xC09\r |
7aec2926 | 86 | #define ARM_CPU_TYPE_A7 0xC07\r |
bd6b9799 | 87 | #define ARM_CPU_TYPE_A5 0xC05\r |
1bfda055 | 88 | \r |
b7dd4dbd OM |
89 | #define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )\r |
90 | #define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))\r | |
91 | \r | |
01bd6ea8 | 92 | #define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 5)-1)\r |
93 | \r | |
1bfda055 | 94 | VOID\r |
95 | EFIAPI\r | |
bd6b9799 | 96 | ArmEnableSWPInstruction (\r |
1bfda055 | 97 | VOID\r |
98 | );\r | |
99 | \r | |
3402aac7 | 100 | UINTN\r |
1bfda055 | 101 | EFIAPI\r |
9e2b420e | 102 | ArmReadCbar (\r |
103 | VOID\r | |
104 | );\r | |
1bfda055 | 105 | \r |
0530bfe3 | 106 | UINTN\r |
107 | EFIAPI\r | |
9e2b420e | 108 | ArmReadTpidrurw (\r |
109 | VOID\r | |
110 | );\r | |
0530bfe3 | 111 | \r |
0530bfe3 | 112 | VOID\r |
113 | EFIAPI\r | |
9e2b420e | 114 | ArmWriteTpidrurw (\r |
115 | UINTN Value\r | |
116 | );\r | |
0530bfe3 | 117 | \r |
d6dc67ba OM |
118 | UINT32\r |
119 | EFIAPI\r | |
120 | ArmReadNsacr (\r | |
121 | VOID\r | |
122 | );\r | |
123 | \r | |
124 | VOID\r | |
125 | EFIAPI\r | |
126 | ArmWriteNsacr (\r | |
127 | IN UINT32 Nsacr\r | |
128 | );\r | |
129 | \r | |
5dea9bd6 | 130 | #endif // __ARM_V7_H__\r |