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Commit | Line | Data |
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25402f5d HL |
1 | #------------------------------------------------------------------------------\r |
2 | #\r | |
3 | # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r | |
9401d6f4 | 4 | # Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r |
0efaa42f | 5 | # Copyright (c) 2016, Linaro Limited. All rights reserved.\r |
25402f5d HL |
6 | #\r |
7 | # This program and the accompanying materials\r | |
8 | # are licensed and made available under the terms and conditions of the BSD License\r | |
9 | # which accompanies this distribution. The full text of the license may be found at\r | |
10 | # http://opensource.org/licenses/bsd-license.php\r | |
11 | #\r | |
12 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | #\r | |
15 | #------------------------------------------------------------------------------\r | |
16 | \r | |
17 | #include <Chipset/AArch64.h>\r | |
18 | #include <AsmMacroIoLibV8.h>\r | |
19 | \r | |
25402f5d HL |
20 | .set CTRL_M_BIT, (1 << 0)\r |
21 | .set CTRL_A_BIT, (1 << 1)\r | |
22 | .set CTRL_C_BIT, (1 << 2)\r | |
97f0d01d | 23 | .set CTRL_SA_BIT, (1 << 3)\r |
25402f5d HL |
24 | .set CTRL_I_BIT, (1 << 12)\r |
25 | .set CTRL_V_BIT, (1 << 12)\r | |
26 | .set CPACR_VFP_BITS, (3 << 20)\r | |
27 | \r | |
0efaa42f | 28 | ASM_FUNC(ArmInvalidateDataCacheEntryByMVA)\r |
25402f5d | 29 | dc ivac, x0 // Invalidate single data cache line\r |
25402f5d HL |
30 | ret\r |
31 | \r | |
32 | \r | |
0efaa42f | 33 | ASM_FUNC(ArmCleanDataCacheEntryByMVA)\r |
25402f5d | 34 | dc cvac, x0 // Clean single data cache line\r |
25402f5d HL |
35 | ret\r |
36 | \r | |
37 | \r | |
0efaa42f | 38 | ASM_FUNC(ArmCleanDataCacheEntryToPoUByMVA)\r |
b7de7e3c EC |
39 | dc cvau, x0 // Clean single data cache line to PoU\r |
40 | ret\r | |
41 | \r | |
0efaa42f | 42 | ASM_FUNC(ArmInvalidateInstructionCacheEntryToPoUByMVA)\r |
cf580da1 AB |
43 | ic ivau, x0 // Invalidate single instruction cache line to PoU\r |
44 | ret\r | |
45 | \r | |
b7de7e3c | 46 | \r |
0efaa42f | 47 | ASM_FUNC(ArmCleanInvalidateDataCacheEntryByMVA)\r |
25402f5d | 48 | dc civac, x0 // Clean and invalidate single data cache line\r |
25402f5d HL |
49 | ret\r |
50 | \r | |
51 | \r | |
0efaa42f | 52 | ASM_FUNC(ArmInvalidateDataCacheEntryBySetWay)\r |
25402f5d | 53 | dc isw, x0 // Invalidate this line\r |
25402f5d HL |
54 | ret\r |
55 | \r | |
56 | \r | |
0efaa42f | 57 | ASM_FUNC(ArmCleanInvalidateDataCacheEntryBySetWay)\r |
25402f5d | 58 | dc cisw, x0 // Clean and Invalidate this line\r |
25402f5d HL |
59 | ret\r |
60 | \r | |
61 | \r | |
0efaa42f | 62 | ASM_FUNC(ArmCleanDataCacheEntryBySetWay)\r |
25402f5d | 63 | dc csw, x0 // Clean this line\r |
25402f5d HL |
64 | ret\r |
65 | \r | |
66 | \r | |
0efaa42f | 67 | ASM_FUNC(ArmInvalidateInstructionCache)\r |
25402f5d HL |
68 | ic iallu // Invalidate entire instruction cache\r |
69 | dsb sy\r | |
70 | isb\r | |
71 | ret\r | |
72 | \r | |
73 | \r | |
0efaa42f | 74 | ASM_FUNC(ArmEnableMmu)\r |
25402f5d HL |
75 | EL1_OR_EL2_OR_EL3(x1)\r |
76 | 1: mrs x0, sctlr_el1 // Read System control register EL1\r | |
77 | b 4f\r | |
78 | 2: mrs x0, sctlr_el2 // Read System control register EL2\r | |
79 | b 4f\r | |
80 | 3: mrs x0, sctlr_el3 // Read System control register EL3\r | |
81 | 4: orr x0, x0, #CTRL_M_BIT // Set MMU enable bit\r | |
82 | EL1_OR_EL2_OR_EL3(x1)\r | |
70f89c0b | 83 | 1: tlbi vmalle1\r |
ee95f9e1 | 84 | dsb nsh\r |
25402f5d HL |
85 | isb\r |
86 | msr sctlr_el1, x0 // Write back\r | |
87 | b 4f\r | |
88 | 2: tlbi alle2\r | |
ee95f9e1 | 89 | dsb nsh\r |
25402f5d HL |
90 | isb\r |
91 | msr sctlr_el2, x0 // Write back\r | |
92 | b 4f\r | |
93 | 3: tlbi alle3\r | |
ee95f9e1 | 94 | dsb nsh\r |
25402f5d HL |
95 | isb\r |
96 | msr sctlr_el3, x0 // Write back\r | |
ee95f9e1 | 97 | 4: isb\r |
25402f5d HL |
98 | ret\r |
99 | \r | |
100 | \r | |
0efaa42f | 101 | ASM_FUNC(ArmDisableMmu)\r |
25402f5d HL |
102 | EL1_OR_EL2_OR_EL3(x1)\r |
103 | 1: mrs x0, sctlr_el1 // Read System Control Register EL1\r | |
104 | b 4f\r | |
105 | 2: mrs x0, sctlr_el2 // Read System Control Register EL2\r | |
106 | b 4f\r | |
107 | 3: mrs x0, sctlr_el3 // Read System Control Register EL3\r | |
73ca5009 | 108 | 4: and x0, x0, #~CTRL_M_BIT // Clear MMU enable bit\r |
25402f5d HL |
109 | EL1_OR_EL2_OR_EL3(x1)\r |
110 | 1: msr sctlr_el1, x0 // Write back\r | |
70f89c0b | 111 | tlbi vmalle1\r |
25402f5d HL |
112 | b 4f\r |
113 | 2: msr sctlr_el2, x0 // Write back\r | |
114 | tlbi alle2\r | |
115 | b 4f\r | |
116 | 3: msr sctlr_el3, x0 // Write back\r | |
117 | tlbi alle3\r | |
118 | 4: dsb sy\r | |
119 | isb\r | |
120 | ret\r | |
121 | \r | |
122 | \r | |
0efaa42f | 123 | ASM_FUNC(ArmDisableCachesAndMmu)\r |
25402f5d HL |
124 | EL1_OR_EL2_OR_EL3(x1)\r |
125 | 1: mrs x0, sctlr_el1 // Get control register EL1\r | |
126 | b 4f\r | |
127 | 2: mrs x0, sctlr_el2 // Get control register EL2\r | |
128 | b 4f\r | |
129 | 3: mrs x0, sctlr_el3 // Get control register EL3\r | |
73ca5009 BJ |
130 | 4: mov x1, #~(CTRL_M_BIT | CTRL_C_BIT | CTRL_I_BIT) // Disable MMU, D & I caches\r |
131 | and x0, x0, x1\r | |
25402f5d HL |
132 | EL1_OR_EL2_OR_EL3(x1)\r |
133 | 1: msr sctlr_el1, x0 // Write back control register\r | |
134 | b 4f\r | |
135 | 2: msr sctlr_el2, x0 // Write back control register\r | |
136 | b 4f\r | |
137 | 3: msr sctlr_el3, x0 // Write back control register\r | |
138 | 4: dsb sy\r | |
139 | isb\r | |
140 | ret\r | |
141 | \r | |
142 | \r | |
0efaa42f | 143 | ASM_FUNC(ArmMmuEnabled)\r |
25402f5d HL |
144 | EL1_OR_EL2_OR_EL3(x1)\r |
145 | 1: mrs x0, sctlr_el1 // Get control register EL1\r | |
146 | b 4f\r | |
147 | 2: mrs x0, sctlr_el2 // Get control register EL2\r | |
148 | b 4f\r | |
149 | 3: mrs x0, sctlr_el3 // Get control register EL3\r | |
150 | 4: and x0, x0, #CTRL_M_BIT\r | |
151 | ret\r | |
152 | \r | |
153 | \r | |
0efaa42f | 154 | ASM_FUNC(ArmEnableDataCache)\r |
25402f5d HL |
155 | EL1_OR_EL2_OR_EL3(x1)\r |
156 | 1: mrs x0, sctlr_el1 // Get control register EL1\r | |
157 | b 4f\r | |
158 | 2: mrs x0, sctlr_el2 // Get control register EL2\r | |
159 | b 4f\r | |
160 | 3: mrs x0, sctlr_el3 // Get control register EL3\r | |
161 | 4: orr x0, x0, #CTRL_C_BIT // Set C bit\r | |
162 | EL1_OR_EL2_OR_EL3(x1)\r | |
163 | 1: msr sctlr_el1, x0 // Write back control register\r | |
164 | b 4f\r | |
165 | 2: msr sctlr_el2, x0 // Write back control register\r | |
166 | b 4f\r | |
167 | 3: msr sctlr_el3, x0 // Write back control register\r | |
168 | 4: dsb sy\r | |
169 | isb\r | |
170 | ret\r | |
171 | \r | |
172 | \r | |
0efaa42f | 173 | ASM_FUNC(ArmDisableDataCache)\r |
25402f5d HL |
174 | EL1_OR_EL2_OR_EL3(x1)\r |
175 | 1: mrs x0, sctlr_el1 // Get control register EL1\r | |
176 | b 4f\r | |
177 | 2: mrs x0, sctlr_el2 // Get control register EL2\r | |
178 | b 4f\r | |
179 | 3: mrs x0, sctlr_el3 // Get control register EL3\r | |
73ca5009 | 180 | 4: and x0, x0, #~CTRL_C_BIT // Clear C bit\r |
25402f5d HL |
181 | EL1_OR_EL2_OR_EL3(x1)\r |
182 | 1: msr sctlr_el1, x0 // Write back control register\r | |
183 | b 4f\r | |
184 | 2: msr sctlr_el2, x0 // Write back control register\r | |
185 | b 4f\r | |
186 | 3: msr sctlr_el3, x0 // Write back control register\r | |
187 | 4: dsb sy\r | |
188 | isb\r | |
189 | ret\r | |
190 | \r | |
191 | \r | |
0efaa42f | 192 | ASM_FUNC(ArmEnableInstructionCache)\r |
25402f5d HL |
193 | EL1_OR_EL2_OR_EL3(x1)\r |
194 | 1: mrs x0, sctlr_el1 // Get control register EL1\r | |
195 | b 4f\r | |
196 | 2: mrs x0, sctlr_el2 // Get control register EL2\r | |
197 | b 4f\r | |
198 | 3: mrs x0, sctlr_el3 // Get control register EL3\r | |
199 | 4: orr x0, x0, #CTRL_I_BIT // Set I bit\r | |
200 | EL1_OR_EL2_OR_EL3(x1)\r | |
201 | 1: msr sctlr_el1, x0 // Write back control register\r | |
202 | b 4f\r | |
203 | 2: msr sctlr_el2, x0 // Write back control register\r | |
204 | b 4f\r | |
205 | 3: msr sctlr_el3, x0 // Write back control register\r | |
206 | 4: dsb sy\r | |
207 | isb\r | |
208 | ret\r | |
209 | \r | |
210 | \r | |
0efaa42f | 211 | ASM_FUNC(ArmDisableInstructionCache)\r |
25402f5d HL |
212 | EL1_OR_EL2_OR_EL3(x1)\r |
213 | 1: mrs x0, sctlr_el1 // Get control register EL1\r | |
214 | b 4f\r | |
215 | 2: mrs x0, sctlr_el2 // Get control register EL2\r | |
216 | b 4f\r | |
217 | 3: mrs x0, sctlr_el3 // Get control register EL3\r | |
73ca5009 | 218 | 4: and x0, x0, #~CTRL_I_BIT // Clear I bit\r |
25402f5d HL |
219 | EL1_OR_EL2_OR_EL3(x1)\r |
220 | 1: msr sctlr_el1, x0 // Write back control register\r | |
221 | b 4f\r | |
222 | 2: msr sctlr_el2, x0 // Write back control register\r | |
223 | b 4f\r | |
224 | 3: msr sctlr_el3, x0 // Write back control register\r | |
225 | 4: dsb sy\r | |
226 | isb\r | |
227 | ret\r | |
228 | \r | |
229 | \r | |
0efaa42f | 230 | ASM_FUNC(ArmEnableAlignmentCheck)\r |
25402f5d HL |
231 | EL1_OR_EL2(x1)\r |
232 | 1: mrs x0, sctlr_el1 // Get control register EL1\r | |
233 | b 3f\r | |
234 | 2: mrs x0, sctlr_el2 // Get control register EL2\r | |
235 | 3: orr x0, x0, #CTRL_A_BIT // Set A (alignment check) bit\r | |
236 | EL1_OR_EL2(x1)\r | |
237 | 1: msr sctlr_el1, x0 // Write back control register\r | |
238 | b 3f\r | |
239 | 2: msr sctlr_el2, x0 // Write back control register\r | |
240 | 3: dsb sy\r | |
241 | isb\r | |
242 | ret\r | |
243 | \r | |
244 | \r | |
0efaa42f | 245 | ASM_FUNC(ArmDisableAlignmentCheck)\r |
25402f5d HL |
246 | EL1_OR_EL2_OR_EL3(x1)\r |
247 | 1: mrs x0, sctlr_el1 // Get control register EL1\r | |
248 | b 4f\r | |
249 | 2: mrs x0, sctlr_el2 // Get control register EL2\r | |
250 | b 4f\r | |
251 | 3: mrs x0, sctlr_el3 // Get control register EL3\r | |
73ca5009 | 252 | 4: and x0, x0, #~CTRL_A_BIT // Clear A (alignment check) bit\r |
25402f5d HL |
253 | EL1_OR_EL2_OR_EL3(x1)\r |
254 | 1: msr sctlr_el1, x0 // Write back control register\r | |
255 | b 4f\r | |
256 | 2: msr sctlr_el2, x0 // Write back control register\r | |
257 | b 4f\r | |
258 | 3: msr sctlr_el3, x0 // Write back control register\r | |
259 | 4: dsb sy\r | |
260 | isb\r | |
261 | ret\r | |
262 | \r | |
97f0d01d AB |
263 | ASM_FUNC(ArmEnableStackAlignmentCheck)\r |
264 | EL1_OR_EL2(x1)\r | |
265 | 1: mrs x0, sctlr_el1 // Get control register EL1\r | |
266 | b 3f\r | |
267 | 2: mrs x0, sctlr_el2 // Get control register EL2\r | |
268 | 3: orr x0, x0, #CTRL_SA_BIT // Set SA (stack alignment check) bit\r | |
269 | EL1_OR_EL2(x1)\r | |
270 | 1: msr sctlr_el1, x0 // Write back control register\r | |
271 | b 3f\r | |
272 | 2: msr sctlr_el2, x0 // Write back control register\r | |
273 | 3: dsb sy\r | |
274 | isb\r | |
275 | ret\r | |
276 | \r | |
277 | \r | |
278 | ASM_FUNC(ArmDisableStackAlignmentCheck)\r | |
279 | EL1_OR_EL2_OR_EL3(x1)\r | |
280 | 1: mrs x0, sctlr_el1 // Get control register EL1\r | |
281 | b 4f\r | |
282 | 2: mrs x0, sctlr_el2 // Get control register EL2\r | |
283 | b 4f\r | |
284 | 3: mrs x0, sctlr_el3 // Get control register EL3\r | |
285 | 4: bic x0, x0, #CTRL_SA_BIT // Clear SA (stack alignment check) bit\r | |
286 | EL1_OR_EL2_OR_EL3(x1)\r | |
287 | 1: msr sctlr_el1, x0 // Write back control register\r | |
288 | b 4f\r | |
289 | 2: msr sctlr_el2, x0 // Write back control register\r | |
290 | b 4f\r | |
291 | 3: msr sctlr_el3, x0 // Write back control register\r | |
292 | 4: dsb sy\r | |
293 | isb\r | |
294 | ret\r | |
295 | \r | |
25402f5d HL |
296 | \r |
297 | // Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now\r | |
0efaa42f | 298 | ASM_FUNC(ArmEnableBranchPrediction)\r |
25402f5d HL |
299 | ret\r |
300 | \r | |
301 | \r | |
302 | // Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now.\r | |
0efaa42f | 303 | ASM_FUNC(ArmDisableBranchPrediction)\r |
25402f5d HL |
304 | ret\r |
305 | \r | |
306 | \r | |
0efaa42f | 307 | ASM_FUNC(AArch64AllDataCachesOperation)\r |
25402f5d | 308 | // We can use regs 0-7 and 9-15 without having to save/restore.\r |
fb7ea611 | 309 | // Save our link register on the stack. - The stack must always be quad-word aligned\r |
de2a7824 AB |
310 | stp x29, x30, [sp, #-16]!\r |
311 | mov x29, sp\r | |
25402f5d HL |
312 | mov x1, x0 // Save Function call in x1\r |
313 | mrs x6, clidr_el1 // Read EL1 CLIDR\r | |
314 | and x3, x6, #0x7000000 // Mask out all but Level of Coherency (LoC)\r | |
433a49a0 OM |
315 | lsr x3, x3, #23 // Left align cache level value - the level is shifted by 1 to the\r |
316 | // right to ease the access to CSSELR and the Set/Way operation.\r | |
25402f5d HL |
317 | cbz x3, L_Finished // No need to clean if LoC is 0\r |
318 | mov x10, #0 // Start clean at cache level 0\r | |
25402f5d HL |
319 | \r |
320 | Loop1:\r | |
321 | add x2, x10, x10, lsr #1 // Work out 3x cachelevel for cache info\r | |
322 | lsr x12, x6, x2 // bottom 3 bits are the Cache type for this level\r | |
323 | and x12, x12, #7 // get those 3 bits alone\r | |
324 | cmp x12, #2 // what cache at this level?\r | |
325 | b.lt L_Skip // no cache or only instruction cache at this level\r | |
326 | msr csselr_el1, x10 // write the Cache Size selection register with current level (CSSELR)\r | |
327 | isb // isb to sync the change to the CacheSizeID reg\r | |
328 | mrs x12, ccsidr_el1 // reads current Cache Size ID register (CCSIDR)\r | |
329 | and x2, x12, #0x7 // extract the line length field\r | |
330 | add x2, x2, #4 // add 4 for the line length offset (log2 16 bytes)\r | |
331 | mov x4, #0x400\r | |
332 | sub x4, x4, #1\r | |
333 | and x4, x4, x12, lsr #3 // x4 is the max number on the way size (right aligned)\r | |
334 | clz w5, w4 // w5 is the bit position of the way size increment\r | |
335 | mov x7, #0x00008000\r | |
336 | sub x7, x7, #1\r | |
337 | and x7, x7, x12, lsr #13 // x7 is the max number of the index size (right aligned)\r | |
338 | \r | |
339 | Loop2:\r | |
340 | mov x9, x4 // x9 working copy of the max way size (right aligned)\r | |
341 | \r | |
342 | Loop3:\r | |
343 | lsl x11, x9, x5\r | |
344 | orr x0, x10, x11 // factor in the way number and cache number\r | |
345 | lsl x11, x7, x2\r | |
346 | orr x0, x0, x11 // factor in the index number\r | |
347 | \r | |
348 | blr x1 // Goto requested cache operation\r | |
349 | \r | |
350 | subs x9, x9, #1 // decrement the way number\r | |
351 | b.ge Loop3\r | |
352 | subs x7, x7, #1 // decrement the index\r | |
353 | b.ge Loop2\r | |
354 | L_Skip:\r | |
355 | add x10, x10, #2 // increment the cache number\r | |
356 | cmp x3, x10\r | |
357 | b.gt Loop1\r | |
358 | \r | |
359 | L_Finished:\r | |
360 | dsb sy\r | |
361 | isb\r | |
de2a7824 | 362 | ldp x29, x30, [sp], #0x10\r |
25402f5d HL |
363 | ret\r |
364 | \r | |
365 | \r | |
0efaa42f | 366 | ASM_FUNC(ArmDataMemoryBarrier)\r |
25402f5d HL |
367 | dmb sy\r |
368 | ret\r | |
369 | \r | |
370 | \r | |
0efaa42f | 371 | ASM_FUNC(ArmDataSynchronizationBarrier)\r |
25402f5d HL |
372 | dsb sy\r |
373 | ret\r | |
374 | \r | |
375 | \r | |
0efaa42f | 376 | ASM_FUNC(ArmInstructionSynchronizationBarrier)\r |
25402f5d HL |
377 | isb\r |
378 | ret\r | |
379 | \r | |
380 | \r | |
0efaa42f | 381 | ASM_FUNC(ArmWriteVBar)\r |
25402f5d HL |
382 | EL1_OR_EL2_OR_EL3(x1)\r |
383 | 1: msr vbar_el1, x0 // Set the Address of the EL1 Vector Table in the VBAR register\r | |
384 | b 4f\r | |
385 | 2: msr vbar_el2, x0 // Set the Address of the EL2 Vector Table in the VBAR register\r | |
386 | b 4f\r | |
387 | 3: msr vbar_el3, x0 // Set the Address of the EL3 Vector Table in the VBAR register\r | |
388 | 4: isb\r | |
389 | ret\r | |
390 | \r | |
0efaa42f | 391 | ASM_FUNC(ArmReadVBar)\r |
f0247796 OM |
392 | EL1_OR_EL2_OR_EL3(x1)\r |
393 | 1: mrs x0, vbar_el1 // Set the Address of the EL1 Vector Table in the VBAR register\r | |
394 | ret\r | |
395 | 2: mrs x0, vbar_el2 // Set the Address of the EL2 Vector Table in the VBAR register\r | |
396 | ret\r | |
397 | 3: mrs x0, vbar_el3 // Set the Address of the EL3 Vector Table in the VBAR register\r | |
398 | ret\r | |
399 | \r | |
400 | \r | |
0efaa42f | 401 | ASM_FUNC(ArmEnableVFP)\r |
25402f5d HL |
402 | // Check whether floating-point is implemented in the processor.\r |
403 | mov x1, x30 // Save LR\r | |
404 | bl ArmReadIdPfr0 // Read EL1 Processor Feature Register (PFR0)\r | |
405 | mov x30, x1 // Restore LR\r | |
406 | ands x0, x0, #AARCH64_PFR0_FP// Extract bits indicating VFP implementation\r | |
407 | cmp x0, #0 // VFP is implemented if '0'.\r | |
408 | b.ne 4f // Exit if VFP not implemented.\r | |
409 | // FVP is implemented.\r | |
410 | // Make sure VFP exceptions are not trapped (to any exception level).\r | |
411 | mrs x0, cpacr_el1 // Read EL1 Coprocessor Access Control Register (CPACR)\r | |
412 | orr x0, x0, #CPACR_VFP_BITS // Disable FVP traps to EL1\r | |
413 | msr cpacr_el1, x0 // Write back EL1 Coprocessor Access Control Register (CPACR)\r | |
414 | mov x1, #AARCH64_CPTR_TFP // TFP Bit for trapping VFP Exceptions\r | |
415 | EL1_OR_EL2_OR_EL3(x2)\r | |
416 | 1:ret // Not configurable in EL1\r | |
417 | 2:mrs x0, cptr_el2 // Disable VFP traps to EL2\r | |
418 | bic x0, x0, x1\r | |
419 | msr cptr_el2, x0\r | |
420 | ret\r | |
421 | 3:mrs x0, cptr_el3 // Disable VFP traps to EL3\r | |
422 | bic x0, x0, x1\r | |
423 | msr cptr_el3, x0\r | |
424 | 4:ret\r | |
425 | \r | |
426 | \r | |
0efaa42f | 427 | ASM_FUNC(ArmCallWFI)\r |
25402f5d HL |
428 | wfi\r |
429 | ret\r | |
430 | \r | |
431 | \r | |
0efaa42f | 432 | ASM_FUNC(ArmReadMpidr)\r |
25402f5d HL |
433 | mrs x0, mpidr_el1 // read EL1 MPIDR\r |
434 | ret\r | |
435 | \r | |
436 | \r | |
437 | // Keep old function names for C compatibilty for now. Change later?\r | |
0efaa42f | 438 | ASM_FUNC(ArmReadTpidrurw)\r |
25402f5d HL |
439 | mrs x0, tpidr_el0 // read tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)\r |
440 | ret\r | |
441 | \r | |
442 | \r | |
443 | // Keep old function names for C compatibilty for now. Change later?\r | |
0efaa42f | 444 | ASM_FUNC(ArmWriteTpidrurw)\r |
25402f5d HL |
445 | msr tpidr_el0, x0 // write tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)\r |
446 | ret\r | |
447 | \r | |
448 | \r | |
449 | // Arch timers are mandatory on AArch64\r | |
0efaa42f | 450 | ASM_FUNC(ArmIsArchTimerImplemented)\r |
25402f5d HL |
451 | mov x0, #1\r |
452 | ret\r | |
453 | \r | |
454 | \r | |
0efaa42f | 455 | ASM_FUNC(ArmReadIdPfr0)\r |
25402f5d HL |
456 | mrs x0, id_aa64pfr0_el1 // Read ID_AA64PFR0 Register\r |
457 | ret\r | |
458 | \r | |
459 | \r | |
460 | // Q: id_aa64pfr1_el1 not defined yet. What does this funtion want to access?\r | |
461 | // A: used to setup arch timer. Check if we have security extensions, permissions to set stuff.\r | |
462 | // See: ArmPkg/Library/ArmArchTimerLib/AArch64/ArmArchTimerLib.c\r | |
463 | // Not defined yet, but stick in here for now, should read all zeros.\r | |
0efaa42f | 464 | ASM_FUNC(ArmReadIdPfr1)\r |
25402f5d HL |
465 | mrs x0, id_aa64pfr1_el1 // Read ID_PFR1 Register\r |
466 | ret\r | |
467 | \r | |
468 | // VOID ArmWriteHcr(UINTN Hcr)\r | |
0efaa42f | 469 | ASM_FUNC(ArmWriteHcr)\r |
25402f5d HL |
470 | msr hcr_el2, x0 // Write the passed HCR value\r |
471 | ret\r | |
472 | \r | |
d2bb61a2 | 473 | // UINTN ArmReadHcr(VOID)\r |
0efaa42f | 474 | ASM_FUNC(ArmReadHcr)\r |
d2bb61a2 EC |
475 | mrs x0, hcr_el2\r |
476 | ret\r | |
477 | \r | |
25402f5d | 478 | // UINTN ArmReadCurrentEL(VOID)\r |
0efaa42f | 479 | ASM_FUNC(ArmReadCurrentEL)\r |
25402f5d HL |
480 | mrs x0, CurrentEL\r |
481 | ret\r | |
482 | \r | |
23d6348f SM |
483 | // UINT32 ArmReadCntHctl(VOID)\r |
484 | ASM_FUNC(ArmReadCntHctl)\r | |
485 | mrs x0, cnthctl_el2\r | |
486 | ret\r | |
487 | \r | |
488 | // VOID ArmWriteCntHctl(UINT32 CntHctl)\r | |
489 | ASM_FUNC(ArmWriteCntHctl)\r | |
490 | msr cnthctl_el2, x0\r | |
491 | ret\r | |
492 | \r | |
25402f5d | 493 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r |