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Commit | Line | Data |
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25402f5d HL |
1 | #------------------------------------------------------------------------------\r |
2 | #\r | |
3 | # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r | |
2f16993c | 4 | # Copyright (c) 2011 - 2017, ARM Limited. All rights reserved.\r |
0efaa42f | 5 | # Copyright (c) 2016, Linaro Limited. All rights reserved.\r |
25402f5d | 6 | #\r |
4059386c | 7 | # SPDX-License-Identifier: BSD-2-Clause-Patent\r |
25402f5d HL |
8 | #\r |
9 | #------------------------------------------------------------------------------\r | |
10 | \r | |
11 | #include <Chipset/AArch64.h>\r | |
12 | #include <AsmMacroIoLibV8.h>\r | |
13 | \r | |
25402f5d HL |
14 | .set CTRL_M_BIT, (1 << 0)\r |
15 | .set CTRL_A_BIT, (1 << 1)\r | |
16 | .set CTRL_C_BIT, (1 << 2)\r | |
97f0d01d | 17 | .set CTRL_SA_BIT, (1 << 3)\r |
25402f5d HL |
18 | .set CTRL_I_BIT, (1 << 12)\r |
19 | .set CTRL_V_BIT, (1 << 12)\r | |
20 | .set CPACR_VFP_BITS, (3 << 20)\r | |
21 | \r | |
0efaa42f | 22 | ASM_FUNC(ArmInvalidateDataCacheEntryByMVA)\r |
25402f5d | 23 | dc ivac, x0 // Invalidate single data cache line\r |
25402f5d HL |
24 | ret\r |
25 | \r | |
26 | \r | |
0efaa42f | 27 | ASM_FUNC(ArmCleanDataCacheEntryByMVA)\r |
25402f5d | 28 | dc cvac, x0 // Clean single data cache line\r |
25402f5d HL |
29 | ret\r |
30 | \r | |
31 | \r | |
0efaa42f | 32 | ASM_FUNC(ArmCleanDataCacheEntryToPoUByMVA)\r |
b7de7e3c EC |
33 | dc cvau, x0 // Clean single data cache line to PoU\r |
34 | ret\r | |
35 | \r | |
0efaa42f | 36 | ASM_FUNC(ArmInvalidateInstructionCacheEntryToPoUByMVA)\r |
cf580da1 AB |
37 | ic ivau, x0 // Invalidate single instruction cache line to PoU\r |
38 | ret\r | |
39 | \r | |
b7de7e3c | 40 | \r |
0efaa42f | 41 | ASM_FUNC(ArmCleanInvalidateDataCacheEntryByMVA)\r |
25402f5d | 42 | dc civac, x0 // Clean and invalidate single data cache line\r |
25402f5d HL |
43 | ret\r |
44 | \r | |
45 | \r | |
0efaa42f | 46 | ASM_FUNC(ArmInvalidateDataCacheEntryBySetWay)\r |
25402f5d | 47 | dc isw, x0 // Invalidate this line\r |
25402f5d HL |
48 | ret\r |
49 | \r | |
50 | \r | |
0efaa42f | 51 | ASM_FUNC(ArmCleanInvalidateDataCacheEntryBySetWay)\r |
25402f5d | 52 | dc cisw, x0 // Clean and Invalidate this line\r |
25402f5d HL |
53 | ret\r |
54 | \r | |
55 | \r | |
0efaa42f | 56 | ASM_FUNC(ArmCleanDataCacheEntryBySetWay)\r |
25402f5d | 57 | dc csw, x0 // Clean this line\r |
25402f5d HL |
58 | ret\r |
59 | \r | |
60 | \r | |
0efaa42f | 61 | ASM_FUNC(ArmInvalidateInstructionCache)\r |
25402f5d HL |
62 | ic iallu // Invalidate entire instruction cache\r |
63 | dsb sy\r | |
64 | isb\r | |
65 | ret\r | |
66 | \r | |
67 | \r | |
0efaa42f | 68 | ASM_FUNC(ArmEnableMmu)\r |
25402f5d HL |
69 | EL1_OR_EL2_OR_EL3(x1)\r |
70 | 1: mrs x0, sctlr_el1 // Read System control register EL1\r | |
71 | b 4f\r | |
72 | 2: mrs x0, sctlr_el2 // Read System control register EL2\r | |
73 | b 4f\r | |
74 | 3: mrs x0, sctlr_el3 // Read System control register EL3\r | |
75 | 4: orr x0, x0, #CTRL_M_BIT // Set MMU enable bit\r | |
76 | EL1_OR_EL2_OR_EL3(x1)\r | |
70f89c0b | 77 | 1: tlbi vmalle1\r |
ee95f9e1 | 78 | dsb nsh\r |
25402f5d HL |
79 | isb\r |
80 | msr sctlr_el1, x0 // Write back\r | |
81 | b 4f\r | |
82 | 2: tlbi alle2\r | |
ee95f9e1 | 83 | dsb nsh\r |
25402f5d HL |
84 | isb\r |
85 | msr sctlr_el2, x0 // Write back\r | |
86 | b 4f\r | |
87 | 3: tlbi alle3\r | |
ee95f9e1 | 88 | dsb nsh\r |
25402f5d HL |
89 | isb\r |
90 | msr sctlr_el3, x0 // Write back\r | |
ee95f9e1 | 91 | 4: isb\r |
25402f5d HL |
92 | ret\r |
93 | \r | |
94 | \r | |
0efaa42f | 95 | ASM_FUNC(ArmDisableMmu)\r |
25402f5d HL |
96 | EL1_OR_EL2_OR_EL3(x1)\r |
97 | 1: mrs x0, sctlr_el1 // Read System Control Register EL1\r | |
98 | b 4f\r | |
99 | 2: mrs x0, sctlr_el2 // Read System Control Register EL2\r | |
100 | b 4f\r | |
101 | 3: mrs x0, sctlr_el3 // Read System Control Register EL3\r | |
73ca5009 | 102 | 4: and x0, x0, #~CTRL_M_BIT // Clear MMU enable bit\r |
25402f5d HL |
103 | EL1_OR_EL2_OR_EL3(x1)\r |
104 | 1: msr sctlr_el1, x0 // Write back\r | |
70f89c0b | 105 | tlbi vmalle1\r |
25402f5d HL |
106 | b 4f\r |
107 | 2: msr sctlr_el2, x0 // Write back\r | |
108 | tlbi alle2\r | |
109 | b 4f\r | |
110 | 3: msr sctlr_el3, x0 // Write back\r | |
111 | tlbi alle3\r | |
112 | 4: dsb sy\r | |
113 | isb\r | |
114 | ret\r | |
115 | \r | |
116 | \r | |
0efaa42f | 117 | ASM_FUNC(ArmDisableCachesAndMmu)\r |
25402f5d HL |
118 | EL1_OR_EL2_OR_EL3(x1)\r |
119 | 1: mrs x0, sctlr_el1 // Get control register EL1\r | |
120 | b 4f\r | |
121 | 2: mrs x0, sctlr_el2 // Get control register EL2\r | |
122 | b 4f\r | |
123 | 3: mrs x0, sctlr_el3 // Get control register EL3\r | |
73ca5009 BJ |
124 | 4: mov x1, #~(CTRL_M_BIT | CTRL_C_BIT | CTRL_I_BIT) // Disable MMU, D & I caches\r |
125 | and x0, x0, x1\r | |
25402f5d HL |
126 | EL1_OR_EL2_OR_EL3(x1)\r |
127 | 1: msr sctlr_el1, x0 // Write back control register\r | |
128 | b 4f\r | |
129 | 2: msr sctlr_el2, x0 // Write back control register\r | |
130 | b 4f\r | |
131 | 3: msr sctlr_el3, x0 // Write back control register\r | |
132 | 4: dsb sy\r | |
133 | isb\r | |
134 | ret\r | |
135 | \r | |
136 | \r | |
0efaa42f | 137 | ASM_FUNC(ArmMmuEnabled)\r |
25402f5d HL |
138 | EL1_OR_EL2_OR_EL3(x1)\r |
139 | 1: mrs x0, sctlr_el1 // Get control register EL1\r | |
140 | b 4f\r | |
141 | 2: mrs x0, sctlr_el2 // Get control register EL2\r | |
142 | b 4f\r | |
143 | 3: mrs x0, sctlr_el3 // Get control register EL3\r | |
144 | 4: and x0, x0, #CTRL_M_BIT\r | |
145 | ret\r | |
146 | \r | |
147 | \r | |
0efaa42f | 148 | ASM_FUNC(ArmEnableDataCache)\r |
25402f5d HL |
149 | EL1_OR_EL2_OR_EL3(x1)\r |
150 | 1: mrs x0, sctlr_el1 // Get control register EL1\r | |
151 | b 4f\r | |
152 | 2: mrs x0, sctlr_el2 // Get control register EL2\r | |
153 | b 4f\r | |
154 | 3: mrs x0, sctlr_el3 // Get control register EL3\r | |
155 | 4: orr x0, x0, #CTRL_C_BIT // Set C bit\r | |
156 | EL1_OR_EL2_OR_EL3(x1)\r | |
157 | 1: msr sctlr_el1, x0 // Write back control register\r | |
158 | b 4f\r | |
159 | 2: msr sctlr_el2, x0 // Write back control register\r | |
160 | b 4f\r | |
161 | 3: msr sctlr_el3, x0 // Write back control register\r | |
162 | 4: dsb sy\r | |
163 | isb\r | |
164 | ret\r | |
165 | \r | |
166 | \r | |
0efaa42f | 167 | ASM_FUNC(ArmDisableDataCache)\r |
25402f5d HL |
168 | EL1_OR_EL2_OR_EL3(x1)\r |
169 | 1: mrs x0, sctlr_el1 // Get control register EL1\r | |
170 | b 4f\r | |
171 | 2: mrs x0, sctlr_el2 // Get control register EL2\r | |
172 | b 4f\r | |
173 | 3: mrs x0, sctlr_el3 // Get control register EL3\r | |
73ca5009 | 174 | 4: and x0, x0, #~CTRL_C_BIT // Clear C bit\r |
25402f5d HL |
175 | EL1_OR_EL2_OR_EL3(x1)\r |
176 | 1: msr sctlr_el1, x0 // Write back control register\r | |
177 | b 4f\r | |
178 | 2: msr sctlr_el2, x0 // Write back control register\r | |
179 | b 4f\r | |
180 | 3: msr sctlr_el3, x0 // Write back control register\r | |
181 | 4: dsb sy\r | |
182 | isb\r | |
183 | ret\r | |
184 | \r | |
185 | \r | |
0efaa42f | 186 | ASM_FUNC(ArmEnableInstructionCache)\r |
25402f5d HL |
187 | EL1_OR_EL2_OR_EL3(x1)\r |
188 | 1: mrs x0, sctlr_el1 // Get control register EL1\r | |
189 | b 4f\r | |
190 | 2: mrs x0, sctlr_el2 // Get control register EL2\r | |
191 | b 4f\r | |
192 | 3: mrs x0, sctlr_el3 // Get control register EL3\r | |
193 | 4: orr x0, x0, #CTRL_I_BIT // Set I bit\r | |
194 | EL1_OR_EL2_OR_EL3(x1)\r | |
195 | 1: msr sctlr_el1, x0 // Write back control register\r | |
196 | b 4f\r | |
197 | 2: msr sctlr_el2, x0 // Write back control register\r | |
198 | b 4f\r | |
199 | 3: msr sctlr_el3, x0 // Write back control register\r | |
200 | 4: dsb sy\r | |
201 | isb\r | |
202 | ret\r | |
203 | \r | |
204 | \r | |
0efaa42f | 205 | ASM_FUNC(ArmDisableInstructionCache)\r |
25402f5d HL |
206 | EL1_OR_EL2_OR_EL3(x1)\r |
207 | 1: mrs x0, sctlr_el1 // Get control register EL1\r | |
208 | b 4f\r | |
209 | 2: mrs x0, sctlr_el2 // Get control register EL2\r | |
210 | b 4f\r | |
211 | 3: mrs x0, sctlr_el3 // Get control register EL3\r | |
73ca5009 | 212 | 4: and x0, x0, #~CTRL_I_BIT // Clear I bit\r |
25402f5d HL |
213 | EL1_OR_EL2_OR_EL3(x1)\r |
214 | 1: msr sctlr_el1, x0 // Write back control register\r | |
215 | b 4f\r | |
216 | 2: msr sctlr_el2, x0 // Write back control register\r | |
217 | b 4f\r | |
218 | 3: msr sctlr_el3, x0 // Write back control register\r | |
219 | 4: dsb sy\r | |
220 | isb\r | |
221 | ret\r | |
222 | \r | |
223 | \r | |
0efaa42f | 224 | ASM_FUNC(ArmEnableAlignmentCheck)\r |
25402f5d HL |
225 | EL1_OR_EL2(x1)\r |
226 | 1: mrs x0, sctlr_el1 // Get control register EL1\r | |
227 | b 3f\r | |
228 | 2: mrs x0, sctlr_el2 // Get control register EL2\r | |
229 | 3: orr x0, x0, #CTRL_A_BIT // Set A (alignment check) bit\r | |
230 | EL1_OR_EL2(x1)\r | |
231 | 1: msr sctlr_el1, x0 // Write back control register\r | |
232 | b 3f\r | |
233 | 2: msr sctlr_el2, x0 // Write back control register\r | |
234 | 3: dsb sy\r | |
235 | isb\r | |
236 | ret\r | |
237 | \r | |
238 | \r | |
0efaa42f | 239 | ASM_FUNC(ArmDisableAlignmentCheck)\r |
25402f5d HL |
240 | EL1_OR_EL2_OR_EL3(x1)\r |
241 | 1: mrs x0, sctlr_el1 // Get control register EL1\r | |
242 | b 4f\r | |
243 | 2: mrs x0, sctlr_el2 // Get control register EL2\r | |
244 | b 4f\r | |
245 | 3: mrs x0, sctlr_el3 // Get control register EL3\r | |
73ca5009 | 246 | 4: and x0, x0, #~CTRL_A_BIT // Clear A (alignment check) bit\r |
25402f5d HL |
247 | EL1_OR_EL2_OR_EL3(x1)\r |
248 | 1: msr sctlr_el1, x0 // Write back control register\r | |
249 | b 4f\r | |
250 | 2: msr sctlr_el2, x0 // Write back control register\r | |
251 | b 4f\r | |
252 | 3: msr sctlr_el3, x0 // Write back control register\r | |
253 | 4: dsb sy\r | |
254 | isb\r | |
255 | ret\r | |
256 | \r | |
97f0d01d AB |
257 | ASM_FUNC(ArmEnableStackAlignmentCheck)\r |
258 | EL1_OR_EL2(x1)\r | |
259 | 1: mrs x0, sctlr_el1 // Get control register EL1\r | |
260 | b 3f\r | |
261 | 2: mrs x0, sctlr_el2 // Get control register EL2\r | |
262 | 3: orr x0, x0, #CTRL_SA_BIT // Set SA (stack alignment check) bit\r | |
263 | EL1_OR_EL2(x1)\r | |
264 | 1: msr sctlr_el1, x0 // Write back control register\r | |
265 | b 3f\r | |
266 | 2: msr sctlr_el2, x0 // Write back control register\r | |
267 | 3: dsb sy\r | |
268 | isb\r | |
269 | ret\r | |
270 | \r | |
271 | \r | |
272 | ASM_FUNC(ArmDisableStackAlignmentCheck)\r | |
273 | EL1_OR_EL2_OR_EL3(x1)\r | |
274 | 1: mrs x0, sctlr_el1 // Get control register EL1\r | |
275 | b 4f\r | |
276 | 2: mrs x0, sctlr_el2 // Get control register EL2\r | |
277 | b 4f\r | |
278 | 3: mrs x0, sctlr_el3 // Get control register EL3\r | |
279 | 4: bic x0, x0, #CTRL_SA_BIT // Clear SA (stack alignment check) bit\r | |
280 | EL1_OR_EL2_OR_EL3(x1)\r | |
281 | 1: msr sctlr_el1, x0 // Write back control register\r | |
282 | b 4f\r | |
283 | 2: msr sctlr_el2, x0 // Write back control register\r | |
284 | b 4f\r | |
285 | 3: msr sctlr_el3, x0 // Write back control register\r | |
286 | 4: dsb sy\r | |
287 | isb\r | |
288 | ret\r | |
289 | \r | |
25402f5d HL |
290 | \r |
291 | // Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now\r | |
0efaa42f | 292 | ASM_FUNC(ArmEnableBranchPrediction)\r |
25402f5d HL |
293 | ret\r |
294 | \r | |
295 | \r | |
296 | // Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now.\r | |
0efaa42f | 297 | ASM_FUNC(ArmDisableBranchPrediction)\r |
25402f5d HL |
298 | ret\r |
299 | \r | |
300 | \r | |
0efaa42f | 301 | ASM_FUNC(AArch64AllDataCachesOperation)\r |
25402f5d | 302 | // We can use regs 0-7 and 9-15 without having to save/restore.\r |
fb7ea611 | 303 | // Save our link register on the stack. - The stack must always be quad-word aligned\r |
de2a7824 AB |
304 | stp x29, x30, [sp, #-16]!\r |
305 | mov x29, sp\r | |
25402f5d HL |
306 | mov x1, x0 // Save Function call in x1\r |
307 | mrs x6, clidr_el1 // Read EL1 CLIDR\r | |
308 | and x3, x6, #0x7000000 // Mask out all but Level of Coherency (LoC)\r | |
433a49a0 OM |
309 | lsr x3, x3, #23 // Left align cache level value - the level is shifted by 1 to the\r |
310 | // right to ease the access to CSSELR and the Set/Way operation.\r | |
25402f5d HL |
311 | cbz x3, L_Finished // No need to clean if LoC is 0\r |
312 | mov x10, #0 // Start clean at cache level 0\r | |
25402f5d HL |
313 | \r |
314 | Loop1:\r | |
315 | add x2, x10, x10, lsr #1 // Work out 3x cachelevel for cache info\r | |
316 | lsr x12, x6, x2 // bottom 3 bits are the Cache type for this level\r | |
317 | and x12, x12, #7 // get those 3 bits alone\r | |
318 | cmp x12, #2 // what cache at this level?\r | |
319 | b.lt L_Skip // no cache or only instruction cache at this level\r | |
320 | msr csselr_el1, x10 // write the Cache Size selection register with current level (CSSELR)\r | |
321 | isb // isb to sync the change to the CacheSizeID reg\r | |
322 | mrs x12, ccsidr_el1 // reads current Cache Size ID register (CCSIDR)\r | |
323 | and x2, x12, #0x7 // extract the line length field\r | |
324 | add x2, x2, #4 // add 4 for the line length offset (log2 16 bytes)\r | |
325 | mov x4, #0x400\r | |
326 | sub x4, x4, #1\r | |
327 | and x4, x4, x12, lsr #3 // x4 is the max number on the way size (right aligned)\r | |
328 | clz w5, w4 // w5 is the bit position of the way size increment\r | |
329 | mov x7, #0x00008000\r | |
330 | sub x7, x7, #1\r | |
331 | and x7, x7, x12, lsr #13 // x7 is the max number of the index size (right aligned)\r | |
332 | \r | |
333 | Loop2:\r | |
334 | mov x9, x4 // x9 working copy of the max way size (right aligned)\r | |
335 | \r | |
336 | Loop3:\r | |
337 | lsl x11, x9, x5\r | |
338 | orr x0, x10, x11 // factor in the way number and cache number\r | |
339 | lsl x11, x7, x2\r | |
340 | orr x0, x0, x11 // factor in the index number\r | |
341 | \r | |
342 | blr x1 // Goto requested cache operation\r | |
343 | \r | |
344 | subs x9, x9, #1 // decrement the way number\r | |
345 | b.ge Loop3\r | |
346 | subs x7, x7, #1 // decrement the index\r | |
347 | b.ge Loop2\r | |
348 | L_Skip:\r | |
349 | add x10, x10, #2 // increment the cache number\r | |
350 | cmp x3, x10\r | |
351 | b.gt Loop1\r | |
352 | \r | |
353 | L_Finished:\r | |
354 | dsb sy\r | |
355 | isb\r | |
de2a7824 | 356 | ldp x29, x30, [sp], #0x10\r |
25402f5d HL |
357 | ret\r |
358 | \r | |
359 | \r | |
0efaa42f | 360 | ASM_FUNC(ArmDataMemoryBarrier)\r |
25402f5d HL |
361 | dmb sy\r |
362 | ret\r | |
363 | \r | |
364 | \r | |
0efaa42f | 365 | ASM_FUNC(ArmDataSynchronizationBarrier)\r |
25402f5d HL |
366 | dsb sy\r |
367 | ret\r | |
368 | \r | |
369 | \r | |
0efaa42f | 370 | ASM_FUNC(ArmInstructionSynchronizationBarrier)\r |
25402f5d HL |
371 | isb\r |
372 | ret\r | |
373 | \r | |
374 | \r | |
0efaa42f | 375 | ASM_FUNC(ArmWriteVBar)\r |
25402f5d HL |
376 | EL1_OR_EL2_OR_EL3(x1)\r |
377 | 1: msr vbar_el1, x0 // Set the Address of the EL1 Vector Table in the VBAR register\r | |
378 | b 4f\r | |
379 | 2: msr vbar_el2, x0 // Set the Address of the EL2 Vector Table in the VBAR register\r | |
380 | b 4f\r | |
381 | 3: msr vbar_el3, x0 // Set the Address of the EL3 Vector Table in the VBAR register\r | |
382 | 4: isb\r | |
383 | ret\r | |
384 | \r | |
0efaa42f | 385 | ASM_FUNC(ArmReadVBar)\r |
f0247796 OM |
386 | EL1_OR_EL2_OR_EL3(x1)\r |
387 | 1: mrs x0, vbar_el1 // Set the Address of the EL1 Vector Table in the VBAR register\r | |
388 | ret\r | |
389 | 2: mrs x0, vbar_el2 // Set the Address of the EL2 Vector Table in the VBAR register\r | |
390 | ret\r | |
391 | 3: mrs x0, vbar_el3 // Set the Address of the EL3 Vector Table in the VBAR register\r | |
392 | ret\r | |
393 | \r | |
394 | \r | |
0efaa42f | 395 | ASM_FUNC(ArmEnableVFP)\r |
25402f5d HL |
396 | // Check whether floating-point is implemented in the processor.\r |
397 | mov x1, x30 // Save LR\r | |
398 | bl ArmReadIdPfr0 // Read EL1 Processor Feature Register (PFR0)\r | |
399 | mov x30, x1 // Restore LR\r | |
2f16993c SM |
400 | ubfx x0, x0, #16, #4 // Extract the FP bits 16:19\r |
401 | cmp x0, #0xF // Check if FP bits are '1111b',\r | |
402 | // i.e. Floating Point not implemented\r | |
403 | b.eq 4f // Exit when VFP is not implemented.\r | |
404 | \r | |
25402f5d HL |
405 | // FVP is implemented.\r |
406 | // Make sure VFP exceptions are not trapped (to any exception level).\r | |
407 | mrs x0, cpacr_el1 // Read EL1 Coprocessor Access Control Register (CPACR)\r | |
408 | orr x0, x0, #CPACR_VFP_BITS // Disable FVP traps to EL1\r | |
409 | msr cpacr_el1, x0 // Write back EL1 Coprocessor Access Control Register (CPACR)\r | |
410 | mov x1, #AARCH64_CPTR_TFP // TFP Bit for trapping VFP Exceptions\r | |
411 | EL1_OR_EL2_OR_EL3(x2)\r | |
412 | 1:ret // Not configurable in EL1\r | |
413 | 2:mrs x0, cptr_el2 // Disable VFP traps to EL2\r | |
414 | bic x0, x0, x1\r | |
415 | msr cptr_el2, x0\r | |
416 | ret\r | |
417 | 3:mrs x0, cptr_el3 // Disable VFP traps to EL3\r | |
418 | bic x0, x0, x1\r | |
419 | msr cptr_el3, x0\r | |
420 | 4:ret\r | |
421 | \r | |
422 | \r | |
0efaa42f | 423 | ASM_FUNC(ArmCallWFI)\r |
25402f5d HL |
424 | wfi\r |
425 | ret\r | |
426 | \r | |
427 | \r | |
0efaa42f | 428 | ASM_FUNC(ArmReadMpidr)\r |
25402f5d HL |
429 | mrs x0, mpidr_el1 // read EL1 MPIDR\r |
430 | ret\r | |
431 | \r | |
432 | \r | |
ff5fef14 | 433 | // Keep old function names for C compatibility for now. Change later?\r |
0efaa42f | 434 | ASM_FUNC(ArmReadTpidrurw)\r |
25402f5d HL |
435 | mrs x0, tpidr_el0 // read tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)\r |
436 | ret\r | |
437 | \r | |
438 | \r | |
ff5fef14 | 439 | // Keep old function names for C compatibility for now. Change later?\r |
0efaa42f | 440 | ASM_FUNC(ArmWriteTpidrurw)\r |
25402f5d HL |
441 | msr tpidr_el0, x0 // write tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)\r |
442 | ret\r | |
443 | \r | |
444 | \r | |
445 | // Arch timers are mandatory on AArch64\r | |
0efaa42f | 446 | ASM_FUNC(ArmIsArchTimerImplemented)\r |
25402f5d HL |
447 | mov x0, #1\r |
448 | ret\r | |
449 | \r | |
450 | \r | |
0efaa42f | 451 | ASM_FUNC(ArmReadIdPfr0)\r |
25402f5d HL |
452 | mrs x0, id_aa64pfr0_el1 // Read ID_AA64PFR0 Register\r |
453 | ret\r | |
454 | \r | |
455 | \r | |
25402f5d | 456 | // VOID ArmWriteHcr(UINTN Hcr)\r |
0efaa42f | 457 | ASM_FUNC(ArmWriteHcr)\r |
25402f5d HL |
458 | msr hcr_el2, x0 // Write the passed HCR value\r |
459 | ret\r | |
460 | \r | |
d2bb61a2 | 461 | // UINTN ArmReadHcr(VOID)\r |
0efaa42f | 462 | ASM_FUNC(ArmReadHcr)\r |
d2bb61a2 EC |
463 | mrs x0, hcr_el2\r |
464 | ret\r | |
465 | \r | |
25402f5d | 466 | // UINTN ArmReadCurrentEL(VOID)\r |
0efaa42f | 467 | ASM_FUNC(ArmReadCurrentEL)\r |
25402f5d HL |
468 | mrs x0, CurrentEL\r |
469 | ret\r | |
470 | \r | |
23d6348f SM |
471 | // UINT32 ArmReadCntHctl(VOID)\r |
472 | ASM_FUNC(ArmReadCntHctl)\r | |
473 | mrs x0, cnthctl_el2\r | |
474 | ret\r | |
475 | \r | |
476 | // VOID ArmWriteCntHctl(UINT32 CntHctl)\r | |
477 | ASM_FUNC(ArmWriteCntHctl)\r | |
478 | msr cnthctl_el2, x0\r | |
479 | ret\r | |
480 | \r | |
25402f5d | 481 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r |