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1 | //------------------------------------------------------------------------------ |
2 | // | |
3 | // Copyright (c) 2008-2009 Apple Inc. All rights reserved. | |
4 | // | |
5 | // All rights reserved. This program and the accompanying materials | |
6 | // are licensed and made available under the terms and conditions of the BSD License | |
7 | // which accompanies this distribution. The full text of the license may be found at | |
8 | // http://opensource.org/licenses/bsd-license.php | |
9 | // | |
10 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
11 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
12 | // | |
13 | //------------------------------------------------------------------------------ | |
14 | ||
15 | EXPORT ArmInvalidateInstructionCache | |
16 | EXPORT ArmInvalidateDataCacheEntryByMVA | |
17 | EXPORT ArmCleanDataCacheEntryByMVA | |
18 | EXPORT ArmCleanInvalidateDataCacheEntryByMVA | |
19 | EXPORT ArmInvalidateDataCacheEntryBySetWay | |
20 | EXPORT ArmCleanDataCacheEntryBySetWay | |
21 | EXPORT ArmCleanInvalidateDataCacheEntryBySetWay | |
22 | EXPORT ArmDrainWriteBuffer | |
23 | EXPORT ArmEnableMmu | |
24 | EXPORT ArmDisableMmu | |
c2b5ca8b | 25 | EXPORT ArmMmuEnabled |
2ef2b01e A |
26 | EXPORT ArmEnableDataCache |
27 | EXPORT ArmDisableDataCache | |
28 | EXPORT ArmEnableInstructionCache | |
29 | EXPORT ArmDisableInstructionCache | |
30 | EXPORT ArmEnableBranchPrediction | |
31 | EXPORT ArmDisableBranchPrediction | |
37b91c49 | 32 | EXPORT ArmV7AllDataCachesOperation |
026c3d34 | 33 | EXPORT ArmDataMemoryBarrier |
34 | EXPORT ArmDataSyncronizationBarrier | |
35 | EXPORT ArmInstructionSynchronizationBarrier | |
36 | ||
548af3e7 | 37 | AREA ArmCacheLib, CODE, READONLY |
38 | PRESERVE8 | |
2ef2b01e A |
39 | |
40 | DC_ON EQU ( 0x1:SHL:2 ) | |
41 | IC_ON EQU ( 0x1:SHL:12 ) | |
2ef2b01e A |
42 | |
43 | ||
2ef2b01e A |
44 | |
45 | ArmInvalidateDataCacheEntryByMVA | |
548af3e7 | 46 | mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line |
47 | dsb | |
48 | isb | |
49 | bx lr | |
2ef2b01e A |
50 | |
51 | ||
52 | ArmCleanDataCacheEntryByMVA | |
548af3e7 | 53 | mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line |
54 | dsb | |
55 | isb | |
56 | bx lr | |
2ef2b01e A |
57 | |
58 | ||
59 | ArmCleanInvalidateDataCacheEntryByMVA | |
548af3e7 | 60 | mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line |
61 | dsb | |
62 | isb | |
63 | bx lr | |
2ef2b01e A |
64 | |
65 | ||
66 | ArmInvalidateDataCacheEntryBySetWay | |
67 | mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line | |
548af3e7 | 68 | dsb |
69 | isb | |
2ef2b01e A |
70 | bx lr |
71 | ||
72 | ||
73 | ArmCleanInvalidateDataCacheEntryBySetWay | |
74 | mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line | |
548af3e7 | 75 | dsb |
76 | isb | |
2ef2b01e A |
77 | bx lr |
78 | ||
79 | ||
80 | ArmCleanDataCacheEntryBySetWay | |
81 | mcr p15, 0, r0, c7, c10, 2 ; Clean this line | |
548af3e7 | 82 | dsb |
83 | isb | |
2ef2b01e A |
84 | bx lr |
85 | ||
86 | ||
2ef2b01e | 87 | ArmInvalidateInstructionCache |
548af3e7 | 88 | mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache |
548af3e7 | 89 | dsb |
90 | isb | |
91 | bx LR | |
2ef2b01e A |
92 | |
93 | ArmEnableMmu | |
94 | mrc p15,0,R0,c1,c0,0 | |
95 | orr R0,R0,#1 | |
96 | mcr p15,0,R0,c1,c0,0 | |
548af3e7 | 97 | dsb |
98 | isb | |
2ef2b01e A |
99 | bx LR |
100 | ||
c2b5ca8b A |
101 | ArmMmuEnabled |
102 | mrc p15,0,R0,c1,c0,0 | |
103 | and R0,R0,#1 | |
104 | bx LR | |
105 | ||
2ef2b01e | 106 | ArmDisableMmu |
2ef2b01e A |
107 | mrc p15,0,R0,c1,c0,0 |
108 | bic R0,R0,#1 | |
109 | mcr p15,0,R0,c1,c0,0 ;Disable MMU | |
7800c283 | 110 | |
111 | mcr p15,0,R0,c8,c7,0 ;Invalidate TLB | |
112 | mcr p15,0,R0,c7,c5,6 ;Invalidate Branch predictor array | |
548af3e7 | 113 | dsb |
114 | isb | |
2ef2b01e A |
115 | bx LR |
116 | ||
117 | ArmEnableDataCache | |
548af3e7 | 118 | ldr R1,=DC_ON |
119 | mrc p15,0,R0,c1,c0,0 ;Read control register configuration data | |
120 | orr R0,R0,R1 ;Set C bit | |
7800c283 | 121 | mcr p15,0,R0,c1,c0,0 ;Write control register configuration data |
548af3e7 | 122 | dsb |
123 | isb | |
124 | bx LR | |
2ef2b01e A |
125 | |
126 | ArmDisableDataCache | |
548af3e7 | 127 | ldr R1,=DC_ON |
128 | mrc p15,0,R0,c1,c0,0 ;Read control register configuration data | |
129 | bic R0,R0,R1 ;Clear C bit | |
7800c283 | 130 | mcr p15,0,R0,c1,c0,0 ;Write control register configuration data |
548af3e7 | 131 | isb |
132 | bx LR | |
2ef2b01e A |
133 | |
134 | ArmEnableInstructionCache | |
548af3e7 | 135 | ldr R1,=IC_ON |
136 | mrc p15,0,R0,c1,c0,0 ;Read control register configuration data | |
137 | orr R0,R0,R1 ;Set I bit | |
7800c283 | 138 | mcr p15,0,R0,c1,c0,0 ;Write control register configuration data |
548af3e7 | 139 | dsb |
140 | isb | |
141 | bx LR | |
2ef2b01e A |
142 | |
143 | ArmDisableInstructionCache | |
548af3e7 | 144 | ldr R1,=IC_ON |
145 | mrc p15,0,R0,c1,c0,0 ;Read control register configuration data | |
2ef2b01e | 146 | BIC R0,R0,R1 ;Clear I bit. |
7800c283 | 147 | mcr p15,0,R0,c1,c0,0 ;Write control register configuration data |
548af3e7 | 148 | isb |
149 | bx LR | |
2ef2b01e A |
150 | |
151 | ArmEnableBranchPrediction | |
152 | mrc p15, 0, r0, c1, c0, 0 | |
153 | orr r0, r0, #0x00000800 | |
154 | mcr p15, 0, r0, c1, c0, 0 | |
548af3e7 | 155 | isb |
2ef2b01e A |
156 | bx LR |
157 | ||
158 | ArmDisableBranchPrediction | |
159 | mrc p15, 0, r0, c1, c0, 0 | |
160 | bic r0, r0, #0x00000800 | |
161 | mcr p15, 0, r0, c1, c0, 0 | |
548af3e7 | 162 | isb |
2ef2b01e A |
163 | bx LR |
164 | ||
98bc0c8c | 165 | |
166 | ArmV7AllDataCachesOperation | |
548af3e7 | 167 | stmfd SP!,{r4-r12, LR} |
168 | mov R1, R0 ; Save Function call in R1 | |
169 | mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR | |
170 | ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC) | |
171 | mov R3, R3, LSR #23 ; Cache level value (naturally aligned) | |
172 | beq Finished | |
173 | mov R10, #0 | |
98bc0c8c | 174 | |
175 | Loop1 | |
548af3e7 | 176 | add R2, R10, R10, LSR #1 ; Work out 3xcachelevel |
177 | mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level | |
178 | and R12, R12, #7 ; get those 3 bits alone | |
179 | cmp R12, #2 | |
180 | blt Skip ; no cache or only instruction cache at this level | |
181 | mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction | |
182 | isb ; isb to sync the change to the CacheSizeID reg | |
183 | mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR) | |
184 | and R2, R12, #&7 ; extract the line length field | |
185 | add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes) | |
186 | ldr R4, =0x3FF | |
187 | ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned) | |
188 | clz R5, R4 ; R5 is the bit position of the way size increment | |
189 | ldr R7, =0x00007FFF | |
190 | ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned) | |
98bc0c8c | 191 | |
192 | Loop2 | |
548af3e7 | 193 | mov R9, R4 ; R9 working copy of the max way size (right aligned) |
98bc0c8c | 194 | |
195 | Loop3 | |
548af3e7 | 196 | orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11 |
197 | orr R0, R0, R7, LSL R2 ; factor in the index number | |
98bc0c8c | 198 | |
548af3e7 | 199 | blx R1 |
98bc0c8c | 200 | |
548af3e7 | 201 | subs R9, R9, #1 ; decrement the way number |
202 | bge Loop3 | |
203 | subs R7, R7, #1 ; decrement the index | |
204 | bge Loop2 | |
98bc0c8c | 205 | Skip |
548af3e7 | 206 | add R10, R10, #2 ; increment the cache number |
207 | cmp R3, R10 | |
208 | bgt Loop1 | |
98bc0c8c | 209 | |
210 | Finished | |
7800c283 | 211 | dsb |
548af3e7 | 212 | ldmfd SP!, {r4-r12, lr} |
213 | bx LR | |
98bc0c8c | 214 | |
026c3d34 | 215 | |
216 | ArmDataMemoryBarrier | |
548af3e7 | 217 | dmb |
218 | bx LR | |
026c3d34 | 219 | |
220 | ArmDataSyncronizationBarrier | |
7800c283 | 221 | ArmDrainWriteBuffer |
548af3e7 | 222 | dsb |
223 | bx LR | |
026c3d34 | 224 | |
225 | ArmInstructionSynchronizationBarrier | |
548af3e7 | 226 | isb |
227 | bx LR | |
026c3d34 | 228 | |
2ef2b01e | 229 | END |