| c52e2dca |
1 | //\r |
| 2 | // Copyright (c) 2011, ARM Limited. All rights reserved.\r |
| 3 | //\r |
| 4 | // This program and the accompanying materials\r |
| 5 | // are licensed and made available under the terms and conditions of the BSD License\r |
| 6 | // which accompanies this distribution. The full text of the license may be found at\r |
| 7 | // http://opensource.org/licenses/bsd-license.php\r |
| 8 | //\r |
| 9 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 10 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| 11 | //\r |
| 12 | //\r |
| 13 | \r |
| 14 | #include <AsmMacroIoLib.h>\r |
| 15 | #include <Base.h>\r |
| 16 | #include <Library/ArmPlatformLib.h>\r |
| 17 | #include <Drivers/PL35xSmc.h>\r |
| 18 | #include <ArmPlatform.h>\r |
| 19 | #include <AutoGen.h>\r |
| 20 | \r |
| 21 | INCLUDE AsmMacroIoLib.inc\r |
| 22 | \r |
| 23 | EXPORT ArmPlatformInitializeBootMemory\r |
| 24 | IMPORT PL35xSmcInitialize\r |
| 25 | \r |
| 26 | PRESERVE8\r |
| 27 | AREA CTA9x4BootMode, CODE, READONLY\r |
| 28 | \r |
| 29 | //\r |
| 30 | // For each Chip Select: ChipSelect / SetCycle / SetOpMode\r |
| 31 | //\r |
| 32 | VersatileExpressSmcConfiguration\r |
| 33 | // NOR Flash 0\r |
| 34 | DCD PL350_SMC_DIRECT_CMD_ADDR_CS(0)\r |
| 35 | DCD PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) :OR: PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) :OR: PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) :OR: PL350_SMC_SET_CYCLE_NAND_T_AR(0x1)\r |
| 36 | DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_ADV\r |
| 37 | \r |
| 38 | // NOR Flash 1\r |
| 39 | DCD PL350_SMC_DIRECT_CMD_ADDR_CS(4)\r |
| 40 | DCD PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) :OR: PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) :OR: PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) :OR: PL350_SMC_SET_CYCLE_NAND_T_AR(0x1)\r |
| 41 | DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_ADV\r |
| 42 | \r |
| 43 | // SRAM\r |
| 44 | DCD PL350_SMC_DIRECT_CMD_ADDR_CS(2)\r |
| 45 | DCD PL350_SMC_SET_CYCLE_SRAM_T_RC(0x8) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x6) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1)\r |
| 46 | DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_ADV\r |
| 47 | \r |
| 48 | // Usb/Eth/VRAM\r |
| 49 | DCD PL350_SMC_DIRECT_CMD_ADDR_CS(3)\r |
| 50 | DCD PL350_SMC_SET_CYCLE_SRAM_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0xA) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x3) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x6)\r |
| 51 | DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC\r |
| 52 | \r |
| 53 | // Memory Mapped Peripherals\r |
| 54 | DCD PL350_SMC_DIRECT_CMD_ADDR_CS(7)\r |
| 55 | DCD PL350_SMC_SET_CYCLE_SRAM_T_RC(0x6) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1)\r |
| 56 | DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC\r |
| 57 | \r |
| 58 | // VRAM\r |
| 59 | DCD PL350_SMC_DIRECT_CMD_ADDR_CS(1)\r |
| 60 | DCD 0x00049249\r |
| 61 | DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC\r |
| 62 | VersatileExpressSmcConfigurationEnd\r |
| 63 | \r |
| 64 | /**\r |
| 65 | Initialize the memory where the initial stacks will reside\r |
| 66 | \r |
| 67 | This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r |
| 68 | In some platform, this region is already initialized and the implementation of this function can\r |
| 69 | do nothing. This memory can also represent the Secure RAM.\r |
| 70 | This function is called before the satck has been set up. Its implementation must ensure the stack\r |
| 71 | pointer is not used (probably required to use assembly language)\r |
| 72 | \r |
| 73 | **/\r |
| 74 | ArmPlatformInitializeBootMemory\r |
| 75 | mov r5, lr\r |
| 76 | \r |
| 77 | //\r |
| 78 | // Initialize PL354 SMC\r |
| 79 | //\r |
| 80 | LoadConstantToReg (ARM_VE_SMC_CTRL_BASE, r1)\r |
| 81 | ldr r2, =VersatileExpressSmcConfiguration\r |
| 82 | ldr r3, =VersatileExpressSmcConfigurationEnd\r |
| 83 | blx PL35xSmcInitialize\r |
| 84 | \r |
| 85 | //\r |
| 86 | // Page mode setup for VRAM\r |
| 87 | //\r |
| 88 | LoadConstantToReg (VRAM_MOTHERBOARD_BASE, r2)\r |
| 89 | \r |
| 90 | // Read current state\r |
| 91 | ldr r0, [r2, #0]\r |
| 92 | ldr r0, [r2, #0]\r |
| 93 | ldr r0, = 0x00000000\r |
| 94 | str r0, [r2, #0]\r |
| 95 | ldr r0, [r2, #0]\r |
| 96 | \r |
| 97 | // Enable page mode\r |
| 98 | ldr r0, [r2, #0]\r |
| 99 | ldr r0, [r2, #0]\r |
| 100 | ldr r0, = 0x00000000\r |
| 101 | str r0, [r2, #0]\r |
| 102 | ldr r0, = 0x00900090\r |
| 103 | str r0, [r2, #0]\r |
| 104 | \r |
| 105 | // Confirm page mode enabled\r |
| 106 | ldr r0, [r2, #0]\r |
| 107 | ldr r0, [r2, #0]\r |
| 108 | ldr r0, = 0x00000000\r |
| 109 | str r0, [r2, #0]\r |
| 110 | ldr r0, [r2, #0]\r |
| 111 | \r |
| 112 | bx r5\r |
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