ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Boot.asm

   1 //
   2 //  Copyright (c) 2011, ARM Limited. All rights reserved.
   3 //
   4 //  This program and the accompanying materials
   5 //  are licensed and made available under the terms and conditions of the BSD License
   6 //  which accompanies this distribution.  The full text of the license may be found at
   7 //  http://opensource.org/licenses/bsd-license.php
   8 //
   9 //  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 //  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 //
  12 //
  13
  14 #include <AsmMacroIoLib.h>
  15 #include <Base.h>
  16 #include <Library/ArmPlatformLib.h>
  17 #include <Drivers/PL35xSmc.h>
  18 #include <ArmPlatform.h>
  19 #include <AutoGen.h>
  20
  21   INCLUDE AsmMacroIoLib.inc
  22
  23   EXPORT  ArmPlatformInitializeBootMemory
  24   IMPORT  PL35xSmcInitialize
  25
  26   PRESERVE8
  27   AREA    CTA9x4BootMode, CODE, READONLY
  28
  29 //
  30 // For each Chip Select: ChipSelect / SetCycle / SetOpMode
  31 //
  32 VersatileExpressSmcConfiguration
  33     // NOR Flash 0
  34     DCD     PL350_SMC_DIRECT_CMD_ADDR_CS(0)
  35     DCD     PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) :OR: PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) :OR: PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) :OR: PL350_SMC_SET_CYCLE_NAND_T_AR(0x1)
  36     DCD     PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_ADV
  37
  38     // NOR Flash 1
  39     DCD     PL350_SMC_DIRECT_CMD_ADDR_CS(4)
  40     DCD     PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) :OR: PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) :OR: PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) :OR: PL350_SMC_SET_CYCLE_NAND_T_AR(0x1)
  41     DCD     PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_ADV
  42
  43     // SRAM
  44     DCD     PL350_SMC_DIRECT_CMD_ADDR_CS(2)
  45     DCD     PL350_SMC_SET_CYCLE_SRAM_T_RC(0x8) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x6) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1)
  46     DCD     PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_ADV
  47
  48     // Usb/Eth/VRAM
  49     DCD     PL350_SMC_DIRECT_CMD_ADDR_CS(3)
  50     DCD     PL350_SMC_SET_CYCLE_SRAM_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0xA) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x3) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x6)
  51     DCD     PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC
  52
  53     // Memory Mapped Peripherals
  54     DCD     PL350_SMC_DIRECT_CMD_ADDR_CS(7)
  55     DCD     PL350_SMC_SET_CYCLE_SRAM_T_RC(0x6) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1)
  56     DCD     PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC
  57
  58     // VRAM
  59     DCD     PL350_SMC_DIRECT_CMD_ADDR_CS(1)
  60     DCD     0x00049249
  61     DCD     PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC
  62 VersatileExpressSmcConfigurationEnd
  63
  64 /**
  65   Initialize the memory where the initial stacks will reside
  66
  67   This memory can contain the initial stacks (Secure and Secure Monitor stacks).
  68   In some platform, this region is already initialized and the implementation of this function can
  69   do nothing. This memory can also represent the Secure RAM.
  70   This function is called before the satck has been set up. Its implementation must ensure the stack
  71   pointer is not used (probably required to use assembly language)
  72
  73 **/
  74 ArmPlatformInitializeBootMemory
  75   mov   r5, lr
  76
  77   //
  78   // Initialize PL354 SMC
  79   //
  80   LoadConstantToReg (ARM_VE_SMC_CTRL_BASE, r1)
  81   ldr   r2, =VersatileExpressSmcConfiguration
  82   ldr   r3, =VersatileExpressSmcConfigurationEnd
  83   blx   PL35xSmcInitialize
  84
  85   //
  86   // Page mode setup for VRAM
  87   //
  88   LoadConstantToReg (VRAM_MOTHERBOARD_BASE, r2)
  89
  90   // Read current state
  91   ldr     r0, [r2, #0]
  92   ldr     r0, [r2, #0]
  93   ldr     r0, = 0x00000000
  94   str     r0, [r2, #0]
  95   ldr     r0, [r2, #0]
  96
  97   // Enable page mode
  98   ldr     r0, [r2, #0]
  99   ldr     r0, [r2, #0]
 100   ldr     r0, = 0x00000000
 101   str     r0, [r2, #0]
 102   ldr     r0, = 0x00900090
 103   str     r0, [r2, #0]
 104
 105   // Confirm page mode enabled
 106   ldr     r0, [r2, #0]
 107   ldr     r0, [r2, #0]
 108   ldr     r0, = 0x00000000
 109   str     r0, [r2, #0]
 110   ldr     r0, [r2, #0]
 111
 112   bx    r5