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1d5d0ae9 | 1 | /** @file\r |
2 | *\r | |
1b0ac0de | 3 | * Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r |
1d5d0ae9 | 4 | *\r |
5 | * This program and the accompanying materials\r | |
6 | * are licensed and made available under the terms and conditions of the BSD License\r | |
7 | * which accompanies this distribution. The full text of the license may be found at\r | |
8 | * http://opensource.org/licenses/bsd-license.php\r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | *\r | |
13 | **/\r | |
14 | \r | |
55a0d64b | 15 | #include <Library/ArmGicLib.h>\r |
44788bae | 16 | \r |
17 | #include <Ppi/ArmMpCoreInfo.h>\r | |
18 | \r | |
f598bf12 | 19 | #include "PrePeiCore.h"\r |
20 | \r | |
1d5d0ae9 | 21 | /*\r |
22 | * This is the main function for secondary cores. They loop around until a non Null value is written to\r | |
23 | * SYS_FLAGS register.The SYS_FLAGS register is platform specific.\r | |
24 | * Note:The secondary cores, while executing secondary_main, assumes that:\r | |
25 | * : SGI 0 is configured as Non-secure interrupt\r | |
26 | * : Priority Mask is configured to allow SGI 0\r | |
27 | * : Interrupt Distributor and CPU interfaces are enabled\r | |
28 | *\r | |
29 | */\r | |
30 | VOID\r | |
31 | EFIAPI\r | |
f598bf12 | 32 | SecondaryMain (\r |
0787bc61 | 33 | IN UINTN MpId\r |
f598bf12 | 34 | )\r |
1d5d0ae9 | 35 | {\r |
44788bae | 36 | EFI_STATUS Status;\r |
37 | UINTN PpiListSize;\r | |
38 | UINTN PpiListCount;\r | |
39 | EFI_PEI_PPI_DESCRIPTOR *PpiList;\r | |
40 | ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;\r | |
41 | UINTN Index;\r | |
42 | UINTN ArmCoreCount;\r | |
43 | ARM_CORE_INFO *ArmCoreInfoTable;\r | |
44 | UINT32 ClusterId;\r | |
45 | UINT32 CoreId;\r | |
46 | VOID (*SecondaryStart)(VOID);\r | |
47 | UINTN SecondaryEntryAddr;\r | |
1b0ac0de OM |
48 | UINTN AcknowledgeInterrupt;\r |
49 | UINTN InterruptId;\r | |
44788bae | 50 | \r |
51 | ClusterId = GET_CLUSTER_ID(MpId);\r | |
52 | CoreId = GET_CORE_ID(MpId);\r | |
53 | \r | |
54 | // Get the gArmMpCoreInfoPpiGuid\r | |
55 | PpiListSize = 0;\r | |
56 | ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);\r | |
57 | PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR);\r | |
58 | for (Index = 0; Index < PpiListCount; Index++, PpiList++) {\r | |
59 | if (CompareGuid (PpiList->Guid, &gArmMpCoreInfoPpiGuid) == TRUE) {\r | |
60 | break;\r | |
61 | }\r | |
62 | }\r | |
63 | \r | |
64 | // On MP Core Platform we must implement the ARM MP Core Info PPI\r | |
65 | ASSERT (Index != PpiListCount);\r | |
66 | \r | |
67 | ArmMpCoreInfoPpi = PpiList->Ppi;\r | |
68 | ArmCoreCount = 0;\r | |
69 | Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);\r | |
70 | ASSERT_EFI_ERROR (Status);\r | |
71 | \r | |
72 | // Find the core in the ArmCoreTable\r | |
73 | for (Index = 0; Index < ArmCoreCount; Index++) {\r | |
74 | if ((ArmCoreInfoTable[Index].ClusterId == ClusterId) && (ArmCoreInfoTable[Index].CoreId == CoreId)) {\r | |
75 | break;\r | |
76 | }\r | |
77 | }\r | |
78 | \r | |
79 | // The ARM Core Info Table must define every core\r | |
80 | ASSERT (Index != ArmCoreCount);\r | |
1d5d0ae9 | 81 | \r |
f598bf12 | 82 | // Clear Secondary cores MailBox\r |
44788bae | 83 | MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);\r |
1d5d0ae9 | 84 | \r |
315649cd | 85 | do {\r |
44788bae | 86 | ArmCallWFI ();\r |
315649cd | 87 | \r |
88 | // Read the Mailbox\r | |
89 | SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);\r | |
90 | \r | |
f598bf12 | 91 | // Acknowledge the interrupt and send End of Interrupt signal.\r |
1b0ac0de | 92 | AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), &InterruptId);\r |
2ca815a4 | 93 | // Check if it is a valid interrupt ID\r |
1b0ac0de | 94 | if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet32 (PcdGicDistributorBase))) {\r |
2ca815a4 | 95 | // Got a valid SGI number hence signal End of Interrupt\r |
1b0ac0de | 96 | ArmGicEndOfInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt);\r |
2ca815a4 | 97 | }\r |
f93f248a | 98 | } while (SecondaryEntryAddr == 0);\r |
1d5d0ae9 | 99 | \r |
f598bf12 | 100 | // Jump to secondary core entry point.\r |
44788bae | 101 | SecondaryStart = (VOID (*)())SecondaryEntryAddr;\r |
102 | SecondaryStart();\r | |
1d5d0ae9 | 103 | \r |
f598bf12 | 104 | // The secondaries shouldn't reach here\r |
105 | ASSERT(FALSE);\r | |
1d5d0ae9 | 106 | }\r |
107 | \r | |
f598bf12 | 108 | VOID\r |
109 | EFIAPI\r | |
110 | PrimaryMain (\r | |
1d5d0ae9 | 111 | IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint\r |
112 | )\r | |
113 | {\r | |
f598bf12 | 114 | EFI_SEC_PEI_HAND_OFF SecCoreData;\r |
77de7e53 | 115 | UINTN PpiListSize;\r |
116 | EFI_PEI_PPI_DESCRIPTOR *PpiList;\r | |
117 | UINTN TemporaryRamBase;\r | |
118 | UINTN TemporaryRamSize;\r | |
119 | \r | |
120 | CreatePpiList (&PpiListSize, &PpiList);\r | |
1d5d0ae9 | 121 | \r |
55a0d64b | 122 | // Enable the GIC Distributor\r |
6f711615 | 123 | ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));\r |
1d5d0ae9 | 124 | \r |
f598bf12 | 125 | // If ArmVe has not been built as Standalone then we need to wake up the secondary cores\r |
55a0d64b | 126 | if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) {\r |
f598bf12 | 127 | // Sending SGI to all the Secondary CPU interfaces\r |
4c19ece3 | 128 | ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));\r |
f598bf12 | 129 | }\r |
1d5d0ae9 | 130 | \r |
77de7e53 | 131 | // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at\r |
132 | // the base of the primary core stack\r | |
133 | PpiListSize = ALIGN_VALUE(PpiListSize, 0x4);\r | |
bb5420bb | 134 | TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize;\r |
77de7e53 | 135 | TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;\r |
136 | \r | |
3222e7b1 | 137 | // Make sure the size is 8-byte aligned. Once divided by 2, the size should be 4-byte aligned\r |
138 | // to ensure the stack pointer is 4-byte aligned.\r | |
139 | TemporaryRamSize = TemporaryRamSize - (TemporaryRamSize & (0x8-1));\r | |
140 | \r | |
f598bf12 | 141 | //\r |
142 | // Bind this information into the SEC hand-off state\r | |
143 | // Note: this must be in sync with the stuff in the asm file\r | |
144 | // Note also: HOBs (pei temp ram) MUST be above stack\r | |
145 | //\r | |
146 | SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);\r | |
bb5420bb | 147 | SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64 (PcdFvBaseAddress);\r |
f92b93c9 | 148 | SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);\r |
77de7e53 | 149 | SecCoreData.TemporaryRamBase = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)\r |
150 | SecCoreData.TemporaryRamSize = TemporaryRamSize;\r | |
151 | SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;\r | |
f598bf12 | 152 | SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize / 2;\r |
3222e7b1 | 153 | SecCoreData.StackBase = (VOID *)ALIGN_VALUE((UINTN)(SecCoreData.TemporaryRamBase) + SecCoreData.PeiTemporaryRamSize, 0x4);\r |
154 | SecCoreData.StackSize = (TemporaryRamBase + TemporaryRamSize) - (UINTN)SecCoreData.StackBase;\r | |
1d5d0ae9 | 155 | \r |
f598bf12 | 156 | // Jump to PEI core entry point\r |
6f711615 | 157 | PeiCoreEntryPoint (&SecCoreData, PpiList);\r |
1d5d0ae9 | 158 | }\r |