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1d5d0ae9 | 1 | /** @file\r |
2 | *\r | |
3222e7b1 | 3 | * Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r |
1d5d0ae9 | 4 | *\r |
5 | * This program and the accompanying materials\r | |
6 | * are licensed and made available under the terms and conditions of the BSD License\r | |
7 | * which accompanies this distribution. The full text of the license may be found at\r | |
8 | * http://opensource.org/licenses/bsd-license.php\r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | *\r | |
13 | **/\r | |
14 | \r | |
f598bf12 | 15 | #include "PrePeiCore.h"\r |
16 | \r | |
1d5d0ae9 | 17 | VOID\r |
18 | EFIAPI\r | |
f598bf12 | 19 | SecondaryMain (\r |
0787bc61 | 20 | IN UINTN MpId\r |
f598bf12 | 21 | )\r |
1d5d0ae9 | 22 | {\r |
f598bf12 | 23 | ASSERT(FALSE);\r |
1d5d0ae9 | 24 | }\r |
25 | \r | |
f598bf12 | 26 | VOID\r |
27 | EFIAPI\r | |
28 | PrimaryMain (\r | |
1d5d0ae9 | 29 | IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint\r |
30 | )\r | |
31 | {\r | |
f598bf12 | 32 | EFI_SEC_PEI_HAND_OFF SecCoreData;\r |
77de7e53 | 33 | UINTN PpiListSize;\r |
34 | EFI_PEI_PPI_DESCRIPTOR *PpiList;\r | |
35 | UINTN TemporaryRamBase;\r | |
36 | UINTN TemporaryRamSize;\r | |
f598bf12 | 37 | \r |
77de7e53 | 38 | CreatePpiList (&PpiListSize, &PpiList);\r |
39 | \r | |
40 | // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at\r | |
41 | // the base of the primary core stack\r | |
7945b29c | 42 | PpiListSize = ALIGN_VALUE(PpiListSize, CPU_STACK_ALIGNMENT);\r |
bb5420bb | 43 | TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize;\r |
77de7e53 | 44 | TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;\r |
f598bf12 | 45 | \r |
46 | //\r | |
47 | // Bind this information into the SEC hand-off state\r | |
48 | // Note: this must be in sync with the stuff in the asm file\r | |
49 | // Note also: HOBs (pei temp ram) MUST be above stack\r | |
50 | //\r | |
51 | SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);\r | |
bb5420bb | 52 | SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64 (PcdFvBaseAddress);\r |
f92b93c9 | 53 | SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);\r |
77de7e53 | 54 | SecCoreData.TemporaryRamBase = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)\r |
55 | SecCoreData.TemporaryRamSize = TemporaryRamSize;\r | |
56 | SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;\r | |
7945b29c | 57 | SecCoreData.PeiTemporaryRamSize = ALIGN_VALUE (SecCoreData.TemporaryRamSize / 2, CPU_STACK_ALIGNMENT);\r |
bc299a9f | 58 | SecCoreData.StackBase = (VOID *)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize);\r |
3222e7b1 | 59 | SecCoreData.StackSize = (TemporaryRamBase + TemporaryRamSize) - (UINTN)SecCoreData.StackBase;\r |
f598bf12 | 60 | \r |
77de7e53 | 61 | // Jump to PEI core entry point\r |
62 | (PeiCoreEntryPoint)(&SecCoreData, PpiList);\r | |
1d5d0ae9 | 63 | }\r |