ArmPlatformPkg/PrePeiCore: permit entry with the MMU enabled

[mirror_edk2.git] / ArmPlatformPkg / PrePeiCore / PrePeiCore.c

/** @file\r
  Main file supporting the transition to PEI Core in Normal World for Versatile Express\r
\r
  Copyright (c) 2011 - 2022, ARM Limited. All rights reserved.\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include <Library/BaseLib.h>\r
#include <Library/CacheMaintenanceLib.h>\r
#include <Library/DebugAgentLib.h>\r
#include <Library/ArmLib.h>\r
\r
#include "PrePeiCore.h"\r
\r
CONST EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI  mTemporaryRamSupportPpi = { PrePeiCoreTemporaryRamSupport };\r
\r
CONST EFI_PEI_PPI_DESCRIPTOR  gCommonPpiTable[] = {\r
  {\r
    EFI_PEI_PPI_DESCRIPTOR_PPI,\r
    &gEfiTemporaryRamSupportPpiGuid,\r
    (VOID *)&mTemporaryRamSupportPpi\r
  }\r
};\r
\r
VOID\r
CreatePpiList (\r
  OUT UINTN                   *PpiListSize,\r
  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList\r
  )\r
{\r
  EFI_PEI_PPI_DESCRIPTOR  *PlatformPpiList;\r
  UINTN                   PlatformPpiListSize;\r
  UINTN                   ListBase;\r
  EFI_PEI_PPI_DESCRIPTOR  *LastPpi;\r
\r
  // Get the Platform PPIs\r
  PlatformPpiListSize = 0;\r
  ArmPlatformGetPlatformPpiList (&PlatformPpiListSize, &PlatformPpiList);\r
\r
  // Copy the Common and Platform PPis in Temporary Memory\r
  ListBase = PcdGet64 (PcdCPUCoresStackBase);\r
  CopyMem ((VOID *)ListBase, gCommonPpiTable, sizeof (gCommonPpiTable));\r
  CopyMem ((VOID *)(ListBase + sizeof (gCommonPpiTable)), PlatformPpiList, PlatformPpiListSize);\r
\r
  // Set the Terminate flag on the last PPI entry\r
  LastPpi         = (EFI_PEI_PPI_DESCRIPTOR *)ListBase + ((sizeof (gCommonPpiTable) + PlatformPpiListSize) / sizeof (EFI_PEI_PPI_DESCRIPTOR)) - 1;\r
  LastPpi->Flags |= EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;\r
\r
  *PpiList     = (EFI_PEI_PPI_DESCRIPTOR *)ListBase;\r
  *PpiListSize = sizeof (gCommonPpiTable) + PlatformPpiListSize;\r
}\r
\r
VOID\r
CEntryPoint (\r
  IN  UINTN                     MpId,\r
  IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint\r
  )\r
{\r
  if (!ArmMmuEnabled ()) {\r
    // Data Cache enabled on Primary core when MMU is enabled.\r
    ArmDisableDataCache ();\r
    // Invalidate instruction cache\r
    ArmInvalidateInstructionCache ();\r
    // Enable Instruction Caches on all cores.\r
    ArmEnableInstructionCache ();\r
\r
    InvalidateDataCacheRange (\r
      (VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase),\r
      PcdGet32 (PcdCPUCorePrimaryStackSize)\r
      );\r
  }\r
\r
  //\r
  // Note: Doesn't have to Enable CPU interface in non-secure world,\r
  // as Non-secure interface is already enabled in Secure world.\r
  //\r
\r
  // Write VBAR - The Exception Vector table must be aligned to its requirement\r
  // Note: The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure\r
  // 'Align=4K' is defined into your FDF for this module.\r
  ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);\r
  ArmWriteVBar ((UINTN)PeiVectorTable);\r
\r
  // Enable Floating Point\r
  if (FixedPcdGet32 (PcdVFPEnabled)) {\r
    ArmEnableVFP ();\r
  }\r
\r
  // Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.\r
\r
  // If not primary Jump to Secondary Main\r
  if (ArmPlatformIsPrimaryCore (MpId)) {\r
    // Invoke "ProcessLibraryConstructorList" to have all library constructors\r
    // called.\r
    ProcessLibraryConstructorList ();\r
\r
    // Initialize the Debug Agent for Source Level Debugging\r
    InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);\r
    SaveAndSetDebugTimerInterrupt (TRUE);\r
\r
    // Initialize the platform specific controllers\r
    ArmPlatformInitialize (MpId);\r
\r
    // Goto primary Main.\r
    PrimaryMain (PeiCoreEntryPoint);\r
  } else {\r
    SecondaryMain (MpId);\r
  }\r
\r
  // PEI Core should always load and never return\r
  ASSERT (FALSE);\r
}\r
\r
EFI_STATUS\r
EFIAPI\r
PrePeiCoreTemporaryRamSupport (\r
  IN CONST EFI_PEI_SERVICES  **PeiServices,\r
  IN EFI_PHYSICAL_ADDRESS    TemporaryMemoryBase,\r
  IN EFI_PHYSICAL_ADDRESS    PermanentMemoryBase,\r
  IN UINTN                   CopySize\r
  )\r
{\r
  VOID   *OldHeap;\r
  VOID   *NewHeap;\r
  VOID   *OldStack;\r
  VOID   *NewStack;\r
  UINTN  HeapSize;\r
\r
  HeapSize = ALIGN_VALUE (CopySize / 2, CPU_STACK_ALIGNMENT);\r
\r
  OldHeap = (VOID *)(UINTN)TemporaryMemoryBase;\r
  NewHeap = (VOID *)((UINTN)PermanentMemoryBase + (CopySize - HeapSize));\r
\r
  OldStack = (VOID *)((UINTN)TemporaryMemoryBase + HeapSize);\r
  NewStack = (VOID *)(UINTN)PermanentMemoryBase;\r
\r
  //\r
  // Migrate the temporary memory stack to permanent memory stack.\r
  //\r
  CopyMem (NewStack, OldStack, CopySize - HeapSize);\r
\r
  //\r
  // Migrate the temporary memory heap to permanent memory heap.\r
  //\r
  CopyMem (NewHeap, OldHeap, HeapSize);\r
\r
  SecSwitchStack ((UINTN)NewStack - (UINTN)OldStack);\r
\r
  return EFI_SUCCESS;\r
}\r