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11c20f4e | 1 | //\r |
2 | // Copyright (c) 2011, ARM Limited. All rights reserved.\r | |
3 | // \r | |
4 | // This program and the accompanying materials \r | |
5 | // are licensed and made available under the terms and conditions of the BSD License \r | |
6 | // which accompanies this distribution. The full text of the license may be found at \r | |
7 | // http://opensource.org/licenses/bsd-license.php \r | |
8 | //\r | |
9 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
10 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
11 | //\r | |
12 | //\r | |
13 | \r | |
14 | #include <AsmMacroIoLib.h>\r | |
15 | #include <Base.h>\r | |
16 | #include <Library/PcdLib.h>\r | |
17 | #include <AutoGen.h>\r | |
18 | \r | |
19 | .text\r | |
20 | .align 3\r | |
21 | \r | |
11c20f4e | 22 | GCC_ASM_IMPORT(CEntryPoint)\r |
0787bc61 | 23 | GCC_ASM_IMPORT(ArmReadMpidr)\r |
11c20f4e | 24 | GCC_ASM_EXPORT(_ModuleEntryPoint)\r |
25 | \r | |
0787bc61 | 26 | StartupAddr: .word CEntryPoint\r |
11c20f4e | 27 | \r |
28 | ASM_PFX(_ModuleEntryPoint):\r | |
2dbcb8f0 | 29 | // Identify CPU ID\r |
0787bc61 | 30 | bl ASM_PFX(ArmReadMpidr)\r |
31 | // Get ID of this CPU in Multicore system\r | |
32 | LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r | |
1377db63 | 33 | and r5, r0, r1\r |
34 | \r | |
35 | // Get the top of the primary stacks (and the base of the secondary stacks)\r | |
2dbcb8f0 | 36 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoresStackBase), r1)\r |
37 | LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)\r | |
1377db63 | 38 | add r1, r1, r2\r |
2dbcb8f0 | 39 | \r |
40 | // Is it the Primary Core ?\r | |
1377db63 | 41 | LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3)\r |
42 | cmp r5, r3\r | |
2dbcb8f0 | 43 | beq _SetupPrimaryCoreStack\r |
44 | \r | |
45 | _SetupSecondaryCoreStack:\r | |
1377db63 | 46 | // r1 contains the base of the secondary stacks\r |
2dbcb8f0 | 47 | \r |
1377db63 | 48 | // Get the Core Position (ClusterId * 4) + CoreId\r |
a32dae48 | 49 | GetCorePositionFromMpId(r0, r5, r2)\r |
2dbcb8f0 | 50 | // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r |
1377db63 | 51 | add r0, r0, #1\r |
2dbcb8f0 | 52 | \r |
2dbcb8f0 | 53 | // StackOffset = CorePos * StackSize\r |
1377db63 | 54 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r2)\r |
55 | mul r0, r0, r2\r | |
2dbcb8f0 | 56 | // SP = StackBase + StackOffset\r |
1377db63 | 57 | add sp, r1, r0\r |
11c20f4e | 58 | \r |
59 | _PrepareArguments:\r | |
2dbcb8f0 | 60 | // The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector\r |
f92b93c9 | 61 | LoadConstantToReg (FixedPcdGet32(PcdFvBaseAddress), r2)\r |
11c20f4e | 62 | add r2, r2, #4\r |
63 | ldr r1, [r2]\r | |
64 | \r | |
1377db63 | 65 | // Move sec startup address into a data register\r |
66 | // Ensure we're jumping to FV version of the code (not boot remapped alias)\r | |
67 | ldr r3, StartupAddr\r | |
68 | \r | |
69 | // Jump to PrePeiCore C code\r | |
2dbcb8f0 | 70 | // r0 = mp_id\r |
71 | // r1 = pei_core_address\r | |
1377db63 | 72 | mov r0, r5\r |
73 | blx r3\r | |
74 | \r | |
75 | _SetupPrimaryCoreStack:\r | |
76 | // r1 contains the top of the primary stack\r | |
77 | LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), r2)\r | |
78 | \r | |
79 | // The reserved space for global variable must be 8-bytes aligned for pushing\r | |
80 | // 64-bit variable on the stack\r | |
81 | SetPrimaryStack (r1, r2, r3)\r | |
82 | b _PrepareArguments\r | |
2dbcb8f0 | 83 | \r |
84 | _NeverReturn:\r | |
85 | b _NeverReturn\r |