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cd872e40 | 1 | //\r |
5dbacdb2 | 2 | // Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r |
cd872e40 | 3 | //\r |
4 | // This program and the accompanying materials\r | |
5 | // are licensed and made available under the terms and conditions of the BSD License\r | |
6 | // which accompanies this distribution. The full text of the license may be found at\r | |
7 | // http://opensource.org/licenses/bsd-license.php\r | |
8 | //\r | |
9 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
10 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
11 | //\r | |
12 | //\r | |
13 | \r | |
14 | #include <AsmMacroIoLib.h>\r | |
15 | #include <Base.h>\r | |
16 | #include <Library/PcdLib.h>\r | |
17 | #include <AutoGen.h>\r | |
18 | \r | |
063ad84e | 19 | #include <Chipset/ArmV7.h>\r |
20 | \r | |
cd872e40 | 21 | INCLUDE AsmMacroIoLib.inc\r |
3402aac7 | 22 | \r |
cd872e40 | 23 | IMPORT CEntryPoint\r |
bebda7ce | 24 | IMPORT ArmPlatformIsPrimaryCore\r |
0787bc61 | 25 | IMPORT ArmReadMpidr\r |
b5a57223 | 26 | IMPORT ArmPlatformPeiBootAction\r |
695df8ba | 27 | IMPORT ArmPlatformStackSet\r |
3402aac7 | 28 | \r |
cd872e40 | 29 | EXPORT _ModuleEntryPoint\r |
5dbacdb2 | 30 | EXPORT mSystemMemoryEnd\r |
cd872e40 | 31 | \r |
32 | PRESERVE8\r | |
33 | AREA PrePiCoreEntryPoint, CODE, READONLY\r | |
3402aac7 | 34 | \r |
cd872e40 | 35 | StartupAddr DCD CEntryPoint\r |
5dbacdb2 | 36 | mSystemMemoryEnd DCQ 0\r |
cd872e40 | 37 | \r |
38 | _ModuleEntryPoint\r | |
b5a57223 | 39 | // Do early platform specific actions\r |
40 | bl ArmPlatformPeiBootAction\r | |
41 | \r | |
0787bc61 | 42 | // Get ID of this CPU in Multicore system\r |
43 | bl ArmReadMpidr\r | |
bebda7ce | 44 | // Keep a copy of the MpId register value\r |
c2d87a49 | 45 | mov r8, r0\r |
cd872e40 | 46 | \r |
d269095b | 47 | _SetSVCMode\r |
99565b88 | 48 | // Enter SVC mode, Disable FIQ and IRQ\r |
063ad84e | 49 | mov r1, #(CPSR_MODE_SVC :OR: CPSR_IRQ :OR: CPSR_FIQ)\r |
d269095b | 50 | msr CPSR_c, r1\r |
51 | \r | |
2dbcb8f0 | 52 | // Check if we can install the stack at the top of the System Memory or if we need\r |
d269095b | 53 | // to install the stacks at the bottom of the Firmware Device (case the FD is located\r |
54 | // at the top of the DRAM)\r | |
5dbacdb2 OM |
55 | _SystemMemoryEndInit\r |
56 | ldr r1, mSystemMemoryEnd\r | |
57 | \r | |
58 | // Is mSystemMemoryEnd initialized?\r | |
59 | cmp r1, #0\r | |
60 | bne _SetupStackPosition\r | |
61 | \r | |
62 | LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryBase), r1)\r | |
63 | LoadConstantToReg (FixedPcdGet32(PcdSystemMemorySize), r2)\r | |
2569b068 | 64 | sub r2, r2, #1\r |
5dbacdb2 OM |
65 | add r1, r1, r2\r |
66 | // Update the global variable\r | |
67 | adr r2, mSystemMemoryEnd\r | |
68 | str r1, [r2]\r | |
69 | \r | |
70 | _SetupStackPosition\r | |
71 | // r1 = SystemMemoryTop\r | |
cd872e40 | 72 | \r |
d269095b | 73 | // Calculate Top of the Firmware Device\r |
f92b93c9 | 74 | LoadConstantToReg (FixedPcdGet32(PcdFdBaseAddress), r2)\r |
75 | LoadConstantToReg (FixedPcdGet32(PcdFdSize), r3)\r | |
2569b068 | 76 | sub r3, r3, #1\r |
7defe7b3 | 77 | add r3, r3, r2 // r3 = FdTop = PcdFdBaseAddress + PcdFdSize\r |
d269095b | 78 | \r |
79 | // UEFI Memory Size (stacks are allocated in this region)\r | |
80 | LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryUefiRegionSize), r4)\r | |
81 | \r | |
82 | //\r | |
83 | // Reserve the memory for the UEFI region (contain stacks on its top)\r | |
84 | //\r | |
85 | \r | |
86 | // Calculate how much space there is between the top of the Firmware and the Top of the System Memory\r | |
91c38d4e RC |
87 | subs r0, r1, r3 // r0 = SystemMemoryTop - FdTop\r |
88 | bmi _SetupStack // Jump if negative (FdTop > SystemMemoryTop). Case when the PrePi is in XIP memory outside of the DRAM\r | |
89 | cmp r0, r4\r | |
90 | bge _SetupStack\r | |
d269095b | 91 | \r |
92 | // Case the top of stacks is the FdBaseAddress\r | |
91c38d4e | 93 | mov r1, r2\r |
cd872e40 | 94 | \r |
95 | _SetupStack\r | |
2dbcb8f0 | 96 | // r1 contains the top of the stack (and the UEFI Memory)\r |
d269095b | 97 | \r |
2569b068 | 98 | // Because the 'push' instruction is equivalent to 'stmdb' (decrement before), we need to increment\r |
99 | // one to the top of the stack. We check if incrementing one does not overflow (case of DRAM at the\r | |
100 | // top of the memory space)\r | |
c2d87a49 | 101 | adds r9, r1, #1\r |
2569b068 | 102 | bcs _SetupOverflowStack\r |
103 | \r | |
104 | _SetupAlignedStack\r | |
c2d87a49 | 105 | mov r1, r9\r |
2569b068 | 106 | b _GetBaseUefiMemory\r |
107 | \r | |
108 | _SetupOverflowStack\r | |
109 | // Case memory at the top of the address space. Ensure the top of the stack is EFI_PAGE_SIZE\r | |
110 | // aligned (4KB)\r | |
c2d87a49 OM |
111 | LoadConstantToReg (EFI_PAGE_MASK, r9)\r |
112 | and r9, r9, r1\r | |
113 | sub r1, r1, r9\r | |
2569b068 | 114 | \r |
115 | _GetBaseUefiMemory\r | |
d269095b | 116 | // Calculate the Base of the UEFI Memory\r |
c2d87a49 | 117 | sub r9, r1, r4\r |
cd872e40 | 118 | \r |
2dbcb8f0 | 119 | _GetStackBase\r |
1377db63 | 120 | // r1 = The top of the Mpcore Stacks\r |
2dbcb8f0 | 121 | // Stack for the primary core = PrimaryCoreStack\r |
122 | LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)\r | |
c2d87a49 | 123 | sub r10, r1, r2\r |
695df8ba | 124 | \r |
125 | // Stack for the secondary core = Number of Cores - 1\r | |
126 | LoadConstantToReg (FixedPcdGet32(PcdCoreCount), r0)\r | |
91c38d4e | 127 | sub r0, r0, #1\r |
695df8ba | 128 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r1)\r |
129 | mul r1, r1, r0\r | |
c2d87a49 | 130 | sub r10, r10, r1\r |
695df8ba | 131 | \r |
c2d87a49 | 132 | // r10 = The base of the MpCore Stacks (primary stack & secondary stacks)\r |
91c38d4e RC |
133 | mov r0, r10\r |
134 | mov r1, r8\r | |
695df8ba | 135 | //ArmPlatformStackSet(StackBase, MpId, PrimaryStackSize, SecondaryStackSize)\r |
136 | LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)\r | |
2dbcb8f0 | 137 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r3)\r |
91c38d4e | 138 | bl ArmPlatformStackSet\r |
2dbcb8f0 | 139 | \r |
140 | // Is it the Primary Core ?\r | |
c2d87a49 | 141 | mov r0, r8\r |
bebda7ce | 142 | bl ArmPlatformIsPrimaryCore\r |
143 | cmp r0, #1\r | |
cd872e40 | 144 | bne _PrepareArguments\r |
145 | \r | |
cd872e40 | 146 | _PrepareArguments\r |
c2d87a49 OM |
147 | mov r0, r8\r |
148 | mov r1, r9\r | |
149 | mov r2, r10\r | |
c524ffbb | 150 | \r |
cd872e40 | 151 | // Move sec startup address into a data register\r |
152 | // Ensure we're jumping to FV version of the code (not boot remapped alias)\r | |
c524ffbb | 153 | ldr r4, StartupAddr\r |
cd872e40 | 154 | \r |
d269095b | 155 | // Jump to PrePiCore C code\r |
0787bc61 | 156 | // r0 = MpId\r |
cd872e40 | 157 | // r1 = UefiMemoryBase\r |
c524ffbb | 158 | // r2 = StacksBase\r |
c524ffbb | 159 | blx r4\r |
cd872e40 | 160 | \r |
2dbcb8f0 | 161 | _NeverReturn\r |
162 | b _NeverReturn\r | |
163 | \r | |
cd872e40 | 164 | END\r |