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2dbcb8f0 | 1 | //\r |
2 | // Copyright (c) 2011, ARM Limited. All rights reserved.\r | |
3 | // \r | |
4 | // This program and the accompanying materials \r | |
5 | // are licensed and made available under the terms and conditions of the BSD License \r | |
6 | // which accompanies this distribution. The full text of the license may be found at \r | |
7 | // http://opensource.org/licenses/bsd-license.php \r | |
8 | //\r | |
9 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
10 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
11 | //\r | |
12 | //\r | |
11c20f4e | 13 | \r |
2dbcb8f0 | 14 | #include <AutoGen.h>\r |
11c20f4e | 15 | #include <AsmMacroIoLib.h>\r |
90d6a1bb | 16 | #include "SecInternal.h"\r |
11c20f4e | 17 | \r |
11c20f4e | 18 | .text\r |
19 | .align 3\r | |
20 | \r | |
11c20f4e | 21 | GCC_ASM_IMPORT(CEntryPoint)\r |
44e272fd | 22 | GCC_ASM_IMPORT(ArmPlatformSecBootAction)\r |
11c20f4e | 23 | GCC_ASM_IMPORT(ArmPlatformInitializeBootMemory)\r |
24 | GCC_ASM_IMPORT(ArmDisableInterrupts)\r | |
25 | GCC_ASM_IMPORT(ArmDisableCachesAndMmu)\r | |
26 | GCC_ASM_IMPORT(ArmWriteVBar)\r | |
0787bc61 | 27 | GCC_ASM_IMPORT(ArmReadMpidr)\r |
11c20f4e | 28 | GCC_ASM_IMPORT(SecVectorTable)\r |
90d6a1bb | 29 | GCC_ASM_IMPORT(ArmCpuSynchronizeWait)\r |
30 | GCC_ASM_EXPORT(_ModuleEntryPoint)\r | |
11c20f4e | 31 | \r |
2dbcb8f0 | 32 | StartupAddr: .word ASM_PFX(CEntryPoint)\r |
11c20f4e | 33 | \r |
34 | ASM_PFX(_ModuleEntryPoint):\r | |
2dbcb8f0 | 35 | // First ensure all interrupts are disabled\r |
36 | bl ASM_PFX(ArmDisableInterrupts)\r | |
11c20f4e | 37 | \r |
2dbcb8f0 | 38 | // Ensure that the MMU and caches are off\r |
39 | bl ASM_PFX(ArmDisableCachesAndMmu)\r | |
11c20f4e | 40 | \r |
2dbcb8f0 | 41 | // Jump to Platform Specific Boot Action function\r |
44e272fd | 42 | blx ASM_PFX(ArmPlatformSecBootAction)\r |
43 | \r | |
2dbcb8f0 | 44 | // Set VBAR to the start of the exception vectors in Secure Mode\r |
89bbce11 | 45 | LoadConstantToReg (ASM_PFX(SecVectorTable), r0)\r |
44e272fd | 46 | bl ASM_PFX(ArmWriteVBar)\r |
47 | \r | |
2dbcb8f0 | 48 | _IdentifyCpu:\r |
49 | // Identify CPU ID\r | |
11c20f4e | 50 | bl ASM_PFX(ArmReadMpidr)\r |
0787bc61 | 51 | // Get ID of this CPU in Multicore system\r |
52 | LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r | |
53 | and r5, r0, r1\r | |
11c20f4e | 54 | \r |
2dbcb8f0 | 55 | // Is it the Primary Core ?\r |
0787bc61 | 56 | LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r1)\r |
57 | cmp r5, r1\r | |
2dbcb8f0 | 58 | // Only the primary core initialize the memory (SMC)\r |
11c20f4e | 59 | beq _InitMem\r |
60 | \r | |
90d6a1bb | 61 | _WaitInitMem:\r |
62 | mov r0, #ARM_CPU_EVENT_BOOT_MEM_INIT\r | |
63 | bl ASM_PFX(ArmCpuSynchronizeWait)\r | |
64 | // Now the Init Mem is initialized, we setup the secondary core stacks\r | |
2dbcb8f0 | 65 | b _SetupSecondaryCoreStack\r |
11c20f4e | 66 | \r |
67 | _InitMem:\r | |
f156d5b4 | 68 | // Initialize Init Boot Memory\r |
11c20f4e | 69 | bl ASM_PFX(ArmPlatformInitializeBootMemory)\r |
2dbcb8f0 | 70 | \r |
71 | // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)\r | |
72 | LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)\r | |
73 | \r | |
74 | _SetupPrimaryCoreStack:\r | |
75 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r2)\r | |
76 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r3)\r | |
77 | // Calculate the Top of the Stack\r | |
78 | add r2, r2, r3\r | |
79 | LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r3)\r | |
80 | \r | |
81 | // The reserved space for global variable must be 8-bytes aligned for pushing\r | |
82 | // 64-bit variable on the stack\r | |
83 | SetPrimaryStack (r2, r3, r1)\r | |
84 | \r | |
85 | // Set all the SEC global variables to 0\r | |
86 | mov r3, sp\r | |
87 | mov r1, #0x0\r | |
88 | _InitGlobals:\r | |
89 | str r1, [r3], #4\r | |
90 | cmp r3, r2\r | |
031f52ce | 91 | bne _InitGlobals\r |
2dbcb8f0 | 92 | \r |
93 | b _PrepareArguments\r | |
94 | \r | |
95 | _SetupSecondaryCoreStack:\r | |
96 | // Get the Core Position (ClusterId * 4) + CoreId\r | |
97 | GetCorePositionInStack(r0, r5, r1)\r | |
98 | // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r | |
99 | add r0, r0, #1\r | |
100 | \r | |
101 | // Get the base of the stack for the secondary cores\r | |
11c20f4e | 102 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r |
90d6a1bb | 103 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)\r |
2dbcb8f0 | 104 | add r1, r1, r2\r |
11c20f4e | 105 | \r |
2dbcb8f0 | 106 | // StackOffset = CorePos * StackSize\r |
107 | mul r0, r0, r2\r | |
108 | // SP = StackBase + StackOffset\r | |
109 | add sp, r1, r0\r | |
11c20f4e | 110 | \r |
2dbcb8f0 | 111 | \r |
112 | _PrepareArguments:\r | |
113 | // Move sec startup address into a data register\r | |
114 | // Ensure we're jumping to FV version of the code (not boot remapped alias)\r | |
11c20f4e | 115 | ldr r3, StartupAddr\r |
116 | \r | |
2dbcb8f0 | 117 | // Jump to SEC C code\r |
118 | // r0 = mp_id\r | |
11c20f4e | 119 | mov r0, r5\r |
2dbcb8f0 | 120 | blx r3\r |
121 | \r | |
122 | _NeverReturn:\r | |
123 | b _NeverReturn\r |