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2dbcb8f0 | 1 | //\r |
1377db63 | 2 | // Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r |
2dbcb8f0 | 3 | // \r |
4 | // This program and the accompanying materials \r | |
5 | // are licensed and made available under the terms and conditions of the BSD License \r | |
6 | // which accompanies this distribution. The full text of the license may be found at \r | |
7 | // http://opensource.org/licenses/bsd-license.php \r | |
8 | //\r | |
9 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
10 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
11 | //\r | |
12 | //\r | |
11c20f4e | 13 | \r |
2dbcb8f0 | 14 | #include <AutoGen.h>\r |
11c20f4e | 15 | #include <AsmMacroIoLib.h>\r |
90d6a1bb | 16 | #include "SecInternal.h"\r |
11c20f4e | 17 | \r |
11c20f4e | 18 | .text\r |
19 | .align 3\r | |
20 | \r | |
11c20f4e | 21 | GCC_ASM_IMPORT(CEntryPoint)\r |
44e272fd | 22 | GCC_ASM_IMPORT(ArmPlatformSecBootAction)\r |
e314d564 | 23 | GCC_ASM_IMPORT(ArmPlatformSecBootMemoryInit)\r |
11c20f4e | 24 | GCC_ASM_IMPORT(ArmDisableInterrupts)\r |
25 | GCC_ASM_IMPORT(ArmDisableCachesAndMmu)\r | |
26 | GCC_ASM_IMPORT(ArmWriteVBar)\r | |
0787bc61 | 27 | GCC_ASM_IMPORT(ArmReadMpidr)\r |
11c20f4e | 28 | GCC_ASM_IMPORT(SecVectorTable)\r |
b1d41be7 | 29 | GCC_ASM_IMPORT(ArmCallWFE)\r |
90d6a1bb | 30 | GCC_ASM_EXPORT(_ModuleEntryPoint)\r |
11c20f4e | 31 | \r |
2dbcb8f0 | 32 | StartupAddr: .word ASM_PFX(CEntryPoint)\r |
11c20f4e | 33 | \r |
34 | ASM_PFX(_ModuleEntryPoint):\r | |
2dbcb8f0 | 35 | // First ensure all interrupts are disabled\r |
36 | bl ASM_PFX(ArmDisableInterrupts)\r | |
11c20f4e | 37 | \r |
2dbcb8f0 | 38 | // Ensure that the MMU and caches are off\r |
39 | bl ASM_PFX(ArmDisableCachesAndMmu)\r | |
11c20f4e | 40 | \r |
a75568e9 | 41 | // By default, we are doing a cold boot\r |
42 | mov r10, #ARM_SEC_COLD_BOOT\r | |
43 | \r | |
2dbcb8f0 | 44 | // Jump to Platform Specific Boot Action function\r |
44e272fd | 45 | blx ASM_PFX(ArmPlatformSecBootAction)\r |
46 | \r | |
2dbcb8f0 | 47 | // Set VBAR to the start of the exception vectors in Secure Mode\r |
89bbce11 | 48 | LoadConstantToReg (ASM_PFX(SecVectorTable), r0)\r |
44e272fd | 49 | bl ASM_PFX(ArmWriteVBar)\r |
50 | \r | |
2dbcb8f0 | 51 | _IdentifyCpu:\r |
52 | // Identify CPU ID\r | |
11c20f4e | 53 | bl ASM_PFX(ArmReadMpidr)\r |
0787bc61 | 54 | // Get ID of this CPU in Multicore system\r |
55 | LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r | |
56 | and r5, r0, r1\r | |
11c20f4e | 57 | \r |
2dbcb8f0 | 58 | // Is it the Primary Core ?\r |
1377db63 | 59 | LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3)\r |
60 | cmp r5, r3\r | |
2dbcb8f0 | 61 | // Only the primary core initialize the memory (SMC)\r |
11c20f4e | 62 | beq _InitMem\r |
63 | \r | |
90d6a1bb | 64 | _WaitInitMem:\r |
a75568e9 | 65 | // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r |
66 | // Otherwise we have to wait the Primary Core to finish the initialization\r | |
67 | cmp r10, #ARM_SEC_COLD_BOOT\r | |
68 | bne _SetupSecondaryCoreStack\r | |
69 | \r | |
b1d41be7 | 70 | // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)\r |
71 | bl ASM_PFX(ArmCallWFE)\r | |
90d6a1bb | 72 | // Now the Init Mem is initialized, we setup the secondary core stacks\r |
2dbcb8f0 | 73 | b _SetupSecondaryCoreStack\r |
11c20f4e | 74 | \r |
75 | _InitMem:\r | |
8cfd2e24 | 76 | // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r |
77 | cmp r10, #ARM_SEC_COLD_BOOT\r | |
78 | bne _SetupPrimaryCoreStack\r | |
79 | \r | |
f156d5b4 | 80 | // Initialize Init Boot Memory\r |
e314d564 | 81 | bl ASM_PFX(ArmPlatformSecBootMemoryInit)\r |
2dbcb8f0 | 82 | \r |
83 | // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)\r | |
84 | LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)\r | |
85 | \r | |
86 | _SetupPrimaryCoreStack:\r | |
1377db63 | 87 | // Get the top of the primary stacks (and the base of the secondary stacks)\r |
88 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r | |
89 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r | |
90 | add r1, r1, r2\r | |
91 | \r | |
92 | LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r2)\r | |
2dbcb8f0 | 93 | \r |
94 | // The reserved space for global variable must be 8-bytes aligned for pushing\r | |
95 | // 64-bit variable on the stack\r | |
1377db63 | 96 | SetPrimaryStack (r1, r2, r3)\r |
97 | b _PrepareArguments\r | |
2dbcb8f0 | 98 | \r |
99 | _SetupSecondaryCoreStack:\r | |
1377db63 | 100 | // Get the top of the primary stacks (and the base of the secondary stacks)\r |
101 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r | |
102 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r | |
103 | add r1, r1, r2\r | |
104 | \r | |
2dbcb8f0 | 105 | // Get the Core Position (ClusterId * 4) + CoreId\r |
a32dae48 | 106 | GetCorePositionFromMpId(r0, r5, r2)\r |
2dbcb8f0 | 107 | // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r |
108 | add r0, r0, #1\r | |
109 | \r | |
2dbcb8f0 | 110 | // StackOffset = CorePos * StackSize\r |
1377db63 | 111 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)\r |
2dbcb8f0 | 112 | mul r0, r0, r2\r |
113 | // SP = StackBase + StackOffset\r | |
114 | add sp, r1, r0\r | |
11c20f4e | 115 | \r |
2dbcb8f0 | 116 | _PrepareArguments:\r |
117 | // Move sec startup address into a data register\r | |
118 | // Ensure we're jumping to FV version of the code (not boot remapped alias)\r | |
11c20f4e | 119 | ldr r3, StartupAddr\r |
120 | \r | |
2dbcb8f0 | 121 | // Jump to SEC C code\r |
122 | // r0 = mp_id\r | |
a75568e9 | 123 | // r1 = Boot Mode\r |
11c20f4e | 124 | mov r0, r5\r |
a75568e9 | 125 | mov r1, r10\r |
2dbcb8f0 | 126 | blx r3\r |
127 | \r | |
128 | _NeverReturn:\r | |
129 | b _NeverReturn\r |