IntelFsp2Pkg: Add FSPx_ARCH2_UPD support for X64

[mirror_edk2.git] / IntelFsp2Pkg / FspSecCore / Ia32 / FspApiEntryT.nasm

;; @file\r
;  Provide FSP API entry points.\r
;\r
; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;;\r
\r
    SECTION .text\r
\r
%include    "SaveRestoreSseNasm.inc"\r
%include    "MicrocodeLoadNasm.inc"\r
\r
;\r
; Following are fixed PCDs\r
;\r
extern   ASM_PFX(PcdGet32 (PcdTemporaryRamBase))\r
extern   ASM_PFX(PcdGet32 (PcdTemporaryRamSize))\r
extern   ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))\r
\r
;\r
; Following functions will be provided in PlatformSecLib\r
;\r
extern ASM_PFX(AsmGetFspBaseAddress)\r
extern ASM_PFX(AsmGetFspInfoHeader)\r
;extern ASM_PFX(LoadMicrocode)    ; @todo: needs a weak implementation\r
extern ASM_PFX(SecPlatformInit)   ; @todo: needs a weak implementation\r
extern ASM_PFX(SecCarInit)\r
\r
;\r
; Define the data length that we saved on the stack top\r
;\r
DATA_LEN_OF_PER0         EQU   18h\r
DATA_LEN_OF_MCUD         EQU   18h\r
DATA_LEN_AT_STACK_TOP    EQU   (DATA_LEN_OF_PER0 + DATA_LEN_OF_MCUD + 4)\r
\r
;\r
; @todo: These structures are moved from MicrocodeLoadNasm.inc to avoid\r
;        build error. This needs to be fixed later on.\r
;\r
struc MicrocodeHdr\r
    .MicrocodeHdrVersion:      resd    1\r
    .MicrocodeHdrRevision:     resd    1\r
    .MicrocodeHdrDate:         resd    1\r
    .MicrocodeHdrProcessor:    resd    1\r
    .MicrocodeHdrChecksum:     resd    1\r
    .MicrocodeHdrLoader:       resd    1\r
    .MicrocodeHdrFlags:        resd    1\r
    .MicrocodeHdrDataSize:     resd    1\r
    .MicrocodeHdrTotalSize:    resd    1\r
    .MicrocodeHdrRsvd:         resd    3\r
    .size:\r
endstruc\r
\r
struc ExtSigHdr\r
    .ExtSigHdrCount:          resd    1\r
    .ExtSigHdrChecksum:       resd    1\r
    .ExtSigHdrRsvd:           resd    3\r
    .size:\r
endstruc\r
\r
struc ExtSig\r
    .ExtSigProcessor:         resd    1\r
    .ExtSigFlags:             resd    1\r
    .ExtSigChecksum:          resd    1\r
    .size:\r
endstruc\r
\r
struc LoadMicrocodeParams\r
    ; FSP_UPD_HEADER {\r
    .FspUpdHeader:            resd    8\r
    ; }\r
    ; FSPT_CORE_UPD {\r
    .MicrocodeCodeAddr:       resd    1\r
    .MicrocodeCodeSize:       resd    1\r
    .CodeRegionBase:          resd    1\r
    .CodeRegionSize:          resd    1\r
    ; }\r
    .size:\r
endstruc\r
\r
struc LoadMicrocodeParamsFsp22\r
    ; FSP_UPD_HEADER {\r
    .FspUpdHeaderSignature:   resd    2\r
    .FspUpdHeaderRevision:    resb    1\r
    .FspUpdHeaderReserved:    resb   23\r
    ; }\r
    ; FSPT_ARCH_UPD {\r
    .FsptArchRevision:        resb    1\r
    .FsptArchReserved:        resb    3\r
    .FsptArchUpd:             resd    7\r
    ; }\r
    ; FSPT_CORE_UPD {\r
    .MicrocodeCodeAddr:       resd    1\r
    .MicrocodeCodeSize:       resd    1\r
    .CodeRegionBase:          resd    1\r
    .CodeRegionSize:          resd    1\r
    ; }\r
    .size:\r
endstruc\r
\r
struc LoadMicrocodeParamsFsp24\r
    ; FSP_UPD_HEADER {\r
    .FspUpdHeaderSignature:   resd    2\r
    .FspUpdHeaderRevision:    resb    1\r
    .FspUpdHeaderReserved:    resb   23\r
    ; }\r
    ; FSPT_ARCH2_UPD {\r
    .FsptArchRevision:        resb    1\r
    .FsptArchReserved:        resb    3\r
    .FsptArchLength:          resd    1\r
    .FspDebugHandler          resq    1\r
    .FsptArchUpd:             resd    4\r
    ; }\r
    ; FSPT_CORE_UPD {\r
    .MicrocodeCodeAddr:       resq    1\r
    .MicrocodeCodeSize:       resq    1\r
    .CodeRegionBase:          resq    1\r
    .CodeRegionSize:          resq    1\r
    ; }\r
    .size:\r
endstruc\r
\r
;\r
; Define SSE macros\r
;\r
;\r
;args 1: ReturnAddress  2:MmxRegister\r
;\r
%macro LOAD_MMX_EXT 2\r
  mov     esi, %1\r
  movd    %2, esi              ; save ReturnAddress into MMX\r
%endmacro\r
\r
;\r
;args 1: RoutineLabel  2:MmxRegister\r
;\r
%macro CALL_MMX_EXT  2\r
  mov     esi, %%ReturnAddress\r
  movd    %2, esi              ; save ReturnAddress into MMX\r
  jmp     %1\r
%%ReturnAddress:\r
%endmacro\r
\r
;\r
;arg 1:MmxRegister\r
;\r
%macro RET_ESI_EXT   1\r
  movd    esi, %1              ; move ReturnAddress from MMX to ESI\r
  jmp     esi\r
%endmacro\r
\r
;\r
;arg 1:RoutineLabel\r
;\r
%macro CALL_MMX   1\r
         CALL_MMX_EXT  %1, mm7\r
%endmacro\r
\r
%macro RET_ESI 0\r
         RET_ESI_EXT   mm7\r
%endmacro\r
\r
;\r
; @todo: The strong/weak implementation does not work.\r
;        This needs to be reviewed later.\r
;\r
;------------------------------------------------------------------------------\r
;\r
;;global ASM_PFX(SecPlatformInitDefault)\r
;ASM_PFX(SecPlatformInitDefault):\r
;   ; Inputs:\r
;   ;   mm7 -> Return address\r
;   ; Outputs:\r
;   ;   eax -> 0 - Successful, Non-zero - Failed.\r
;   ; Register Usage:\r
;   ;   eax is cleared and ebp is used for return address.\r
;   ;   All others reserved.\r
;\r
;   ; Save return address to EBP\r
;   movd  ebp, mm7\r
;\r
;   xor   eax, eax\r
;Exit1:\r
;   jmp   ebp\r
\r
;------------------------------------------------------------------------------\r
global ASM_PFX(LoadMicrocodeDefault)\r
ASM_PFX(LoadMicrocodeDefault):\r
   ; Inputs:\r
   ;   esp -> LoadMicrocodeParams pointer\r
   ; Register Usage:\r
   ;   esp  Preserved\r
   ;   All others destroyed\r
   ; Assumptions:\r
   ;   No memory available, stack is hard-coded and used for return address\r
   ;   Executed by SBSP and NBSP\r
   ;   Beginning of microcode update region starts on paragraph boundary\r
\r
   ;\r
   ; Save return address to EBP\r
   ;\r
   movd   ebp, mm7\r
\r
   cmp    esp, 0\r
   jz     ParamError\r
   mov    eax, dword [esp + 4]    ; Parameter pointer\r
   cmp    eax, 0\r
   jz     ParamError\r
   mov    esp, eax\r
\r
   ; skip loading Microcode if the MicrocodeCodeSize is zero\r
   ; and report error if size is less than 2k\r
   ; first check UPD header revision\r
   cmp    byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2\r
   jb     Fsp20UpdHeader\r
   cmp    byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2\r
   je     Fsp24UpdHeader\r
   jmp    Fsp22UpdHeader\r
\r
Fsp20UpdHeader:\r
   ; UPD structure is compliant with FSP spec 2.0/2.1\r
   mov    eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeSize]\r
   cmp    eax, 0\r
   jz     Exit2\r
   cmp    eax, 0800h\r
   jl     ParamError\r
\r
   mov    esi, dword [esp + LoadMicrocodeParams.MicrocodeCodeAddr]\r
   cmp    esi, 0\r
   jnz    CheckMainHeader\r
   jmp    ParamError\r
\r
Fsp22UpdHeader:\r
   ; UPD structure is compliant with FSP spec 2.2\r
   mov    eax, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeSize]\r
   cmp    eax, 0\r
   jz     Exit2\r
   cmp    eax, 0800h\r
   jl     ParamError\r
\r
   mov    esi, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr]\r
   cmp    esi, 0\r
   jnz    CheckMainHeader\r
   jmp    ParamError\r
\r
Fsp24UpdHeader:\r
   ; UPD structure is compliant with FSP spec 2.4\r
   mov    eax, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]\r
   cmp    eax, 0\r
   jz     Exit2\r
   cmp    eax, 0800h\r
   jl     ParamError\r
\r
   mov    esi, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]\r
   cmp    esi, 0\r
   jnz    CheckMainHeader\r
\r
ParamError:\r
   mov    eax, 080000002h\r
   jmp    Exit2\r
\r
CheckMainHeader:\r
   ; Get processor signature and platform ID from the installed processor\r
   ; and save into registers for later use\r
   ; ebx = processor signature\r
   ; edx = platform ID\r
   mov   eax, 1\r
   cpuid\r
   mov   ebx, eax\r
   mov   ecx, MSR_IA32_PLATFORM_ID\r
   rdmsr\r
   mov   ecx, edx\r
   shr   ecx, 50-32                          ; shift (50d-32d=18d=0x12) bits\r
   and   ecx, 7h                             ; platform id at bit[52..50]\r
   mov   edx, 1\r
   shl   edx, cl\r
\r
   ; Current register usage\r
   ; esp -> stack with parameters\r
   ; esi -> microcode update to check\r
   ; ebx = processor signature\r
   ; edx = platform ID\r
\r
   ; Check for valid microcode header\r
   ; Minimal test checking for header version and loader version as 1\r
   mov   eax, dword 1\r
   cmp   dword [esi + MicrocodeHdr.MicrocodeHdrVersion], eax\r
   jne   AdvanceFixedSize\r
   cmp   dword [esi + MicrocodeHdr.MicrocodeHdrLoader], eax\r
   jne   AdvanceFixedSize\r
\r
   ; Check if signature and plaform ID match\r
   cmp   ebx, dword [esi + MicrocodeHdr.MicrocodeHdrProcessor]\r
   jne   LoadMicrocodeDefault1\r
   test  edx, dword [esi + MicrocodeHdr.MicrocodeHdrFlags ]\r
   jnz   LoadCheck  ; Jif signature and platform ID match\r
\r
LoadMicrocodeDefault1:\r
   ; Check if extended header exists\r
   ; First check if MicrocodeHdrTotalSize and MicrocodeHdrDataSize are valid\r
   xor   eax, eax\r
   cmp   dword [esi + MicrocodeHdr.MicrocodeHdrTotalSize], eax\r
   je    NextMicrocode\r
   cmp   dword [esi + MicrocodeHdr.MicrocodeHdrDataSize], eax\r
   je    NextMicrocode\r
\r
   ; Then verify total size - sizeof header > data size\r
   mov   ecx, dword [esi + MicrocodeHdr.MicrocodeHdrTotalSize]\r
   sub   ecx, MicrocodeHdr.size\r
   cmp   ecx, dword [esi + MicrocodeHdr.MicrocodeHdrDataSize]\r
   jng   NextMicrocode    ; Jif extended header does not exist\r
\r
   ; Set edi -> extended header\r
   mov   edi, esi\r
   add   edi, MicrocodeHdr.size\r
   add   edi, dword [esi + MicrocodeHdr.MicrocodeHdrDataSize]\r
\r
   ; Get count of extended structures\r
   mov   ecx, dword [edi + ExtSigHdr.ExtSigHdrCount]\r
\r
   ; Move pointer to first signature structure\r
   add   edi, ExtSigHdr.size\r
\r
CheckExtSig:\r
   ; Check if extended signature and platform ID match\r
   cmp   dword [edi + ExtSig.ExtSigProcessor], ebx\r
   jne   LoadMicrocodeDefault2\r
   test  dword [edi + ExtSig.ExtSigFlags], edx\r
   jnz   LoadCheck      ; Jif signature and platform ID match\r
LoadMicrocodeDefault2:\r
   ; Check if any more extended signatures exist\r
   add   edi, ExtSig.size\r
   loop  CheckExtSig\r
\r
NextMicrocode:\r
   ; Advance just after end of this microcode\r
   xor   eax, eax\r
   cmp   dword [esi + MicrocodeHdr.MicrocodeHdrTotalSize], eax\r
   je    LoadMicrocodeDefault3\r
   add   esi, dword [esi + MicrocodeHdr.MicrocodeHdrTotalSize]\r
   jmp   CheckAddress\r
LoadMicrocodeDefault3:\r
   add   esi, dword  2048\r
   jmp   CheckAddress\r
\r
AdvanceFixedSize:\r
   ; Advance by 4X dwords\r
   add   esi, dword  1024\r
\r
CheckAddress:\r
   ; Check UPD header revision\r
   cmp   byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2\r
   jb     Fsp20UpdHeader1\r
   cmp    byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2\r
   je     Fsp24UpdHeader1;\r
   jmp    Fsp22UpdHeader1\r
\r
Fsp20UpdHeader1:\r
   ; UPD structure is compliant with FSP spec 2.0/2.1\r
   ; Is automatic size detection ?\r
   mov   eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeSize]\r
   cmp   eax, 0ffffffffh\r
   jz    LoadMicrocodeDefault4\r
\r
   ; Address >= microcode region address + microcode region size?\r
   add   eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeAddr]\r
   cmp   esi, eax\r
   jae   Done        ;Jif address is outside of microcode region\r
   jmp   CheckMainHeader\r
\r
Fsp22UpdHeader1:\r
   ; UPD structure is compliant with FSP spec 2.2\r
   ; Is automatic size detection ?\r
   mov   eax, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeSize]\r
   cmp   eax, 0ffffffffh\r
   jz    LoadMicrocodeDefault4\r
\r
   ; Address >= microcode region address + microcode region size?\r
   add   eax, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr]\r
   cmp   esi, eax\r
   jae   Done        ;Jif address is outside of microcode region\r
   jmp   CheckMainHeader\r
\r
Fsp24UpdHeader1:\r
   ; UPD structure is compliant with FSP spec 2.4\r
   ; Is automatic size detection ?\r
   mov   eax, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]\r
   cmp   eax, 0ffffffffh\r
   jz    LoadMicrocodeDefault4\r
\r
   ; Address >= microcode region address + microcode region size?\r
   add   eax, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]\r
   cmp   esi, eax\r
   jae   Done        ;Jif address is outside of microcode region\r
   jmp   CheckMainHeader\r
\r
LoadMicrocodeDefault4:\r
   ; Is valid Microcode start point ?\r
   cmp   dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0ffffffffh\r
   jz    Done\r
\r
LoadCheck:\r
   ; Get the revision of the current microcode update loaded\r
   mov   ecx, MSR_IA32_BIOS_SIGN_ID\r
   xor   eax, eax               ; Clear EAX\r
   xor   edx, edx               ; Clear EDX\r
   wrmsr                        ; Load 0 to MSR at 8Bh\r
\r
   mov   eax, 1\r
   cpuid\r
   mov   ecx, MSR_IA32_BIOS_SIGN_ID\r
   rdmsr                        ; Get current microcode signature\r
\r
   ; Verify this microcode update is not already loaded\r
   cmp   dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx\r
   je    Continue\r
\r
LoadMicrocode:\r
   ; EAX contains the linear address of the start of the Update Data\r
   ; EDX contains zero\r
   ; ECX contains 79h (IA32_BIOS_UPDT_TRIG)\r
   ; Start microcode load with wrmsr\r
   mov   eax, esi\r
   add   eax, MicrocodeHdr.size\r
   xor   edx, edx\r
   mov   ecx, MSR_IA32_BIOS_UPDT_TRIG\r
   wrmsr\r
   mov   eax, 1\r
   cpuid\r
\r
Continue:\r
   jmp   NextMicrocode\r
\r
Done:\r
   mov   eax, 1\r
   cpuid\r
   mov   ecx, MSR_IA32_BIOS_SIGN_ID\r
   rdmsr                         ; Get current microcode signature\r
   xor   eax, eax\r
   cmp   edx, 0\r
   jnz   Exit2\r
   mov   eax, 08000000Eh\r
\r
Exit2:\r
   jmp   ebp\r
\r
\r
global ASM_PFX(EstablishStackFsp)\r
ASM_PFX(EstablishStackFsp):\r
  ;\r
  ; Save parameter pointer in edx\r
  ;\r
  mov       edx, dword [esp + 4]\r
\r
  ;\r
  ; Enable FSP STACK\r
  ;\r
  mov       esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]\r
  add       esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))]\r
\r
  push      DATA_LEN_OF_MCUD     ; Size of the data region\r
  push      4455434Dh            ; Signature of the  data region 'MCUD'\r
\r
  ; check UPD structure revision (edx + 8)\r
  cmp       byte [edx + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2\r
  jb        Fsp20UpdHeader2\r
  cmp       byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2\r
  je        Fsp24UpdHeader2\r
  jmp       Fsp22UpdHeader2\r
\r
Fsp20UpdHeader2:\r
  ; UPD structure is compliant with FSP spec 2.0/2.1\r
  push      dword [edx + LoadMicrocodeParams.CodeRegionSize]     ; Code size       sizeof(FSPT_UPD_COMMON) + 12\r
  push      dword [edx + LoadMicrocodeParams.CodeRegionBase]     ; Code base       sizeof(FSPT_UPD_COMMON) + 8\r
  push      dword [edx + LoadMicrocodeParams.MicrocodeCodeSize]  ; Microcode size  sizeof(FSPT_UPD_COMMON) + 4\r
  push      dword [edx + LoadMicrocodeParams.MicrocodeCodeAddr]  ; Microcode base  sizeof(FSPT_UPD_COMMON) + 0\r
  jmp       ContinueAfterUpdPush\r
\r
Fsp22UpdHeader2:\r
  ; UPD structure is compliant with FSP spec 2.2\r
  push      dword [edx + LoadMicrocodeParamsFsp22.CodeRegionSize]     ; Code size       sizeof(FSPT_UPD_COMMON) + 12\r
  push      dword [edx + LoadMicrocodeParamsFsp22.CodeRegionBase]     ; Code base       sizeof(FSPT_UPD_COMMON) + 8\r
  push      dword [edx + LoadMicrocodeParamsFsp22.MicrocodeCodeSize]  ; Microcode size  sizeof(FSPT_UPD_COMMON) + 4\r
  push      dword [edx + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr]  ; Microcode base  sizeof(FSPT_UPD_COMMON) + 0\r
  jmp       ContinueAfterUpdPush\r
\r
Fsp24UpdHeader2:\r
  ; UPD structure is compliant with FSP spec 2.4\r
  push      dword [edx + LoadMicrocodeParamsFsp24.CodeRegionSize]     ; Code size       sizeof(FSPT_UPD_COMMON) + 24\r
  push      dword [edx + LoadMicrocodeParamsFsp24.CodeRegionBase]     ; Code base       sizeof(FSPT_UPD_COMMON) + 16\r
  push      dword [edx + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]  ; Microcode size  sizeof(FSPT_UPD_COMMON) + 8\r
  push      dword [edx + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr]  ; Microcode base  sizeof(FSPT_UPD_COMMON) + 0\r
\r
ContinueAfterUpdPush:\r
  ;\r
  ; Save API entry/exit timestamp into stack\r
  ;\r
  push      DATA_LEN_OF_PER0     ; Size of the data region\r
  push      30524550h            ; Signature of the  data region 'PER0'\r
  rdtsc\r
  push      edx\r
  push      eax\r
  LOAD_EDX\r
  push      edx\r
  LOAD_EAX\r
  push      eax\r
\r
  ;\r
  ; Terminator for the data on stack\r
  ;\r
  push      0\r
\r
  ;\r
  ; Set ECX/EDX to the BootLoader temporary memory range\r
  ;\r
  mov       ecx,  [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]\r
  mov       edx, ecx\r
  add       edx,  [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))]\r
  sub       edx,  [ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))]\r
\r
  cmp       ecx, edx        ;If PcdFspReservedBufferSize >= PcdTemporaryRamSize, then error.\r
  jb        EstablishStackFspSuccess\r
  mov       eax, 80000003h  ;EFI_UNSUPPORTED\r
  jmp       EstablishStackFspExit\r
EstablishStackFspSuccess:\r
  xor       eax, eax\r
\r
EstablishStackFspExit:\r
  RET_ESI\r
\r
;----------------------------------------------------------------------------\r
; TempRamInit API\r
;\r
; This FSP API will load the microcode update, enable code caching for the\r
; region specified by the boot loader and also setup a temporary stack to be\r
; used till main memory is initialized.\r
;\r
;----------------------------------------------------------------------------\r
global ASM_PFX(TempRamInitApi)\r
ASM_PFX(TempRamInitApi):\r
  ;\r
  ; Ensure SSE is enabled\r
  ;\r
  ENABLE_SSE\r
\r
  ;\r
  ; Save EBP, EBX, ESI, EDI & ESP in XMM7 & XMM6\r
  ;\r
  SAVE_REGS\r
\r
  ;\r
  ; Save timestamp into XMM6\r
  ;\r
  rdtsc\r
  SAVE_EAX\r
  SAVE_EDX\r
\r
  ;\r
  ; Check Parameter\r
  ;\r
  mov       eax, dword [esp + 4]\r
  cmp       eax, 0\r
  mov       eax, 80000002h\r
  jz        TempRamInitExit\r
\r
  ;\r
  ; Sec Platform Init\r
  ;\r
  CALL_MMX  ASM_PFX(SecPlatformInit)\r
  cmp       eax, 0\r
  jnz       TempRamInitExit\r
\r
  ; Load microcode\r
  LOAD_ESP\r
  CALL_MMX  ASM_PFX(LoadMicrocodeDefault)\r
  SXMMN     xmm6, 3, eax            ;Save microcode return status in ECX-SLOT 3 in xmm6.\r
  ;@note If return value eax is not 0, microcode did not load, but continue and attempt to boot.\r
\r
  ; Call Sec CAR Init\r
  LOAD_ESP\r
  CALL_MMX  ASM_PFX(SecCarInit)\r
  cmp       eax, 0\r
  jnz       TempRamInitExit\r
\r
  LOAD_ESP\r
  CALL_MMX  ASM_PFX(EstablishStackFsp)\r
  cmp       eax, 0\r
  jnz       TempRamInitExit\r
\r
  LXMMN     xmm6, eax, 3  ;Restore microcode status if no CAR init error from ECX-SLOT 3 in xmm6.\r
\r
TempRamInitExit:\r
  mov       bl, al                  ; save al data in bl\r
  mov       al, 07Fh                ; API exit postcode 7f\r
  out       080h, al\r
  mov       al, bl                  ; restore al data from bl\r
\r
  ;\r
  ; Load EBP, EBX, ESI, EDI & ESP from XMM7 & XMM6\r
  ;\r
  LOAD_REGS\r
  ret\r
\r
;----------------------------------------------------------------------------\r
; Module Entrypoint API\r
;----------------------------------------------------------------------------\r
global ASM_PFX(_ModuleEntryPoint)\r
ASM_PFX(_ModuleEntryPoint):\r
  jmp $\r