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7e74fd57 JY |
1 | /** @file\r |
2 | IGD OpRegion definition from Intel Integrated Graphics Device OpRegion\r | |
3 | Specification.\r | |
4 | \r | |
98e059ba | 5 | https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.pdf\r |
7e74fd57 | 6 | \r |
d4a9b90f GM |
7 | @note Fixed bug in the spec Mailbox3 - RM31 size from 0x45(69) to 0x46(70)\r |
8 | \r | |
7e74fd57 JY |
9 | Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r |
10 | This program and the accompanying materials\r | |
11 | are licensed and made available under the terms and conditions of the BSD License\r | |
12 | which accompanies this distribution. The full text of the license may be found at\r | |
13 | http://opensource.org/licenses/bsd-license.php\r | |
14 | \r | |
15 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
16 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
17 | \r | |
18 | **/\r | |
19 | #ifndef _IGD_OPREGION_H_\r | |
20 | #define _IGD_OPREGION_H_\r | |
21 | \r | |
98e059ba GM |
22 | #define IGD_OPREGION_HEADER_SIGN "IntelGraphicsMem"\r |
23 | #define IGD_OPREGION_HEADER_MBOX1 BIT0\r | |
24 | #define IGD_OPREGION_HEADER_MBOX2 BIT1\r | |
25 | #define IGD_OPREGION_HEADER_MBOX3 BIT2\r | |
26 | #define IGD_OPREGION_HEADER_MBOX4 BIT3\r | |
27 | #define IGD_OPREGION_HEADER_MBOX5 BIT4\r | |
28 | \r | |
7e74fd57 | 29 | /**\r |
5c66efd0 MG |
30 | OpRegion structures:\r |
31 | Sub-structures define the different parts of the OpRegion followed by the\r | |
32 | main structure representing the entire OpRegion.\r | |
7e74fd57 | 33 | \r |
6e9e19aa | 34 | @note These structures are packed to 1 byte offsets because the exact\r |
5c66efd0 MG |
35 | data location is required by the supporting design specification due to\r |
36 | the fact that the data is used by ASL and Graphics driver code compiled\r | |
37 | separately.\r | |
7e74fd57 JY |
38 | **/\r |
39 | #pragma pack(1)\r | |
40 | ///\r | |
72092534 | 41 | /// OpRegion Mailbox 0 Header structure. The OpRegion Header is used to\r |
5c66efd0 | 42 | /// identify a block of memory as the graphics driver OpRegion.\r |
72092534 | 43 | /// Offset 0x0, Size 0x100\r |
7e74fd57 JY |
44 | ///\r |
45 | typedef struct {\r | |
5c66efd0 MG |
46 | CHAR8 SIGN[0x10]; ///< Offset 0x00 OpRegion Signature\r |
47 | UINT32 SIZE; ///< Offset 0x10 OpRegion Size\r | |
48 | UINT32 OVER; ///< Offset 0x14 OpRegion Structure Version\r | |
49 | UINT8 SVER[0x20]; ///< Offset 0x18 System BIOS Build Version\r | |
50 | UINT8 VVER[0x10]; ///< Offset 0x38 Video BIOS Build Version\r | |
51 | UINT8 GVER[0x10]; ///< Offset 0x48 Graphic Driver Build Version\r | |
52 | UINT32 MBOX; ///< Offset 0x58 Supported Mailboxes\r | |
53 | UINT32 DMOD; ///< Offset 0x5C Driver Model\r | |
98e059ba | 54 | UINT32 PCON; ///< Offset 0x60 Platform Configuration\r |
c3aa61b5 | 55 | CHAR16 DVER[0x10]; ///< Offset 0x64 GOP Version\r |
98e059ba | 56 | UINT8 RM01[0x7C]; ///< Offset 0x84 Reserved Must be zero\r |
72092534 | 57 | } IGD_OPREGION_HEADER;\r |
7e74fd57 JY |
58 | \r |
59 | ///\r | |
72092534 MG |
60 | /// OpRegion Mailbox 1 - Public ACPI Methods\r |
61 | /// Offset 0x100, Size 0x100\r | |
7e74fd57 JY |
62 | ///\r |
63 | typedef struct {\r | |
5c66efd0 MG |
64 | UINT32 DRDY; ///< Offset 0x100 Driver Readiness\r |
65 | UINT32 CSTS; ///< Offset 0x104 Status\r | |
66 | UINT32 CEVT; ///< Offset 0x108 Current Event\r | |
98e059ba | 67 | UINT8 RM11[0x14]; ///< Offset 0x10C Reserved Must be Zero\r |
5c66efd0 MG |
68 | UINT32 DIDL[8]; ///< Offset 0x120 Supported Display Devices ID List\r |
69 | UINT32 CPDL[8]; ///< Offset 0x140 Currently Attached Display Devices List\r | |
70 | UINT32 CADL[8]; ///< Offset 0x160 Currently Active Display Devices List\r | |
71 | UINT32 NADL[8]; ///< Offset 0x180 Next Active Devices List\r | |
72 | UINT32 ASLP; ///< Offset 0x1A0 ASL Sleep Time Out\r | |
73 | UINT32 TIDX; ///< Offset 0x1A4 Toggle Table Index\r | |
74 | UINT32 CHPD; ///< Offset 0x1A8 Current Hotplug Enable Indicator\r | |
75 | UINT32 CLID; ///< Offset 0x1AC Current Lid State Indicator\r | |
76 | UINT32 CDCK; ///< Offset 0x1B0 Current Docking State Indicator\r | |
77 | UINT32 SXSW; ///< Offset 0x1B4 Display Switch Notification on Sx State Resume\r | |
78 | UINT32 EVTS; ///< Offset 0x1B8 Events supported by ASL\r | |
79 | UINT32 CNOT; ///< Offset 0x1BC Current OS Notification\r | |
80 | UINT32 NRDY; ///< Offset 0x1C0 Driver Status\r | |
98e059ba GM |
81 | UINT8 DID2[0x1C]; ///< Offset 0x1C4 Extended Supported Devices ID List (DOD)\r |
82 | UINT8 CPD2[0x1C]; ///< Offset 0x1E0 Extended Attached Display Devices List\r | |
83 | UINT8 RM12[4]; ///< Offset 0x1FC - 0x1FF Reserved Must be zero\r | |
72092534 | 84 | } IGD_OPREGION_MBOX1;\r |
7e74fd57 JY |
85 | \r |
86 | ///\r | |
72092534 MG |
87 | /// OpRegion Mailbox 2 - Software SCI Interface\r |
88 | /// Offset 0x200, Size 0x100\r | |
7e74fd57 JY |
89 | ///\r |
90 | typedef struct {\r | |
5c66efd0 MG |
91 | UINT32 SCIC; ///< Offset 0x200 Software SCI Command / Status / Data\r |
92 | UINT32 PARM; ///< Offset 0x204 Software SCI Parameters\r | |
93 | UINT32 DSLP; ///< Offset 0x208 Driver Sleep Time Out\r | |
98e059ba | 94 | UINT8 RM21[0xF4]; ///< Offset 0x20C - 0x2FF Reserved Must be zero\r |
72092534 | 95 | } IGD_OPREGION_MBOX2;\r |
7e74fd57 JY |
96 | \r |
97 | ///\r | |
72092534 MG |
98 | /// OpRegion Mailbox 3 - BIOS/Driver Notification - ASLE Support\r |
99 | /// Offset 0x300, Size 0x100\r | |
7e74fd57 JY |
100 | ///\r |
101 | typedef struct {\r | |
5c66efd0 MG |
102 | UINT32 ARDY; ///< Offset 0x300 Driver Readiness\r |
103 | UINT32 ASLC; ///< Offset 0x304 ASLE Interrupt Command / Status\r | |
104 | UINT32 TCHE; ///< Offset 0x308 Technology Enabled Indicator\r | |
105 | UINT32 ALSI; ///< Offset 0x30C Current ALS Luminance Reading\r | |
106 | UINT32 BCLP; ///< Offset 0x310 Requested Backlight Brightness\r | |
107 | UINT32 PFIT; ///< Offset 0x314 Panel Fitting State or Request\r | |
108 | UINT32 CBLV; ///< Offset 0x318 Current Brightness Level\r | |
109 | UINT16 BCLM[0x14]; ///< Offset 0x31C Backlight Brightness Levels Duty Cycle Mapping Table\r | |
110 | UINT32 CPFM; ///< Offset 0x344 Current Panel Fitting Mode\r | |
111 | UINT32 EPFM; ///< Offset 0x348 Enabled Panel Fitting Modes\r | |
112 | UINT8 PLUT[0x4A]; ///< Offset 0x34C Panel Look Up Table & Identifier\r | |
113 | UINT32 PFMB; ///< Offset 0x396 PWM Frequency and Minimum Brightness\r | |
114 | UINT32 CCDV; ///< Offset 0x39A Color Correction Default Values\r | |
98e059ba GM |
115 | UINT32 PCFT; ///< Offset 0x39E Power Conservation Features\r |
116 | UINT32 SROT; ///< Offset 0x3A2 Supported Rotation Angles\r | |
117 | UINT32 IUER; ///< Offset 0x3A6 Intel Ultrabook(TM) Event Register\r | |
118 | UINT64 FDSS; ///< Offset 0x3AA DSS Buffer address allocated for IFFS feature\r | |
119 | UINT32 FDSP; ///< Offset 0x3B2 Size of DSS buffer\r | |
120 | UINT32 STAT; ///< Offset 0x3B6 State Indicator\r | |
d4a9b90f | 121 | UINT8 RM31[0x46]; ///< Offset 0x3BA - 0x3FF Reserved Must be zero. Bug in spec 0x45(69)\r |
72092534 | 122 | } IGD_OPREGION_MBOX3;\r |
7e74fd57 JY |
123 | \r |
124 | ///\r | |
72092534 MG |
125 | /// OpRegion Mailbox 4 - VBT Video BIOS Table\r |
126 | /// Offset 0x400, Size 0x1800\r | |
7e74fd57 JY |
127 | ///\r |
128 | typedef struct {\r | |
5c66efd0 | 129 | UINT8 RVBT[0x1800]; ///< Offset 0x400 - 0x1BFF Raw VBT Data\r |
72092534 | 130 | } IGD_OPREGION_MBOX4;\r |
7e74fd57 | 131 | \r |
98e059ba GM |
132 | ///\r |
133 | /// OpRegion Mailbox 5 - BIOS/Driver Notification - Data storage BIOS to Driver data sync\r | |
134 | /// Offset 0x1C00, Size 0x400\r | |
135 | ///\r | |
136 | typedef struct {\r | |
137 | UINT32 PHED; ///< Offset 0x1C00 Panel Header\r | |
138 | UINT8 BDDC[0x100]; ///< Offset 0x1C04 Panel EDID (DDC data)\r | |
139 | UINT8 RM51[0x2FC]; ///< Offset 0x1D04 - 0x1FFF Reserved Must be zero\r | |
140 | } IGD_OPREGION_MBOX5;\r | |
141 | \r | |
7e74fd57 JY |
142 | ///\r |
143 | /// IGD OpRegion Structure\r | |
144 | ///\r | |
145 | typedef struct {\r | |
72092534 MG |
146 | IGD_OPREGION_HEADER Header; ///< OpRegion header (Offset 0x0, Size 0x100)\r |
147 | IGD_OPREGION_MBOX1 MBox1; ///< Mailbox 1: Public ACPI Methods (Offset 0x100, Size 0x100)\r | |
148 | IGD_OPREGION_MBOX2 MBox2; ///< Mailbox 2: Software SCI Interface (Offset 0x200, Size 0x100)\r | |
149 | IGD_OPREGION_MBOX3 MBox3; ///< Mailbox 3: BIOS to Driver Notification (Offset 0x300, Size 0x100)\r | |
150 | IGD_OPREGION_MBOX4 MBox4; ///< Mailbox 4: Video BIOS Table (VBT) (Offset 0x400, Size 0x1800)\r | |
98e059ba | 151 | IGD_OPREGION_MBOX5 MBox5; ///< Mailbox 5: BIOS to Driver Notification Extension (Offset 0x1C00, Size 0x400)\r |
72092534 | 152 | } IGD_OPREGION_STRUCTURE;\r |
9fb16e21 JY |
153 | #pragma pack()\r |
154 | \r | |
155 | #endif\r |