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913cb9dc | 1 | /** @file\r |
2 | \r | |
78c2ffb5 | 3 | Provides some data struct used by EHCI controller driver.\r |
4 | \r | |
d1102dba | 5 | Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r |
9d510e61 | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
913cb9dc | 7 | \r |
913cb9dc | 8 | **/\r |
9 | \r | |
10 | #ifndef _EFI_EHCI_H_\r | |
11 | #define _EFI_EHCI_H_\r | |
12 | \r | |
ed7748fe | 13 | \r |
60c93673 | 14 | #include <Uefi.h>\r |
ed7748fe | 15 | \r |
913cb9dc | 16 | #include <Protocol/Usb2HostController.h>\r |
17 | #include <Protocol/PciIo.h>\r | |
ed7748fe | 18 | \r |
0428a6cb | 19 | #include <Guid/EventGroup.h>\r |
20 | \r | |
913cb9dc | 21 | #include <Library/DebugLib.h>\r |
22 | #include <Library/BaseMemoryLib.h>\r | |
23 | #include <Library/UefiDriverEntryPoint.h>\r | |
24 | #include <Library/UefiBootServicesTableLib.h>\r | |
25 | #include <Library/UefiLib.h>\r | |
26 | #include <Library/BaseLib.h>\r | |
27 | #include <Library/MemoryAllocationLib.h>\r | |
dd4047a5 | 28 | #include <Library/PcdLib.h>\r |
37623a5c | 29 | #include <Library/ReportStatusCodeLib.h>\r |
913cb9dc | 30 | \r |
a261044c | 31 | #include <IndustryStandard/Pci.h>\r |
913cb9dc | 32 | \r |
33 | typedef struct _USB2_HC_DEV USB2_HC_DEV;\r | |
34 | \r | |
35 | #include "UsbHcMem.h"\r | |
36 | #include "EhciReg.h"\r | |
37 | #include "EhciUrb.h"\r | |
38 | #include "EhciSched.h"\r | |
39 | #include "EhciDebug.h"\r | |
aa79b0b3 | 40 | #include "ComponentName.h"\r |
913cb9dc | 41 | \r |
1ccdbf2a | 42 | //\r |
43 | // EHC timeout experience values\r | |
44 | //\r | |
45 | \r | |
46 | #define EHC_1_MICROSECOND 1\r | |
47 | #define EHC_1_MILLISECOND (1000 * EHC_1_MICROSECOND)\r | |
48 | #define EHC_1_SECOND (1000 * EHC_1_MILLISECOND)\r | |
49 | \r | |
50 | //\r | |
51 | // EHCI register operation timeout, set by experience\r | |
52 | //\r | |
53 | #define EHC_RESET_TIMEOUT (1 * EHC_1_SECOND)\r | |
54 | #define EHC_GENERIC_TIMEOUT (10 * EHC_1_MILLISECOND)\r | |
78c2ffb5 | 55 | \r |
1ccdbf2a | 56 | //\r |
57 | // Wait for roothub port power stable, refers to Spec[EHCI1.0-2.3.9]\r | |
58 | //\r | |
59 | #define EHC_ROOT_PORT_RECOVERY_STALL (20 * EHC_1_MILLISECOND)\r | |
60 | \r | |
61 | //\r | |
62 | // Sync and Async transfer polling interval, set by experience,\r | |
d525ec10 | 63 | // and the unit of Async is 100us, means 1ms as interval.\r |
1ccdbf2a | 64 | //\r |
65 | #define EHC_SYNC_POLL_INTERVAL (1 * EHC_1_MILLISECOND)\r | |
d525ec10 | 66 | #define EHC_ASYNC_POLL_INTERVAL EFI_TIMER_PERIOD_MILLISECONDS(1)\r |
41e8ff27 | 67 | \r |
09943f5e | 68 | //\r |
69 | // EHCI debug port control status register bit definition\r | |
70 | //\r | |
71 | #define USB_DEBUG_PORT_IN_USE BIT10\r | |
72 | #define USB_DEBUG_PORT_ENABLE BIT28\r | |
73 | #define USB_DEBUG_PORT_OWNER BIT30\r | |
b48ec0e8 LE |
74 | #define USB_DEBUG_PORT_IN_USE_MASK (USB_DEBUG_PORT_IN_USE | \\r |
75 | USB_DEBUG_PORT_OWNER)\r | |
09943f5e | 76 | \r |
597f4ee2 | 77 | //\r |
78 | // EHC raises TPL to TPL_NOTIFY to serialize all its operations\r | |
79 | // to protect shared data structures.\r | |
80 | //\r | |
09943f5e | 81 | #define EHC_TPL TPL_NOTIFY\r |
41e8ff27 | 82 | \r |
913cb9dc | 83 | //\r |
ed356b9e | 84 | //Iterate through the double linked list. NOT delete safe\r |
913cb9dc | 85 | //\r |
86 | #define EFI_LIST_FOR_EACH(Entry, ListHead) \\r | |
87 | for(Entry = (ListHead)->ForwardLink; Entry != (ListHead); Entry = Entry->ForwardLink)\r | |
88 | \r | |
89 | //\r | |
ed356b9e | 90 | //Iterate through the double linked list. This is delete-safe.\r |
913cb9dc | 91 | //Don't touch NextEntry\r |
92 | //\r | |
93 | #define EFI_LIST_FOR_EACH_SAFE(Entry, NextEntry, ListHead) \\r | |
94 | for(Entry = (ListHead)->ForwardLink, NextEntry = Entry->ForwardLink;\\r | |
95 | Entry != (ListHead); Entry = NextEntry, NextEntry = Entry->ForwardLink)\r | |
96 | \r | |
50d7ebad | 97 | #define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, Field)\r |
913cb9dc | 98 | \r |
99 | \r | |
100 | #define EHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))\r | |
101 | #define EHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))\r | |
102 | #define EHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))\r | |
103 | \r | |
104 | #define EHC_REG_BIT_IS_SET(Ehc, Offset, Bit) \\r | |
105 | (EHC_BIT_IS_SET(EhcReadOpReg ((Ehc), (Offset)), (Bit)))\r | |
106 | \r | |
597f4ee2 | 107 | #define USB2_HC_DEV_SIGNATURE SIGNATURE_32 ('e', 'h', 'c', 'i')\r |
108 | #define EHC_FROM_THIS(a) CR(a, USB2_HC_DEV, Usb2Hc, USB2_HC_DEV_SIGNATURE)\r | |
913cb9dc | 109 | \r |
c52fa98c | 110 | struct _USB2_HC_DEV {\r |
913cb9dc | 111 | UINTN Signature;\r |
112 | EFI_USB2_HC_PROTOCOL Usb2Hc;\r | |
113 | \r | |
114 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
37623a5c | 115 | EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r |
68246fa8 | 116 | UINT64 OriginalPciAttributes;\r |
913cb9dc | 117 | USBHC_MEM_POOL *MemPool;\r |
118 | \r | |
119 | //\r | |
120 | // Schedule data shared between asynchronous and periodic\r | |
121 | // transfers:\r | |
122 | // ShortReadStop, as its name indicates, is used to terminate\r | |
123 | // the short read except the control transfer. EHCI follows\r | |
124 | // the alternative next QTD point when a short read happens.\r | |
125 | // For control transfer, even the short read happens, try the\r | |
126 | // status stage.\r | |
127 | //\r | |
128 | EHC_QTD *ShortReadStop;\r | |
129 | EFI_EVENT PollTimer;\r | |
130 | \r | |
0428a6cb | 131 | //\r |
d1102dba | 132 | // ExitBootServicesEvent is used to stop the EHC DMA operation\r |
0428a6cb | 133 | // after exit boot service.\r |
134 | //\r | |
135 | EFI_EVENT ExitBootServiceEvent;\r | |
136 | \r | |
913cb9dc | 137 | //\r |
138 | // Asynchronous(bulk and control) transfer schedule data:\r | |
139 | // ReclaimHead is used as the head of the asynchronous transfer\r | |
140 | // list. It acts as the reclamation header.\r | |
141 | //\r | |
142 | EHC_QH *ReclaimHead;\r | |
143 | \r | |
144 | //\r | |
ed356b9e | 145 | // Periodic (interrupt) transfer schedule data:\r |
913cb9dc | 146 | //\r |
592b87a4 | 147 | VOID *PeriodFrame; // the buffer pointed by this pointer is used to store pci bus address of the QH descriptor.\r |
148 | VOID *PeriodFrameHost; // the buffer pointed by this pointer is used to store host memory address of the QH descriptor.\r | |
913cb9dc | 149 | VOID *PeriodFrameMap;\r |
150 | \r | |
151 | EHC_QH *PeriodOne;\r | |
152 | LIST_ENTRY AsyncIntTransfers;\r | |
153 | \r | |
154 | //\r | |
155 | // EHCI configuration data\r | |
156 | //\r | |
157 | UINT32 HcStructParams; // Cache of HC structure parameter, EHC_HCSPARAMS_OFFSET\r | |
158 | UINT32 HcCapParams; // Cache of HC capability parameter, HCCPARAMS\r | |
159 | UINT32 CapLen; // Capability length\r | |
913cb9dc | 160 | \r |
161 | //\r | |
162 | // Misc\r | |
163 | //\r | |
164 | EFI_UNICODE_STRING_TABLE *ControllerNameTable;\r | |
09943f5e | 165 | \r |
166 | //\r | |
167 | // EHCI debug port info\r | |
168 | //\r | |
169 | UINT16 DebugPortOffset; // The offset of debug port mmio register\r | |
170 | UINT8 DebugPortBarNum; // The bar number of debug port mmio register\r | |
171 | UINT8 DebugPortNum; // The port number of usb debug port\r | |
167c3fb4 AB |
172 | \r |
173 | BOOLEAN Support64BitDma; // Whether 64 bit DMA may be used with this device\r | |
c52fa98c | 174 | };\r |
913cb9dc | 175 | \r |
176 | \r | |
f527bce3 | 177 | extern EFI_DRIVER_BINDING_PROTOCOL gEhciDriverBinding;\r |
178 | extern EFI_COMPONENT_NAME_PROTOCOL gEhciComponentName;\r | |
179 | extern EFI_COMPONENT_NAME2_PROTOCOL gEhciComponentName2;\r | |
913cb9dc | 180 | \r |
aa79b0b3 | 181 | /**\r |
182 | Test to see if this driver supports ControllerHandle. Any\r | |
183 | ControllerHandle that has Usb2HcProtocol installed will\r | |
184 | be supported.\r | |
185 | \r | |
186 | @param This Protocol instance pointer.\r | |
187 | @param Controller Handle of device to test.\r | |
188 | @param RemainingDevicePath Not used.\r | |
189 | \r | |
190 | @return EFI_SUCCESS This driver supports this device.\r | |
191 | @return EFI_UNSUPPORTED This driver does not support this device.\r | |
192 | \r | |
193 | **/\r | |
194 | EFI_STATUS\r | |
195 | EFIAPI\r | |
196 | EhcDriverBindingSupported (\r | |
197 | IN EFI_DRIVER_BINDING_PROTOCOL *This,\r | |
198 | IN EFI_HANDLE Controller,\r | |
199 | IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r | |
200 | );\r | |
201 | \r | |
202 | /**\r | |
203 | Starting the Usb EHCI Driver.\r | |
204 | \r | |
205 | @param This Protocol instance pointer.\r | |
206 | @param Controller Handle of device to test.\r | |
207 | @param RemainingDevicePath Not used.\r | |
208 | \r | |
209 | @return EFI_SUCCESS supports this device.\r | |
210 | @return EFI_UNSUPPORTED do not support this device.\r | |
211 | @return EFI_DEVICE_ERROR cannot be started due to device Error.\r | |
212 | @return EFI_OUT_OF_RESOURCES cannot allocate resources.\r | |
213 | \r | |
214 | **/\r | |
215 | EFI_STATUS\r | |
216 | EFIAPI\r | |
217 | EhcDriverBindingStart (\r | |
218 | IN EFI_DRIVER_BINDING_PROTOCOL *This,\r | |
219 | IN EFI_HANDLE Controller,\r | |
220 | IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r | |
221 | );\r | |
222 | \r | |
223 | /**\r | |
ed356b9e | 224 | Stop this driver on ControllerHandle. Support stopping any child handles\r |
aa79b0b3 | 225 | created by this driver.\r |
226 | \r | |
227 | @param This Protocol instance pointer.\r | |
228 | @param Controller Handle of device to stop driver on.\r | |
229 | @param NumberOfChildren Number of Children in the ChildHandleBuffer.\r | |
230 | @param ChildHandleBuffer List of handles for the children we need to stop.\r | |
231 | \r | |
232 | @return EFI_SUCCESS Success.\r | |
233 | @return EFI_DEVICE_ERROR Fail.\r | |
234 | \r | |
235 | **/\r | |
236 | EFI_STATUS\r | |
237 | EFIAPI\r | |
238 | EhcDriverBindingStop (\r | |
239 | IN EFI_DRIVER_BINDING_PROTOCOL *This,\r | |
240 | IN EFI_HANDLE Controller,\r | |
241 | IN UINTN NumberOfChildren,\r | |
242 | IN EFI_HANDLE *ChildHandleBuffer\r | |
243 | );\r | |
244 | \r | |
913cb9dc | 245 | #endif\r |
aa79b0b3 | 246 | \r |