[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciDxe / XhciReg.h

/** @file\r
\r
  This file contains the register definition of XHCI host controller.\r
\r
Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef _EFI_XHCI_REG_H_\r
#define _EFI_XHCI_REG_H_\r
\r
#define PCI_IF_XHCI  0x30\r
\r
//\r
// PCI Configuration Registers\r
//\r
#define XHC_BAR_INDEX  0x00\r
\r
#define XHC_PCI_BAR_OFFSET  0x10               // Memory Bar Register Offset\r
#define XHC_PCI_BAR_MASK    0xFFFF             // Memory Base Address Mask\r
\r
#define XHC_PCI_SBRN_OFFSET  0x60              // Serial Bus Release Number Register Offset\r
\r
#define USB_HUB_CLASS_CODE     0x09\r
#define USB_HUB_SUBCLASS_CODE  0x00\r
\r
#define XHC_CAP_USB_LEGACY  0x01\r
#define XHC_CAP_USB_DEBUG   0x0A\r
\r
// ============================================//\r
//           XHCI register offset             //\r
// ============================================//\r
\r
//\r
// Capability registers offset\r
//\r
#define XHC_CAPLENGTH_OFFSET   0x00             // Capability register length offset\r
#define XHC_HCIVERSION_OFFSET  0x02             // Interface Version Number 02-03h\r
#define XHC_HCSPARAMS1_OFFSET  0x04             // Structural Parameters 1\r
#define XHC_HCSPARAMS2_OFFSET  0x08             // Structural Parameters 2\r
#define XHC_HCSPARAMS3_OFFSET  0x0c             // Structural Parameters 3\r
#define XHC_HCCPARAMS_OFFSET   0x10             // Capability Parameters\r
#define XHC_DBOFF_OFFSET       0x14             // Doorbell Offset\r
#define XHC_RTSOFF_OFFSET      0x18             // Runtime Register Space Offset\r
\r
//\r
// Operational registers offset\r
//\r
#define XHC_USBCMD_OFFSET    0x0000               // USB Command Register Offset\r
#define XHC_USBSTS_OFFSET    0x0004               // USB Status Register Offset\r
#define XHC_PAGESIZE_OFFSET  0x0008               // USB Page Size Register Offset\r
#define XHC_DNCTRL_OFFSET    0x0014               // Device Notification Control Register Offset\r
#define XHC_CRCR_OFFSET      0x0018               // Command Ring Control Register Offset\r
#define XHC_DCBAAP_OFFSET    0x0030               // Device Context Base Address Array Pointer Register Offset\r
#define XHC_CONFIG_OFFSET    0x0038               // Configure Register Offset\r
#define XHC_PORTSC_OFFSET    0x0400               // Port Status and Control Register Offset\r
\r
//\r
// Runtime registers offset\r
//\r
#define XHC_MFINDEX_OFFSET  0x00                // Microframe Index Register Offset\r
#define XHC_IMAN_OFFSET     0x20                // Interrupter X Management Register Offset\r
#define XHC_IMOD_OFFSET     0x24                // Interrupter X Moderation Register Offset\r
#define XHC_ERSTSZ_OFFSET   0x28                // Event Ring Segment Table Size Register Offset\r
#define XHC_ERSTBA_OFFSET   0x30                // Event Ring Segment Table Base Address Register Offset\r
#define XHC_ERDP_OFFSET     0x38                // Event Ring Dequeue Pointer Register Offset\r
\r
//\r
// Debug registers offset\r
//\r
#define XHC_DC_DCCTRL  0x20\r
\r
#define USBLEGSP_BIOS_SEMAPHORE  BIT16           // HC BIOS Owned Semaphore\r
#define USBLEGSP_OS_SEMAPHORE    BIT24           // HC OS Owned Semaphore\r
\r
#pragma pack (1)\r
typedef struct {\r
  UINT8     MaxSlots;                     // Number of Device Slots\r
  UINT16    MaxIntrs : 11;                // Number of Interrupters\r
  UINT16    Rsvd     : 5;\r
  UINT8     MaxPorts;                     // Number of Ports\r
} HCSPARAMS1;\r
\r
//\r
// Structural Parameters 1 Register Bitmap Definition\r
//\r
typedef union {\r
  UINT32        Dword;\r
  HCSPARAMS1    Data;\r
} XHC_HCSPARAMS1;\r
\r
typedef struct {\r
  UINT32    Ist          : 4;             // Isochronous Scheduling Threshold\r
  UINT32    Erst         : 4;             // Event Ring Segment Table Max\r
  UINT32    Rsvd         : 13;\r
  UINT32    ScratchBufHi : 5;             // Max Scratchpad Buffers Hi\r
  UINT32    Spr          : 1;             // Scratchpad Restore\r
  UINT32    ScratchBufLo : 5;             // Max Scratchpad Buffers Lo\r
} HCSPARAMS2;\r
\r
//\r
// Structural Parameters 2 Register Bitmap Definition\r
//\r
typedef union {\r
  UINT32        Dword;\r
  HCSPARAMS2    Data;\r
} XHC_HCSPARAMS2;\r
\r
typedef struct {\r
  UINT16    Ac64       : 1;              // 64-bit Addressing Capability\r
  UINT16    Bnc        : 1;              // BW Negotiation Capability\r
  UINT16    Csz        : 1;              // Context Size\r
  UINT16    Ppc        : 1;              // Port Power Control\r
  UINT16    Pind       : 1;              // Port Indicators\r
  UINT16    Lhrc       : 1;              // Light HC Reset Capability\r
  UINT16    Ltc        : 1;              // Latency Tolerance Messaging Capability\r
  UINT16    Nss        : 1;              // No Secondary SID Support\r
  UINT16    Pae        : 1;              // Parse All Event Data\r
  UINT16    Rsvd       : 3;\r
  UINT16    MaxPsaSize : 4;              // Maximum Primary Stream Array Size\r
  UINT16    ExtCapReg;                   // xHCI Extended Capabilities Pointer\r
} HCCPARAMS;\r
\r
//\r
// Capability Parameters Register Bitmap Definition\r
//\r
typedef union {\r
  UINT32       Dword;\r
  HCCPARAMS    Data;\r
} XHC_HCCPARAMS;\r
\r
#pragma pack ()\r
\r
//\r
// Register Bit Definition\r
//\r
#define XHC_USBCMD_RUN    BIT0                   // Run/Stop\r
#define XHC_USBCMD_RESET  BIT1                   // Host Controller Reset\r
#define XHC_USBCMD_INTE   BIT2                   // Interrupter Enable\r
#define XHC_USBCMD_HSEE   BIT3                   // Host System Error Enable\r
\r
#define XHC_USBSTS_HALT  BIT0                    // Host Controller Halted\r
#define XHC_USBSTS_HSE   BIT2                    // Host System Error\r
#define XHC_USBSTS_EINT  BIT3                    // Event Interrupt\r
#define XHC_USBSTS_PCD   BIT4                    // Port Change Detect\r
#define XHC_USBSTS_SSS   BIT8                    // Save State Status\r
#define XHC_USBSTS_RSS   BIT9                    // Restore State Status\r
#define XHC_USBSTS_SRE   BIT10                   // Save/Restore Error\r
#define XHC_USBSTS_CNR   BIT11                   // Host Controller Not Ready\r
#define XHC_USBSTS_HCE   BIT12                   // Host Controller Error\r
\r
#define XHC_PAGESIZE_MASK  0xFFFF                 // Page Size\r
\r
#define XHC_CRCR_RCS  BIT0                       // Ring Cycle State\r
#define XHC_CRCR_CS   BIT1                       // Command Stop\r
#define XHC_CRCR_CA   BIT2                       // Command Abort\r
#define XHC_CRCR_CRR  BIT3                       // Command Ring Running\r
\r
#define XHC_CONFIG_MASK  0xFF                    // Command Ring Running\r
\r
#define XHC_PORTSC_CCS    BIT0                      // Current Connect Status\r
#define XHC_PORTSC_PED    BIT1                      // Port Enabled/Disabled\r
#define XHC_PORTSC_OCA    BIT3                      // Over-current Active\r
#define XHC_PORTSC_RESET  BIT4                      // Port Reset\r
#define XHC_PORTSC_PLS    (BIT5|BIT6|BIT7|BIT8)     // Port Link State\r
#define XHC_PORTSC_PP     BIT9                      // Port Power\r
#define XHC_PORTSC_PS     (BIT10|BIT11|BIT12|BIT13) // Port Speed\r
#define XHC_PORTSC_LWS    BIT16                     // Port Link State Write Strobe\r
#define XHC_PORTSC_CSC    BIT17                     // Connect Status Change\r
#define XHC_PORTSC_PEC    BIT18                     // Port Enabled/Disabled Change\r
#define XHC_PORTSC_WRC    BIT19                     // Warm Port Reset Change\r
#define XHC_PORTSC_OCC    BIT20                     // Over-Current Change\r
#define XHC_PORTSC_PRC    BIT21                     // Port Reset Change\r
#define XHC_PORTSC_PLC    BIT22                     // Port Link State Change\r
#define XHC_PORTSC_CEC    BIT23                     // Port Config Error Change\r
#define XHC_PORTSC_CAS    BIT24                     // Cold Attach Status\r
\r
#define XHC_HUB_PORTSC_CCS    BIT0               // Hub's Current Connect Status\r
#define XHC_HUB_PORTSC_PED    BIT1               // Hub's Port Enabled/Disabled\r
#define XHC_HUB_PORTSC_OCA    BIT3               // Hub's Over-current Active\r
#define XHC_HUB_PORTSC_RESET  BIT4               // Hub's Port Reset\r
#define XHC_HUB_PORTSC_PP     BIT9               // Hub's Port Power\r
#define XHC_HUB_PORTSC_CSC    BIT16              // Hub's Connect Status Change\r
#define XHC_HUB_PORTSC_PEC    BIT17              // Hub's Port Enabled/Disabled Change\r
#define XHC_HUB_PORTSC_OCC    BIT19              // Hub's Over-Current Change\r
#define XHC_HUB_PORTSC_PRC    BIT20              // Hub's Port Reset Change\r
#define XHC_HUB_PORTSC_BHRC   BIT21              // Hub's Port Warm Reset Change\r
#define XHC_IMAN_IP           BIT0               // Interrupt Pending\r
#define XHC_IMAN_IE           BIT1               // Interrupt Enable\r
\r
#define XHC_IMODI_MASK  0x0000FFFF                     // Interrupt Moderation Interval\r
#define XHC_IMODC_MASK  0xFFFF0000                     // Interrupt Moderation Counter\r
\r
//\r
//  Hub Class Feature Selector for Clear Port Feature Request\r
//  It's the extension of hub class feature selector of USB 2.0 in USB 3.0 Spec.\r
//  For more details, Please refer to USB 3.0 Spec Table 10-7.\r
//\r
typedef enum {\r
  Usb3PortBHPortReset       = 28,\r
  Usb3PortBHPortResetChange = 29\r
} XHC_PORT_FEATURE;\r
\r
//\r
// Structure to map the hardware port states to the\r
// UEFI's port states.\r
//\r
typedef struct {\r
  UINT32    HwState;\r
  UINT16    UefiState;\r
} USB_PORT_STATE_MAP;\r
\r
//\r
// Structure to map the hardware port states to feature selector for clear port feature request.\r
//\r
typedef struct {\r
  UINT32    HwState;\r
  UINT16    Selector;\r
} USB_CLEAR_PORT_MAP;\r
\r
/**\r
  Read 1-byte width XHCI capability register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the 1-byte width capability register.\r
\r
  @return The register content read.\r
  @retval If err, return 0xFFFF.\r
\r
**/\r
UINT8\r
XhcReadCapReg8 (\r
  IN  USB_XHCI_INSTANCE  *Xhc,\r
  IN  UINT32             Offset\r
  );\r
\r
/**\r
  Read 4-bytes width XHCI capability register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the 4-bytes width capability register.\r
\r
  @return The register content read.\r
  @retval If err, return 0xFFFFFFFF.\r
\r
**/\r
UINT32\r
XhcReadCapReg (\r
  IN  USB_XHCI_INSTANCE  *Xhc,\r
  IN  UINT32             Offset\r
  );\r
\r
/**\r
  Read 4-bytes width XHCI Operational register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the 4-bytes width operational register.\r
\r
  @return The register content read.\r
  @retval If err, return 0xFFFFFFFF.\r
\r
**/\r
UINT32\r
XhcReadOpReg (\r
  IN  USB_XHCI_INSTANCE  *Xhc,\r
  IN  UINT32             Offset\r
  );\r
\r
/**\r
  Write the data to the 4-bytes width XHCI operational register.\r
\r
  @param  Xhc      The XHCI Instance.\r
  @param  Offset   The offset of the 4-bytes width operational register.\r
  @param  Data     The data to write.\r
\r
**/\r
VOID\r
XhcWriteOpReg (\r
  IN USB_XHCI_INSTANCE  *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Data\r
  );\r
\r
/**\r
  Read XHCI runtime register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
\r
  @return The register content read\r
\r
**/\r
UINT32\r
XhcReadRuntimeReg (\r
  IN  USB_XHCI_INSTANCE  *Xhc,\r
  IN  UINT32             Offset\r
  );\r
\r
/**\r
  Write the data to the XHCI runtime register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
  @param  Data         The data to write.\r
\r
**/\r
VOID\r
XhcWriteRuntimeReg (\r
  IN USB_XHCI_INSTANCE  *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Data\r
  );\r
\r
/**\r
  Write the data to the XHCI door bell register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the door bell register.\r
  @param  Data         The data to write.\r
\r
**/\r
VOID\r
XhcWriteDoorBellReg (\r
  IN USB_XHCI_INSTANCE  *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Data\r
  );\r
\r
/**\r
  Set one bit of the operational register while keeping other bits.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the operational register.\r
  @param  Bit          The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcSetOpRegBit (\r
  IN USB_XHCI_INSTANCE  *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Bit\r
  );\r
\r
/**\r
  Clear one bit of the operational register while keeping other bits.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the operational register.\r
  @param  Bit          The bit mask of the register to clear.\r
\r
**/\r
VOID\r
XhcClearOpRegBit (\r
  IN USB_XHCI_INSTANCE  *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Bit\r
  );\r
\r
/**\r
  Wait the operation register's bit as specified by Bit\r
  to be set (or clear).\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the operational register.\r
  @param  Bit          The bit of the register to wait for.\r
  @param  WaitToSet    Wait the bit to set or clear.\r
  @param  Timeout      The time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS  The bit successfully changed by host controller.\r
  @retval EFI_TIMEOUT  The time out occurred.\r
\r
**/\r
EFI_STATUS\r
XhcWaitOpRegBit (\r
  IN USB_XHCI_INSTANCE  *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Bit,\r
  IN BOOLEAN            WaitToSet,\r
  IN UINT32             Timeout\r
  );\r
\r
/**\r
  Read XHCI runtime register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
\r
  @return The register content read\r
\r
**/\r
UINT32\r
XhcReadRuntimeReg (\r
  IN  USB_XHCI_INSTANCE  *Xhc,\r
  IN  UINT32             Offset\r
  );\r
\r
/**\r
  Write the data to the XHCI runtime register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
  @param  Data         The data to write.\r
\r
**/\r
VOID\r
XhcWriteRuntimeReg (\r
  IN USB_XHCI_INSTANCE  *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Data\r
  );\r
\r
/**\r
  Set one bit of the runtime register while keeping other bits.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
  @param  Bit          The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcSetRuntimeRegBit (\r
  IN USB_XHCI_INSTANCE  *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Bit\r
  );\r
\r
/**\r
  Clear one bit of the runtime register while keeping other bits.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
  @param  Bit          The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcClearRuntimeRegBit (\r
  IN USB_XHCI_INSTANCE  *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Bit\r
  );\r
\r
/**\r
  Read XHCI extended capability register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the extended capability register.\r
\r
  @return The register content read\r
\r
**/\r
UINT32\r
XhcReadExtCapReg (\r
  IN  USB_XHCI_INSTANCE  *Xhc,\r
  IN  UINT32             Offset\r
  );\r
\r
/**\r
  Whether the XHCI host controller is halted.\r
\r
  @param  Xhc     The XHCI Instance.\r
\r
  @retval TRUE    The controller is halted.\r
  @retval FALSE   It isn't halted.\r
\r
**/\r
BOOLEAN\r
XhcIsHalt (\r
  IN USB_XHCI_INSTANCE  *Xhc\r
  );\r
\r
/**\r
  Whether system error occurred.\r
\r
  @param  Xhc      The XHCI Instance.\r
\r
  @retval TRUE     System error happened.\r
  @retval FALSE    No system error.\r
\r
**/\r
BOOLEAN\r
XhcIsSysError (\r
  IN USB_XHCI_INSTANCE  *Xhc\r
  );\r
\r
/**\r
  Reset the XHCI host controller.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS  The XHCI host controller is reset.\r
  @return Others       Failed to reset the XHCI before Timeout.\r
\r
**/\r
EFI_STATUS\r
XhcResetHC (\r
  IN USB_XHCI_INSTANCE  *Xhc,\r
  IN UINT32             Timeout\r
  );\r
\r
/**\r
  Halt the XHCI host controller.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
\r
  @return EFI_SUCCESS  The XHCI host controller is halt.\r
  @return EFI_TIMEOUT  Failed to halt the XHCI before Timeout.\r
\r
**/\r
EFI_STATUS\r
XhcHaltHC (\r
  IN USB_XHCI_INSTANCE  *Xhc,\r
  IN UINT32             Timeout\r
  );\r
\r
/**\r
  Set the XHCI host controller to run.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
\r
  @return EFI_SUCCESS  The XHCI host controller is running.\r
  @return EFI_TIMEOUT  Failed to set the XHCI to run before Timeout.\r
\r
**/\r
EFI_STATUS\r
XhcRunHC (\r
  IN USB_XHCI_INSTANCE  *Xhc,\r
  IN UINT32             Timeout\r
  );\r
\r
/**\r
  Calculate the offset of the XHCI capability.\r
\r
  @param  Xhc     The XHCI Instance.\r
  @param  CapId   The XHCI Capability ID.\r
\r
  @return The offset of XHCI legacy support capability register.\r
\r
**/\r
UINT32\r
XhcGetCapabilityAddr (\r
  IN USB_XHCI_INSTANCE  *Xhc,\r
  IN UINT8              CapId\r
  );\r
\r
#endif\r
Commit	Line	Data
92870c98	1	/** @file\r
	2	\r
	3	This file contains the register definition of XHCI host controller.\r
	4	\r
4a723d3d	5	Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>\r
9d510e61	6	SPDX-License-Identifier: BSD-2-Clause-Patent\r
92870c98	7	\r
	8	**/\r
	9	\r
	10	#ifndef _EFI_XHCI_REG_H_\r
	11	#define _EFI_XHCI_REG_H_\r
	12	\r
1436aea4	13	#define PCI_IF_XHCI 0x30\r
92870c98	14	\r
	15	//\r
	16	// PCI Configuration Registers\r
	17	//\r
1436aea4	18	#define XHC_BAR_INDEX 0x00\r
92870c98	19	\r
1436aea4 MK	20	#define XHC_PCI_BAR_OFFSET 0x10 // Memory Bar Register Offset\r
1436aea4 MK	21	#define XHC_PCI_BAR_MASK 0xFFFF // Memory Base Address Mask\r
92870c98	22	\r
1436aea4	23	#define XHC_PCI_SBRN_OFFSET 0x60 // Serial Bus Release Number Register Offset\r
fed6cf25	24	\r
1436aea4 MK	25	#define USB_HUB_CLASS_CODE 0x09\r
1436aea4 MK	26	#define USB_HUB_SUBCLASS_CODE 0x00\r
92870c98	27	\r
1436aea4 MK	28	#define XHC_CAP_USB_LEGACY 0x01\r
1436aea4 MK	29	#define XHC_CAP_USB_DEBUG 0x0A\r
5bcb62a4	30	\r
1436aea4	31	// ============================================//\r
92870c98	32	// XHCI register offset //\r
1436aea4	33	// ============================================//\r
92870c98	34	\r
	35	//\r
	36	// Capability registers offset\r
	37	//\r
1436aea4 MK	38	#define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset\r
	39	#define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h\r
	40	#define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1\r
	41	#define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2\r
	42	#define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3\r
	43	#define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters\r
	44	#define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset\r
	45	#define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset\r
92870c98	46	\r
	47	//\r
	48	// Operational registers offset\r
	49	//\r
1436aea4 MK	50	#define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset\r
	51	#define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset\r
	52	#define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset\r
	53	#define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset\r
	54	#define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset\r
	55	#define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset\r
	56	#define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset\r
	57	#define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset\r
92870c98	58	\r
	59	//\r
	60	// Runtime registers offset\r
	61	//\r
1436aea4 MK	62	#define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset\r
	63	#define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset\r
	64	#define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset\r
	65	#define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset\r
	66	#define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset\r
	67	#define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset\r
92870c98	68	\r
5bcb62a4 EL	69	//\r
	70	// Debug registers offset\r
	71	//\r
1436aea4	72	#define XHC_DC_DCCTRL 0x20\r
5bcb62a4	73	\r
1436aea4 MK	74	#define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore\r
1436aea4 MK	75	#define USBLEGSP_OS_SEMAPHORE BIT24 // HC OS Owned Semaphore\r
92870c98	76	\r
92870c98	77	#pragma pack (1)\r
a9292c13	78	typedef struct {\r
1436aea4 MK	79	UINT8 MaxSlots; // Number of Device Slots\r
	80	UINT16 MaxIntrs : 11; // Number of Interrupters\r
	81	UINT16 Rsvd : 5;\r
	82	UINT8 MaxPorts; // Number of Ports\r
a9292c13	83	} HCSPARAMS1;\r
a9292c13	84	\r
92870c98	85	//\r
	86	// Structural Parameters 1 Register Bitmap Definition\r
	87	//\r
a9292c13	88	typedef union {\r
1436aea4 MK	89	UINT32 Dword;\r
1436aea4 MK	90	HCSPARAMS1 Data;\r
92870c98	91	} XHC_HCSPARAMS1;\r
92870c98	92	\r
a9292c13	93	typedef struct {\r
1436aea4 MK	94	UINT32 Ist : 4; // Isochronous Scheduling Threshold\r
	95	UINT32 Erst : 4; // Event Ring Segment Table Max\r
	96	UINT32 Rsvd : 13;\r
	97	UINT32 ScratchBufHi : 5; // Max Scratchpad Buffers Hi\r
	98	UINT32 Spr : 1; // Scratchpad Restore\r
	99	UINT32 ScratchBufLo : 5; // Max Scratchpad Buffers Lo\r
a9292c13	100	} HCSPARAMS2;\r
a9292c13	101	\r
92870c98	102	//\r
	103	// Structural Parameters 2 Register Bitmap Definition\r
	104	//\r
a9292c13	105	typedef union {\r
1436aea4 MK	106	UINT32 Dword;\r
1436aea4 MK	107	HCSPARAMS2 Data;\r
92870c98	108	} XHC_HCSPARAMS2;\r
92870c98	109	\r
a9292c13	110	typedef struct {\r
1436aea4 MK	111	UINT16 Ac64 : 1; // 64-bit Addressing Capability\r
	112	UINT16 Bnc : 1; // BW Negotiation Capability\r
	113	UINT16 Csz : 1; // Context Size\r
	114	UINT16 Ppc : 1; // Port Power Control\r
	115	UINT16 Pind : 1; // Port Indicators\r
	116	UINT16 Lhrc : 1; // Light HC Reset Capability\r
	117	UINT16 Ltc : 1; // Latency Tolerance Messaging Capability\r
	118	UINT16 Nss : 1; // No Secondary SID Support\r
	119	UINT16 Pae : 1; // Parse All Event Data\r
	120	UINT16 Rsvd : 3;\r
	121	UINT16 MaxPsaSize : 4; // Maximum Primary Stream Array Size\r
	122	UINT16 ExtCapReg; // xHCI Extended Capabilities Pointer\r
a9292c13	123	} HCCPARAMS;\r
a9292c13	124	\r
92870c98	125	//\r
	126	// Capability Parameters Register Bitmap Definition\r
	127	//\r
a9292c13	128	typedef union {\r
1436aea4 MK	129	UINT32 Dword;\r
1436aea4 MK	130	HCCPARAMS Data;\r
92870c98	131	} XHC_HCCPARAMS;\r
	132	\r
	133	#pragma pack ()\r
	134	\r
	135	//\r
	136	// Register Bit Definition\r
	137	//\r
1436aea4 MK	138	#define XHC_USBCMD_RUN BIT0 // Run/Stop\r
	139	#define XHC_USBCMD_RESET BIT1 // Host Controller Reset\r
	140	#define XHC_USBCMD_INTE BIT2 // Interrupter Enable\r
	141	#define XHC_USBCMD_HSEE BIT3 // Host System Error Enable\r
	142	\r
	143	#define XHC_USBSTS_HALT BIT0 // Host Controller Halted\r
	144	#define XHC_USBSTS_HSE BIT2 // Host System Error\r
	145	#define XHC_USBSTS_EINT BIT3 // Event Interrupt\r
	146	#define XHC_USBSTS_PCD BIT4 // Port Change Detect\r
	147	#define XHC_USBSTS_SSS BIT8 // Save State Status\r
	148	#define XHC_USBSTS_RSS BIT9 // Restore State Status\r
	149	#define XHC_USBSTS_SRE BIT10 // Save/Restore Error\r
	150	#define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready\r
	151	#define XHC_USBSTS_HCE BIT12 // Host Controller Error\r
	152	\r
	153	#define XHC_PAGESIZE_MASK 0xFFFF // Page Size\r
	154	\r
	155	#define XHC_CRCR_RCS BIT0 // Ring Cycle State\r
	156	#define XHC_CRCR_CS BIT1 // Command Stop\r
	157	#define XHC_CRCR_CA BIT2 // Command Abort\r
	158	#define XHC_CRCR_CRR BIT3 // Command Ring Running\r
	159	\r
	160	#define XHC_CONFIG_MASK 0xFF // Command Ring Running\r
	161	\r
	162	#define XHC_PORTSC_CCS BIT0 // Current Connect Status\r
	163	#define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled\r
	164	#define XHC_PORTSC_OCA BIT3 // Over-current Active\r
	165	#define XHC_PORTSC_RESET BIT4 // Port Reset\r
	166	#define XHC_PORTSC_PLS (BIT5\|BIT6\|BIT7\|BIT8) // Port Link State\r
	167	#define XHC_PORTSC_PP BIT9 // Port Power\r
	168	#define XHC_PORTSC_PS (BIT10\|BIT11\|BIT12\|BIT13) // Port Speed\r
	169	#define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe\r
	170	#define XHC_PORTSC_CSC BIT17 // Connect Status Change\r
	171	#define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change\r
	172	#define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change\r
	173	#define XHC_PORTSC_OCC BIT20 // Over-Current Change\r
	174	#define XHC_PORTSC_PRC BIT21 // Port Reset Change\r
	175	#define XHC_PORTSC_PLC BIT22 // Port Link State Change\r
	176	#define XHC_PORTSC_CEC BIT23 // Port Config Error Change\r
	177	#define XHC_PORTSC_CAS BIT24 // Cold Attach Status\r
	178	\r
	179	#define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status\r
	180	#define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled\r
	181	#define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active\r
	182	#define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset\r
	183	#define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power\r
	184	#define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change\r
	185	#define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change\r
	186	#define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change\r
	187	#define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change\r
	188	#define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change\r
	189	#define XHC_IMAN_IP BIT0 // Interrupt Pending\r
	190	#define XHC_IMAN_IE BIT1 // Interrupt Enable\r
	191	\r
	192	#define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval\r
	193	#define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter\r
92870c98	194	\r
c3f44a77 FT	195	//\r
c3f44a77 FT	196	// Hub Class Feature Selector for Clear Port Feature Request\r
8d84dbe9 FT	197	// It's the extension of hub class feature selector of USB 2.0 in USB 3.0 Spec.\r
8d84dbe9 FT	198	// For more details, Please refer to USB 3.0 Spec Table 10-7.\r
c3f44a77	199	//\r
8d84dbe9	200	typedef enum {\r
1436aea4 MK	201	Usb3PortBHPortReset = 28,\r
1436aea4 MK	202	Usb3PortBHPortResetChange = 29\r
8d84dbe9	203	} XHC_PORT_FEATURE;\r
c3f44a77	204	\r
92870c98	205	//\r
	206	// Structure to map the hardware port states to the\r
	207	// UEFI's port states.\r
	208	//\r
	209	typedef struct {\r
1436aea4 MK	210	UINT32 HwState;\r
1436aea4 MK	211	UINT16 UefiState;\r
92870c98	212	} USB_PORT_STATE_MAP;\r
92870c98	213	\r
c3f44a77 FT	214	//\r
	215	// Structure to map the hardware port states to feature selector for clear port feature request.\r
	216	//\r
	217	typedef struct {\r
1436aea4 MK	218	UINT32 HwState;\r
1436aea4 MK	219	UINT16 Selector;\r
c3f44a77 FT	220	} USB_CLEAR_PORT_MAP;\r
c3f44a77 FT	221	\r
92870c98	222	/**\r
	223	Read 1-byte width XHCI capability register.\r
	224	\r
a9292c13	225	@param Xhc The XHCI Instance.\r
92870c98	226	@param Offset The offset of the 1-byte width capability register.\r
	227	\r
	228	@return The register content read.\r
	229	@retval If err, return 0xFFFF.\r
	230	\r
	231	**/\r
	232	UINT8\r
	233	XhcReadCapReg8 (\r
1436aea4 MK	234	IN USB_XHCI_INSTANCE *Xhc,\r
1436aea4 MK	235	IN UINT32 Offset\r
92870c98	236	);\r
	237	\r
	238	/**\r
	239	Read 4-bytes width XHCI capability register.\r
	240	\r
a9292c13	241	@param Xhc The XHCI Instance.\r
92870c98	242	@param Offset The offset of the 4-bytes width capability register.\r
	243	\r
	244	@return The register content read.\r
	245	@retval If err, return 0xFFFFFFFF.\r
	246	\r
	247	**/\r
	248	UINT32\r
	249	XhcReadCapReg (\r
1436aea4 MK	250	IN USB_XHCI_INSTANCE *Xhc,\r
1436aea4 MK	251	IN UINT32 Offset\r
92870c98	252	);\r
	253	\r
	254	/**\r
	255	Read 4-bytes width XHCI Operational register.\r
	256	\r
a9292c13	257	@param Xhc The XHCI Instance.\r
92870c98	258	@param Offset The offset of the 4-bytes width operational register.\r
	259	\r
	260	@return The register content read.\r
	261	@retval If err, return 0xFFFFFFFF.\r
	262	\r
	263	**/\r
	264	UINT32\r
	265	XhcReadOpReg (\r
1436aea4 MK	266	IN USB_XHCI_INSTANCE *Xhc,\r
1436aea4 MK	267	IN UINT32 Offset\r
92870c98	268	);\r
	269	\r
	270	/**\r
	271	Write the data to the 4-bytes width XHCI operational register.\r
	272	\r
a9292c13	273	@param Xhc The XHCI Instance.\r
92870c98	274	@param Offset The offset of the 4-bytes width operational register.\r
	275	@param Data The data to write.\r
	276	\r
	277	**/\r
	278	VOID\r
	279	XhcWriteOpReg (\r
1436aea4 MK	280	IN USB_XHCI_INSTANCE *Xhc,\r
	281	IN UINT32 Offset,\r
	282	IN UINT32 Data\r
92870c98	283	);\r
92870c98	284	\r
92870c98	285	/**\r
	286	Read XHCI runtime register.\r
	287	\r
a9292c13	288	@param Xhc The XHCI Instance.\r
92870c98	289	@param Offset The offset of the runtime register.\r
	290	\r
	291	@return The register content read\r
	292	\r
	293	**/\r
	294	UINT32\r
	295	XhcReadRuntimeReg (\r
1436aea4 MK	296	IN USB_XHCI_INSTANCE *Xhc,\r
1436aea4 MK	297	IN UINT32 Offset\r
92870c98	298	);\r
92870c98	299	\r
92870c98	300	/**\r
	301	Write the data to the XHCI runtime register.\r
	302	\r
a9292c13	303	@param Xhc The XHCI Instance.\r
92870c98	304	@param Offset The offset of the runtime register.\r
	305	@param Data The data to write.\r
	306	\r
	307	**/\r
	308	VOID\r
	309	XhcWriteRuntimeReg (\r
1436aea4 MK	310	IN USB_XHCI_INSTANCE *Xhc,\r
	311	IN UINT32 Offset,\r
	312	IN UINT32 Data\r
92870c98	313	);\r
92870c98	314	\r
92870c98	315	/**\r
	316	Write the data to the XHCI door bell register.\r
	317	\r
a9292c13	318	@param Xhc The XHCI Instance.\r
92870c98	319	@param Offset The offset of the door bell register.\r
	320	@param Data The data to write.\r
	321	\r
	322	**/\r
	323	VOID\r
	324	XhcWriteDoorBellReg (\r
1436aea4 MK	325	IN USB_XHCI_INSTANCE *Xhc,\r
	326	IN UINT32 Offset,\r
	327	IN UINT32 Data\r
92870c98	328	);\r
	329	\r
	330	/**\r
	331	Set one bit of the operational register while keeping other bits.\r
	332	\r
a9292c13	333	@param Xhc The XHCI Instance.\r
92870c98	334	@param Offset The offset of the operational register.\r
	335	@param Bit The bit mask of the register to set.\r
	336	\r
	337	**/\r
	338	VOID\r
	339	XhcSetOpRegBit (\r
1436aea4 MK	340	IN USB_XHCI_INSTANCE *Xhc,\r
	341	IN UINT32 Offset,\r
	342	IN UINT32 Bit\r
92870c98	343	);\r
	344	\r
	345	/**\r
	346	Clear one bit of the operational register while keeping other bits.\r
	347	\r
a9292c13	348	@param Xhc The XHCI Instance.\r
92870c98	349	@param Offset The offset of the operational register.\r
	350	@param Bit The bit mask of the register to clear.\r
	351	\r
	352	**/\r
	353	VOID\r
	354	XhcClearOpRegBit (\r
1436aea4 MK	355	IN USB_XHCI_INSTANCE *Xhc,\r
	356	IN UINT32 Offset,\r
	357	IN UINT32 Bit\r
92870c98	358	);\r
	359	\r
	360	/**\r
	361	Wait the operation register's bit as specified by Bit\r
	362	to be set (or clear).\r
	363	\r
a9292c13	364	@param Xhc The XHCI Instance.\r
92870c98	365	@param Offset The offset of the operational register.\r
	366	@param Bit The bit of the register to wait for.\r
	367	@param WaitToSet Wait the bit to set or clear.\r
2f6ef874	368	@param Timeout The time to wait before abort (in millisecond, ms).\r
92870c98	369	\r
	370	@retval EFI_SUCCESS The bit successfully changed by host controller.\r
	371	@retval EFI_TIMEOUT The time out occurred.\r
	372	\r
	373	**/\r
	374	EFI_STATUS\r
	375	XhcWaitOpRegBit (\r
1436aea4 MK	376	IN USB_XHCI_INSTANCE *Xhc,\r
	377	IN UINT32 Offset,\r
	378	IN UINT32 Bit,\r
	379	IN BOOLEAN WaitToSet,\r
	380	IN UINT32 Timeout\r
92870c98	381	);\r
	382	\r
	383	/**\r
	384	Read XHCI runtime register.\r
	385	\r
a9292c13	386	@param Xhc The XHCI Instance.\r
92870c98	387	@param Offset The offset of the runtime register.\r
	388	\r
	389	@return The register content read\r
	390	\r
	391	**/\r
	392	UINT32\r
	393	XhcReadRuntimeReg (\r
1436aea4 MK	394	IN USB_XHCI_INSTANCE *Xhc,\r
1436aea4 MK	395	IN UINT32 Offset\r
92870c98	396	);\r
	397	\r
	398	/**\r
	399	Write the data to the XHCI runtime register.\r
	400	\r
a9292c13	401	@param Xhc The XHCI Instance.\r
92870c98	402	@param Offset The offset of the runtime register.\r
	403	@param Data The data to write.\r
	404	\r
	405	**/\r
	406	VOID\r
	407	XhcWriteRuntimeReg (\r
1436aea4 MK	408	IN USB_XHCI_INSTANCE *Xhc,\r
	409	IN UINT32 Offset,\r
	410	IN UINT32 Data\r
92870c98	411	);\r
	412	\r
	413	/**\r
	414	Set one bit of the runtime register while keeping other bits.\r
	415	\r
a9292c13	416	@param Xhc The XHCI Instance.\r
92870c98	417	@param Offset The offset of the runtime register.\r
	418	@param Bit The bit mask of the register to set.\r
	419	\r
	420	**/\r
	421	VOID\r
	422	XhcSetRuntimeRegBit (\r
1436aea4 MK	423	IN USB_XHCI_INSTANCE *Xhc,\r
	424	IN UINT32 Offset,\r
	425	IN UINT32 Bit\r
92870c98	426	);\r
	427	\r
	428	/**\r
	429	Clear one bit of the runtime register while keeping other bits.\r
	430	\r
a9292c13	431	@param Xhc The XHCI Instance.\r
92870c98	432	@param Offset The offset of the runtime register.\r
	433	@param Bit The bit mask of the register to set.\r
	434	\r
	435	**/\r
	436	VOID\r
	437	XhcClearRuntimeRegBit (\r
1436aea4 MK	438	IN USB_XHCI_INSTANCE *Xhc,\r
	439	IN UINT32 Offset,\r
	440	IN UINT32 Bit\r
92870c98	441	);\r
92870c98	442	\r
5bcb62a4 EL	443	/**\r
	444	Read XHCI extended capability register.\r
	445	\r
	446	@param Xhc The XHCI Instance.\r
	447	@param Offset The offset of the extended capability register.\r
	448	\r
	449	@return The register content read\r
	450	\r
	451	**/\r
	452	UINT32\r
	453	XhcReadExtCapReg (\r
1436aea4 MK	454	IN USB_XHCI_INSTANCE *Xhc,\r
1436aea4 MK	455	IN UINT32 Offset\r
5bcb62a4 EL	456	);\r
5bcb62a4 EL	457	\r
92870c98	458	/**\r
	459	Whether the XHCI host controller is halted.\r
	460	\r
a9292c13	461	@param Xhc The XHCI Instance.\r
92870c98	462	\r
	463	@retval TRUE The controller is halted.\r
	464	@retval FALSE It isn't halted.\r
	465	\r
	466	**/\r
	467	BOOLEAN\r
	468	XhcIsHalt (\r
1436aea4	469	IN USB_XHCI_INSTANCE *Xhc\r
92870c98	470	);\r
	471	\r
	472	/**\r
	473	Whether system error occurred.\r
	474	\r
a9292c13	475	@param Xhc The XHCI Instance.\r
92870c98	476	\r
	477	@retval TRUE System error happened.\r
	478	@retval FALSE No system error.\r
	479	\r
	480	**/\r
	481	BOOLEAN\r
	482	XhcIsSysError (\r
1436aea4	483	IN USB_XHCI_INSTANCE *Xhc\r
92870c98	484	);\r
	485	\r
	486	/**\r
	487	Reset the XHCI host controller.\r
	488	\r
a9292c13	489	@param Xhc The XHCI Instance.\r
2f6ef874	490	@param Timeout Time to wait before abort (in millisecond, ms).\r
92870c98	491	\r
	492	@retval EFI_SUCCESS The XHCI host controller is reset.\r
	493	@return Others Failed to reset the XHCI before Timeout.\r
	494	\r
	495	**/\r
	496	EFI_STATUS\r
	497	XhcResetHC (\r
1436aea4 MK	498	IN USB_XHCI_INSTANCE *Xhc,\r
1436aea4 MK	499	IN UINT32 Timeout\r
92870c98	500	);\r
	501	\r
	502	/**\r
	503	Halt the XHCI host controller.\r
	504	\r
a9292c13	505	@param Xhc The XHCI Instance.\r
2f6ef874	506	@param Timeout Time to wait before abort (in millisecond, ms).\r
92870c98	507	\r
	508	@return EFI_SUCCESS The XHCI host controller is halt.\r
	509	@return EFI_TIMEOUT Failed to halt the XHCI before Timeout.\r
	510	\r
	511	**/\r
	512	EFI_STATUS\r
	513	XhcHaltHC (\r
1436aea4 MK	514	IN USB_XHCI_INSTANCE *Xhc,\r
1436aea4 MK	515	IN UINT32 Timeout\r
92870c98	516	);\r
	517	\r
	518	/**\r
	519	Set the XHCI host controller to run.\r
	520	\r
a9292c13	521	@param Xhc The XHCI Instance.\r
2f6ef874	522	@param Timeout Time to wait before abort (in millisecond, ms).\r
92870c98	523	\r
	524	@return EFI_SUCCESS The XHCI host controller is running.\r
	525	@return EFI_TIMEOUT Failed to set the XHCI to run before Timeout.\r
	526	\r
	527	**/\r
	528	EFI_STATUS\r
	529	XhcRunHC (\r
1436aea4 MK	530	IN USB_XHCI_INSTANCE *Xhc,\r
1436aea4 MK	531	IN UINT32 Timeout\r
92870c98	532	);\r
	533	\r
	534	/**\r
5bcb62a4	535	Calculate the offset of the XHCI capability.\r
92870c98	536	\r
a9292c13	537	@param Xhc The XHCI Instance.\r
5bcb62a4	538	@param CapId The XHCI Capability ID.\r
92870c98	539	\r
	540	@return The offset of XHCI legacy support capability register.\r
	541	\r
	542	**/\r
	543	UINT32\r
5bcb62a4	544	XhcGetCapabilityAddr (\r
1436aea4 MK	545	IN USB_XHCI_INSTANCE *Xhc,\r
1436aea4 MK	546	IN UINT8 CapId\r
92870c98	547	);\r
	548	\r
	549	#endif\r