[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciDxe / XhciReg.h

/** @file\r
\r
  This file contains the register definition of XHCI host controller.\r
\r
Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef _EFI_XHCI_REG_H_\r
#define _EFI_XHCI_REG_H_\r
\r
#define PCI_IF_XHCI                 0x30\r
\r
//\r
// PCI Configuration Registers\r
//\r
#define XHC_BAR_INDEX               0x00\r
\r
#define XHC_PCI_BAR_OFFSET          0x10       // Memory Bar Register Offset\r
#define XHC_PCI_BAR_MASK            0xFFFF     // Memory Base Address Mask\r
\r
#define XHC_PCI_SBRN_OFFSET         0x60       // Serial Bus Release Number Register Offset\r
\r
#define USB_HUB_CLASS_CODE          0x09\r
#define USB_HUB_SUBCLASS_CODE       0x00\r
\r
#define XHC_CAP_USB_LEGACY          0x01\r
#define XHC_CAP_USB_DEBUG           0x0A\r
\r
//============================================//\r
//           XHCI register offset             //\r
//============================================//\r
\r
//\r
// Capability registers offset\r
//\r
#define XHC_CAPLENGTH_OFFSET               0x00 // Capability register length offset\r
#define XHC_HCIVERSION_OFFSET              0x02 // Interface Version Number 02-03h\r
#define XHC_HCSPARAMS1_OFFSET              0x04 // Structural Parameters 1\r
#define XHC_HCSPARAMS2_OFFSET              0x08 // Structural Parameters 2\r
#define XHC_HCSPARAMS3_OFFSET              0x0c // Structural Parameters 3\r
#define XHC_HCCPARAMS_OFFSET               0x10 // Capability Parameters\r
#define XHC_DBOFF_OFFSET                   0x14 // Doorbell Offset\r
#define XHC_RTSOFF_OFFSET                  0x18 // Runtime Register Space Offset\r
\r
//\r
// Operational registers offset\r
//\r
#define XHC_USBCMD_OFFSET                  0x0000 // USB Command Register Offset\r
#define XHC_USBSTS_OFFSET                  0x0004 // USB Status Register Offset\r
#define XHC_PAGESIZE_OFFSET                0x0008 // USB Page Size Register Offset\r
#define XHC_DNCTRL_OFFSET                  0x0014 // Device Notification Control Register Offset\r
#define XHC_CRCR_OFFSET                    0x0018 // Command Ring Control Register Offset\r
#define XHC_DCBAAP_OFFSET                  0x0030 // Device Context Base Address Array Pointer Register Offset\r
#define XHC_CONFIG_OFFSET                  0x0038 // Configure Register Offset\r
#define XHC_PORTSC_OFFSET                  0x0400 // Port Status and Control Register Offset\r
\r
//\r
// Runtime registers offset\r
//\r
#define XHC_MFINDEX_OFFSET                 0x00 // Microframe Index Register Offset\r
#define XHC_IMAN_OFFSET                    0x20 // Interrupter X Management Register Offset\r
#define XHC_IMOD_OFFSET                    0x24 // Interrupter X Moderation Register Offset\r
#define XHC_ERSTSZ_OFFSET                  0x28 // Event Ring Segment Table Size Register Offset\r
#define XHC_ERSTBA_OFFSET                  0x30 // Event Ring Segment Table Base Address Register Offset\r
#define XHC_ERDP_OFFSET                    0x38 // Event Ring Dequeue Pointer Register Offset\r
\r
//\r
// Debug registers offset\r
//\r
#define XHC_DC_DCCTRL                      0x20\r
\r
#define USBLEGSP_BIOS_SEMAPHORE            BIT16 // HC BIOS Owned Semaphore\r
#define USBLEGSP_OS_SEMAPHORE              BIT24 // HC OS Owned Semaphore\r
\r
#pragma pack (1)\r
typedef struct {\r
  UINT8                   MaxSlots;       // Number of Device Slots\r
  UINT16                  MaxIntrs:11;    // Number of Interrupters\r
  UINT16                  Rsvd:5;\r
  UINT8                   MaxPorts;       // Number of Ports\r
} HCSPARAMS1;\r
\r
//\r
// Structural Parameters 1 Register Bitmap Definition\r
//\r
typedef union {\r
  UINT32                  Dword;\r
  HCSPARAMS1              Data;\r
} XHC_HCSPARAMS1;\r
\r
typedef struct {\r
  UINT32                  Ist:4;          // Isochronous Scheduling Threshold\r
  UINT32                  Erst:4;         // Event Ring Segment Table Max\r
  UINT32                  Rsvd:13;\r
  UINT32                  ScratchBufHi:5; // Max Scratchpad Buffers Hi\r
  UINT32                  Spr:1;          // Scratchpad Restore\r
  UINT32                  ScratchBufLo:5; // Max Scratchpad Buffers Lo\r
} HCSPARAMS2;\r
\r
//\r
// Structural Parameters 2 Register Bitmap Definition\r
//\r
typedef union {\r
  UINT32                  Dword;\r
  HCSPARAMS2              Data;\r
} XHC_HCSPARAMS2;\r
\r
typedef struct {\r
  UINT16                  Ac64:1;        // 64-bit Addressing Capability\r
  UINT16                  Bnc:1;         // BW Negotiation Capability\r
  UINT16                  Csz:1;         // Context Size\r
  UINT16                  Ppc:1;         // Port Power Control\r
  UINT16                  Pind:1;        // Port Indicators\r
  UINT16                  Lhrc:1;        // Light HC Reset Capability\r
  UINT16                  Ltc:1;         // Latency Tolerance Messaging Capability\r
  UINT16                  Nss:1;         // No Secondary SID Support\r
  UINT16                  Pae:1;         // Parse All Event Data\r
  UINT16                  Rsvd:3;\r
  UINT16                  MaxPsaSize:4;  // Maximum Primary Stream Array Size\r
  UINT16                  ExtCapReg;     // xHCI Extended Capabilities Pointer\r
} HCCPARAMS;\r
\r
//\r
// Capability Parameters Register Bitmap Definition\r
//\r
typedef union {\r
  UINT32                  Dword;\r
  HCCPARAMS               Data;\r
} XHC_HCCPARAMS;\r
\r
#pragma pack ()\r
\r
//\r
// Register Bit Definition\r
//\r
#define XHC_USBCMD_RUN                     BIT0  // Run/Stop\r
#define XHC_USBCMD_RESET                   BIT1  // Host Controller Reset\r
#define XHC_USBCMD_INTE                    BIT2  // Interrupter Enable\r
#define XHC_USBCMD_HSEE                    BIT3  // Host System Error Enable\r
\r
#define XHC_USBSTS_HALT                    BIT0  // Host Controller Halted\r
#define XHC_USBSTS_HSE                     BIT2  // Host System Error\r
#define XHC_USBSTS_EINT                    BIT3  // Event Interrupt\r
#define XHC_USBSTS_PCD                     BIT4  // Port Change Detect\r
#define XHC_USBSTS_SSS                     BIT8  // Save State Status\r
#define XHC_USBSTS_RSS                     BIT9  // Restore State Status\r
#define XHC_USBSTS_SRE                     BIT10 // Save/Restore Error\r
#define XHC_USBSTS_CNR                     BIT11 // Host Controller Not Ready\r
#define XHC_USBSTS_HCE                     BIT12 // Host Controller Error\r
\r
#define XHC_PAGESIZE_MASK                  0xFFFF // Page Size\r
\r
#define XHC_CRCR_RCS                       BIT0  // Ring Cycle State\r
#define XHC_CRCR_CS                        BIT1  // Command Stop\r
#define XHC_CRCR_CA                        BIT2  // Command Abort\r
#define XHC_CRCR_CRR                       BIT3  // Command Ring Running\r
\r
#define XHC_CONFIG_MASK                    0xFF  // Command Ring Running\r
\r
#define XHC_PORTSC_CCS                     BIT0  // Current Connect Status\r
#define XHC_PORTSC_PED                     BIT1  // Port Enabled/Disabled\r
#define XHC_PORTSC_OCA                     BIT3  // Over-current Active\r
#define XHC_PORTSC_RESET                   BIT4  // Port Reset\r
#define XHC_PORTSC_PLS                     (BIT5|BIT6|BIT7|BIT8)     // Port Link State\r
#define XHC_PORTSC_PP                      BIT9  // Port Power\r
#define XHC_PORTSC_PS                      (BIT10|BIT11|BIT12)       // Port Speed\r
#define XHC_PORTSC_LWS                     BIT16 // Port Link State Write Strobe\r
#define XHC_PORTSC_CSC                     BIT17 // Connect Status Change\r
#define XHC_PORTSC_PEC                     BIT18 // Port Enabled/Disabled Change\r
#define XHC_PORTSC_WRC                     BIT19 // Warm Port Reset Change\r
#define XHC_PORTSC_OCC                     BIT20 // Over-Current Change\r
#define XHC_PORTSC_PRC                     BIT21 // Port Reset Change\r
#define XHC_PORTSC_PLC                     BIT22 // Port Link State Change\r
#define XHC_PORTSC_CEC                     BIT23 // Port Config Error Change\r
#define XHC_PORTSC_CAS                     BIT24 // Cold Attach Status\r
\r
#define XHC_HUB_PORTSC_CCS                 BIT0  // Hub's Current Connect Status\r
#define XHC_HUB_PORTSC_PED                 BIT1  // Hub's Port Enabled/Disabled\r
#define XHC_HUB_PORTSC_OCA                 BIT3  // Hub's Over-current Active\r
#define XHC_HUB_PORTSC_RESET               BIT4  // Hub's Port Reset\r
#define XHC_HUB_PORTSC_PP                  BIT9  // Hub's Port Power\r
#define XHC_HUB_PORTSC_CSC                 BIT16 // Hub's Connect Status Change\r
#define XHC_HUB_PORTSC_PEC                 BIT17 // Hub's Port Enabled/Disabled Change\r
#define XHC_HUB_PORTSC_OCC                 BIT19 // Hub's Over-Current Change\r
#define XHC_HUB_PORTSC_PRC                 BIT20 // Hub's Port Reset Change\r
#define XHC_HUB_PORTSC_BHRC                BIT21 // Hub's Port Warm Reset Change\r
#define XHC_IMAN_IP                        BIT0  // Interrupt Pending\r
#define XHC_IMAN_IE                        BIT1  // Interrupt Enable\r
\r
#define XHC_IMODI_MASK                     0x0000FFFF  // Interrupt Moderation Interval\r
#define XHC_IMODC_MASK                     0xFFFF0000  // Interrupt Moderation Counter\r
\r
//\r
//  Hub Class Feature Selector for Clear Port Feature Request\r
//  It's the extension of hub class feature selector of USB 2.0 in USB 3.0 Spec.\r
//  For more details, Please refer to USB 3.0 Spec Table 10-7.\r
//\r
typedef enum {\r
  Usb3PortBHPortReset          = 28,\r
  Usb3PortBHPortResetChange    = 29\r
} XHC_PORT_FEATURE;\r
\r
//\r
// Structure to map the hardware port states to the\r
// UEFI's port states.\r
//\r
typedef struct {\r
  UINT32                  HwState;\r
  UINT16                  UefiState;\r
} USB_PORT_STATE_MAP;\r
\r
//\r
// Structure to map the hardware port states to feature selector for clear port feature request.\r
//\r
typedef struct {\r
  UINT32                  HwState;\r
  UINT16                  Selector;\r
} USB_CLEAR_PORT_MAP;\r
\r
/**\r
  Read 1-byte width XHCI capability register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the 1-byte width capability register.\r
\r
  @return The register content read.\r
  @retval If err, return 0xFFFF.\r
\r
**/\r
UINT8\r
XhcReadCapReg8 (\r
  IN  USB_XHCI_INSTANCE   *Xhc,\r
  IN  UINT32              Offset\r
  );\r
\r
/**\r
  Read 4-bytes width XHCI capability register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the 4-bytes width capability register.\r
\r
  @return The register content read.\r
  @retval If err, return 0xFFFFFFFF.\r
\r
**/\r
UINT32\r
XhcReadCapReg (\r
  IN  USB_XHCI_INSTANCE   *Xhc,\r
  IN  UINT32              Offset\r
  );\r
\r
/**\r
  Read 4-bytes width XHCI Operational register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the 4-bytes width operational register.\r
\r
  @return The register content read.\r
  @retval If err, return 0xFFFFFFFF.\r
\r
**/\r
UINT32\r
XhcReadOpReg (\r
  IN  USB_XHCI_INSTANCE   *Xhc,\r
  IN  UINT32              Offset\r
  );\r
\r
/**\r
  Write the data to the 4-bytes width XHCI operational register.\r
\r
  @param  Xhc      The XHCI Instance.\r
  @param  Offset   The offset of the 4-bytes width operational register.\r
  @param  Data     The data to write.\r
\r
**/\r
VOID\r
XhcWriteOpReg (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Data\r
  );\r
\r
\r
/**\r
  Read XHCI runtime register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
\r
  @return The register content read\r
\r
**/\r
UINT32\r
XhcReadRuntimeReg (\r
  IN  USB_XHCI_INSTANCE   *Xhc,\r
  IN  UINT32              Offset\r
  );\r
\r
/**\r
  Write the data to the XHCI runtime register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
  @param  Data         The data to write.\r
\r
**/\r
VOID\r
XhcWriteRuntimeReg (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Data\r
  );\r
\r
\r
/**\r
  Write the data to the XHCI door bell register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the door bell register.\r
  @param  Data         The data to write.\r
\r
**/\r
VOID\r
XhcWriteDoorBellReg (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Data\r
  );\r
\r
/**\r
  Set one bit of the operational register while keeping other bits.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the operational register.\r
  @param  Bit          The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcSetOpRegBit (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit\r
  );\r
\r
/**\r
  Clear one bit of the operational register while keeping other bits.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the operational register.\r
  @param  Bit          The bit mask of the register to clear.\r
\r
**/\r
VOID\r
XhcClearOpRegBit (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit\r
  );\r
\r
/**\r
  Wait the operation register's bit as specified by Bit\r
  to be set (or clear).\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the operational register.\r
  @param  Bit          The bit of the register to wait for.\r
  @param  WaitToSet    Wait the bit to set or clear.\r
  @param  Timeout      The time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS  The bit successfully changed by host controller.\r
  @retval EFI_TIMEOUT  The time out occurred.\r
\r
**/\r
EFI_STATUS\r
XhcWaitOpRegBit (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit,\r
  IN BOOLEAN              WaitToSet,\r
  IN UINT32               Timeout\r
  );\r
\r
/**\r
  Read XHCI runtime register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
\r
  @return The register content read\r
\r
**/\r
UINT32\r
XhcReadRuntimeReg (\r
  IN  USB_XHCI_INSTANCE   *Xhc,\r
  IN  UINT32              Offset\r
  );\r
\r
/**\r
  Write the data to the XHCI runtime register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
  @param  Data         The data to write.\r
\r
**/\r
VOID\r
XhcWriteRuntimeReg (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Data\r
  );\r
\r
/**\r
  Set one bit of the runtime register while keeping other bits.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
  @param  Bit          The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcSetRuntimeRegBit (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit\r
  );\r
\r
/**\r
  Clear one bit of the runtime register while keeping other bits.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
  @param  Bit          The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcClearRuntimeRegBit (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Offset,\r
  IN UINT32               Bit\r
  );\r
\r
/**\r
  Read XHCI extended capability register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the extended capability register.\r
\r
  @return The register content read\r
\r
**/\r
UINT32\r
XhcReadExtCapReg (\r
  IN  USB_XHCI_INSTANCE   *Xhc,\r
  IN  UINT32              Offset\r
  );\r
\r
/**\r
  Whether the XHCI host controller is halted.\r
\r
  @param  Xhc     The XHCI Instance.\r
\r
  @retval TRUE    The controller is halted.\r
  @retval FALSE   It isn't halted.\r
\r
**/\r
BOOLEAN\r
XhcIsHalt (\r
  IN USB_XHCI_INSTANCE    *Xhc\r
  );\r
\r
/**\r
  Whether system error occurred.\r
\r
  @param  Xhc      The XHCI Instance.\r
\r
  @retval TRUE     System error happened.\r
  @retval FALSE    No system error.\r
\r
**/\r
BOOLEAN\r
XhcIsSysError (\r
  IN USB_XHCI_INSTANCE    *Xhc\r
  );\r
\r
/**\r
  Reset the XHCI host controller.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS  The XHCI host controller is reset.\r
  @return Others       Failed to reset the XHCI before Timeout.\r
\r
**/\r
EFI_STATUS\r
XhcResetHC (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Timeout\r
  );\r
\r
/**\r
  Halt the XHCI host controller.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
\r
  @return EFI_SUCCESS  The XHCI host controller is halt.\r
  @return EFI_TIMEOUT  Failed to halt the XHCI before Timeout.\r
\r
**/\r
EFI_STATUS\r
XhcHaltHC (\r
  IN USB_XHCI_INSTANCE   *Xhc,\r
  IN UINT32              Timeout\r
  );\r
\r
/**\r
  Set the XHCI host controller to run.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
\r
  @return EFI_SUCCESS  The XHCI host controller is running.\r
  @return EFI_TIMEOUT  Failed to set the XHCI to run before Timeout.\r
\r
**/\r
EFI_STATUS\r
XhcRunHC (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT32               Timeout\r
  );\r
\r
/**\r
  Calculate the offset of the XHCI capability.\r
\r
  @param  Xhc     The XHCI Instance.\r
  @param  CapId   The XHCI Capability ID.\r
\r
  @return The offset of XHCI legacy support capability register.\r
\r
**/\r
UINT32\r
XhcGetCapabilityAddr (\r
  IN USB_XHCI_INSTANCE    *Xhc,\r
  IN UINT8                CapId\r
  );\r
\r
#endif\r
Commit	Line	Data
92870c98	1	/** @file\r
	2	\r
	3	This file contains the register definition of XHCI host controller.\r
	4	\r
2f6ef874	5	Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR>\r
92870c98	6	This program and the accompanying materials\r
	7	are licensed and made available under the terms and conditions of the BSD License\r
	8	which accompanies this distribution. The full text of the license may be found at\r
	9	http://opensource.org/licenses/bsd-license.php\r
	10	\r
	11	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	\r
	14	**/\r
	15	\r
	16	#ifndef _EFI_XHCI_REG_H_\r
	17	#define _EFI_XHCI_REG_H_\r
	18	\r
	19	#define PCI_IF_XHCI 0x30\r
	20	\r
	21	//\r
	22	// PCI Configuration Registers\r
	23	//\r
	24	#define XHC_BAR_INDEX 0x00\r
	25	\r
	26	#define XHC_PCI_BAR_OFFSET 0x10 // Memory Bar Register Offset\r
	27	#define XHC_PCI_BAR_MASK 0xFFFF // Memory Base Address Mask\r
	28	\r
fed6cf25 SZ	29	#define XHC_PCI_SBRN_OFFSET 0x60 // Serial Bus Release Number Register Offset\r
fed6cf25 SZ	30	\r
92870c98	31	#define USB_HUB_CLASS_CODE 0x09\r
	32	#define USB_HUB_SUBCLASS_CODE 0x00\r
	33	\r
5bcb62a4 EL	34	#define XHC_CAP_USB_LEGACY 0x01\r
	35	#define XHC_CAP_USB_DEBUG 0x0A\r
	36	\r
92870c98	37	//============================================//\r
	38	// XHCI register offset //\r
	39	//============================================//\r
	40	\r
	41	//\r
	42	// Capability registers offset\r
	43	//\r
	44	#define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset\r
	45	#define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h\r
	46	#define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1\r
	47	#define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2\r
	48	#define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3\r
	49	#define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters\r
	50	#define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset\r
	51	#define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset\r
	52	\r
	53	//\r
	54	// Operational registers offset\r
	55	//\r
	56	#define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset\r
	57	#define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset\r
	58	#define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset\r
	59	#define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset\r
	60	#define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset\r
	61	#define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset\r
	62	#define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset\r
	63	#define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset\r
	64	\r
	65	//\r
	66	// Runtime registers offset\r
	67	//\r
	68	#define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset\r
	69	#define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset\r
	70	#define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset\r
	71	#define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset\r
	72	#define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset\r
	73	#define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset\r
	74	\r
5bcb62a4 EL	75	//\r
	76	// Debug registers offset\r
	77	//\r
	78	#define XHC_DC_DCCTRL 0x20\r
	79	\r
92870c98	80	#define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore\r
	81	#define USBLEGSP_OS_SEMAPHORE BIT24 // HC OS Owned Semaphore\r
	82	\r
	83	#pragma pack (1)\r
a9292c13	84	typedef struct {\r
	85	UINT8 MaxSlots; // Number of Device Slots\r
	86	UINT16 MaxIntrs:11; // Number of Interrupters\r
	87	UINT16 Rsvd:5;\r
	88	UINT8 MaxPorts; // Number of Ports\r
	89	} HCSPARAMS1;\r
	90	\r
92870c98	91	//\r
	92	// Structural Parameters 1 Register Bitmap Definition\r
	93	//\r
a9292c13	94	typedef union {\r
	95	UINT32 Dword;\r
	96	HCSPARAMS1 Data;\r
92870c98	97	} XHC_HCSPARAMS1;\r
92870c98	98	\r
a9292c13	99	typedef struct {\r
	100	UINT32 Ist:4; // Isochronous Scheduling Threshold\r
	101	UINT32 Erst:4; // Event Ring Segment Table Max\r
	102	UINT32 Rsvd:13;\r
	103	UINT32 ScratchBufHi:5; // Max Scratchpad Buffers Hi\r
	104	UINT32 Spr:1; // Scratchpad Restore\r
	105	UINT32 ScratchBufLo:5; // Max Scratchpad Buffers Lo\r
	106	} HCSPARAMS2;\r
	107	\r
92870c98	108	//\r
	109	// Structural Parameters 2 Register Bitmap Definition\r
	110	//\r
a9292c13	111	typedef union {\r
	112	UINT32 Dword;\r
	113	HCSPARAMS2 Data;\r
92870c98	114	} XHC_HCSPARAMS2;\r
92870c98	115	\r
a9292c13	116	typedef struct {\r
	117	UINT16 Ac64:1; // 64-bit Addressing Capability\r
	118	UINT16 Bnc:1; // BW Negotiation Capability\r
	119	UINT16 Csz:1; // Context Size\r
	120	UINT16 Ppc:1; // Port Power Control\r
	121	UINT16 Pind:1; // Port Indicators\r
	122	UINT16 Lhrc:1; // Light HC Reset Capability\r
	123	UINT16 Ltc:1; // Latency Tolerance Messaging Capability\r
	124	UINT16 Nss:1; // No Secondary SID Support\r
	125	UINT16 Pae:1; // Parse All Event Data\r
	126	UINT16 Rsvd:3;\r
	127	UINT16 MaxPsaSize:4; // Maximum Primary Stream Array Size\r
	128	UINT16 ExtCapReg; // xHCI Extended Capabilities Pointer\r
	129	} HCCPARAMS;\r
	130	\r
92870c98	131	//\r
	132	// Capability Parameters Register Bitmap Definition\r
	133	//\r
a9292c13	134	typedef union {\r
	135	UINT32 Dword;\r
	136	HCCPARAMS Data;\r
92870c98	137	} XHC_HCCPARAMS;\r
	138	\r
	139	#pragma pack ()\r
	140	\r
	141	//\r
	142	// Register Bit Definition\r
	143	//\r
	144	#define XHC_USBCMD_RUN BIT0 // Run/Stop\r
	145	#define XHC_USBCMD_RESET BIT1 // Host Controller Reset\r
	146	#define XHC_USBCMD_INTE BIT2 // Interrupter Enable\r
	147	#define XHC_USBCMD_HSEE BIT3 // Host System Error Enable\r
	148	\r
	149	#define XHC_USBSTS_HALT BIT0 // Host Controller Halted\r
	150	#define XHC_USBSTS_HSE BIT2 // Host System Error\r
	151	#define XHC_USBSTS_EINT BIT3 // Event Interrupt\r
	152	#define XHC_USBSTS_PCD BIT4 // Port Change Detect\r
	153	#define XHC_USBSTS_SSS BIT8 // Save State Status\r
	154	#define XHC_USBSTS_RSS BIT9 // Restore State Status\r
	155	#define XHC_USBSTS_SRE BIT10 // Save/Restore Error\r
	156	#define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready\r
	157	#define XHC_USBSTS_HCE BIT12 // Host Controller Error\r
	158	\r
	159	#define XHC_PAGESIZE_MASK 0xFFFF // Page Size\r
	160	\r
	161	#define XHC_CRCR_RCS BIT0 // Ring Cycle State\r
	162	#define XHC_CRCR_CS BIT1 // Command Stop\r
	163	#define XHC_CRCR_CA BIT2 // Command Abort\r
	164	#define XHC_CRCR_CRR BIT3 // Command Ring Running\r
	165	\r
	166	#define XHC_CONFIG_MASK 0xFF // Command Ring Running\r
	167	\r
	168	#define XHC_PORTSC_CCS BIT0 // Current Connect Status\r
	169	#define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled\r
	170	#define XHC_PORTSC_OCA BIT3 // Over-current Active\r
	171	#define XHC_PORTSC_RESET BIT4 // Port Reset\r
	172	#define XHC_PORTSC_PLS (BIT5\|BIT6\|BIT7\|BIT8) // Port Link State\r
	173	#define XHC_PORTSC_PP BIT9 // Port Power\r
c3f44a77	174	#define XHC_PORTSC_PS (BIT10\|BIT11\|BIT12) // Port Speed\r
92870c98	175	#define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe\r
	176	#define XHC_PORTSC_CSC BIT17 // Connect Status Change\r
	177	#define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change\r
	178	#define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change\r
	179	#define XHC_PORTSC_OCC BIT20 // Over-Current Change\r
	180	#define XHC_PORTSC_PRC BIT21 // Port Reset Change\r
	181	#define XHC_PORTSC_PLC BIT22 // Port Link State Change\r
	182	#define XHC_PORTSC_CEC BIT23 // Port Config Error Change\r
	183	#define XHC_PORTSC_CAS BIT24 // Cold Attach Status\r
	184	\r
a50f7c4c	185	#define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status\r
	186	#define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled\r
	187	#define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active\r
	188	#define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset\r
	189	#define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power\r
	190	#define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change\r
	191	#define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change\r
	192	#define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change\r
	193	#define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change\r
c3f44a77	194	#define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change\r
92870c98	195	#define XHC_IMAN_IP BIT0 // Interrupt Pending\r
	196	#define XHC_IMAN_IE BIT1 // Interrupt Enable\r
	197	\r
	198	#define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval\r
	199	#define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter\r
	200	\r
c3f44a77 FT	201	//\r
c3f44a77 FT	202	// Hub Class Feature Selector for Clear Port Feature Request\r
8d84dbe9 FT	203	// It's the extension of hub class feature selector of USB 2.0 in USB 3.0 Spec.\r
8d84dbe9 FT	204	// For more details, Please refer to USB 3.0 Spec Table 10-7.\r
c3f44a77	205	//\r
8d84dbe9 FT	206	typedef enum {\r
	207	Usb3PortBHPortReset = 28,\r
	208	Usb3PortBHPortResetChange = 29\r
	209	} XHC_PORT_FEATURE;\r
c3f44a77	210	\r
92870c98	211	//\r
	212	// Structure to map the hardware port states to the\r
	213	// UEFI's port states.\r
	214	//\r
	215	typedef struct {\r
	216	UINT32 HwState;\r
	217	UINT16 UefiState;\r
	218	} USB_PORT_STATE_MAP;\r
	219	\r
c3f44a77 FT	220	//\r
	221	// Structure to map the hardware port states to feature selector for clear port feature request.\r
	222	//\r
	223	typedef struct {\r
	224	UINT32 HwState;\r
	225	UINT16 Selector;\r
	226	} USB_CLEAR_PORT_MAP;\r
	227	\r
92870c98	228	/**\r
	229	Read 1-byte width XHCI capability register.\r
	230	\r
a9292c13	231	@param Xhc The XHCI Instance.\r
92870c98	232	@param Offset The offset of the 1-byte width capability register.\r
	233	\r
	234	@return The register content read.\r
	235	@retval If err, return 0xFFFF.\r
	236	\r
	237	**/\r
	238	UINT8\r
	239	XhcReadCapReg8 (\r
a9292c13	240	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	241	IN UINT32 Offset\r
	242	);\r
	243	\r
	244	/**\r
	245	Read 4-bytes width XHCI capability register.\r
	246	\r
a9292c13	247	@param Xhc The XHCI Instance.\r
92870c98	248	@param Offset The offset of the 4-bytes width capability register.\r
	249	\r
	250	@return The register content read.\r
	251	@retval If err, return 0xFFFFFFFF.\r
	252	\r
	253	**/\r
	254	UINT32\r
	255	XhcReadCapReg (\r
a9292c13	256	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	257	IN UINT32 Offset\r
	258	);\r
	259	\r
	260	/**\r
	261	Read 4-bytes width XHCI Operational register.\r
	262	\r
a9292c13	263	@param Xhc The XHCI Instance.\r
92870c98	264	@param Offset The offset of the 4-bytes width operational register.\r
	265	\r
	266	@return The register content read.\r
	267	@retval If err, return 0xFFFFFFFF.\r
	268	\r
	269	**/\r
	270	UINT32\r
	271	XhcReadOpReg (\r
a9292c13	272	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	273	IN UINT32 Offset\r
	274	);\r
	275	\r
	276	/**\r
	277	Write the data to the 4-bytes width XHCI operational register.\r
	278	\r
a9292c13	279	@param Xhc The XHCI Instance.\r
92870c98	280	@param Offset The offset of the 4-bytes width operational register.\r
	281	@param Data The data to write.\r
	282	\r
	283	**/\r
	284	VOID\r
	285	XhcWriteOpReg (\r
a9292c13	286	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	287	IN UINT32 Offset,\r
	288	IN UINT32 Data\r
	289	);\r
	290	\r
92870c98	291	\r
92870c98	292	/**\r
	293	Read XHCI runtime register.\r
	294	\r
a9292c13	295	@param Xhc The XHCI Instance.\r
92870c98	296	@param Offset The offset of the runtime register.\r
	297	\r
	298	@return The register content read\r
	299	\r
	300	**/\r
	301	UINT32\r
	302	XhcReadRuntimeReg (\r
a9292c13	303	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	304	IN UINT32 Offset\r
	305	);\r
	306	\r
92870c98	307	/**\r
	308	Write the data to the XHCI runtime register.\r
	309	\r
a9292c13	310	@param Xhc The XHCI Instance.\r
92870c98	311	@param Offset The offset of the runtime register.\r
	312	@param Data The data to write.\r
	313	\r
	314	**/\r
	315	VOID\r
	316	XhcWriteRuntimeReg (\r
a9292c13	317	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	318	IN UINT32 Offset,\r
	319	IN UINT32 Data\r
	320	);\r
	321	\r
92870c98	322	\r
	323	/**\r
	324	Write the data to the XHCI door bell register.\r
	325	\r
a9292c13	326	@param Xhc The XHCI Instance.\r
92870c98	327	@param Offset The offset of the door bell register.\r
	328	@param Data The data to write.\r
	329	\r
	330	**/\r
	331	VOID\r
	332	XhcWriteDoorBellReg (\r
a9292c13	333	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	334	IN UINT32 Offset,\r
	335	IN UINT32 Data\r
	336	);\r
	337	\r
	338	/**\r
	339	Set one bit of the operational register while keeping other bits.\r
	340	\r
a9292c13	341	@param Xhc The XHCI Instance.\r
92870c98	342	@param Offset The offset of the operational register.\r
	343	@param Bit The bit mask of the register to set.\r
	344	\r
	345	**/\r
	346	VOID\r
	347	XhcSetOpRegBit (\r
a9292c13	348	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	349	IN UINT32 Offset,\r
	350	IN UINT32 Bit\r
	351	);\r
	352	\r
	353	/**\r
	354	Clear one bit of the operational register while keeping other bits.\r
	355	\r
a9292c13	356	@param Xhc The XHCI Instance.\r
92870c98	357	@param Offset The offset of the operational register.\r
	358	@param Bit The bit mask of the register to clear.\r
	359	\r
	360	**/\r
	361	VOID\r
	362	XhcClearOpRegBit (\r
a9292c13	363	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	364	IN UINT32 Offset,\r
	365	IN UINT32 Bit\r
	366	);\r
	367	\r
	368	/**\r
	369	Wait the operation register's bit as specified by Bit\r
	370	to be set (or clear).\r
	371	\r
a9292c13	372	@param Xhc The XHCI Instance.\r
92870c98	373	@param Offset The offset of the operational register.\r
	374	@param Bit The bit of the register to wait for.\r
	375	@param WaitToSet Wait the bit to set or clear.\r
2f6ef874	376	@param Timeout The time to wait before abort (in millisecond, ms).\r
92870c98	377	\r
	378	@retval EFI_SUCCESS The bit successfully changed by host controller.\r
	379	@retval EFI_TIMEOUT The time out occurred.\r
	380	\r
	381	**/\r
	382	EFI_STATUS\r
	383	XhcWaitOpRegBit (\r
a9292c13	384	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	385	IN UINT32 Offset,\r
	386	IN UINT32 Bit,\r
	387	IN BOOLEAN WaitToSet,\r
	388	IN UINT32 Timeout\r
	389	);\r
	390	\r
	391	/**\r
	392	Read XHCI runtime register.\r
	393	\r
a9292c13	394	@param Xhc The XHCI Instance.\r
92870c98	395	@param Offset The offset of the runtime register.\r
	396	\r
	397	@return The register content read\r
	398	\r
	399	**/\r
	400	UINT32\r
	401	XhcReadRuntimeReg (\r
a9292c13	402	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	403	IN UINT32 Offset\r
	404	);\r
	405	\r
	406	/**\r
	407	Write the data to the XHCI runtime register.\r
	408	\r
a9292c13	409	@param Xhc The XHCI Instance.\r
92870c98	410	@param Offset The offset of the runtime register.\r
	411	@param Data The data to write.\r
	412	\r
	413	**/\r
	414	VOID\r
	415	XhcWriteRuntimeReg (\r
a9292c13	416	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	417	IN UINT32 Offset,\r
	418	IN UINT32 Data\r
	419	);\r
	420	\r
	421	/**\r
	422	Set one bit of the runtime register while keeping other bits.\r
	423	\r
a9292c13	424	@param Xhc The XHCI Instance.\r
92870c98	425	@param Offset The offset of the runtime register.\r
	426	@param Bit The bit mask of the register to set.\r
	427	\r
	428	**/\r
	429	VOID\r
	430	XhcSetRuntimeRegBit (\r
a9292c13	431	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	432	IN UINT32 Offset,\r
	433	IN UINT32 Bit\r
	434	);\r
	435	\r
	436	/**\r
	437	Clear one bit of the runtime register while keeping other bits.\r
	438	\r
a9292c13	439	@param Xhc The XHCI Instance.\r
92870c98	440	@param Offset The offset of the runtime register.\r
	441	@param Bit The bit mask of the register to set.\r
	442	\r
	443	**/\r
	444	VOID\r
	445	XhcClearRuntimeRegBit (\r
a9292c13	446	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	447	IN UINT32 Offset,\r
	448	IN UINT32 Bit\r
	449	);\r
	450	\r
5bcb62a4 EL	451	/**\r
	452	Read XHCI extended capability register.\r
	453	\r
	454	@param Xhc The XHCI Instance.\r
	455	@param Offset The offset of the extended capability register.\r
	456	\r
	457	@return The register content read\r
	458	\r
	459	**/\r
	460	UINT32\r
	461	XhcReadExtCapReg (\r
	462	IN USB_XHCI_INSTANCE *Xhc,\r
	463	IN UINT32 Offset\r
	464	);\r
	465	\r
92870c98	466	/**\r
	467	Whether the XHCI host controller is halted.\r
	468	\r
a9292c13	469	@param Xhc The XHCI Instance.\r
92870c98	470	\r
	471	@retval TRUE The controller is halted.\r
	472	@retval FALSE It isn't halted.\r
	473	\r
	474	**/\r
	475	BOOLEAN\r
	476	XhcIsHalt (\r
a9292c13	477	IN USB_XHCI_INSTANCE *Xhc\r
92870c98	478	);\r
	479	\r
	480	/**\r
	481	Whether system error occurred.\r
	482	\r
a9292c13	483	@param Xhc The XHCI Instance.\r
92870c98	484	\r
	485	@retval TRUE System error happened.\r
	486	@retval FALSE No system error.\r
	487	\r
	488	**/\r
	489	BOOLEAN\r
	490	XhcIsSysError (\r
a9292c13	491	IN USB_XHCI_INSTANCE *Xhc\r
92870c98	492	);\r
	493	\r
	494	/**\r
	495	Reset the XHCI host controller.\r
	496	\r
a9292c13	497	@param Xhc The XHCI Instance.\r
2f6ef874	498	@param Timeout Time to wait before abort (in millisecond, ms).\r
92870c98	499	\r
	500	@retval EFI_SUCCESS The XHCI host controller is reset.\r
	501	@return Others Failed to reset the XHCI before Timeout.\r
	502	\r
	503	**/\r
	504	EFI_STATUS\r
	505	XhcResetHC (\r
a9292c13	506	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	507	IN UINT32 Timeout\r
	508	);\r
	509	\r
	510	/**\r
	511	Halt the XHCI host controller.\r
	512	\r
a9292c13	513	@param Xhc The XHCI Instance.\r
2f6ef874	514	@param Timeout Time to wait before abort (in millisecond, ms).\r
92870c98	515	\r
	516	@return EFI_SUCCESS The XHCI host controller is halt.\r
	517	@return EFI_TIMEOUT Failed to halt the XHCI before Timeout.\r
	518	\r
	519	**/\r
	520	EFI_STATUS\r
	521	XhcHaltHC (\r
a9292c13	522	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	523	IN UINT32 Timeout\r
	524	);\r
	525	\r
	526	/**\r
	527	Set the XHCI host controller to run.\r
	528	\r
a9292c13	529	@param Xhc The XHCI Instance.\r
2f6ef874	530	@param Timeout Time to wait before abort (in millisecond, ms).\r
92870c98	531	\r
	532	@return EFI_SUCCESS The XHCI host controller is running.\r
	533	@return EFI_TIMEOUT Failed to set the XHCI to run before Timeout.\r
	534	\r
	535	**/\r
	536	EFI_STATUS\r
	537	XhcRunHC (\r
a9292c13	538	IN USB_XHCI_INSTANCE *Xhc,\r
92870c98	539	IN UINT32 Timeout\r
	540	);\r
	541	\r
	542	/**\r
5bcb62a4	543	Calculate the offset of the XHCI capability.\r
92870c98	544	\r
a9292c13	545	@param Xhc The XHCI Instance.\r
5bcb62a4	546	@param CapId The XHCI Capability ID.\r
92870c98	547	\r
	548	@return The offset of XHCI legacy support capability register.\r
	549	\r
	550	**/\r
	551	UINT32\r
5bcb62a4 EL	552	XhcGetCapabilityAddr (\r
	553	IN USB_XHCI_INSTANCE *Xhc,\r
	554	IN UINT8 CapId\r
92870c98	555	);\r
	556	\r
	557	#endif\r