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Commit | Line | Data |
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92870c98 | 1 | /** @file\r |
2 | \r | |
3 | This file contains the register definition of XHCI host controller.\r | |
4 | \r | |
4a723d3d | 5 | Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>\r |
9d510e61 | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
92870c98 | 7 | \r |
8 | **/\r | |
9 | \r | |
10 | #ifndef _EFI_XHCI_REG_H_\r | |
11 | #define _EFI_XHCI_REG_H_\r | |
12 | \r | |
1436aea4 | 13 | #define PCI_IF_XHCI 0x30\r |
92870c98 | 14 | \r |
15 | //\r | |
16 | // PCI Configuration Registers\r | |
17 | //\r | |
1436aea4 | 18 | #define XHC_BAR_INDEX 0x00\r |
92870c98 | 19 | \r |
1436aea4 MK |
20 | #define XHC_PCI_BAR_OFFSET 0x10 // Memory Bar Register Offset\r |
21 | #define XHC_PCI_BAR_MASK 0xFFFF // Memory Base Address Mask\r | |
92870c98 | 22 | \r |
1436aea4 | 23 | #define XHC_PCI_SBRN_OFFSET 0x60 // Serial Bus Release Number Register Offset\r |
fed6cf25 | 24 | \r |
1436aea4 MK |
25 | #define USB_HUB_CLASS_CODE 0x09\r |
26 | #define USB_HUB_SUBCLASS_CODE 0x00\r | |
92870c98 | 27 | \r |
7f4eca4c IC |
28 | #define XHC_CAP_USB_LEGACY 0x01\r |
29 | #define XHC_CAP_USB_DEBUG 0x0A\r | |
30 | #define XHC_CAP_USB_SUPPORTED_PROTOCOL 0x02\r | |
5bcb62a4 | 31 | \r |
1436aea4 | 32 | // ============================================//\r |
92870c98 | 33 | // XHCI register offset //\r |
1436aea4 | 34 | // ============================================//\r |
92870c98 | 35 | \r |
36 | //\r | |
37 | // Capability registers offset\r | |
38 | //\r | |
1436aea4 MK |
39 | #define XHC_CAPLENGTH_OFFSET 0x00 // Capability register length offset\r |
40 | #define XHC_HCIVERSION_OFFSET 0x02 // Interface Version Number 02-03h\r | |
41 | #define XHC_HCSPARAMS1_OFFSET 0x04 // Structural Parameters 1\r | |
42 | #define XHC_HCSPARAMS2_OFFSET 0x08 // Structural Parameters 2\r | |
43 | #define XHC_HCSPARAMS3_OFFSET 0x0c // Structural Parameters 3\r | |
44 | #define XHC_HCCPARAMS_OFFSET 0x10 // Capability Parameters\r | |
45 | #define XHC_DBOFF_OFFSET 0x14 // Doorbell Offset\r | |
46 | #define XHC_RTSOFF_OFFSET 0x18 // Runtime Register Space Offset\r | |
92870c98 | 47 | \r |
48 | //\r | |
49 | // Operational registers offset\r | |
50 | //\r | |
1436aea4 MK |
51 | #define XHC_USBCMD_OFFSET 0x0000 // USB Command Register Offset\r |
52 | #define XHC_USBSTS_OFFSET 0x0004 // USB Status Register Offset\r | |
53 | #define XHC_PAGESIZE_OFFSET 0x0008 // USB Page Size Register Offset\r | |
54 | #define XHC_DNCTRL_OFFSET 0x0014 // Device Notification Control Register Offset\r | |
55 | #define XHC_CRCR_OFFSET 0x0018 // Command Ring Control Register Offset\r | |
56 | #define XHC_DCBAAP_OFFSET 0x0030 // Device Context Base Address Array Pointer Register Offset\r | |
57 | #define XHC_CONFIG_OFFSET 0x0038 // Configure Register Offset\r | |
58 | #define XHC_PORTSC_OFFSET 0x0400 // Port Status and Control Register Offset\r | |
92870c98 | 59 | \r |
60 | //\r | |
61 | // Runtime registers offset\r | |
62 | //\r | |
1436aea4 MK |
63 | #define XHC_MFINDEX_OFFSET 0x00 // Microframe Index Register Offset\r |
64 | #define XHC_IMAN_OFFSET 0x20 // Interrupter X Management Register Offset\r | |
65 | #define XHC_IMOD_OFFSET 0x24 // Interrupter X Moderation Register Offset\r | |
66 | #define XHC_ERSTSZ_OFFSET 0x28 // Event Ring Segment Table Size Register Offset\r | |
67 | #define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset\r | |
68 | #define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset\r | |
92870c98 | 69 | \r |
5bcb62a4 EL |
70 | //\r |
71 | // Debug registers offset\r | |
72 | //\r | |
1436aea4 | 73 | #define XHC_DC_DCCTRL 0x20\r |
5bcb62a4 | 74 | \r |
1436aea4 MK |
75 | #define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore\r |
76 | #define USBLEGSP_OS_SEMAPHORE BIT24 // HC OS Owned Semaphore\r | |
92870c98 | 77 | \r |
7f4eca4c IC |
78 | //\r |
79 | // xHCI Supported Protocol Capability\r | |
80 | //\r | |
81 | #define XHC_SUPPORTED_PROTOCOL_DW0_MAJOR_REVISION_USB2 0x02\r | |
82 | #define XHC_SUPPORTED_PROTOCOL_DW0_MAJOR_REVISION_USB3 0x03\r | |
83 | #define XHC_SUPPORTED_PROTOCOL_NAME_STRING_OFFSET 0x04\r | |
84 | #define XHC_SUPPORTED_PROTOCOL_NAME_STRING_VALUE 0x20425355\r | |
85 | #define XHC_SUPPORTED_PROTOCOL_DW2_OFFSET 0x08\r | |
86 | #define XHC_SUPPORTED_PROTOCOL_PSI_OFFSET 0x10\r | |
87 | #define XHC_SUPPORTED_PROTOCOL_USB2_HIGH_SPEED_PSIM 480\r | |
88 | #define XHC_SUPPORTED_PROTOCOL_USB2_LOW_SPEED_PSIM 1500\r | |
89 | \r | |
92870c98 | 90 | #pragma pack (1)\r |
a9292c13 | 91 | typedef struct {\r |
1436aea4 MK |
92 | UINT8 MaxSlots; // Number of Device Slots\r |
93 | UINT16 MaxIntrs : 11; // Number of Interrupters\r | |
94 | UINT16 Rsvd : 5;\r | |
95 | UINT8 MaxPorts; // Number of Ports\r | |
a9292c13 | 96 | } HCSPARAMS1;\r |
97 | \r | |
92870c98 | 98 | //\r |
99 | // Structural Parameters 1 Register Bitmap Definition\r | |
100 | //\r | |
a9292c13 | 101 | typedef union {\r |
1436aea4 MK |
102 | UINT32 Dword;\r |
103 | HCSPARAMS1 Data;\r | |
92870c98 | 104 | } XHC_HCSPARAMS1;\r |
105 | \r | |
a9292c13 | 106 | typedef struct {\r |
1436aea4 MK |
107 | UINT32 Ist : 4; // Isochronous Scheduling Threshold\r |
108 | UINT32 Erst : 4; // Event Ring Segment Table Max\r | |
109 | UINT32 Rsvd : 13;\r | |
110 | UINT32 ScratchBufHi : 5; // Max Scratchpad Buffers Hi\r | |
111 | UINT32 Spr : 1; // Scratchpad Restore\r | |
112 | UINT32 ScratchBufLo : 5; // Max Scratchpad Buffers Lo\r | |
a9292c13 | 113 | } HCSPARAMS2;\r |
114 | \r | |
92870c98 | 115 | //\r |
116 | // Structural Parameters 2 Register Bitmap Definition\r | |
117 | //\r | |
a9292c13 | 118 | typedef union {\r |
1436aea4 MK |
119 | UINT32 Dword;\r |
120 | HCSPARAMS2 Data;\r | |
92870c98 | 121 | } XHC_HCSPARAMS2;\r |
122 | \r | |
a9292c13 | 123 | typedef struct {\r |
1436aea4 MK |
124 | UINT16 Ac64 : 1; // 64-bit Addressing Capability\r |
125 | UINT16 Bnc : 1; // BW Negotiation Capability\r | |
126 | UINT16 Csz : 1; // Context Size\r | |
127 | UINT16 Ppc : 1; // Port Power Control\r | |
128 | UINT16 Pind : 1; // Port Indicators\r | |
129 | UINT16 Lhrc : 1; // Light HC Reset Capability\r | |
130 | UINT16 Ltc : 1; // Latency Tolerance Messaging Capability\r | |
131 | UINT16 Nss : 1; // No Secondary SID Support\r | |
132 | UINT16 Pae : 1; // Parse All Event Data\r | |
133 | UINT16 Rsvd : 3;\r | |
134 | UINT16 MaxPsaSize : 4; // Maximum Primary Stream Array Size\r | |
135 | UINT16 ExtCapReg; // xHCI Extended Capabilities Pointer\r | |
a9292c13 | 136 | } HCCPARAMS;\r |
137 | \r | |
92870c98 | 138 | //\r |
139 | // Capability Parameters Register Bitmap Definition\r | |
140 | //\r | |
a9292c13 | 141 | typedef union {\r |
1436aea4 MK |
142 | UINT32 Dword;\r |
143 | HCCPARAMS Data;\r | |
92870c98 | 144 | } XHC_HCCPARAMS;\r |
145 | \r | |
7f4eca4c IC |
146 | //\r |
147 | // xHCI Supported Protocol Cabability\r | |
148 | //\r | |
149 | typedef struct {\r | |
150 | UINT8 CapId;\r | |
151 | UINT8 NextExtCapReg;\r | |
152 | UINT8 RevMinor;\r | |
153 | UINT8 RevMajor;\r | |
154 | } SUPPORTED_PROTOCOL_DW0;\r | |
155 | \r | |
156 | typedef union {\r | |
157 | UINT32 Dword;\r | |
158 | SUPPORTED_PROTOCOL_DW0 Data;\r | |
159 | } XHC_SUPPORTED_PROTOCOL_DW0;\r | |
160 | \r | |
161 | typedef struct {\r | |
162 | UINT32 NameString;\r | |
163 | } XHC_SUPPORTED_PROTOCOL_DW1;\r | |
164 | \r | |
165 | typedef struct {\r | |
166 | UINT8 CompPortOffset;\r | |
167 | UINT8 CompPortCount;\r | |
168 | UINT16 ProtocolDef : 12;\r | |
169 | UINT16 Psic : 4;\r | |
170 | } SUPPORTED_PROTOCOL_DW2;\r | |
171 | \r | |
172 | typedef union {\r | |
173 | UINT32 Dword;\r | |
174 | SUPPORTED_PROTOCOL_DW2 Data;\r | |
175 | } XHC_SUPPORTED_PROTOCOL_DW2;\r | |
176 | \r | |
177 | typedef struct {\r | |
178 | UINT16 Psiv : 4;\r | |
179 | UINT16 Psie : 2;\r | |
180 | UINT16 Plt : 2;\r | |
181 | UINT16 Pfd : 1;\r | |
182 | UINT16 RsvdP : 5;\r | |
183 | UINT16 Lp : 2;\r | |
184 | UINT16 Psim;\r | |
185 | } SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID;\r | |
186 | \r | |
187 | typedef union {\r | |
188 | UINT32 Dword;\r | |
189 | SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID Data;\r | |
190 | } XHC_SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID;\r | |
191 | \r | |
92870c98 | 192 | #pragma pack ()\r |
193 | \r | |
194 | //\r | |
195 | // Register Bit Definition\r | |
196 | //\r | |
1436aea4 MK |
197 | #define XHC_USBCMD_RUN BIT0 // Run/Stop\r |
198 | #define XHC_USBCMD_RESET BIT1 // Host Controller Reset\r | |
199 | #define XHC_USBCMD_INTE BIT2 // Interrupter Enable\r | |
200 | #define XHC_USBCMD_HSEE BIT3 // Host System Error Enable\r | |
201 | \r | |
202 | #define XHC_USBSTS_HALT BIT0 // Host Controller Halted\r | |
203 | #define XHC_USBSTS_HSE BIT2 // Host System Error\r | |
204 | #define XHC_USBSTS_EINT BIT3 // Event Interrupt\r | |
205 | #define XHC_USBSTS_PCD BIT4 // Port Change Detect\r | |
206 | #define XHC_USBSTS_SSS BIT8 // Save State Status\r | |
207 | #define XHC_USBSTS_RSS BIT9 // Restore State Status\r | |
208 | #define XHC_USBSTS_SRE BIT10 // Save/Restore Error\r | |
209 | #define XHC_USBSTS_CNR BIT11 // Host Controller Not Ready\r | |
210 | #define XHC_USBSTS_HCE BIT12 // Host Controller Error\r | |
211 | \r | |
212 | #define XHC_PAGESIZE_MASK 0xFFFF // Page Size\r | |
213 | \r | |
214 | #define XHC_CRCR_RCS BIT0 // Ring Cycle State\r | |
215 | #define XHC_CRCR_CS BIT1 // Command Stop\r | |
216 | #define XHC_CRCR_CA BIT2 // Command Abort\r | |
217 | #define XHC_CRCR_CRR BIT3 // Command Ring Running\r | |
218 | \r | |
219 | #define XHC_CONFIG_MASK 0xFF // Command Ring Running\r | |
220 | \r | |
221 | #define XHC_PORTSC_CCS BIT0 // Current Connect Status\r | |
222 | #define XHC_PORTSC_PED BIT1 // Port Enabled/Disabled\r | |
223 | #define XHC_PORTSC_OCA BIT3 // Over-current Active\r | |
224 | #define XHC_PORTSC_RESET BIT4 // Port Reset\r | |
225 | #define XHC_PORTSC_PLS (BIT5|BIT6|BIT7|BIT8) // Port Link State\r | |
226 | #define XHC_PORTSC_PP BIT9 // Port Power\r | |
227 | #define XHC_PORTSC_PS (BIT10|BIT11|BIT12|BIT13) // Port Speed\r | |
228 | #define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe\r | |
229 | #define XHC_PORTSC_CSC BIT17 // Connect Status Change\r | |
230 | #define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change\r | |
231 | #define XHC_PORTSC_WRC BIT19 // Warm Port Reset Change\r | |
232 | #define XHC_PORTSC_OCC BIT20 // Over-Current Change\r | |
233 | #define XHC_PORTSC_PRC BIT21 // Port Reset Change\r | |
234 | #define XHC_PORTSC_PLC BIT22 // Port Link State Change\r | |
235 | #define XHC_PORTSC_CEC BIT23 // Port Config Error Change\r | |
236 | #define XHC_PORTSC_CAS BIT24 // Cold Attach Status\r | |
237 | \r | |
238 | #define XHC_HUB_PORTSC_CCS BIT0 // Hub's Current Connect Status\r | |
239 | #define XHC_HUB_PORTSC_PED BIT1 // Hub's Port Enabled/Disabled\r | |
240 | #define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active\r | |
241 | #define XHC_HUB_PORTSC_RESET BIT4 // Hub's Port Reset\r | |
242 | #define XHC_HUB_PORTSC_PP BIT9 // Hub's Port Power\r | |
243 | #define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change\r | |
244 | #define XHC_HUB_PORTSC_PEC BIT17 // Hub's Port Enabled/Disabled Change\r | |
245 | #define XHC_HUB_PORTSC_OCC BIT19 // Hub's Over-Current Change\r | |
246 | #define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change\r | |
247 | #define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change\r | |
248 | #define XHC_IMAN_IP BIT0 // Interrupt Pending\r | |
249 | #define XHC_IMAN_IE BIT1 // Interrupt Enable\r | |
250 | \r | |
251 | #define XHC_IMODI_MASK 0x0000FFFF // Interrupt Moderation Interval\r | |
252 | #define XHC_IMODC_MASK 0xFFFF0000 // Interrupt Moderation Counter\r | |
92870c98 | 253 | \r |
c3f44a77 FT |
254 | //\r |
255 | // Hub Class Feature Selector for Clear Port Feature Request\r | |
8d84dbe9 FT |
256 | // It's the extension of hub class feature selector of USB 2.0 in USB 3.0 Spec.\r |
257 | // For more details, Please refer to USB 3.0 Spec Table 10-7.\r | |
c3f44a77 | 258 | //\r |
8d84dbe9 | 259 | typedef enum {\r |
1436aea4 MK |
260 | Usb3PortBHPortReset = 28,\r |
261 | Usb3PortBHPortResetChange = 29\r | |
8d84dbe9 | 262 | } XHC_PORT_FEATURE;\r |
c3f44a77 | 263 | \r |
92870c98 | 264 | //\r |
265 | // Structure to map the hardware port states to the\r | |
266 | // UEFI's port states.\r | |
267 | //\r | |
268 | typedef struct {\r | |
1436aea4 MK |
269 | UINT32 HwState;\r |
270 | UINT16 UefiState;\r | |
92870c98 | 271 | } USB_PORT_STATE_MAP;\r |
272 | \r | |
c3f44a77 FT |
273 | //\r |
274 | // Structure to map the hardware port states to feature selector for clear port feature request.\r | |
275 | //\r | |
276 | typedef struct {\r | |
1436aea4 MK |
277 | UINT32 HwState;\r |
278 | UINT16 Selector;\r | |
c3f44a77 FT |
279 | } USB_CLEAR_PORT_MAP;\r |
280 | \r | |
92870c98 | 281 | /**\r |
282 | Read 1-byte width XHCI capability register.\r | |
283 | \r | |
a9292c13 | 284 | @param Xhc The XHCI Instance.\r |
92870c98 | 285 | @param Offset The offset of the 1-byte width capability register.\r |
286 | \r | |
287 | @return The register content read.\r | |
288 | @retval If err, return 0xFFFF.\r | |
289 | \r | |
290 | **/\r | |
291 | UINT8\r | |
292 | XhcReadCapReg8 (\r | |
1436aea4 MK |
293 | IN USB_XHCI_INSTANCE *Xhc,\r |
294 | IN UINT32 Offset\r | |
92870c98 | 295 | );\r |
296 | \r | |
297 | /**\r | |
298 | Read 4-bytes width XHCI capability register.\r | |
299 | \r | |
a9292c13 | 300 | @param Xhc The XHCI Instance.\r |
92870c98 | 301 | @param Offset The offset of the 4-bytes width capability register.\r |
302 | \r | |
303 | @return The register content read.\r | |
304 | @retval If err, return 0xFFFFFFFF.\r | |
305 | \r | |
306 | **/\r | |
307 | UINT32\r | |
308 | XhcReadCapReg (\r | |
1436aea4 MK |
309 | IN USB_XHCI_INSTANCE *Xhc,\r |
310 | IN UINT32 Offset\r | |
92870c98 | 311 | );\r |
312 | \r | |
313 | /**\r | |
314 | Read 4-bytes width XHCI Operational register.\r | |
315 | \r | |
a9292c13 | 316 | @param Xhc The XHCI Instance.\r |
92870c98 | 317 | @param Offset The offset of the 4-bytes width operational register.\r |
318 | \r | |
319 | @return The register content read.\r | |
320 | @retval If err, return 0xFFFFFFFF.\r | |
321 | \r | |
322 | **/\r | |
323 | UINT32\r | |
324 | XhcReadOpReg (\r | |
1436aea4 MK |
325 | IN USB_XHCI_INSTANCE *Xhc,\r |
326 | IN UINT32 Offset\r | |
92870c98 | 327 | );\r |
328 | \r | |
329 | /**\r | |
330 | Write the data to the 4-bytes width XHCI operational register.\r | |
331 | \r | |
a9292c13 | 332 | @param Xhc The XHCI Instance.\r |
92870c98 | 333 | @param Offset The offset of the 4-bytes width operational register.\r |
334 | @param Data The data to write.\r | |
335 | \r | |
336 | **/\r | |
337 | VOID\r | |
338 | XhcWriteOpReg (\r | |
1436aea4 MK |
339 | IN USB_XHCI_INSTANCE *Xhc,\r |
340 | IN UINT32 Offset,\r | |
341 | IN UINT32 Data\r | |
92870c98 | 342 | );\r |
343 | \r | |
92870c98 | 344 | /**\r |
345 | Read XHCI runtime register.\r | |
346 | \r | |
a9292c13 | 347 | @param Xhc The XHCI Instance.\r |
92870c98 | 348 | @param Offset The offset of the runtime register.\r |
349 | \r | |
350 | @return The register content read\r | |
351 | \r | |
352 | **/\r | |
353 | UINT32\r | |
354 | XhcReadRuntimeReg (\r | |
1436aea4 MK |
355 | IN USB_XHCI_INSTANCE *Xhc,\r |
356 | IN UINT32 Offset\r | |
92870c98 | 357 | );\r |
358 | \r | |
92870c98 | 359 | /**\r |
360 | Write the data to the XHCI runtime register.\r | |
361 | \r | |
a9292c13 | 362 | @param Xhc The XHCI Instance.\r |
92870c98 | 363 | @param Offset The offset of the runtime register.\r |
364 | @param Data The data to write.\r | |
365 | \r | |
366 | **/\r | |
367 | VOID\r | |
368 | XhcWriteRuntimeReg (\r | |
1436aea4 MK |
369 | IN USB_XHCI_INSTANCE *Xhc,\r |
370 | IN UINT32 Offset,\r | |
371 | IN UINT32 Data\r | |
92870c98 | 372 | );\r |
373 | \r | |
92870c98 | 374 | /**\r |
375 | Write the data to the XHCI door bell register.\r | |
376 | \r | |
a9292c13 | 377 | @param Xhc The XHCI Instance.\r |
92870c98 | 378 | @param Offset The offset of the door bell register.\r |
379 | @param Data The data to write.\r | |
380 | \r | |
381 | **/\r | |
382 | VOID\r | |
383 | XhcWriteDoorBellReg (\r | |
1436aea4 MK |
384 | IN USB_XHCI_INSTANCE *Xhc,\r |
385 | IN UINT32 Offset,\r | |
386 | IN UINT32 Data\r | |
92870c98 | 387 | );\r |
388 | \r | |
389 | /**\r | |
390 | Set one bit of the operational register while keeping other bits.\r | |
391 | \r | |
a9292c13 | 392 | @param Xhc The XHCI Instance.\r |
92870c98 | 393 | @param Offset The offset of the operational register.\r |
394 | @param Bit The bit mask of the register to set.\r | |
395 | \r | |
396 | **/\r | |
397 | VOID\r | |
398 | XhcSetOpRegBit (\r | |
1436aea4 MK |
399 | IN USB_XHCI_INSTANCE *Xhc,\r |
400 | IN UINT32 Offset,\r | |
401 | IN UINT32 Bit\r | |
92870c98 | 402 | );\r |
403 | \r | |
404 | /**\r | |
405 | Clear one bit of the operational register while keeping other bits.\r | |
406 | \r | |
a9292c13 | 407 | @param Xhc The XHCI Instance.\r |
92870c98 | 408 | @param Offset The offset of the operational register.\r |
409 | @param Bit The bit mask of the register to clear.\r | |
410 | \r | |
411 | **/\r | |
412 | VOID\r | |
413 | XhcClearOpRegBit (\r | |
1436aea4 MK |
414 | IN USB_XHCI_INSTANCE *Xhc,\r |
415 | IN UINT32 Offset,\r | |
416 | IN UINT32 Bit\r | |
92870c98 | 417 | );\r |
418 | \r | |
419 | /**\r | |
420 | Wait the operation register's bit as specified by Bit\r | |
421 | to be set (or clear).\r | |
422 | \r | |
a9292c13 | 423 | @param Xhc The XHCI Instance.\r |
92870c98 | 424 | @param Offset The offset of the operational register.\r |
425 | @param Bit The bit of the register to wait for.\r | |
426 | @param WaitToSet Wait the bit to set or clear.\r | |
2f6ef874 | 427 | @param Timeout The time to wait before abort (in millisecond, ms).\r |
92870c98 | 428 | \r |
429 | @retval EFI_SUCCESS The bit successfully changed by host controller.\r | |
430 | @retval EFI_TIMEOUT The time out occurred.\r | |
431 | \r | |
432 | **/\r | |
433 | EFI_STATUS\r | |
434 | XhcWaitOpRegBit (\r | |
1436aea4 MK |
435 | IN USB_XHCI_INSTANCE *Xhc,\r |
436 | IN UINT32 Offset,\r | |
437 | IN UINT32 Bit,\r | |
438 | IN BOOLEAN WaitToSet,\r | |
439 | IN UINT32 Timeout\r | |
92870c98 | 440 | );\r |
441 | \r | |
442 | /**\r | |
443 | Read XHCI runtime register.\r | |
444 | \r | |
a9292c13 | 445 | @param Xhc The XHCI Instance.\r |
92870c98 | 446 | @param Offset The offset of the runtime register.\r |
447 | \r | |
448 | @return The register content read\r | |
449 | \r | |
450 | **/\r | |
451 | UINT32\r | |
452 | XhcReadRuntimeReg (\r | |
1436aea4 MK |
453 | IN USB_XHCI_INSTANCE *Xhc,\r |
454 | IN UINT32 Offset\r | |
92870c98 | 455 | );\r |
456 | \r | |
457 | /**\r | |
458 | Write the data to the XHCI runtime register.\r | |
459 | \r | |
a9292c13 | 460 | @param Xhc The XHCI Instance.\r |
92870c98 | 461 | @param Offset The offset of the runtime register.\r |
462 | @param Data The data to write.\r | |
463 | \r | |
464 | **/\r | |
465 | VOID\r | |
466 | XhcWriteRuntimeReg (\r | |
1436aea4 MK |
467 | IN USB_XHCI_INSTANCE *Xhc,\r |
468 | IN UINT32 Offset,\r | |
469 | IN UINT32 Data\r | |
92870c98 | 470 | );\r |
471 | \r | |
472 | /**\r | |
473 | Set one bit of the runtime register while keeping other bits.\r | |
474 | \r | |
a9292c13 | 475 | @param Xhc The XHCI Instance.\r |
92870c98 | 476 | @param Offset The offset of the runtime register.\r |
477 | @param Bit The bit mask of the register to set.\r | |
478 | \r | |
479 | **/\r | |
480 | VOID\r | |
481 | XhcSetRuntimeRegBit (\r | |
1436aea4 MK |
482 | IN USB_XHCI_INSTANCE *Xhc,\r |
483 | IN UINT32 Offset,\r | |
484 | IN UINT32 Bit\r | |
92870c98 | 485 | );\r |
486 | \r | |
487 | /**\r | |
488 | Clear one bit of the runtime register while keeping other bits.\r | |
489 | \r | |
a9292c13 | 490 | @param Xhc The XHCI Instance.\r |
92870c98 | 491 | @param Offset The offset of the runtime register.\r |
492 | @param Bit The bit mask of the register to set.\r | |
493 | \r | |
494 | **/\r | |
495 | VOID\r | |
496 | XhcClearRuntimeRegBit (\r | |
1436aea4 MK |
497 | IN USB_XHCI_INSTANCE *Xhc,\r |
498 | IN UINT32 Offset,\r | |
499 | IN UINT32 Bit\r | |
92870c98 | 500 | );\r |
501 | \r | |
5bcb62a4 EL |
502 | /**\r |
503 | Read XHCI extended capability register.\r | |
504 | \r | |
505 | @param Xhc The XHCI Instance.\r | |
506 | @param Offset The offset of the extended capability register.\r | |
507 | \r | |
508 | @return The register content read\r | |
509 | \r | |
510 | **/\r | |
511 | UINT32\r | |
512 | XhcReadExtCapReg (\r | |
1436aea4 MK |
513 | IN USB_XHCI_INSTANCE *Xhc,\r |
514 | IN UINT32 Offset\r | |
5bcb62a4 EL |
515 | );\r |
516 | \r | |
92870c98 | 517 | /**\r |
518 | Whether the XHCI host controller is halted.\r | |
519 | \r | |
a9292c13 | 520 | @param Xhc The XHCI Instance.\r |
92870c98 | 521 | \r |
522 | @retval TRUE The controller is halted.\r | |
523 | @retval FALSE It isn't halted.\r | |
524 | \r | |
525 | **/\r | |
526 | BOOLEAN\r | |
527 | XhcIsHalt (\r | |
1436aea4 | 528 | IN USB_XHCI_INSTANCE *Xhc\r |
92870c98 | 529 | );\r |
530 | \r | |
531 | /**\r | |
532 | Whether system error occurred.\r | |
533 | \r | |
a9292c13 | 534 | @param Xhc The XHCI Instance.\r |
92870c98 | 535 | \r |
536 | @retval TRUE System error happened.\r | |
537 | @retval FALSE No system error.\r | |
538 | \r | |
539 | **/\r | |
540 | BOOLEAN\r | |
541 | XhcIsSysError (\r | |
1436aea4 | 542 | IN USB_XHCI_INSTANCE *Xhc\r |
92870c98 | 543 | );\r |
544 | \r | |
545 | /**\r | |
546 | Reset the XHCI host controller.\r | |
547 | \r | |
a9292c13 | 548 | @param Xhc The XHCI Instance.\r |
2f6ef874 | 549 | @param Timeout Time to wait before abort (in millisecond, ms).\r |
92870c98 | 550 | \r |
551 | @retval EFI_SUCCESS The XHCI host controller is reset.\r | |
552 | @return Others Failed to reset the XHCI before Timeout.\r | |
553 | \r | |
554 | **/\r | |
555 | EFI_STATUS\r | |
556 | XhcResetHC (\r | |
1436aea4 MK |
557 | IN USB_XHCI_INSTANCE *Xhc,\r |
558 | IN UINT32 Timeout\r | |
92870c98 | 559 | );\r |
560 | \r | |
561 | /**\r | |
562 | Halt the XHCI host controller.\r | |
563 | \r | |
a9292c13 | 564 | @param Xhc The XHCI Instance.\r |
2f6ef874 | 565 | @param Timeout Time to wait before abort (in millisecond, ms).\r |
92870c98 | 566 | \r |
567 | @return EFI_SUCCESS The XHCI host controller is halt.\r | |
568 | @return EFI_TIMEOUT Failed to halt the XHCI before Timeout.\r | |
569 | \r | |
570 | **/\r | |
571 | EFI_STATUS\r | |
572 | XhcHaltHC (\r | |
1436aea4 MK |
573 | IN USB_XHCI_INSTANCE *Xhc,\r |
574 | IN UINT32 Timeout\r | |
92870c98 | 575 | );\r |
576 | \r | |
577 | /**\r | |
578 | Set the XHCI host controller to run.\r | |
579 | \r | |
a9292c13 | 580 | @param Xhc The XHCI Instance.\r |
2f6ef874 | 581 | @param Timeout Time to wait before abort (in millisecond, ms).\r |
92870c98 | 582 | \r |
583 | @return EFI_SUCCESS The XHCI host controller is running.\r | |
584 | @return EFI_TIMEOUT Failed to set the XHCI to run before Timeout.\r | |
585 | \r | |
586 | **/\r | |
587 | EFI_STATUS\r | |
588 | XhcRunHC (\r | |
1436aea4 MK |
589 | IN USB_XHCI_INSTANCE *Xhc,\r |
590 | IN UINT32 Timeout\r | |
92870c98 | 591 | );\r |
592 | \r | |
593 | /**\r | |
5bcb62a4 | 594 | Calculate the offset of the XHCI capability.\r |
92870c98 | 595 | \r |
a9292c13 | 596 | @param Xhc The XHCI Instance.\r |
5bcb62a4 | 597 | @param CapId The XHCI Capability ID.\r |
92870c98 | 598 | \r |
599 | @return The offset of XHCI legacy support capability register.\r | |
600 | \r | |
601 | **/\r | |
602 | UINT32\r | |
5bcb62a4 | 603 | XhcGetCapabilityAddr (\r |
1436aea4 MK |
604 | IN USB_XHCI_INSTANCE *Xhc,\r |
605 | IN UINT8 CapId\r | |
92870c98 | 606 | );\r |
607 | \r | |
7f4eca4c IC |
608 | /**\r |
609 | Calculate the offset of the xHCI Supported Protocol Capability.\r | |
610 | \r | |
611 | @param Xhc The XHCI Instance.\r | |
612 | @param MajorVersion The USB Major Version in xHCI Support Protocol Capability Field\r | |
613 | \r | |
614 | @return The offset of xHCI Supported Protocol capability register.\r | |
615 | \r | |
616 | **/\r | |
617 | UINT32\r | |
618 | XhcGetSupportedProtocolCapabilityAddr (\r | |
619 | IN USB_XHCI_INSTANCE *Xhc,\r | |
620 | IN UINT8 MajorVersion\r | |
621 | );\r | |
622 | \r | |
623 | /**\r | |
ec25e904 | 624 | Find PortSpeed value match case in XHCI Supported Protocol Capability\r |
7f4eca4c | 625 | \r |
ec25e904 SR |
626 | @param Xhc The XHCI Instance.\r |
627 | @param PortSpeed The Port Speed Field in USB PortSc register\r | |
628 | @param PortNumber The Port Number (0-indexed)\r | |
7f4eca4c IC |
629 | \r |
630 | @return The USB Port Speed.\r | |
631 | \r | |
632 | **/\r | |
633 | UINT16\r | |
634 | XhcCheckUsbPortSpeedUsedPsic (\r | |
635 | IN USB_XHCI_INSTANCE *Xhc,\r | |
ec25e904 SR |
636 | IN UINT8 PortSpeed,\r |
637 | IN UINT8 PortNumber\r | |
7f4eca4c IC |
638 | );\r |
639 | \r | |
92870c98 | 640 | #endif\r |