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92870c98 | 1 | /** @file\r |
2 | \r | |
3 | This file contains the definition for XHCI host controller schedule routines.\r | |
4 | \r | |
39e97c39 | 5 | Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.<BR>\r |
92870c98 | 6 | This program and the accompanying materials\r |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #ifndef _EFI_XHCI_SCHED_H_\r | |
17 | #define _EFI_XHCI_SCHED_H_\r | |
18 | \r | |
19 | #define XHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')\r | |
20 | \r | |
21 | //\r | |
22 | // Transfer types, used in URB to identify the transfer type\r | |
23 | //\r | |
24 | #define XHC_CTRL_TRANSFER 0x01\r | |
25 | #define XHC_BULK_TRANSFER 0x02\r | |
26 | #define XHC_INT_TRANSFER_SYNC 0x04\r | |
27 | #define XHC_INT_TRANSFER_ASYNC 0x08\r | |
28 | #define XHC_INT_ONLY_TRANSFER_ASYNC 0x10\r | |
29 | \r | |
30 | //\r | |
31 | // 6.4.6 TRB Types\r | |
32 | //\r | |
33 | #define TRB_TYPE_NORMAL 1\r | |
34 | #define TRB_TYPE_SETUP_STAGE 2\r | |
35 | #define TRB_TYPE_DATA_STAGE 3\r | |
36 | #define TRB_TYPE_STATUS_STAGE 4\r | |
37 | #define TRB_TYPE_ISOCH 5\r | |
38 | #define TRB_TYPE_LINK 6\r | |
39 | #define TRB_TYPE_EVENT_DATA 7\r | |
40 | #define TRB_TYPE_NO_OP 8\r | |
41 | #define TRB_TYPE_EN_SLOT 9\r | |
42 | #define TRB_TYPE_DIS_SLOT 10\r | |
43 | #define TRB_TYPE_ADDRESS_DEV 11\r | |
44 | #define TRB_TYPE_CON_ENDPOINT 12\r | |
45 | #define TRB_TYPE_EVALU_CONTXT 13\r | |
46 | #define TRB_TYPE_RESET_ENDPOINT 14\r | |
47 | #define TRB_TYPE_STOP_ENDPOINT 15\r | |
48 | #define TRB_TYPE_SET_TR_DEQUE 16\r | |
49 | #define TRB_TYPE_RESET_DEV 17\r | |
50 | #define TRB_TYPE_GET_PORT_BANW 21\r | |
51 | #define TRB_TYPE_FORCE_HEADER 22\r | |
52 | #define TRB_TYPE_NO_OP_COMMAND 23\r | |
53 | #define TRB_TYPE_TRANS_EVENT 32\r | |
54 | #define TRB_TYPE_COMMAND_COMPLT_EVENT 33\r | |
55 | #define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34\r | |
56 | #define TRB_TYPE_HOST_CONTROLLER_EVENT 37\r | |
57 | #define TRB_TYPE_DEVICE_NOTIFI_EVENT 38\r | |
58 | #define TRB_TYPE_MFINDEX_WRAP_EVENT 39\r | |
59 | \r | |
60 | //\r | |
61 | // Endpoint Type (EP Type).\r | |
62 | //\r | |
63 | #define ED_NOT_VALID 0\r | |
64 | #define ED_ISOCH_OUT 1\r | |
65 | #define ED_BULK_OUT 2\r | |
66 | #define ED_INTERRUPT_OUT 3\r | |
67 | #define ED_CONTROL_BIDIR 4\r | |
68 | #define ED_ISOCH_IN 5\r | |
69 | #define ED_BULK_IN 6\r | |
70 | #define ED_INTERRUPT_IN 7\r | |
71 | \r | |
72 | //\r | |
73 | // 6.4.5 TRB Completion Codes\r | |
74 | //\r | |
75 | #define TRB_COMPLETION_INVALID 0\r | |
76 | #define TRB_COMPLETION_SUCCESS 1\r | |
77 | #define TRB_COMPLETION_DATA_BUFFER_ERROR 2\r | |
78 | #define TRB_COMPLETION_BABBLE_ERROR 3\r | |
79 | #define TRB_COMPLETION_USB_TRANSACTION_ERROR 4\r | |
80 | #define TRB_COMPLETION_TRB_ERROR 5\r | |
81 | #define TRB_COMPLETION_STALL_ERROR 6\r | |
82 | #define TRB_COMPLETION_SHORT_PACKET 13\r | |
83 | \r | |
84 | //\r | |
a9292c13 | 85 | // The topology string used to present usb device location\r |
92870c98 | 86 | //\r |
a9292c13 | 87 | typedef struct _USB_DEV_TOPOLOGY {\r |
88 | //\r | |
89 | // The tier concatenation of down stream port.\r | |
90 | //\r | |
91 | UINT32 RouteString:20;\r | |
92 | //\r | |
93 | // The root port number of the chain.\r | |
94 | //\r | |
95 | UINT32 RootPortNum:8;\r | |
96 | //\r | |
97 | // The Tier the device reside.\r | |
98 | //\r | |
99 | UINT32 TierNum:4;\r | |
100 | } USB_DEV_TOPOLOGY;\r | |
101 | \r | |
102 | //\r | |
103 | // USB Device's RouteChart\r | |
104 | //\r | |
105 | typedef union _USB_DEV_ROUTE {\r | |
106 | UINT32 Dword;\r | |
107 | USB_DEV_TOPOLOGY Route;\r | |
92870c98 | 108 | } USB_DEV_ROUTE;\r |
109 | \r | |
110 | //\r | |
111 | // Endpoint address and its capabilities\r | |
112 | //\r | |
113 | typedef struct _USB_ENDPOINT {\r | |
6b4483cd | 114 | //\r |
115 | // Store logical device address assigned by UsbBus\r | |
116 | // It's because some XHCI host controllers may assign the same physcial device\r | |
117 | // address for those devices inserted at different root port.\r | |
118 | //\r | |
119 | UINT8 BusAddr;\r | |
92870c98 | 120 | UINT8 DevAddr;\r |
121 | UINT8 EpAddr;\r | |
122 | EFI_USB_DATA_DIRECTION Direction;\r | |
123 | UINT8 DevSpeed;\r | |
124 | UINTN MaxPacket;\r | |
125 | UINTN Type;\r | |
126 | } USB_ENDPOINT;\r | |
127 | \r | |
128 | //\r | |
a9292c13 | 129 | // TRB Template\r |
92870c98 | 130 | //\r |
a9292c13 | 131 | typedef struct _TRB_TEMPLATE {\r |
132 | UINT32 Parameter1;\r | |
133 | \r | |
134 | UINT32 Parameter2;\r | |
135 | \r | |
136 | UINT32 Status;\r | |
137 | \r | |
92870c98 | 138 | UINT32 CycleBit:1;\r |
139 | UINT32 RsvdZ1:9;\r | |
140 | UINT32 Type:6;\r | |
a9292c13 | 141 | UINT32 Control:16;\r |
142 | } TRB_TEMPLATE;\r | |
92870c98 | 143 | \r |
144 | typedef struct _TRANSFER_RING {\r | |
145 | VOID *RingSeg0;\r | |
146 | UINTN TrbNumber;\r | |
a9292c13 | 147 | TRB_TEMPLATE *RingEnqueue;\r |
148 | TRB_TEMPLATE *RingDequeue;\r | |
92870c98 | 149 | UINT32 RingPCS;\r |
150 | } TRANSFER_RING;\r | |
151 | \r | |
152 | typedef struct _EVENT_RING {\r | |
92870c98 | 153 | VOID *ERSTBase;\r |
154 | VOID *EventRingSeg0;\r | |
155 | UINTN TrbNumber;\r | |
a9292c13 | 156 | TRB_TEMPLATE *EventRingEnqueue;\r |
157 | TRB_TEMPLATE *EventRingDequeue;\r | |
92870c98 | 158 | UINT32 EventRingCCS;\r |
159 | } EVENT_RING;\r | |
160 | \r | |
161 | //\r | |
162 | // URB (Usb Request Block) contains information for all kinds of\r | |
163 | // usb requests.\r | |
164 | //\r | |
165 | typedef struct _URB {\r | |
166 | UINT32 Signature;\r | |
167 | LIST_ENTRY UrbList;\r | |
168 | //\r | |
169 | // Usb Device URB related information\r | |
170 | //\r | |
171 | USB_ENDPOINT Ep;\r | |
172 | EFI_USB_DEVICE_REQUEST *Request;\r | |
173 | VOID *Data;\r | |
174 | UINTN DataLen;\r | |
1847ed0b EL |
175 | VOID *DataPhy;\r |
176 | VOID *DataMap;\r | |
92870c98 | 177 | EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;\r |
178 | VOID *Context;\r | |
179 | //\r | |
180 | // Execute result\r | |
181 | //\r | |
182 | UINT32 Result;\r | |
183 | //\r | |
184 | // completed data length\r | |
185 | //\r | |
186 | UINTN Completed;\r | |
187 | //\r | |
188 | // Command/Tranfer Ring info\r | |
189 | //\r | |
190 | TRANSFER_RING *Ring;\r | |
a9292c13 | 191 | TRB_TEMPLATE *TrbStart;\r |
192 | TRB_TEMPLATE *TrbEnd;\r | |
92870c98 | 193 | UINTN TrbNum;\r |
a50f7c4c | 194 | BOOLEAN StartDone;\r |
195 | BOOLEAN EndDone;\r | |
196 | BOOLEAN Finished;\r | |
197 | \r | |
198 | TRB_TEMPLATE *EvtTrb;\r | |
92870c98 | 199 | } URB;\r |
200 | \r | |
92870c98 | 201 | //\r |
202 | // 6.5 Event Ring Segment Table\r | |
203 | // The Event Ring Segment Table is used to define multi-segment Event Rings and to enable runtime\r | |
204 | // expansion and shrinking of the Event Ring. The location of the Event Ring Segment Table is defined by the\r | |
205 | // Event Ring Segment Table Base Address Register (5.5.2.3.2). The size of the Event Ring Segment Table\r | |
206 | // is defined by the Event Ring Segment Table Base Size Register (5.5.2.3.1).\r | |
207 | //\r | |
208 | typedef struct _EVENT_RING_SEG_TABLE_ENTRY {\r | |
209 | UINT32 PtrLo;\r | |
210 | UINT32 PtrHi;\r | |
211 | UINT32 RingTrbSize:16;\r | |
212 | UINT32 RsvdZ1:16;\r | |
213 | UINT32 RsvdZ2;\r | |
214 | } EVENT_RING_SEG_TABLE_ENTRY;\r | |
215 | \r | |
216 | //\r | |
217 | // 6.4.1.1 Normal TRB\r | |
218 | // A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and\r | |
219 | // Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer\r | |
220 | // Rings, and to define the Data stage information for Control Transfer Rings.\r | |
221 | //\r | |
222 | typedef struct _TRANSFER_TRB_NORMAL {\r | |
223 | UINT32 TRBPtrLo;\r | |
a9292c13 | 224 | \r |
92870c98 | 225 | UINT32 TRBPtrHi;\r |
a9292c13 | 226 | \r |
39e97c39 | 227 | UINT32 Length:17;\r |
92870c98 | 228 | UINT32 TDSize:5;\r |
229 | UINT32 IntTarget:10;\r | |
a9292c13 | 230 | \r |
92870c98 | 231 | UINT32 CycleBit:1;\r |
232 | UINT32 ENT:1;\r | |
233 | UINT32 ISP:1;\r | |
234 | UINT32 NS:1;\r | |
235 | UINT32 CH:1;\r | |
236 | UINT32 IOC:1;\r | |
237 | UINT32 IDT:1;\r | |
238 | UINT32 RsvdZ1:2;\r | |
239 | UINT32 BEI:1;\r | |
240 | UINT32 Type:6;\r | |
241 | UINT32 RsvdZ2:16;\r | |
242 | } TRANSFER_TRB_NORMAL;\r | |
243 | \r | |
244 | //\r | |
245 | // 6.4.1.2.1 Setup Stage TRB\r | |
246 | // A Setup Stage TRB is created by system software to initiate a USB Setup packet on a control endpoint.\r | |
247 | //\r | |
a9292c13 | 248 | typedef struct _TRANSFER_TRB_CONTROL_SETUP {\r |
92870c98 | 249 | UINT32 bmRequestType:8;\r |
250 | UINT32 bRequest:8;\r | |
251 | UINT32 wValue:16;\r | |
252 | \r | |
253 | UINT32 wIndex:16;\r | |
254 | UINT32 wLength:16;\r | |
255 | \r | |
39e97c39 | 256 | UINT32 Length:17;\r |
92870c98 | 257 | UINT32 RsvdZ1:5;\r |
258 | UINT32 IntTarget:10;\r | |
259 | \r | |
260 | UINT32 CycleBit:1;\r | |
261 | UINT32 RsvdZ2:4;\r | |
262 | UINT32 IOC:1;\r | |
263 | UINT32 IDT:1;\r | |
264 | UINT32 RsvdZ3:3;\r | |
265 | UINT32 Type:6;\r | |
266 | UINT32 TRT:2;\r | |
267 | UINT32 RsvdZ4:14;\r | |
268 | } TRANSFER_TRB_CONTROL_SETUP;\r | |
269 | \r | |
270 | //\r | |
271 | // 6.4.1.2.2 Data Stage TRB\r | |
272 | // A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.\r | |
273 | //\r | |
274 | typedef struct _TRANSFER_TRB_CONTROL_DATA {\r | |
275 | UINT32 TRBPtrLo;\r | |
a9292c13 | 276 | \r |
92870c98 | 277 | UINT32 TRBPtrHi;\r |
a9292c13 | 278 | \r |
39e97c39 | 279 | UINT32 Length:17;\r |
92870c98 | 280 | UINT32 TDSize:5;\r |
281 | UINT32 IntTarget:10;\r | |
a9292c13 | 282 | \r |
92870c98 | 283 | UINT32 CycleBit:1;\r |
284 | UINT32 ENT:1;\r | |
285 | UINT32 ISP:1;\r | |
286 | UINT32 NS:1;\r | |
287 | UINT32 CH:1;\r | |
288 | UINT32 IOC:1;\r | |
289 | UINT32 IDT:1;\r | |
290 | UINT32 RsvdZ1:3;\r | |
291 | UINT32 Type:6;\r | |
292 | UINT32 DIR:1;\r | |
293 | UINT32 RsvdZ2:15;\r | |
294 | } TRANSFER_TRB_CONTROL_DATA;\r | |
295 | \r | |
296 | //\r | |
297 | // 6.4.1.2.2 Data Stage TRB\r | |
298 | // A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.\r | |
299 | //\r | |
300 | typedef struct _TRANSFER_TRB_CONTROL_STATUS {\r | |
301 | UINT32 RsvdZ1;\r | |
302 | UINT32 RsvdZ2;\r | |
a9292c13 | 303 | \r |
92870c98 | 304 | UINT32 RsvdZ3:22;\r |
305 | UINT32 IntTarget:10;\r | |
a9292c13 | 306 | \r |
92870c98 | 307 | UINT32 CycleBit:1;\r |
308 | UINT32 ENT:1;\r | |
309 | UINT32 RsvdZ4:2;\r | |
310 | UINT32 CH:1;\r | |
311 | UINT32 IOC:1;\r | |
312 | UINT32 RsvdZ5:4;\r | |
313 | UINT32 Type:6;\r | |
314 | UINT32 DIR:1;\r | |
315 | UINT32 RsvdZ6:15;\r | |
316 | } TRANSFER_TRB_CONTROL_STATUS;\r | |
317 | \r | |
318 | //\r | |
319 | // 6.4.2.1 Transfer Event TRB\r | |
320 | // A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1\r | |
321 | // for more information on the use and operation of Transfer Events.\r | |
322 | //\r | |
323 | typedef struct _EVT_TRB_TRANSFER {\r | |
324 | UINT32 TRBPtrLo;\r | |
a9292c13 | 325 | \r |
92870c98 | 326 | UINT32 TRBPtrHi;\r |
a9292c13 | 327 | \r |
39e97c39 | 328 | UINT32 Length:24;\r |
a9292c13 | 329 | UINT32 Completecode:8;\r |
330 | \r | |
92870c98 | 331 | UINT32 CycleBit:1;\r |
332 | UINT32 RsvdZ1:1;\r | |
333 | UINT32 ED:1;\r | |
334 | UINT32 RsvdZ2:7;\r | |
335 | UINT32 Type:6;\r | |
a9292c13 | 336 | UINT32 EndpointId:5;\r |
92870c98 | 337 | UINT32 RsvdZ3:3;\r |
338 | UINT32 SlotId:8;\r | |
339 | } EVT_TRB_TRANSFER;\r | |
340 | \r | |
341 | //\r | |
342 | // 6.4.2.2 Command Completion Event TRB\r | |
343 | // A Command Completion Event TRB shall be generated by the xHC when a command completes on the\r | |
344 | // Command Ring. Refer to section 4.11.4 for more information on the use of Command Completion Events.\r | |
345 | //\r | |
a9292c13 | 346 | typedef struct _EVT_TRB_COMMAND_COMPLETION {\r |
92870c98 | 347 | UINT32 TRBPtrLo;\r |
a9292c13 | 348 | \r |
92870c98 | 349 | UINT32 TRBPtrHi;\r |
a9292c13 | 350 | \r |
92870c98 | 351 | UINT32 RsvdZ2:24;\r |
a9292c13 | 352 | UINT32 Completecode:8;\r |
353 | \r | |
92870c98 | 354 | UINT32 CycleBit:1;\r |
355 | UINT32 RsvdZ3:9;\r | |
356 | UINT32 Type:6;\r | |
357 | UINT32 VFID:8;\r | |
358 | UINT32 SlotId:8;\r | |
a9292c13 | 359 | } EVT_TRB_COMMAND_COMPLETION;\r |
360 | \r | |
361 | typedef union _TRB {\r | |
362 | TRB_TEMPLATE TrbTemplate;\r | |
363 | TRANSFER_TRB_NORMAL TrbNormal;\r | |
364 | TRANSFER_TRB_CONTROL_SETUP TrbCtrSetup;\r | |
365 | TRANSFER_TRB_CONTROL_DATA TrbCtrData;\r | |
366 | TRANSFER_TRB_CONTROL_STATUS TrbCtrStatus;\r | |
367 | } TRB;\r | |
92870c98 | 368 | \r |
369 | //\r | |
370 | // 6.4.3.1 No Op Command TRB\r | |
371 | // The No Op Command TRB provides a simple means for verifying the operation of the Command Ring\r | |
a9292c13 | 372 | // mechanisms offered by the xHCI.\r |
92870c98 | 373 | //\r |
374 | typedef struct _CMD_TRB_NO_OP {\r | |
375 | UINT32 RsvdZ0;\r | |
376 | UINT32 RsvdZ1;\r | |
377 | UINT32 RsvdZ2;\r | |
a9292c13 | 378 | \r |
92870c98 | 379 | UINT32 CycleBit:1;\r |
380 | UINT32 RsvdZ3:9;\r | |
381 | UINT32 Type:6;\r | |
382 | UINT32 RsvdZ4:16;\r | |
383 | } CMD_TRB_NO_OP;\r | |
384 | \r | |
385 | //\r | |
386 | // 6.4.3.2 Enable Slot Command TRB\r | |
387 | // The Enable Slot Command TRB causes the xHC to select an available Device Slot and return the ID of the\r | |
388 | // selected slot to the host in a Command Completion Event.\r | |
389 | //\r | |
a9292c13 | 390 | typedef struct _CMD_TRB_ENABLE_SLOT {\r |
92870c98 | 391 | UINT32 RsvdZ0;\r |
392 | UINT32 RsvdZ1;\r | |
393 | UINT32 RsvdZ2;\r | |
a9292c13 | 394 | \r |
92870c98 | 395 | UINT32 CycleBit:1;\r |
396 | UINT32 RsvdZ3:9;\r | |
397 | UINT32 Type:6;\r | |
398 | UINT32 RsvdZ4:16;\r | |
a9292c13 | 399 | } CMD_TRB_ENABLE_SLOT;\r |
92870c98 | 400 | \r |
401 | //\r | |
402 | // 6.4.3.3 Disable Slot Command TRB\r | |
403 | // The Disable Slot Command TRB releases any bandwidth assigned to the disabled slot and frees any\r | |
404 | // internal xHC resources assigned to the slot.\r | |
405 | //\r | |
a9292c13 | 406 | typedef struct _CMD_TRB_DISABLE_SLOT {\r |
92870c98 | 407 | UINT32 RsvdZ0;\r |
408 | UINT32 RsvdZ1;\r | |
409 | UINT32 RsvdZ2;\r | |
a9292c13 | 410 | \r |
92870c98 | 411 | UINT32 CycleBit:1;\r |
412 | UINT32 RsvdZ3:9;\r | |
413 | UINT32 Type:6;\r | |
414 | UINT32 RsvdZ4:8;\r | |
415 | UINT32 SlotId:8;\r | |
a9292c13 | 416 | } CMD_TRB_DISABLE_SLOT;\r |
92870c98 | 417 | \r |
418 | //\r | |
419 | // 6.4.3.4 Address Device Command TRB\r | |
420 | // The Address Device Command TRB transitions the selected Device Context from the Default to the\r | |
421 | // Addressed state and causes the xHC to select an address for the USB device in the Default State and\r | |
422 | // issue a SET_ADDRESS request to the USB device.\r | |
423 | //\r | |
a9292c13 | 424 | typedef struct _CMD_TRB_ADDRESS_DEVICE {\r |
92870c98 | 425 | UINT32 PtrLo;\r |
a9292c13 | 426 | \r |
92870c98 | 427 | UINT32 PtrHi;\r |
a9292c13 | 428 | \r |
92870c98 | 429 | UINT32 RsvdZ1;\r |
a9292c13 | 430 | \r |
92870c98 | 431 | UINT32 CycleBit:1;\r |
432 | UINT32 RsvdZ2:8;\r | |
433 | UINT32 BSR:1;\r | |
434 | UINT32 Type:6;\r | |
435 | UINT32 RsvdZ3:8;\r | |
436 | UINT32 SlotId:8;\r | |
a9292c13 | 437 | } CMD_TRB_ADDRESS_DEVICE;\r |
92870c98 | 438 | \r |
439 | //\r | |
440 | // 6.4.3.5 Configure Endpoint Command TRB\r | |
441 | // The Configure Endpoint Command TRB evaluates the bandwidth and resource requirements of the\r | |
442 | // endpoints selected by the command.\r | |
443 | //\r | |
a9292c13 | 444 | typedef struct _CMD_TRB_CONFIG_ENDPOINT {\r |
92870c98 | 445 | UINT32 PtrLo;\r |
a9292c13 | 446 | \r |
92870c98 | 447 | UINT32 PtrHi;\r |
a9292c13 | 448 | \r |
92870c98 | 449 | UINT32 RsvdZ1;\r |
a9292c13 | 450 | \r |
92870c98 | 451 | UINT32 CycleBit:1;\r |
452 | UINT32 RsvdZ2:8;\r | |
453 | UINT32 DC:1;\r | |
454 | UINT32 Type:6;\r | |
455 | UINT32 RsvdZ3:8;\r | |
456 | UINT32 SlotId:8;\r | |
a9292c13 | 457 | } CMD_TRB_CONFIG_ENDPOINT;\r |
92870c98 | 458 | \r |
459 | //\r | |
460 | // 6.4.3.6 Evaluate Context Command TRB\r | |
461 | // The Evaluate Context Command TRB is used by system software to inform the xHC that the selected\r | |
462 | // Context data structures in the Device Context have been modified by system software and that the xHC\r | |
463 | // shall evaluate any changes\r | |
464 | //\r | |
a9292c13 | 465 | typedef struct _CMD_TRB_EVALUATE_CONTEXT {\r |
92870c98 | 466 | UINT32 PtrLo;\r |
a9292c13 | 467 | \r |
92870c98 | 468 | UINT32 PtrHi;\r |
a9292c13 | 469 | \r |
92870c98 | 470 | UINT32 RsvdZ1;\r |
a9292c13 | 471 | \r |
92870c98 | 472 | UINT32 CycleBit:1;\r |
473 | UINT32 RsvdZ2:9;\r | |
474 | UINT32 Type:6;\r | |
475 | UINT32 RsvdZ3:8;\r | |
476 | UINT32 SlotId:8;\r | |
a9292c13 | 477 | } CMD_TRB_EVALUATE_CONTEXT;\r |
92870c98 | 478 | \r |
479 | //\r | |
480 | // 6.4.3.7 Reset Endpoint Command TRB\r | |
481 | // The Reset Endpoint Command TRB is used by system software to reset a specified Transfer Ring\r | |
482 | //\r | |
a9292c13 | 483 | typedef struct _CMD_TRB_RESET_ENDPOINT {\r |
92870c98 | 484 | UINT32 RsvdZ0;\r |
485 | UINT32 RsvdZ1;\r | |
486 | UINT32 RsvdZ2;\r | |
a9292c13 | 487 | \r |
92870c98 | 488 | UINT32 CycleBit:1;\r |
489 | UINT32 RsvdZ3:8;\r | |
490 | UINT32 TSP:1;\r | |
491 | UINT32 Type:6;\r | |
492 | UINT32 EDID:5;\r | |
493 | UINT32 RsvdZ4:3;\r | |
494 | UINT32 SlotId:8;\r | |
a9292c13 | 495 | } CMD_TRB_RESET_ENDPOINT;\r |
92870c98 | 496 | \r |
497 | //\r | |
498 | // 6.4.3.8 Stop Endpoint Command TRB\r | |
499 | // The Stop Endpoint Command TRB command allows software to stop the xHC execution of the TDs on a\r | |
500 | // Transfer Ring and temporarily take ownership of TDs that had previously been passed to the xHC.\r | |
501 | //\r | |
a9292c13 | 502 | typedef struct _CMD_TRB_STOP_ENDPOINT {\r |
92870c98 | 503 | UINT32 RsvdZ0;\r |
504 | UINT32 RsvdZ1;\r | |
505 | UINT32 RsvdZ2;\r | |
a9292c13 | 506 | \r |
92870c98 | 507 | UINT32 CycleBit:1;\r |
508 | UINT32 RsvdZ3:9;\r | |
509 | UINT32 Type:6;\r | |
510 | UINT32 EDID:5;\r | |
511 | UINT32 RsvdZ4:2;\r | |
512 | UINT32 SP:1;\r | |
513 | UINT32 SlotId:8;\r | |
a9292c13 | 514 | } CMD_TRB_STOP_ENDPOINT;\r |
92870c98 | 515 | \r |
516 | //\r | |
517 | // 6.4.3.9 Set TR Dequeue Pointer Command TRB\r | |
518 | // The Set TR Dequeue Pointer Command TRB is used by system software to modify the TR Dequeue\r | |
519 | // Pointer and DCS fields of an Endpoint or Stream Context.\r | |
520 | //\r | |
a9292c13 | 521 | typedef struct _CMD_SET_TR_DEQ_POINTER {\r |
92870c98 | 522 | UINT32 PtrLo;\r |
a9292c13 | 523 | \r |
92870c98 | 524 | UINT32 PtrHi;\r |
a9292c13 | 525 | \r |
92870c98 | 526 | UINT32 RsvdZ1:16;\r |
527 | UINT32 StreamID:16;\r | |
a9292c13 | 528 | \r |
92870c98 | 529 | UINT32 CycleBit:1;\r |
530 | UINT32 RsvdZ2:9;\r | |
531 | UINT32 Type:6;\r | |
532 | UINT32 Endpoint:5;\r | |
533 | UINT32 RsvdZ3:3;\r | |
534 | UINT32 SlotId:8;\r | |
a9292c13 | 535 | } CMD_SET_TR_DEQ_POINTER;\r |
92870c98 | 536 | \r |
537 | //\r | |
a9292c13 | 538 | // 6.4.4.1 Link TRB\r |
92870c98 | 539 | // A Link TRB provides support for non-contiguous TRB Rings.\r |
540 | //\r | |
a9292c13 | 541 | typedef struct _LINK_TRB {\r |
92870c98 | 542 | UINT32 PtrLo;\r |
a9292c13 | 543 | \r |
92870c98 | 544 | UINT32 PtrHi;\r |
a9292c13 | 545 | \r |
92870c98 | 546 | UINT32 RsvdZ1:22;\r |
547 | UINT32 InterTarget:10;\r | |
a9292c13 | 548 | \r |
92870c98 | 549 | UINT32 CycleBit:1;\r |
550 | UINT32 TC:1;\r | |
551 | UINT32 RsvdZ2:2;\r | |
552 | UINT32 CH:1;\r | |
553 | UINT32 IOC:1;\r | |
554 | UINT32 RsvdZ3:4;\r | |
555 | UINT32 Type:6;\r | |
556 | UINT32 RsvdZ4:16;\r | |
a9292c13 | 557 | } LINK_TRB;\r |
92870c98 | 558 | \r |
559 | //\r | |
560 | // 6.2.2 Slot Context\r | |
561 | //\r | |
562 | typedef struct _SLOT_CONTEXT {\r | |
a9292c13 | 563 | UINT32 RouteString:20;\r |
92870c98 | 564 | UINT32 Speed:4;\r |
565 | UINT32 RsvdZ1:1;\r | |
566 | UINT32 MTT:1;\r | |
567 | UINT32 Hub:1;\r | |
568 | UINT32 ContextEntries:5;\r | |
569 | \r | |
570 | UINT32 MaxExitLatency:16;\r | |
571 | UINT32 RootHubPortNum:8;\r | |
572 | UINT32 PortNum:8;\r | |
573 | \r | |
574 | UINT32 TTHubSlotId:8;\r | |
575 | UINT32 TTPortNum:8;\r | |
576 | UINT32 TTT:2;\r | |
577 | UINT32 RsvdZ2:4;\r | |
578 | UINT32 InterTarget:10;\r | |
579 | \r | |
580 | UINT32 DeviceAddress:8;\r | |
581 | UINT32 RsvdZ3:19;\r | |
582 | UINT32 SlotState:5;\r | |
583 | \r | |
584 | UINT32 RsvdZ4;\r | |
585 | UINT32 RsvdZ5;\r | |
586 | UINT32 RsvdZ6;\r | |
587 | UINT32 RsvdZ7;\r | |
588 | } SLOT_CONTEXT;\r | |
589 | \r | |
6b4483cd | 590 | typedef struct _SLOT_CONTEXT_64 {\r |
591 | UINT32 RouteString:20;\r | |
592 | UINT32 Speed:4;\r | |
593 | UINT32 RsvdZ1:1;\r | |
594 | UINT32 MTT:1;\r | |
595 | UINT32 Hub:1;\r | |
596 | UINT32 ContextEntries:5;\r | |
597 | \r | |
598 | UINT32 MaxExitLatency:16;\r | |
599 | UINT32 RootHubPortNum:8;\r | |
600 | UINT32 PortNum:8;\r | |
601 | \r | |
602 | UINT32 TTHubSlotId:8;\r | |
603 | UINT32 TTPortNum:8;\r | |
604 | UINT32 TTT:2;\r | |
605 | UINT32 RsvdZ2:4;\r | |
606 | UINT32 InterTarget:10;\r | |
607 | \r | |
608 | UINT32 DeviceAddress:8;\r | |
609 | UINT32 RsvdZ3:19;\r | |
610 | UINT32 SlotState:5;\r | |
611 | \r | |
612 | UINT32 RsvdZ4;\r | |
613 | UINT32 RsvdZ5;\r | |
614 | UINT32 RsvdZ6;\r | |
615 | UINT32 RsvdZ7;\r | |
616 | \r | |
617 | UINT32 RsvdZ8;\r | |
618 | UINT32 RsvdZ9;\r | |
619 | UINT32 RsvdZ10;\r | |
620 | UINT32 RsvdZ11;\r | |
621 | \r | |
622 | UINT32 RsvdZ12;\r | |
623 | UINT32 RsvdZ13;\r | |
624 | UINT32 RsvdZ14;\r | |
625 | UINT32 RsvdZ15;\r | |
626 | \r | |
627 | } SLOT_CONTEXT_64;\r | |
628 | \r | |
629 | \r | |
92870c98 | 630 | //\r |
631 | // 6.2.3 Endpoint Context\r | |
632 | //\r | |
633 | typedef struct _ENDPOINT_CONTEXT {\r | |
634 | UINT32 EPState:3;\r | |
635 | UINT32 RsvdZ1:5;\r | |
636 | UINT32 Mult:2;\r | |
637 | UINT32 MaxPStreams:5;\r | |
638 | UINT32 LSA:1;\r | |
639 | UINT32 Interval:8;\r | |
640 | UINT32 RsvdZ2:8;\r | |
641 | \r | |
642 | UINT32 RsvdZ3:1;\r | |
643 | UINT32 CErr:2;\r | |
644 | UINT32 EPType:3;\r | |
645 | UINT32 RsvdZ4:1;\r | |
646 | UINT32 HID:1;\r | |
647 | UINT32 MaxBurstSize:8;\r | |
648 | UINT32 MaxPacketSize:16;\r | |
649 | \r | |
650 | UINT32 PtrLo;\r | |
651 | \r | |
652 | UINT32 PtrHi;\r | |
653 | \r | |
654 | UINT32 AverageTRBLength:16;\r | |
655 | UINT32 MaxESITPayload:16;\r | |
656 | \r | |
657 | UINT32 RsvdZ5;\r | |
658 | UINT32 RsvdZ6;\r | |
659 | UINT32 RsvdZ7;\r | |
660 | } ENDPOINT_CONTEXT;\r | |
661 | \r | |
6b4483cd | 662 | typedef struct _ENDPOINT_CONTEXT_64 {\r |
663 | UINT32 EPState:3;\r | |
664 | UINT32 RsvdZ1:5;\r | |
665 | UINT32 Mult:2;\r | |
666 | UINT32 MaxPStreams:5;\r | |
667 | UINT32 LSA:1;\r | |
668 | UINT32 Interval:8;\r | |
669 | UINT32 RsvdZ2:8;\r | |
670 | \r | |
671 | UINT32 RsvdZ3:1;\r | |
672 | UINT32 CErr:2;\r | |
673 | UINT32 EPType:3;\r | |
674 | UINT32 RsvdZ4:1;\r | |
675 | UINT32 HID:1;\r | |
676 | UINT32 MaxBurstSize:8;\r | |
677 | UINT32 MaxPacketSize:16;\r | |
678 | \r | |
679 | UINT32 PtrLo;\r | |
680 | \r | |
681 | UINT32 PtrHi;\r | |
682 | \r | |
683 | UINT32 AverageTRBLength:16;\r | |
684 | UINT32 MaxESITPayload:16;\r | |
685 | \r | |
686 | UINT32 RsvdZ5;\r | |
687 | UINT32 RsvdZ6;\r | |
688 | UINT32 RsvdZ7;\r | |
689 | \r | |
690 | UINT32 RsvdZ8;\r | |
691 | UINT32 RsvdZ9;\r | |
692 | UINT32 RsvdZ10;\r | |
693 | UINT32 RsvdZ11;\r | |
694 | \r | |
695 | UINT32 RsvdZ12;\r | |
696 | UINT32 RsvdZ13;\r | |
697 | UINT32 RsvdZ14;\r | |
698 | UINT32 RsvdZ15;\r | |
699 | \r | |
700 | } ENDPOINT_CONTEXT_64;\r | |
701 | \r | |
702 | \r | |
92870c98 | 703 | //\r |
704 | // 6.2.5.1 Input Control Context\r | |
705 | //\r | |
706 | typedef struct _INPUT_CONTRL_CONTEXT {\r | |
707 | UINT32 Dword1;\r | |
708 | UINT32 Dword2;\r | |
709 | UINT32 RsvdZ1;\r | |
710 | UINT32 RsvdZ2;\r | |
711 | UINT32 RsvdZ3;\r | |
712 | UINT32 RsvdZ4;\r | |
713 | UINT32 RsvdZ5;\r | |
714 | UINT32 RsvdZ6;\r | |
715 | } INPUT_CONTRL_CONTEXT;\r | |
716 | \r | |
6b4483cd | 717 | typedef struct _INPUT_CONTRL_CONTEXT_64 {\r |
718 | UINT32 Dword1;\r | |
719 | UINT32 Dword2;\r | |
720 | UINT32 RsvdZ1;\r | |
721 | UINT32 RsvdZ2;\r | |
722 | UINT32 RsvdZ3;\r | |
723 | UINT32 RsvdZ4;\r | |
724 | UINT32 RsvdZ5;\r | |
725 | UINT32 RsvdZ6;\r | |
726 | UINT32 RsvdZ7;\r | |
727 | UINT32 RsvdZ8;\r | |
728 | UINT32 RsvdZ9;\r | |
729 | UINT32 RsvdZ10;\r | |
730 | UINT32 RsvdZ11;\r | |
731 | UINT32 RsvdZ12;\r | |
732 | UINT32 RsvdZ13;\r | |
733 | UINT32 RsvdZ14;\r | |
734 | } INPUT_CONTRL_CONTEXT_64;\r | |
735 | \r | |
92870c98 | 736 | //\r |
737 | // 6.2.1 Device Context\r | |
738 | //\r | |
739 | typedef struct _DEVICE_CONTEXT {\r | |
740 | SLOT_CONTEXT Slot;\r | |
741 | ENDPOINT_CONTEXT EP[31];\r | |
742 | } DEVICE_CONTEXT;\r | |
743 | \r | |
6b4483cd | 744 | typedef struct _DEVICE_CONTEXT_64 {\r |
745 | SLOT_CONTEXT_64 Slot;\r | |
746 | ENDPOINT_CONTEXT_64 EP[31];\r | |
747 | } DEVICE_CONTEXT_64;\r | |
748 | \r | |
92870c98 | 749 | //\r |
750 | // 6.2.5 Input Context\r | |
751 | //\r | |
752 | typedef struct _INPUT_CONTEXT {\r | |
753 | INPUT_CONTRL_CONTEXT InputControlContext;\r | |
754 | SLOT_CONTEXT Slot;\r | |
755 | ENDPOINT_CONTEXT EP[31];\r | |
756 | } INPUT_CONTEXT;\r | |
757 | \r | |
6b4483cd | 758 | typedef struct _INPUT_CONTEXT_64 {\r |
759 | INPUT_CONTRL_CONTEXT_64 InputControlContext;\r | |
760 | SLOT_CONTEXT_64 Slot;\r | |
761 | ENDPOINT_CONTEXT_64 EP[31];\r | |
762 | } INPUT_CONTEXT_64;\r | |
763 | \r | |
764 | \r | |
92870c98 | 765 | /**\r |
766 | Initialize the XHCI host controller for schedule.\r | |
767 | \r | |
a9292c13 | 768 | @param Xhc The XHCI Instance to be initialized.\r |
92870c98 | 769 | \r |
770 | **/\r | |
771 | VOID\r | |
772 | XhcInitSched (\r | |
a9292c13 | 773 | IN USB_XHCI_INSTANCE *Xhc\r |
92870c98 | 774 | );\r |
775 | \r | |
776 | /**\r | |
777 | Free the resouce allocated at initializing schedule.\r | |
778 | \r | |
a9292c13 | 779 | @param Xhc The XHCI Instance.\r |
92870c98 | 780 | \r |
781 | **/\r | |
782 | VOID\r | |
783 | XhcFreeSched (\r | |
a9292c13 | 784 | IN USB_XHCI_INSTANCE *Xhc\r |
92870c98 | 785 | );\r |
786 | \r | |
787 | /**\r | |
788 | Ring the door bell to notify XHCI there is a transaction to be executed through URB.\r | |
789 | \r | |
a9292c13 | 790 | @param Xhc The XHCI Instance.\r |
92870c98 | 791 | @param Urb The URB to be rung.\r |
792 | \r | |
793 | @retval EFI_SUCCESS Successfully ring the door bell.\r | |
794 | \r | |
795 | **/\r | |
796 | EFI_STATUS\r | |
797 | RingIntTransferDoorBell (\r | |
a9292c13 | 798 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 799 | IN URB *Urb\r |
800 | );\r | |
801 | \r | |
802 | /**\r | |
803 | Execute the transfer by polling the URB. This is a synchronous operation.\r | |
804 | \r | |
a9292c13 | 805 | @param Xhc The XHCI Instance.\r |
92870c98 | 806 | @param CmdTransfer The executed URB is for cmd transfer or not.\r |
807 | @param Urb The URB to execute.\r | |
a9292c13 | 808 | @param Timeout The time to wait before abort, in millisecond.\r |
92870c98 | 809 | \r |
810 | @return EFI_DEVICE_ERROR The transfer failed due to transfer error.\r | |
811 | @return EFI_TIMEOUT The transfer failed due to time out.\r | |
812 | @return EFI_SUCCESS The transfer finished OK.\r | |
813 | \r | |
814 | **/\r | |
815 | EFI_STATUS\r | |
816 | XhcExecTransfer (\r | |
a9292c13 | 817 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 818 | IN BOOLEAN CmdTransfer,\r |
819 | IN URB *Urb,\r | |
a9292c13 | 820 | IN UINTN Timeout\r |
92870c98 | 821 | );\r |
822 | \r | |
823 | /**\r | |
824 | Delete a single asynchronous interrupt transfer for\r | |
825 | the device and endpoint.\r | |
826 | \r | |
a9292c13 | 827 | @param Xhc The XHCI Instance.\r |
6b4483cd | 828 | @param BusAddr The logical device address assigned by UsbBus driver.\r |
92870c98 | 829 | @param EpNum The endpoint of the target.\r |
830 | \r | |
831 | @retval EFI_SUCCESS An asynchronous transfer is removed.\r | |
832 | @retval EFI_NOT_FOUND No transfer for the device is found.\r | |
833 | \r | |
834 | **/\r | |
835 | EFI_STATUS\r | |
836 | XhciDelAsyncIntTransfer (\r | |
a9292c13 | 837 | IN USB_XHCI_INSTANCE *Xhc,\r |
6b4483cd | 838 | IN UINT8 BusAddr,\r |
92870c98 | 839 | IN UINT8 EpNum\r |
840 | );\r | |
841 | \r | |
842 | /**\r | |
843 | Remove all the asynchronous interrupt transfers.\r | |
844 | \r | |
a9292c13 | 845 | @param Xhc The XHCI Instance.\r |
92870c98 | 846 | \r |
847 | **/\r | |
848 | VOID\r | |
849 | XhciDelAllAsyncIntTransfers (\r | |
a9292c13 | 850 | IN USB_XHCI_INSTANCE *Xhc\r |
92870c98 | 851 | );\r |
852 | \r | |
853 | /**\r | |
854 | Set Bios Ownership\r | |
855 | \r | |
a9292c13 | 856 | @param Xhc The XHCI Instance.\r |
92870c98 | 857 | \r |
858 | **/\r | |
859 | VOID\r | |
860 | XhcSetBiosOwnership (\r | |
a9292c13 | 861 | IN USB_XHCI_INSTANCE *Xhc\r |
92870c98 | 862 | );\r |
863 | \r | |
864 | /**\r | |
865 | Clear Bios Ownership\r | |
866 | \r | |
a9292c13 | 867 | @param Xhc The XHCI Instance.\r |
92870c98 | 868 | \r |
869 | **/\r | |
870 | VOID\r | |
871 | XhcClearBiosOwnership (\r | |
a9292c13 | 872 | IN USB_XHCI_INSTANCE *Xhc\r |
92870c98 | 873 | );\r |
874 | \r | |
92870c98 | 875 | /**\r |
876 | Find out the slot id according to the device's route string.\r | |
877 | \r | |
a9292c13 | 878 | @param Xhc The XHCI Instance.\r |
879 | @param RouteString The route string described the device location.\r | |
92870c98 | 880 | \r |
881 | @return The slot id used by the device.\r | |
882 | \r | |
883 | **/\r | |
884 | UINT8\r | |
885 | EFIAPI\r | |
886 | XhcRouteStringToSlotId (\r | |
a9292c13 | 887 | IN USB_XHCI_INSTANCE *Xhc,\r |
888 | IN USB_DEV_ROUTE RouteString\r | |
92870c98 | 889 | );\r |
890 | \r | |
891 | /**\r | |
892 | Calculate the device context index by endpoint address and direction.\r | |
893 | \r | |
894 | @param EpAddr The target endpoint number.\r | |
895 | @param Direction The direction of the target endpoint.\r | |
896 | \r | |
897 | @return The device context index of endpoint.\r | |
898 | \r | |
899 | **/\r | |
900 | UINT8\r | |
901 | XhcEndpointToDci (\r | |
902 | IN UINT8 EpAddr,\r | |
903 | IN UINT8 Direction\r | |
904 | );\r | |
905 | \r | |
906 | /**\r | |
907 | Ring the door bell to notify XHCI there is a transaction to be executed.\r | |
908 | \r | |
a9292c13 | 909 | @param Xhc The XHCI Instance.\r |
92870c98 | 910 | @param SlotId The slot id of the target device.\r |
911 | @param Dci The device context index of the target slot or endpoint.\r | |
912 | \r | |
913 | @retval EFI_SUCCESS Successfully ring the door bell.\r | |
914 | \r | |
915 | **/\r | |
916 | EFI_STATUS\r | |
917 | EFIAPI\r | |
918 | XhcRingDoorBell (\r | |
a9292c13 | 919 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 920 | IN UINT8 SlotId,\r |
921 | IN UINT8 Dci\r | |
922 | );\r | |
923 | \r | |
924 | /**\r | |
925 | Interrupt transfer periodic check handler.\r | |
926 | \r | |
927 | @param Event Interrupt event.\r | |
a9292c13 | 928 | @param Context Pointer to USB_XHCI_INSTANCE.\r |
92870c98 | 929 | \r |
930 | **/\r | |
931 | VOID\r | |
932 | EFIAPI\r | |
933 | XhcMonitorAsyncRequests (\r | |
934 | IN EFI_EVENT Event,\r | |
935 | IN VOID *Context\r | |
936 | );\r | |
937 | \r | |
938 | /**\r | |
939 | Monitor the port status change. Enable/Disable device slot if there is a device attached/detached.\r | |
940 | \r | |
a9292c13 | 941 | @param Xhc The XHCI Instance.\r |
92870c98 | 942 | @param ParentRouteChart The route string pointed to the parent device if it exists.\r |
943 | @param Port The port to be polled.\r | |
944 | @param PortState The port state.\r | |
945 | \r | |
946 | @retval EFI_SUCCESS Successfully enable/disable device slot according to port state.\r | |
947 | @retval Others Should not appear.\r | |
948 | \r | |
949 | **/\r | |
950 | EFI_STATUS\r | |
951 | EFIAPI\r | |
952 | XhcPollPortStatusChange (\r | |
a9292c13 | 953 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 954 | IN USB_DEV_ROUTE ParentRouteChart,\r |
955 | IN UINT8 Port,\r | |
956 | IN EFI_USB_PORT_STATUS *PortState\r | |
957 | );\r | |
958 | \r | |
959 | /**\r | |
960 | Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.\r | |
961 | \r | |
a9292c13 | 962 | @param Xhc The XHCI Instance.\r |
92870c98 | 963 | @param SlotId The slot id to be configured.\r |
964 | @param PortNum The total number of downstream port supported by the hub.\r | |
965 | @param TTT The TT think time of the hub device.\r | |
966 | @param MTT The multi-TT of the hub device.\r | |
967 | \r | |
968 | @retval EFI_SUCCESS Successfully configure the hub device's slot context.\r | |
969 | \r | |
970 | **/\r | |
971 | EFI_STATUS\r | |
972 | XhcConfigHubContext (\r | |
a9292c13 | 973 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 974 | IN UINT8 SlotId,\r |
975 | IN UINT8 PortNum,\r | |
976 | IN UINT8 TTT,\r | |
977 | IN UINT8 MTT\r | |
978 | );\r | |
979 | \r | |
6b4483cd | 980 | \r |
981 | /**\r | |
982 | Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.\r | |
983 | \r | |
984 | @param Xhc The XHCI Instance.\r | |
985 | @param SlotId The slot id to be configured.\r | |
986 | @param PortNum The total number of downstream port supported by the hub.\r | |
987 | @param TTT The TT think time of the hub device.\r | |
988 | @param MTT The multi-TT of the hub device.\r | |
989 | \r | |
990 | @retval EFI_SUCCESS Successfully configure the hub device's slot context.\r | |
991 | \r | |
992 | **/\r | |
993 | EFI_STATUS\r | |
994 | XhcConfigHubContext64 (\r | |
995 | IN USB_XHCI_INSTANCE *Xhc,\r | |
996 | IN UINT8 SlotId,\r | |
997 | IN UINT8 PortNum,\r | |
998 | IN UINT8 TTT,\r | |
999 | IN UINT8 MTT\r | |
1000 | );\r | |
1001 | \r | |
1002 | \r | |
92870c98 | 1003 | /**\r |
1004 | Configure all the device endpoints through XHCI's Configure_Endpoint cmd.\r | |
1005 | \r | |
a9292c13 | 1006 | @param Xhc The XHCI Instance.\r |
92870c98 | 1007 | @param SlotId The slot id to be configured.\r |
1008 | @param DeviceSpeed The device's speed.\r | |
1009 | @param ConfigDesc The pointer to the usb device configuration descriptor.\r | |
1010 | \r | |
1011 | @retval EFI_SUCCESS Successfully configure all the device endpoints.\r | |
1012 | \r | |
1013 | **/\r | |
1014 | EFI_STATUS\r | |
1015 | EFIAPI\r | |
1016 | XhcSetConfigCmd (\r | |
a9292c13 | 1017 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1018 | IN UINT8 SlotId,\r |
1019 | IN UINT8 DeviceSpeed,\r | |
1020 | IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r | |
1021 | );\r | |
1022 | \r | |
6b4483cd | 1023 | \r |
1024 | /**\r | |
1025 | Configure all the device endpoints through XHCI's Configure_Endpoint cmd.\r | |
1026 | \r | |
1027 | @param Xhc The XHCI Instance.\r | |
1028 | @param SlotId The slot id to be configured.\r | |
1029 | @param DeviceSpeed The device's speed.\r | |
1030 | @param ConfigDesc The pointer to the usb device configuration descriptor.\r | |
1031 | \r | |
1032 | @retval EFI_SUCCESS Successfully configure all the device endpoints.\r | |
1033 | \r | |
1034 | **/\r | |
1035 | EFI_STATUS\r | |
1036 | EFIAPI\r | |
1037 | XhcSetConfigCmd64 (\r | |
1038 | IN USB_XHCI_INSTANCE *Xhc,\r | |
1039 | IN UINT8 SlotId,\r | |
1040 | IN UINT8 DeviceSpeed,\r | |
1041 | IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r | |
1042 | );\r | |
1043 | \r | |
e1f2dfec SZ |
1044 | /**\r |
1045 | Set interface through XHCI's Configure_Endpoint cmd.\r | |
1046 | \r | |
1047 | @param Xhc The XHCI Instance.\r | |
1048 | @param SlotId The slot id to be configured.\r | |
1049 | @param DeviceSpeed The device's speed.\r | |
1050 | @param ConfigDesc The pointer to the usb device configuration descriptor.\r | |
1051 | @param Request USB device request to send.\r | |
1052 | \r | |
1053 | @retval EFI_SUCCESS Successfully set interface.\r | |
1054 | \r | |
1055 | **/\r | |
1056 | EFI_STATUS\r | |
1057 | EFIAPI\r | |
1058 | XhcSetInterface (\r | |
1059 | IN USB_XHCI_INSTANCE *Xhc,\r | |
1060 | IN UINT8 SlotId,\r | |
1061 | IN UINT8 DeviceSpeed,\r | |
1062 | IN USB_CONFIG_DESCRIPTOR *ConfigDesc,\r | |
1063 | IN EFI_USB_DEVICE_REQUEST *Request\r | |
1064 | );\r | |
1065 | \r | |
1066 | /**\r | |
1067 | Set interface through XHCI's Configure_Endpoint cmd.\r | |
1068 | \r | |
1069 | @param Xhc The XHCI Instance.\r | |
1070 | @param SlotId The slot id to be configured.\r | |
1071 | @param DeviceSpeed The device's speed.\r | |
1072 | @param ConfigDesc The pointer to the usb device configuration descriptor.\r | |
1073 | @param Request USB device request to send.\r | |
1074 | \r | |
1075 | @retval EFI_SUCCESS Successfully set interface.\r | |
1076 | \r | |
1077 | **/\r | |
1078 | EFI_STATUS\r | |
1079 | EFIAPI\r | |
1080 | XhcSetInterface64 (\r | |
1081 | IN USB_XHCI_INSTANCE *Xhc,\r | |
1082 | IN UINT8 SlotId,\r | |
1083 | IN UINT8 DeviceSpeed,\r | |
1084 | IN USB_CONFIG_DESCRIPTOR *ConfigDesc,\r | |
1085 | IN EFI_USB_DEVICE_REQUEST *Request\r | |
1086 | );\r | |
6b4483cd | 1087 | \r |
92870c98 | 1088 | /**\r |
1089 | Find out the actual device address according to the requested device address from UsbBus.\r | |
1090 | \r | |
a9292c13 | 1091 | @param Xhc The XHCI Instance.\r |
1092 | @param BusDevAddr The requested device address by UsbBus upper driver.\r | |
92870c98 | 1093 | \r |
1094 | @return The actual device address assigned to the device.\r | |
1095 | \r | |
1096 | **/\r | |
1097 | UINT8\r | |
1098 | EFIAPI\r | |
1099 | XhcBusDevAddrToSlotId (\r | |
a9292c13 | 1100 | IN USB_XHCI_INSTANCE *Xhc,\r |
1101 | IN UINT8 BusDevAddr\r | |
92870c98 | 1102 | );\r |
1103 | \r | |
1104 | /**\r | |
1105 | Assign and initialize the device slot for a new device.\r | |
1106 | \r | |
a9292c13 | 1107 | @param Xhc The XHCI Instance.\r |
92870c98 | 1108 | @param ParentRouteChart The route string pointed to the parent device.\r |
1109 | @param ParentPort The port at which the device is located.\r | |
1110 | @param RouteChart The route string pointed to the device.\r | |
1111 | @param DeviceSpeed The device speed.\r | |
1112 | \r | |
1113 | @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.\r | |
1114 | \r | |
1115 | **/\r | |
1116 | EFI_STATUS\r | |
1117 | EFIAPI\r | |
1118 | XhcInitializeDeviceSlot (\r | |
a9292c13 | 1119 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1120 | IN USB_DEV_ROUTE ParentRouteChart,\r |
1121 | IN UINT16 ParentPort,\r | |
1122 | IN USB_DEV_ROUTE RouteChart,\r | |
1123 | IN UINT8 DeviceSpeed\r | |
1124 | );\r | |
1125 | \r | |
6b4483cd | 1126 | /**\r |
1127 | Assign and initialize the device slot for a new device.\r | |
1128 | \r | |
1129 | @param Xhc The XHCI Instance.\r | |
1130 | @param ParentRouteChart The route string pointed to the parent device.\r | |
1131 | @param ParentPort The port at which the device is located.\r | |
1132 | @param RouteChart The route string pointed to the device.\r | |
1133 | @param DeviceSpeed The device speed.\r | |
1134 | \r | |
1135 | @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.\r | |
1136 | \r | |
1137 | **/\r | |
1138 | EFI_STATUS\r | |
1139 | EFIAPI\r | |
1140 | XhcInitializeDeviceSlot64 (\r | |
1141 | IN USB_XHCI_INSTANCE *Xhc,\r | |
1142 | IN USB_DEV_ROUTE ParentRouteChart,\r | |
1143 | IN UINT16 ParentPort,\r | |
1144 | IN USB_DEV_ROUTE RouteChart,\r | |
1145 | IN UINT8 DeviceSpeed\r | |
1146 | );\r | |
1147 | \r | |
92870c98 | 1148 | /**\r |
1149 | Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.\r | |
1150 | \r | |
a9292c13 | 1151 | @param Xhc The XHCI Instance.\r |
92870c98 | 1152 | @param SlotId The slot id to be evaluated.\r |
1153 | @param MaxPacketSize The max packet size supported by the device control transfer.\r | |
1154 | \r | |
1155 | @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.\r | |
1156 | \r | |
1157 | **/\r | |
1158 | EFI_STATUS\r | |
1159 | EFIAPI\r | |
1160 | XhcEvaluateContext (\r | |
a9292c13 | 1161 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1162 | IN UINT8 SlotId,\r |
1163 | IN UINT32 MaxPacketSize\r | |
1164 | );\r | |
1165 | \r | |
6b4483cd | 1166 | \r |
1167 | /**\r | |
1168 | Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.\r | |
1169 | \r | |
1170 | @param Xhc The XHCI Instance.\r | |
1171 | @param SlotId The slot id to be evaluated.\r | |
1172 | @param MaxPacketSize The max packet size supported by the device control transfer.\r | |
1173 | \r | |
1174 | @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.\r | |
1175 | \r | |
1176 | **/\r | |
1177 | EFI_STATUS\r | |
1178 | EFIAPI\r | |
1179 | XhcEvaluateContext64 (\r | |
1180 | IN USB_XHCI_INSTANCE *Xhc,\r | |
1181 | IN UINT8 SlotId,\r | |
1182 | IN UINT32 MaxPacketSize\r | |
1183 | );\r | |
1184 | \r | |
1185 | \r | |
92870c98 | 1186 | /**\r |
1187 | Disable the specified device slot.\r | |
1188 | \r | |
a9292c13 | 1189 | @param Xhc The XHCI Instance.\r |
92870c98 | 1190 | @param SlotId The slot id to be disabled.\r |
1191 | \r | |
1192 | @retval EFI_SUCCESS Successfully disable the device slot.\r | |
1193 | \r | |
1194 | **/\r | |
1195 | EFI_STATUS\r | |
1196 | EFIAPI\r | |
1197 | XhcDisableSlotCmd (\r | |
a9292c13 | 1198 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1199 | IN UINT8 SlotId\r |
1200 | );\r | |
1201 | \r | |
6b4483cd | 1202 | \r |
1203 | /**\r | |
1204 | Disable the specified device slot.\r | |
1205 | \r | |
1206 | @param Xhc The XHCI Instance.\r | |
1207 | @param SlotId The slot id to be disabled.\r | |
1208 | \r | |
1209 | @retval EFI_SUCCESS Successfully disable the device slot.\r | |
1210 | \r | |
1211 | **/\r | |
1212 | EFI_STATUS\r | |
1213 | EFIAPI\r | |
1214 | XhcDisableSlotCmd64 (\r | |
1215 | IN USB_XHCI_INSTANCE *Xhc,\r | |
1216 | IN UINT8 SlotId\r | |
1217 | );\r | |
1218 | \r | |
1219 | \r | |
92870c98 | 1220 | /**\r |
1221 | Synchronize the specified transfer ring to update the enqueue and dequeue pointer.\r | |
1222 | \r | |
a9292c13 | 1223 | @param Xhc The XHCI Instance.\r |
92870c98 | 1224 | @param TrsRing The transfer ring to sync.\r |
1225 | \r | |
1226 | @retval EFI_SUCCESS The transfer ring is synchronized successfully.\r | |
1227 | \r | |
1228 | **/\r | |
1229 | EFI_STATUS\r | |
1230 | EFIAPI\r | |
1231 | XhcSyncTrsRing (\r | |
a9292c13 | 1232 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1233 | TRANSFER_RING *TrsRing\r |
1234 | );\r | |
1235 | \r | |
1236 | /**\r | |
1237 | Synchronize the specified event ring to update the enqueue and dequeue pointer.\r | |
1238 | \r | |
a9292c13 | 1239 | @param Xhc The XHCI Instance.\r |
92870c98 | 1240 | @param EvtRing The event ring to sync.\r |
1241 | \r | |
1242 | @retval EFI_SUCCESS The event ring is synchronized successfully.\r | |
1243 | \r | |
1244 | **/\r | |
1245 | EFI_STATUS\r | |
1246 | EFIAPI\r | |
1247 | XhcSyncEventRing (\r | |
a9292c13 | 1248 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1249 | EVENT_RING *EvtRing\r |
1250 | );\r | |
1251 | \r | |
1252 | /**\r | |
1253 | Check if there is a new generated event.\r | |
1254 | \r | |
a9292c13 | 1255 | @param Xhc The XHCI Instance.\r |
92870c98 | 1256 | @param EvtRing The event ring to check.\r |
1257 | @param NewEvtTrb The new event TRB found.\r | |
1258 | \r | |
1259 | @retval EFI_SUCCESS Found a new event TRB at the event ring.\r | |
1260 | @retval EFI_NOT_READY The event ring has no new event.\r | |
1261 | \r | |
1262 | **/\r | |
1263 | EFI_STATUS\r | |
1264 | EFIAPI\r | |
1265 | XhcCheckNewEvent (\r | |
a9292c13 | 1266 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1267 | IN EVENT_RING *EvtRing,\r |
a9292c13 | 1268 | OUT TRB_TEMPLATE **NewEvtTrb\r |
92870c98 | 1269 | );\r |
1270 | \r | |
1271 | /**\r | |
1272 | Create XHCI transfer ring.\r | |
1273 | \r | |
a9292c13 | 1274 | @param Xhc The XHCI Instance.\r |
92870c98 | 1275 | @param TrbNum The number of TRB in the ring.\r |
1276 | @param TransferRing The created transfer ring.\r | |
1277 | \r | |
1278 | **/\r | |
1279 | VOID\r | |
1280 | CreateTransferRing (\r | |
a9292c13 | 1281 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1282 | IN UINTN TrbNum,\r |
1283 | OUT TRANSFER_RING *TransferRing\r | |
1284 | );\r | |
1285 | \r | |
1286 | /**\r | |
1287 | Create XHCI event ring.\r | |
1288 | \r | |
a9292c13 | 1289 | @param Xhc The XHCI Instance.\r |
92870c98 | 1290 | @param EventRing The created event ring.\r |
1291 | \r | |
1292 | **/\r | |
1293 | VOID\r | |
1294 | CreateEventRing (\r | |
a9292c13 | 1295 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1296 | OUT EVENT_RING *EventRing\r |
1297 | );\r | |
1298 | \r | |
1299 | /**\r | |
1300 | System software shall use a Reset Endpoint Command (section 4.11.4.7) to remove the Halted\r | |
1301 | condition in the xHC. After the successful completion of the Reset Endpoint Command, the Endpoint\r | |
1302 | Context is transitioned from the Halted to the Stopped state and the Transfer Ring of the endpoint is\r | |
1303 | reenabled. The next write to the Doorbell of the Endpoint will transition the Endpoint Context from the\r | |
1304 | Stopped to the Running state.\r | |
1305 | \r | |
a9292c13 | 1306 | @param Xhc The XHCI Instance.\r |
92870c98 | 1307 | @param Urb The urb which makes the endpoint halted.\r |
1308 | \r | |
1309 | @retval EFI_SUCCESS The recovery is successful.\r | |
1310 | @retval Others Failed to recovery halted endpoint.\r | |
1311 | \r | |
1312 | **/\r | |
1313 | EFI_STATUS\r | |
1314 | EFIAPI\r | |
1315 | XhcRecoverHaltedEndpoint (\r | |
a9292c13 | 1316 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1317 | IN URB *Urb\r |
1318 | );\r | |
1319 | \r | |
1320 | /**\r | |
1321 | Create a new URB for a new transaction.\r | |
1322 | \r | |
a9292c13 | 1323 | @param Xhc The XHCI Instance\r |
92870c98 | 1324 | @param DevAddr The device address\r |
1325 | @param EpAddr Endpoint addrress\r | |
1326 | @param DevSpeed The device speed\r | |
1327 | @param MaxPacket The max packet length of the endpoint\r | |
1328 | @param Type The transaction type\r | |
1329 | @param Request The standard USB request for control transfer\r | |
1330 | @param Data The user data to transfer\r | |
1331 | @param DataLen The length of data buffer\r | |
1332 | @param Callback The function to call when data is transferred\r | |
1333 | @param Context The context to the callback\r | |
1334 | \r | |
1335 | @return Created URB or NULL\r | |
1336 | \r | |
1337 | **/\r | |
1338 | URB*\r | |
1339 | XhcCreateUrb (\r | |
a9292c13 | 1340 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1341 | IN UINT8 DevAddr,\r |
1342 | IN UINT8 EpAddr,\r | |
1343 | IN UINT8 DevSpeed,\r | |
1344 | IN UINTN MaxPacket,\r | |
1345 | IN UINTN Type,\r | |
1346 | IN EFI_USB_DEVICE_REQUEST *Request,\r | |
1347 | IN VOID *Data,\r | |
1348 | IN UINTN DataLen,\r | |
1349 | IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,\r | |
1350 | IN VOID *Context\r | |
1351 | );\r | |
1352 | \r | |
1847ed0b EL |
1353 | /**\r |
1354 | Free an allocated URB.\r | |
1355 | \r | |
1356 | @param Xhc The XHCI device.\r | |
1357 | @param Urb The URB to free.\r | |
1358 | \r | |
1359 | **/\r | |
1360 | VOID\r | |
1361 | XhcFreeUrb (\r | |
1362 | IN USB_XHCI_INSTANCE *Xhc,\r | |
1363 | IN URB *Urb\r | |
1364 | );\r | |
1365 | \r | |
92870c98 | 1366 | /**\r |
1367 | Create a transfer TRB.\r | |
1368 | \r | |
a9292c13 | 1369 | @param Xhc The XHCI Instance\r |
92870c98 | 1370 | @param Urb The urb used to construct the transfer TRB.\r |
1371 | \r | |
1372 | @return Created TRB or NULL\r | |
1373 | \r | |
1374 | **/\r | |
1375 | EFI_STATUS\r | |
1376 | XhcCreateTransferTrb (\r | |
a9292c13 | 1377 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1378 | IN URB *Urb\r |
1379 | );\r | |
1380 | \r | |
1381 | #endif\r |