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23c98c94 | 1 | /** @file\r |
e94a9ff7 | 2 | Task priority (TPL) functions.\r |
504214c4 | 3 | \r |
23c98c94 | 4 | Copyright (c) 2006 - 2008, Intel Corporation. <BR>\r |
5 | All rights reserved. This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
28a00297 | 9 | \r |
23c98c94 | 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
28a00297 | 12 | \r |
504214c4 | 13 | **/\r |
28a00297 | 14 | \r |
9c4ac31c | 15 | #include "DxeMain.h"\r |
ec90508b | 16 | #include "Event.h"\r |
162ed594 | 17 | \r |
18 | /**\r | |
19 | Set Interrupt State.\r | |
20 | \r | |
21 | @param Enable The state of enable or disable interrupt\r | |
22 | \r | |
23 | **/\r | |
28a00297 | 24 | VOID\r |
25 | CoreSetInterruptState (\r | |
26 | IN BOOLEAN Enable\r | |
27 | )\r | |
28a00297 | 28 | {\r |
29 | if (gCpu != NULL) {\r | |
30 | if (Enable) {\r | |
31 | gCpu->EnableInterrupt(gCpu);\r | |
32 | } else {\r | |
33 | gCpu->DisableInterrupt(gCpu);\r | |
34 | }\r | |
35 | }\r | |
36 | }\r | |
37 | \r | |
28a00297 | 38 | \r |
162ed594 | 39 | /**\r |
28a00297 | 40 | Raise the task priority level to the new level.\r |
41 | High level is implemented by disabling processor interrupts.\r | |
42 | \r | |
022c6d45 | 43 | @param NewTpl New task priority level\r |
28a00297 | 44 | \r |
162ed594 | 45 | @return The previous task priority level\r |
28a00297 | 46 | \r |
162ed594 | 47 | **/\r |
48 | EFI_TPL\r | |
49 | EFIAPI\r | |
50 | CoreRaiseTpl (\r | |
51 | IN EFI_TPL NewTpl\r | |
52 | )\r | |
28a00297 | 53 | {\r |
54 | EFI_TPL OldTpl;\r | |
55 | \r | |
56 | OldTpl = gEfiCurrentTpl;\r | |
57 | ASSERT (OldTpl <= NewTpl);\r | |
58 | ASSERT (VALID_TPL (NewTpl));\r | |
59 | \r | |
60 | //\r | |
61 | // If raising to high level, disable interrupts\r | |
62 | //\r | |
63 | if (NewTpl >= TPL_HIGH_LEVEL && OldTpl < TPL_HIGH_LEVEL) {\r | |
64 | CoreSetInterruptState (FALSE);\r | |
65 | }\r | |
66 | \r | |
67 | //\r | |
68 | // Set the new value\r | |
69 | //\r | |
70 | gEfiCurrentTpl = NewTpl;\r | |
71 | \r | |
72 | return OldTpl;\r | |
73 | }\r | |
74 | \r | |
75 | \r | |
76 | \r | |
162ed594 | 77 | \r |
78 | /**\r | |
79 | Lowers the task priority to the previous value. If the new\r | |
80 | priority unmasks events at a higher priority, they are dispatched.\r | |
81 | \r | |
82 | @param NewTpl New, lower, task priority\r | |
83 | \r | |
84 | **/\r | |
28a00297 | 85 | VOID\r |
86 | EFIAPI\r | |
87 | CoreRestoreTpl (\r | |
88 | IN EFI_TPL NewTpl\r | |
89 | )\r | |
28a00297 | 90 | {\r |
91 | EFI_TPL OldTpl;\r | |
92 | \r | |
93 | OldTpl = gEfiCurrentTpl;\r | |
94 | ASSERT (NewTpl <= OldTpl);\r | |
95 | ASSERT (VALID_TPL (NewTpl));\r | |
96 | \r | |
97 | //\r | |
98 | // If lowering below HIGH_LEVEL, make sure\r | |
99 | // interrupts are enabled\r | |
100 | //\r | |
101 | \r | |
102 | if (OldTpl >= TPL_HIGH_LEVEL && NewTpl < TPL_HIGH_LEVEL) {\r | |
022c6d45 | 103 | gEfiCurrentTpl = TPL_HIGH_LEVEL;\r |
28a00297 | 104 | }\r |
105 | \r | |
106 | //\r | |
107 | // Dispatch any pending events\r | |
108 | //\r | |
e676c4d0 | 109 | while (((-2 << NewTpl) & gEventPending) != 0) {\r |
110 | gEfiCurrentTpl = HighBitSet64 (gEventPending);\r | |
28a00297 | 111 | if (gEfiCurrentTpl < TPL_HIGH_LEVEL) {\r |
112 | CoreSetInterruptState (TRUE);\r | |
113 | }\r | |
114 | CoreDispatchEventNotifies (gEfiCurrentTpl);\r | |
115 | }\r | |
116 | \r | |
117 | //\r | |
118 | // Set the new value\r | |
119 | //\r | |
120 | \r | |
121 | gEfiCurrentTpl = NewTpl;\r | |
122 | \r | |
123 | //\r | |
124 | // If lowering below HIGH_LEVEL, make sure\r | |
125 | // interrupts are enabled\r | |
126 | //\r | |
127 | if (gEfiCurrentTpl < TPL_HIGH_LEVEL) {\r | |
128 | CoreSetInterruptState (TRUE);\r | |
129 | }\r | |
130 | \r | |
131 | }\r |