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a7ed1e2e | 1 | /** @file\r |
2 | Support for PCI 2.2 standard.\r | |
3 | \r | |
bc14bdb3 | 4 | This file includes the definitions in the following specifications,\r |
427987f5 | 5 | PCI Local Bus Specification, 2.2\r |
6 | PCI-to-PCI Bridge Architecture Specification, Revision 1.2\r | |
bc14bdb3 | 7 | PC Card Standard, 8.0\r |
b219e2cd | 8 | PCI Power Management Interface Specification, Revision 1.2\r |
bc14bdb3 | 9 | \r |
9095d37b | 10 | Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r |
3362c5f1 | 11 | Copyright (c) 2014 - 2015, Hewlett-Packard Development Company, L.P.<BR>\r |
9344f092 | 12 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
a7ed1e2e | 13 | \r |
a7ed1e2e | 14 | **/\r |
15 | \r | |
42eedea9 | 16 | #ifndef _PCI22_H_\r |
17 | #define _PCI22_H_\r | |
a7ed1e2e | 18 | \r |
a7ed1e2e | 19 | #define PCI_MAX_BUS 255\r |
a7ed1e2e | 20 | #define PCI_MAX_DEVICE 31\r |
21 | #define PCI_MAX_FUNC 7\r | |
22 | \r | |
766f4bc1 | 23 | #pragma pack(1)\r |
427987f5 | 24 | \r |
25 | ///\r | |
26 | /// Common header region in PCI Configuration Space\r | |
27 | /// Section 6.1, PCI Local Bus Specification, 2.2\r | |
28 | ///\r | |
a7ed1e2e | 29 | typedef struct {\r |
30 | UINT16 VendorId;\r | |
31 | UINT16 DeviceId;\r | |
32 | UINT16 Command;\r | |
33 | UINT16 Status;\r | |
34 | UINT8 RevisionID;\r | |
35 | UINT8 ClassCode[3];\r | |
36 | UINT8 CacheLineSize;\r | |
37 | UINT8 LatencyTimer;\r | |
38 | UINT8 HeaderType;\r | |
39 | UINT8 BIST;\r | |
40 | } PCI_DEVICE_INDEPENDENT_REGION;\r | |
41 | \r | |
427987f5 | 42 | ///\r |
43 | /// PCI Device header region in PCI Configuration Space\r | |
44 | /// Section 6.1, PCI Local Bus Specification, 2.2\r | |
45 | ///\r | |
a7ed1e2e | 46 | typedef struct {\r |
47 | UINT32 Bar[6];\r | |
48 | UINT32 CISPtr;\r | |
49 | UINT16 SubsystemVendorID;\r | |
50 | UINT16 SubsystemID;\r | |
51 | UINT32 ExpansionRomBar;\r | |
52 | UINT8 CapabilityPtr;\r | |
53 | UINT8 Reserved1[3];\r | |
54 | UINT32 Reserved2;\r | |
55 | UINT8 InterruptLine;\r | |
56 | UINT8 InterruptPin;\r | |
57 | UINT8 MinGnt;\r | |
58 | UINT8 MaxLat;\r | |
59 | } PCI_DEVICE_HEADER_TYPE_REGION;\r | |
60 | \r | |
427987f5 | 61 | ///\r |
62 | /// PCI Device Configuration Space\r | |
63 | /// Section 6.1, PCI Local Bus Specification, 2.2\r | |
64 | ///\r | |
a7ed1e2e | 65 | typedef struct {\r |
66 | PCI_DEVICE_INDEPENDENT_REGION Hdr;\r | |
67 | PCI_DEVICE_HEADER_TYPE_REGION Device;\r | |
68 | } PCI_TYPE00;\r | |
69 | \r | |
bc14bdb3 | 70 | ///\r |
427987f5 | 71 | /// PCI-PCI Bridge header region in PCI Configuration Space\r |
72 | /// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2\r | |
bc14bdb3 | 73 | ///\r |
a7ed1e2e | 74 | typedef struct {\r |
75 | UINT32 Bar[2];\r | |
76 | UINT8 PrimaryBus;\r | |
77 | UINT8 SecondaryBus;\r | |
78 | UINT8 SubordinateBus;\r | |
79 | UINT8 SecondaryLatencyTimer;\r | |
80 | UINT8 IoBase;\r | |
81 | UINT8 IoLimit;\r | |
82 | UINT16 SecondaryStatus;\r | |
83 | UINT16 MemoryBase;\r | |
84 | UINT16 MemoryLimit;\r | |
85 | UINT16 PrefetchableMemoryBase;\r | |
86 | UINT16 PrefetchableMemoryLimit;\r | |
87 | UINT32 PrefetchableBaseUpper32;\r | |
88 | UINT32 PrefetchableLimitUpper32;\r | |
89 | UINT16 IoBaseUpper16;\r | |
90 | UINT16 IoLimitUpper16;\r | |
91 | UINT8 CapabilityPtr;\r | |
92 | UINT8 Reserved[3];\r | |
93 | UINT32 ExpansionRomBAR;\r | |
94 | UINT8 InterruptLine;\r | |
95 | UINT8 InterruptPin;\r | |
96 | UINT16 BridgeControl;\r | |
97 | } PCI_BRIDGE_CONTROL_REGISTER;\r | |
98 | \r | |
427987f5 | 99 | ///\r |
100 | /// PCI-to-PCI Bridge Configuration Space\r | |
101 | /// Section 3.2, PCI-PCI Bridge Architecture, Version 1.2\r | |
102 | ///\r | |
a7ed1e2e | 103 | typedef struct {\r |
104 | PCI_DEVICE_INDEPENDENT_REGION Hdr;\r | |
105 | PCI_BRIDGE_CONTROL_REGISTER Bridge;\r | |
106 | } PCI_TYPE01;\r | |
107 | \r | |
108 | typedef union {\r | |
109 | PCI_TYPE00 Device;\r | |
110 | PCI_TYPE01 Bridge;\r | |
111 | } PCI_TYPE_GENERIC;\r | |
112 | \r | |
9095d37b | 113 | ///\r |
b219e2cd | 114 | /// CardBus Controller Configuration Space,\r |
427987f5 | 115 | /// Section 4.5.1, PC Card Standard. 8.0\r |
bc14bdb3 | 116 | ///\r |
a7ed1e2e | 117 | typedef struct {\r |
b219e2cd | 118 | UINT32 CardBusSocketReg; ///< Cardbus Socket/ExCA Base\r |
bc14bdb3 | 119 | UINT8 Cap_Ptr;\r |
120 | UINT8 Reserved;\r | |
121 | UINT16 SecondaryStatus; ///< Secondary Status\r | |
122 | UINT8 PciBusNumber; ///< PCI Bus Number\r | |
123 | UINT8 CardBusBusNumber; ///< CardBus Bus Number\r | |
124 | UINT8 SubordinateBusNumber; ///< Subordinate Bus Number\r | |
125 | UINT8 CardBusLatencyTimer; ///< CardBus Latency Timer\r | |
126 | UINT32 MemoryBase0; ///< Memory Base Register 0\r | |
127 | UINT32 MemoryLimit0; ///< Memory Limit Register 0\r | |
a7ed1e2e | 128 | UINT32 MemoryBase1;\r |
129 | UINT32 MemoryLimit1;\r | |
130 | UINT32 IoBase0;\r | |
bc14bdb3 | 131 | UINT32 IoLimit0; ///< I/O Base Register 0\r |
132 | UINT32 IoBase1; ///< I/O Limit Register 0\r | |
a7ed1e2e | 133 | UINT32 IoLimit1;\r |
bc14bdb3 | 134 | UINT8 InterruptLine; ///< Interrupt Line\r |
135 | UINT8 InterruptPin; ///< Interrupt Pin\r | |
136 | UINT16 BridgeControl; ///< Bridge Control\r | |
a7ed1e2e | 137 | } PCI_CARDBUS_CONTROL_REGISTER;\r |
138 | \r | |
a2461f6b | 139 | //\r |
140 | // Definitions of PCI class bytes and manipulation macros.\r | |
141 | //\r | |
a7ed1e2e | 142 | #define PCI_CLASS_OLD 0x00\r |
bc14bdb3 | 143 | #define PCI_CLASS_OLD_OTHER 0x00\r |
144 | #define PCI_CLASS_OLD_VGA 0x01\r | |
a7ed1e2e | 145 | \r |
146 | #define PCI_CLASS_MASS_STORAGE 0x01\r | |
bc14bdb3 | 147 | #define PCI_CLASS_MASS_STORAGE_SCSI 0x00\r |
148 | #define PCI_CLASS_MASS_STORAGE_IDE 0x01\r | |
149 | #define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02\r | |
150 | #define PCI_CLASS_MASS_STORAGE_IPI 0x03\r | |
151 | #define PCI_CLASS_MASS_STORAGE_RAID 0x04\r | |
152 | #define PCI_CLASS_MASS_STORAGE_OTHER 0x80\r | |
a7ed1e2e | 153 | \r |
154 | #define PCI_CLASS_NETWORK 0x02\r | |
9095d37b | 155 | #define PCI_CLASS_NETWORK_ETHERNET 0x00\r |
bc14bdb3 | 156 | #define PCI_CLASS_NETWORK_TOKENRING 0x01\r |
157 | #define PCI_CLASS_NETWORK_FDDI 0x02\r | |
158 | #define PCI_CLASS_NETWORK_ATM 0x03\r | |
159 | #define PCI_CLASS_NETWORK_ISDN 0x04\r | |
160 | #define PCI_CLASS_NETWORK_OTHER 0x80\r | |
a7ed1e2e | 161 | \r |
162 | #define PCI_CLASS_DISPLAY 0x03\r | |
bc14bdb3 | 163 | #define PCI_CLASS_DISPLAY_VGA 0x00\r |
164 | #define PCI_IF_VGA_VGA 0x00\r | |
165 | #define PCI_IF_VGA_8514 0x01\r | |
166 | #define PCI_CLASS_DISPLAY_XGA 0x01\r | |
167 | #define PCI_CLASS_DISPLAY_3D 0x02\r | |
9095d37b | 168 | #define PCI_CLASS_DISPLAY_OTHER 0x80\r |
bc14bdb3 | 169 | \r |
170 | #define PCI_CLASS_MEDIA 0x04\r | |
171 | #define PCI_CLASS_MEDIA_VIDEO 0x00\r | |
172 | #define PCI_CLASS_MEDIA_AUDIO 0x01\r | |
173 | #define PCI_CLASS_MEDIA_TELEPHONE 0x02\r | |
174 | #define PCI_CLASS_MEDIA_OTHER 0x80\r | |
175 | \r | |
176 | #define PCI_CLASS_MEMORY_CONTROLLER 0x05\r | |
177 | #define PCI_CLASS_MEMORY_RAM 0x00\r | |
178 | #define PCI_CLASS_MEMORY_FLASH 0x01\r | |
179 | #define PCI_CLASS_MEMORY_OTHER 0x80\r | |
180 | \r | |
a7ed1e2e | 181 | #define PCI_CLASS_BRIDGE 0x06\r |
bc14bdb3 | 182 | #define PCI_CLASS_BRIDGE_HOST 0x00\r |
183 | #define PCI_CLASS_BRIDGE_ISA 0x01\r | |
184 | #define PCI_CLASS_BRIDGE_EISA 0x02\r | |
185 | #define PCI_CLASS_BRIDGE_MCA 0x03\r | |
186 | #define PCI_CLASS_BRIDGE_P2P 0x04\r | |
187 | #define PCI_IF_BRIDGE_P2P 0x00\r | |
188 | #define PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01\r | |
189 | #define PCI_CLASS_BRIDGE_PCMCIA 0x05\r | |
190 | #define PCI_CLASS_BRIDGE_NUBUS 0x06\r | |
191 | #define PCI_CLASS_BRIDGE_CARDBUS 0x07\r | |
192 | #define PCI_CLASS_BRIDGE_RACEWAY 0x08\r | |
193 | #define PCI_CLASS_BRIDGE_OTHER 0x80\r | |
194 | #define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80\r | |
195 | \r | |
9095d37b | 196 | #define PCI_CLASS_SCC 0x07 ///< Simple communications controllers\r |
bc14bdb3 | 197 | #define PCI_SUBCLASS_SERIAL 0x00\r |
198 | #define PCI_IF_GENERIC_XT 0x00\r | |
199 | #define PCI_IF_16450 0x01\r | |
200 | #define PCI_IF_16550 0x02\r | |
201 | #define PCI_IF_16650 0x03\r | |
202 | #define PCI_IF_16750 0x04\r | |
203 | #define PCI_IF_16850 0x05\r | |
204 | #define PCI_IF_16950 0x06\r | |
205 | #define PCI_SUBCLASS_PARALLEL 0x01\r | |
206 | #define PCI_IF_PARALLEL_PORT 0x00\r | |
207 | #define PCI_IF_BI_DIR_PARALLEL_PORT 0x01\r | |
208 | #define PCI_IF_ECP_PARALLEL_PORT 0x02\r | |
209 | #define PCI_IF_1284_CONTROLLER 0x03\r | |
210 | #define PCI_IF_1284_DEVICE 0xFE\r | |
211 | #define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02\r | |
212 | #define PCI_SUBCLASS_MODEM 0x03\r | |
213 | #define PCI_IF_GENERIC_MODEM 0x00\r | |
214 | #define PCI_IF_16450_MODEM 0x01\r | |
215 | #define PCI_IF_16550_MODEM 0x02\r | |
216 | #define PCI_IF_16650_MODEM 0x03\r | |
217 | #define PCI_IF_16750_MODEM 0x04\r | |
826a66d4 | 218 | #define PCI_SUBCLASS_SCC_OTHER 0x80\r |
a7ed1e2e | 219 | \r |
220 | #define PCI_CLASS_SYSTEM_PERIPHERAL 0x08\r | |
bc14bdb3 | 221 | #define PCI_SUBCLASS_PIC 0x00\r |
222 | #define PCI_IF_8259_PIC 0x00\r | |
223 | #define PCI_IF_ISA_PIC 0x01\r | |
224 | #define PCI_IF_EISA_PIC 0x02\r | |
b219e2cd | 225 | #define PCI_IF_APIC_CONTROLLER 0x10 ///< I/O APIC interrupt controller , 32 byte none-prefetchable memory.\r |
9095d37b | 226 | #define PCI_IF_APIC_CONTROLLER2 0x20\r |
bc14bdb3 | 227 | #define PCI_SUBCLASS_DMA 0x01\r |
228 | #define PCI_IF_8237_DMA 0x00\r | |
229 | #define PCI_IF_ISA_DMA 0x01\r | |
230 | #define PCI_IF_EISA_DMA 0x02\r | |
231 | #define PCI_SUBCLASS_TIMER 0x02\r | |
232 | #define PCI_IF_8254_TIMER 0x00\r | |
233 | #define PCI_IF_ISA_TIMER 0x01\r | |
234 | #define PCI_IF_EISA_TIMER 0x02\r | |
235 | #define PCI_SUBCLASS_RTC 0x03\r | |
236 | #define PCI_IF_GENERIC_RTC 0x00\r | |
826a66d4 | 237 | #define PCI_IF_ISA_RTC 0x01\r |
bc14bdb3 | 238 | #define PCI_SUBCLASS_PNP_CONTROLLER 0x04 ///< HotPlug Controller\r |
239 | #define PCI_SUBCLASS_PERIPHERAL_OTHER 0x80\r | |
a7ed1e2e | 240 | \r |
241 | #define PCI_CLASS_INPUT_DEVICE 0x09\r | |
bc14bdb3 | 242 | #define PCI_SUBCLASS_KEYBOARD 0x00\r |
243 | #define PCI_SUBCLASS_PEN 0x01\r | |
244 | #define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02\r | |
245 | #define PCI_SUBCLASS_SCAN_CONTROLLER 0x03\r | |
246 | #define PCI_SUBCLASS_GAMEPORT 0x04\r | |
247 | #define PCI_IF_GAMEPORT 0x00\r | |
826a66d4 | 248 | #define PCI_IF_GAMEPORT1 0x10\r |
bc14bdb3 | 249 | #define PCI_SUBCLASS_INPUT_OTHER 0x80\r |
a7ed1e2e | 250 | \r |
251 | #define PCI_CLASS_DOCKING_STATION 0x0A\r | |
826a66d4 RN |
252 | #define PCI_SUBCLASS_DOCKING_GENERIC 0x00\r |
253 | #define PCI_SUBCLASS_DOCKING_OTHER 0x80\r | |
a7ed1e2e | 254 | \r |
255 | #define PCI_CLASS_PROCESSOR 0x0B\r | |
bc14bdb3 | 256 | #define PCI_SUBCLASS_PROC_386 0x00\r |
257 | #define PCI_SUBCLASS_PROC_486 0x01\r | |
258 | #define PCI_SUBCLASS_PROC_PENTIUM 0x02\r | |
259 | #define PCI_SUBCLASS_PROC_ALPHA 0x10\r | |
260 | #define PCI_SUBCLASS_PROC_POWERPC 0x20\r | |
261 | #define PCI_SUBCLASS_PROC_MIPS 0x30\r | |
262 | #define PCI_SUBCLASS_PROC_CO_PORC 0x40 ///< Co-Processor\r | |
a7ed1e2e | 263 | \r |
264 | #define PCI_CLASS_SERIAL 0x0C\r | |
bc14bdb3 | 265 | #define PCI_CLASS_SERIAL_FIREWIRE 0x00\r |
266 | #define PCI_IF_1394 0x00\r | |
267 | #define PCI_IF_1394_OPEN_HCI 0x10\r | |
268 | #define PCI_CLASS_SERIAL_ACCESS_BUS 0x01\r | |
269 | #define PCI_CLASS_SERIAL_SSA 0x02\r | |
270 | #define PCI_CLASS_SERIAL_USB 0x03\r | |
271 | #define PCI_IF_UHCI 0x00\r | |
272 | #define PCI_IF_OHCI 0x10\r | |
273 | #define PCI_IF_USB_OTHER 0x80\r | |
274 | #define PCI_IF_USB_DEVICE 0xFE\r | |
275 | #define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04\r | |
276 | #define PCI_CLASS_SERIAL_SMB 0x05\r | |
a7ed1e2e | 277 | \r |
278 | #define PCI_CLASS_WIRELESS 0x0D\r | |
bc14bdb3 | 279 | #define PCI_SUBCLASS_IRDA 0x00\r |
280 | #define PCI_SUBCLASS_IR 0x01\r | |
826a66d4 | 281 | #define PCI_SUBCLASS_RF 0x10\r |
bc14bdb3 | 282 | #define PCI_SUBCLASS_WIRELESS_OTHER 0x80\r |
a7ed1e2e | 283 | \r |
284 | #define PCI_CLASS_INTELLIGENT_IO 0x0E\r | |
285 | \r | |
286 | #define PCI_CLASS_SATELLITE 0x0F\r | |
bc14bdb3 | 287 | #define PCI_SUBCLASS_TV 0x01\r |
288 | #define PCI_SUBCLASS_AUDIO 0x02\r | |
289 | #define PCI_SUBCLASS_VOICE 0x03\r | |
290 | #define PCI_SUBCLASS_DATA 0x04\r | |
a7ed1e2e | 291 | \r |
bc14bdb3 | 292 | #define PCI_SECURITY_CONTROLLER 0x10 ///< Encryption and decryption controller\r |
293 | #define PCI_SUBCLASS_NET_COMPUT 0x00\r | |
9095d37b | 294 | #define PCI_SUBCLASS_ENTERTAINMENT 0x10\r |
bc14bdb3 | 295 | #define PCI_SUBCLASS_SECURITY_OTHER 0x80\r |
a7ed1e2e | 296 | \r |
297 | #define PCI_CLASS_DPIO 0x11\r | |
bc14bdb3 | 298 | #define PCI_SUBCLASS_DPIO 0x00\r |
299 | #define PCI_SUBCLASS_DPIO_OTHER 0x80\r | |
a7ed1e2e | 300 | \r |
9095d37b | 301 | /**\r |
1833218d | 302 | Macro that checks whether the Base Class code of device matched.\r |
303 | \r | |
304 | @param _p Specified device.\r | |
305 | @param c Base Class code needs matching.\r | |
306 | \r | |
307 | @retval TRUE Base Class code matches the specified device.\r | |
9095d37b | 308 | @retval FALSE Base Class code doesn't match the specified device.\r |
1833218d | 309 | \r |
310 | **/\r | |
a7ed1e2e | 311 | #define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))\r |
9095d37b | 312 | /**\r |
1833218d | 313 | Macro that checks whether the Base Class code and Sub-Class code of device matched.\r |
314 | \r | |
315 | @param _p Specified device.\r | |
316 | @param c Base Class code needs matching.\r | |
317 | @param s Sub-Class code needs matching.\r | |
318 | \r | |
319 | @retval TRUE Base Class code and Sub-Class code match the specified device.\r | |
9095d37b | 320 | @retval FALSE Base Class code and Sub-Class code don't match the specified device.\r |
1833218d | 321 | \r |
322 | **/\r | |
a7ed1e2e | 323 | #define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))\r |
9095d37b | 324 | /**\r |
1833218d | 325 | Macro that checks whether the Base Class code, Sub-Class code and Interface code of device matched.\r |
326 | \r | |
327 | @param _p Specified device.\r | |
328 | @param c Base Class code needs matching.\r | |
329 | @param s Sub-Class code needs matching.\r | |
330 | @param p Interface code needs matching.\r | |
331 | \r | |
332 | @retval TRUE Base Class code, Sub-Class code and Interface code match the specified device.\r | |
9095d37b | 333 | @retval FALSE Base Class code, Sub-Class code and Interface code don't match the specified device.\r |
1833218d | 334 | \r |
335 | **/\r | |
a7ed1e2e | 336 | #define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))\r |
337 | \r | |
9095d37b | 338 | /**\r |
1833218d | 339 | Macro that checks whether device is a display controller.\r |
340 | \r | |
341 | @param _p Specified device.\r | |
342 | \r | |
343 | @retval TRUE Device is a display controller.\r | |
344 | @retval FALSE Device is not a display controller.\r | |
345 | \r | |
346 | **/\r | |
a7ed1e2e | 347 | #define IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)\r |
9095d37b | 348 | /**\r |
1833218d | 349 | Macro that checks whether device is a VGA-compatible controller.\r |
350 | \r | |
351 | @param _p Specified device.\r | |
352 | \r | |
353 | @retval TRUE Device is a VGA-compatible controller.\r | |
354 | @retval FALSE Device is not a VGA-compatible controller.\r | |
355 | \r | |
356 | **/\r | |
357 | #define IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_VGA)\r | |
9095d37b | 358 | /**\r |
1833218d | 359 | Macro that checks whether device is an 8514-compatible controller.\r |
360 | \r | |
361 | @param _p Specified device.\r | |
362 | \r | |
363 | @retval TRUE Device is an 8514-compatible controller.\r | |
364 | @retval FALSE Device is not an 8514-compatible controller.\r | |
365 | \r | |
366 | **/\r | |
367 | #define IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_8514)\r | |
9095d37b | 368 | /**\r |
1833218d | 369 | Macro that checks whether device is built before the Class Code field was defined.\r |
370 | \r | |
371 | @param _p Specified device.\r | |
372 | \r | |
373 | @retval TRUE Device is an old device.\r | |
374 | @retval FALSE Device is not an old device.\r | |
375 | \r | |
376 | **/\r | |
a7ed1e2e | 377 | #define IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)\r |
9095d37b | 378 | /**\r |
1833218d | 379 | Macro that checks whether device is a VGA-compatible device built before the Class Code field was defined.\r |
380 | \r | |
381 | @param _p Specified device.\r | |
382 | \r | |
383 | @retval TRUE Device is an old VGA-compatible device.\r | |
384 | @retval FALSE Device is not an old VGA-compatible device.\r | |
385 | \r | |
386 | **/\r | |
a7ed1e2e | 387 | #define IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)\r |
9095d37b | 388 | /**\r |
1833218d | 389 | Macro that checks whether device is an IDE controller.\r |
390 | \r | |
391 | @param _p Specified device.\r | |
392 | \r | |
393 | @retval TRUE Device is an IDE controller.\r | |
394 | @retval FALSE Device is not an IDE controller.\r | |
395 | \r | |
396 | **/\r | |
a7ed1e2e | 397 | #define IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)\r |
9095d37b | 398 | /**\r |
1833218d | 399 | Macro that checks whether device is a SCSI bus controller.\r |
400 | \r | |
401 | @param _p Specified device.\r | |
402 | \r | |
403 | @retval TRUE Device is a SCSI bus controller.\r | |
404 | @retval FALSE Device is not a SCSI bus controller.\r | |
405 | \r | |
406 | **/\r | |
407 | #define IS_PCI_SCSI(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI)\r | |
9095d37b | 408 | /**\r |
1833218d | 409 | Macro that checks whether device is a RAID controller.\r |
410 | \r | |
411 | @param _p Specified device.\r | |
412 | \r | |
413 | @retval TRUE Device is a RAID controller.\r | |
414 | @retval FALSE Device is not a RAID controller.\r | |
415 | \r | |
416 | **/\r | |
417 | #define IS_PCI_RAID(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID)\r | |
9095d37b | 418 | /**\r |
1833218d | 419 | Macro that checks whether device is an ISA bridge.\r |
420 | \r | |
421 | @param _p Specified device.\r | |
422 | \r | |
423 | @retval TRUE Device is an ISA bridge.\r | |
424 | @retval FALSE Device is not an ISA bridge.\r | |
425 | \r | |
426 | **/\r | |
427 | #define IS_PCI_LPC(_p) IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)\r | |
9095d37b | 428 | /**\r |
1833218d | 429 | Macro that checks whether device is a PCI-to-PCI bridge.\r |
430 | \r | |
431 | @param _p Specified device.\r | |
432 | \r | |
433 | @retval TRUE Device is a PCI-to-PCI bridge.\r | |
434 | @retval FALSE Device is not a PCI-to-PCI bridge.\r | |
435 | \r | |
436 | **/\r | |
437 | #define IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P)\r | |
9095d37b | 438 | /**\r |
1833218d | 439 | Macro that checks whether device is a Subtractive Decode PCI-to-PCI bridge.\r |
440 | \r | |
441 | @param _p Specified device.\r | |
442 | \r | |
443 | @retval TRUE Device is a Subtractive Decode PCI-to-PCI bridge.\r | |
444 | @retval FALSE Device is not a Subtractive Decode PCI-to-PCI bridge.\r | |
445 | \r | |
446 | **/\r | |
447 | #define IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P_SUBTRACTIVE)\r | |
9095d37b | 448 | /**\r |
1833218d | 449 | Macro that checks whether device is a 16550-compatible serial controller.\r |
450 | \r | |
451 | @param _p Specified device.\r | |
452 | \r | |
453 | @retval TRUE Device is a 16550-compatible serial controller.\r | |
454 | @retval FALSE Device is not a 16550-compatible serial controller.\r | |
455 | \r | |
456 | **/\r | |
a7ed1e2e | 457 | #define IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)\r |
9095d37b | 458 | /**\r |
1833218d | 459 | Macro that checks whether device is a Universal Serial Bus controller.\r |
460 | \r | |
461 | @param _p Specified device.\r | |
462 | \r | |
463 | @retval TRUE Device is a Universal Serial Bus controller.\r | |
464 | @retval FALSE Device is not a Universal Serial Bus controller.\r | |
465 | \r | |
466 | **/\r | |
a7ed1e2e | 467 | #define IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)\r |
468 | \r | |
bc14bdb3 | 469 | //\r |
9095d37b | 470 | // the definition of Header Type\r |
bc14bdb3 | 471 | //\r |
a7ed1e2e | 472 | #define HEADER_TYPE_DEVICE 0x00\r |
473 | #define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01\r | |
474 | #define HEADER_TYPE_CARDBUS_BRIDGE 0x02\r | |
a7ed1e2e | 475 | #define HEADER_TYPE_MULTI_FUNCTION 0x80\r |
bc14bdb3 | 476 | //\r |
477 | // Mask of Header type\r | |
478 | //\r | |
a7ed1e2e | 479 | #define HEADER_LAYOUT_CODE 0x7f\r |
9095d37b | 480 | /**\r |
1833218d | 481 | Macro that checks whether device is a PCI-PCI bridge.\r |
482 | \r | |
483 | @param _p Specified device.\r | |
484 | \r | |
485 | @retval TRUE Device is a PCI-PCI bridge.\r | |
486 | @retval FALSE Device is not a PCI-PCI bridge.\r | |
a7ed1e2e | 487 | \r |
1833218d | 488 | **/\r |
a7ed1e2e | 489 | #define IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))\r |
9095d37b | 490 | /**\r |
1833218d | 491 | Macro that checks whether device is a CardBus bridge.\r |
492 | \r | |
493 | @param _p Specified device.\r | |
494 | \r | |
495 | @retval TRUE Device is a CardBus bridge.\r | |
496 | @retval FALSE Device is not a CardBus bridge.\r | |
497 | \r | |
498 | **/\r | |
a7ed1e2e | 499 | #define IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))\r |
9095d37b | 500 | /**\r |
1833218d | 501 | Macro that checks whether device is a multiple functions device.\r |
502 | \r | |
503 | @param _p Specified device.\r | |
504 | \r | |
505 | @retval TRUE Device is a multiple functions device.\r | |
506 | @retval FALSE Device is not a multiple functions device.\r | |
507 | \r | |
508 | **/\r | |
a7ed1e2e | 509 | #define IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)\r |
510 | \r | |
bc14bdb3 | 511 | ///\r |
b219e2cd | 512 | /// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecture Specification,\r |
bc14bdb3 | 513 | ///\r |
a7ed1e2e | 514 | #define PCI_BRIDGE_ROMBAR 0x38\r |
515 | \r | |
516 | #define PCI_MAX_BAR 0x0006\r | |
517 | #define PCI_MAX_CONFIG_OFFSET 0x0100\r | |
518 | \r | |
519 | #define PCI_VENDOR_ID_OFFSET 0x00\r | |
520 | #define PCI_DEVICE_ID_OFFSET 0x02\r | |
521 | #define PCI_COMMAND_OFFSET 0x04\r | |
522 | #define PCI_PRIMARY_STATUS_OFFSET 0x06\r | |
523 | #define PCI_REVISION_ID_OFFSET 0x08\r | |
524 | #define PCI_CLASSCODE_OFFSET 0x09\r | |
525 | #define PCI_CACHELINE_SIZE_OFFSET 0x0C\r | |
526 | #define PCI_LATENCY_TIMER_OFFSET 0x0D\r | |
527 | #define PCI_HEADER_TYPE_OFFSET 0x0E\r | |
528 | #define PCI_BIST_OFFSET 0x0F\r | |
529 | #define PCI_BASE_ADDRESSREG_OFFSET 0x10\r | |
530 | #define PCI_CARDBUS_CIS_OFFSET 0x28\r | |
bc14bdb3 | 531 | #define PCI_SVID_OFFSET 0x2C ///< SubSystem Vendor id\r |
a7ed1e2e | 532 | #define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C\r |
bc14bdb3 | 533 | #define PCI_SID_OFFSET 0x2E ///< SubSystem ID\r |
a7ed1e2e | 534 | #define PCI_SUBSYSTEM_ID_OFFSET 0x2E\r |
535 | #define PCI_EXPANSION_ROM_BASE 0x30\r | |
536 | #define PCI_CAPBILITY_POINTER_OFFSET 0x34\r | |
bc14bdb3 | 537 | #define PCI_INT_LINE_OFFSET 0x3C ///< Interrupt Line Register\r |
538 | #define PCI_INT_PIN_OFFSET 0x3D ///< Interrupt Pin Register\r | |
539 | #define PCI_MAXGNT_OFFSET 0x3E ///< Max Grant Register\r | |
540 | #define PCI_MAXLAT_OFFSET 0x3F ///< Max Latency Register\r | |
a7ed1e2e | 541 | \r |
a2461f6b | 542 | //\r |
543 | // defined in PCI-to-PCI Bridge Architecture Specification\r | |
544 | //\r | |
9095d37b LG |
545 | #define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18\r |
546 | #define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19\r | |
547 | #define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a\r | |
0e8768b6 | 548 | #define PCI_BRIDGE_SECONDARY_LATENCY_TIMER_OFFSET 0x1b\r |
9095d37b LG |
549 | #define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E\r |
550 | #define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E\r | |
a7ed1e2e | 551 | \r |
bc14bdb3 | 552 | ///\r |
553 | /// Interrupt Line "Unknown" or "No connection" value defined for x86 based system\r | |
554 | ///\r | |
9095d37b | 555 | #define PCI_INT_LINE_UNKNOWN 0xFF\r |
a7ed1e2e | 556 | \r |
1833218d | 557 | ///\r |
558 | /// PCI Access Data Format\r | |
559 | ///\r | |
a7ed1e2e | 560 | typedef union {\r |
561 | struct {\r | |
562 | UINT32 Reg : 8;\r | |
563 | UINT32 Func : 3;\r | |
564 | UINT32 Dev : 5;\r | |
565 | UINT32 Bus : 8;\r | |
566 | UINT32 Reserved : 7;\r | |
567 | UINT32 Enable : 1;\r | |
568 | } Bits;\r | |
569 | UINT32 Uint32;\r | |
570 | } PCI_CONFIG_ACCESS_CF8;\r | |
571 | \r | |
766f4bc1 | 572 | #pragma pack()\r |
573 | \r | |
bc14bdb3 | 574 | #define EFI_PCI_COMMAND_IO_SPACE BIT0 ///< 0x0001\r |
575 | #define EFI_PCI_COMMAND_MEMORY_SPACE BIT1 ///< 0x0002\r | |
576 | #define EFI_PCI_COMMAND_BUS_MASTER BIT2 ///< 0x0004\r | |
577 | #define EFI_PCI_COMMAND_SPECIAL_CYCLE BIT3 ///< 0x0008\r | |
578 | #define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE BIT4 ///< 0x0010\r | |
579 | #define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP BIT5 ///< 0x0020\r | |
580 | #define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND BIT6 ///< 0x0040\r | |
581 | #define EFI_PCI_COMMAND_STEPPING_CONTROL BIT7 ///< 0x0080\r | |
582 | #define EFI_PCI_COMMAND_SERR BIT8 ///< 0x0100\r | |
583 | #define EFI_PCI_COMMAND_FAST_BACK_TO_BACK BIT9 ///< 0x0200\r | |
a7ed1e2e | 584 | \r |
a2461f6b | 585 | //\r |
586 | // defined in PCI-to-PCI Bridge Architecture Specification\r | |
587 | //\r | |
bc14bdb3 | 588 | #define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE BIT0 ///< 0x0001\r |
589 | #define EFI_PCI_BRIDGE_CONTROL_SERR BIT1 ///< 0x0002\r | |
590 | #define EFI_PCI_BRIDGE_CONTROL_ISA BIT2 ///< 0x0004\r | |
591 | #define EFI_PCI_BRIDGE_CONTROL_VGA BIT3 ///< 0x0008\r | |
592 | #define EFI_PCI_BRIDGE_CONTROL_VGA_16 BIT4 ///< 0x0010\r | |
593 | #define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT BIT5 ///< 0x0020\r | |
594 | #define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS BIT6 ///< 0x0040\r | |
595 | #define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK BIT7 ///< 0x0080\r | |
596 | #define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER BIT8 ///< 0x0100\r | |
597 | #define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER BIT9 ///< 0x0200\r | |
598 | #define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS BIT10 ///< 0x0400\r | |
599 | #define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR BIT11 ///< 0x0800\r | |
600 | \r | |
a2461f6b | 601 | //\r |
602 | // Following are the PCI-CARDBUS bridge control bit, defined in PC Card Standard\r | |
603 | //\r | |
bc14bdb3 | 604 | #define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE BIT7 ///< 0x0080\r |
605 | #define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE BIT8 ///< 0x0100\r | |
606 | #define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE BIT9 ///< 0x0200\r | |
607 | #define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE BIT10 ///< 0x0400\r | |
a7ed1e2e | 608 | \r |
609 | //\r | |
610 | // Following are the PCI status control bit\r | |
611 | //\r | |
bc14bdb3 | 612 | #define EFI_PCI_STATUS_CAPABILITY BIT4 ///< 0x0010\r |
613 | #define EFI_PCI_STATUS_66MZ_CAPABLE BIT5 ///< 0x0020\r | |
614 | #define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE BIT7 ///< 0x0080\r | |
615 | #define EFI_PCI_MASTER_DATA_PARITY_ERROR BIT8 ///< 0x0100\r | |
a7ed1e2e | 616 | \r |
bc14bdb3 | 617 | ///\r |
618 | /// defined in PC Card Standard\r | |
619 | ///\r | |
a7ed1e2e | 620 | #define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14\r |
621 | \r | |
766f4bc1 | 622 | #pragma pack(1)\r |
a7ed1e2e | 623 | //\r |
624 | // PCI Capability List IDs and records\r | |
625 | //\r | |
626 | #define EFI_PCI_CAPABILITY_ID_PMI 0x01\r | |
627 | #define EFI_PCI_CAPABILITY_ID_AGP 0x02\r | |
628 | #define EFI_PCI_CAPABILITY_ID_VPD 0x03\r | |
629 | #define EFI_PCI_CAPABILITY_ID_SLOTID 0x04\r | |
630 | #define EFI_PCI_CAPABILITY_ID_MSI 0x05\r | |
631 | #define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06\r | |
12e6f4f1 | 632 | #define EFI_PCI_CAPABILITY_ID_SHPC 0x0C\r |
a2461f6b | 633 | \r |
427987f5 | 634 | ///\r |
635 | /// Capabilities List Header\r | |
636 | /// Section 6.7, PCI Local Bus Specification, 2.2\r | |
637 | ///\r | |
a7ed1e2e | 638 | typedef struct {\r |
639 | UINT8 CapabilityID;\r | |
640 | UINT8 NextItemPtr;\r | |
641 | } EFI_PCI_CAPABILITY_HDR;\r | |
642 | \r | |
f0aa06e3 SEHM |
643 | ///\r |
644 | /// PMC - Power Management Capabilities\r | |
b219e2cd | 645 | /// Section 3.2.3, PCI Power Management Interface Specification, Revision 1.2\r |
f0aa06e3 SEHM |
646 | ///\r |
647 | typedef union {\r | |
648 | struct {\r | |
649 | UINT16 Version : 3;\r | |
650 | UINT16 PmeClock : 1;\r | |
3362c5f1 | 651 | UINT16 Reserved : 1;\r |
f0aa06e3 SEHM |
652 | UINT16 DeviceSpecificInitialization : 1;\r |
653 | UINT16 AuxCurrent : 3;\r | |
654 | UINT16 D1Support : 1;\r | |
655 | UINT16 D2Support : 1;\r | |
656 | UINT16 PmeSupport : 5;\r | |
657 | } Bits;\r | |
658 | UINT16 Data;\r | |
659 | } EFI_PCI_PMC;\r | |
660 | \r | |
661 | #define EFI_PCI_PMC_D3_COLD_MASK (BIT15)\r | |
662 | \r | |
663 | ///\r | |
664 | /// PMCSR - Power Management Control/Status\r | |
b219e2cd | 665 | /// Section 3.2.4, PCI Power Management Interface Specification, Revision 1.2\r |
f0aa06e3 SEHM |
666 | ///\r |
667 | typedef union {\r | |
668 | struct {\r | |
669 | UINT16 PowerState : 2;\r | |
cbedba86 RN |
670 | UINT16 ReservedForPciExpress : 1;\r |
671 | UINT16 NoSoftReset : 1;\r | |
672 | UINT16 Reserved : 4;\r | |
f0aa06e3 SEHM |
673 | UINT16 PmeEnable : 1;\r |
674 | UINT16 DataSelect : 4;\r | |
675 | UINT16 DataScale : 2;\r | |
676 | UINT16 PmeStatus : 1;\r | |
677 | } Bits;\r | |
678 | UINT16 Data;\r | |
679 | } EFI_PCI_PMCSR;\r | |
680 | \r | |
cbedba86 RN |
681 | #define PCI_POWER_STATE_D0 0\r |
682 | #define PCI_POWER_STATE_D1 1\r | |
683 | #define PCI_POWER_STATE_D2 2\r | |
684 | #define PCI_POWER_STATE_D3_HOT 3\r | |
685 | \r | |
686 | ///\r | |
687 | /// PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions\r | |
b219e2cd | 688 | /// Section 3.2.5, PCI Power Management Interface Specification, Revision 1.2\r |
cbedba86 RN |
689 | ///\r |
690 | typedef union {\r | |
691 | struct {\r | |
692 | UINT8 Reserved : 6;\r | |
693 | UINT8 B2B3 : 1;\r | |
694 | UINT8 BusPowerClockControl : 1;\r | |
695 | } Bits;\r | |
696 | UINT8 Uint8;\r | |
697 | } EFI_PCI_PMCSR_BSE;\r | |
698 | \r | |
699 | ///\r | |
700 | /// Power Management Register Block Definition\r | |
b219e2cd | 701 | /// Section 3.2, PCI Power Management Interface Specification, Revision 1.2\r |
cbedba86 RN |
702 | ///\r |
703 | typedef struct {\r | |
704 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
705 | EFI_PCI_PMC PMC;\r | |
706 | EFI_PCI_PMCSR PMCSR;\r | |
707 | EFI_PCI_PMCSR_BSE BridgeExtention;\r | |
708 | UINT8 Data;\r | |
709 | } EFI_PCI_CAPABILITY_PMI;\r | |
710 | \r | |
1bc5d021 | 711 | ///\r |
427987f5 | 712 | /// A.G.P Capability\r |
713 | /// Section 6.1.4, Accelerated Graphics Port Interface Specification, Revision 1.0\r | |
1bc5d021 | 714 | ///\r |
a7ed1e2e | 715 | typedef struct {\r |
716 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
717 | UINT8 Rev;\r | |
718 | UINT8 Reserved;\r | |
719 | UINT32 Status;\r | |
720 | UINT32 Command;\r | |
721 | } EFI_PCI_CAPABILITY_AGP;\r | |
722 | \r | |
1bc5d021 | 723 | ///\r |
427987f5 | 724 | /// VPD Capability Structure\r |
725 | /// Appendix I, PCI Local Bus Specification, 2.2\r | |
1bc5d021 | 726 | ///\r |
a7ed1e2e | 727 | typedef struct {\r |
728 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
729 | UINT16 AddrReg;\r | |
730 | UINT32 DataReg;\r | |
731 | } EFI_PCI_CAPABILITY_VPD;\r | |
732 | \r | |
1bc5d021 | 733 | ///\r |
427987f5 | 734 | /// Slot Numbering Capabilities Register\r |
b219e2cd | 735 | /// Section 3.2.6, PCI-to-PCI Bridge Architecture Specification, Revision 1.2\r |
1bc5d021 | 736 | ///\r |
a7ed1e2e | 737 | typedef struct {\r |
738 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
739 | UINT8 ExpnsSlotReg;\r | |
740 | UINT8 ChassisNo;\r | |
741 | } EFI_PCI_CAPABILITY_SLOTID;\r | |
742 | \r | |
1bc5d021 | 743 | ///\r |
427987f5 | 744 | /// Message Capability Structure for 32-bit Message Address\r |
745 | /// Section 6.8.1, PCI Local Bus Specification, 2.2\r | |
1bc5d021 | 746 | ///\r |
a7ed1e2e | 747 | typedef struct {\r |
748 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
749 | UINT16 MsgCtrlReg;\r | |
750 | UINT32 MsgAddrReg;\r | |
751 | UINT16 MsgDataReg;\r | |
752 | } EFI_PCI_CAPABILITY_MSI32;\r | |
753 | \r | |
427987f5 | 754 | ///\r |
755 | /// Message Capability Structure for 64-bit Message Address\r | |
756 | /// Section 6.8.1, PCI Local Bus Specification, 2.2\r | |
757 | ///\r | |
a7ed1e2e | 758 | typedef struct {\r |
759 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
760 | UINT16 MsgCtrlReg;\r | |
761 | UINT32 MsgAddrRegLsdw;\r | |
762 | UINT32 MsgAddrRegMsdw;\r | |
763 | UINT16 MsgDataReg;\r | |
764 | } EFI_PCI_CAPABILITY_MSI64;\r | |
765 | \r | |
1bc5d021 | 766 | ///\r |
9095d37b | 767 | /// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG,\r |
427987f5 | 768 | /// CompactPCI Hot Swap Specification PICMG 2.1, R1.0\r |
1bc5d021 | 769 | ///\r |
a7ed1e2e | 770 | typedef struct {\r |
771 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
1bc5d021 | 772 | ///\r |
773 | /// not finished - fields need to go here\r | |
774 | ///\r | |
a7ed1e2e | 775 | } EFI_PCI_CAPABILITY_HOTPLUG;\r |
776 | \r | |
a7ed1e2e | 777 | #define PCI_BAR_IDX0 0x00\r |
778 | #define PCI_BAR_IDX1 0x01\r | |
779 | #define PCI_BAR_IDX2 0x02\r | |
780 | #define PCI_BAR_IDX3 0x03\r | |
781 | #define PCI_BAR_IDX4 0x04\r | |
782 | #define PCI_BAR_IDX5 0x05\r | |
a7ed1e2e | 783 | \r |
bc14bdb3 | 784 | ///\r |
785 | /// EFI PCI Option ROM definitions\r | |
9095d37b LG |
786 | ///\r |
787 | #define EFI_ROOT_BRIDGE_LIST 'eprb'\r | |
bc14bdb3 | 788 | #define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1 ///< defined in UEFI Spec.\r |
afcf4907 | 789 | \r |
bc14bdb3 | 790 | #define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55\r |
13c31065 | 791 | #define PCI_DATA_STRUCTURE_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', 'R')\r |
bc14bdb3 | 792 | #define PCI_CODE_TYPE_PCAT_IMAGE 0x00\r |
a2461f6b | 793 | #define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001 ///< defined in UEFI spec.\r |
bc14bdb3 | 794 | \r |
427987f5 | 795 | ///\r |
796 | /// Standard PCI Expansion ROM Header\r | |
797 | /// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1\r | |
798 | ///\r | |
bc14bdb3 | 799 | typedef struct {\r |
800 | UINT16 Signature; ///< 0xaa55\r | |
801 | UINT8 Reserved[0x16];\r | |
802 | UINT16 PcirOffset;\r | |
803 | } PCI_EXPANSION_ROM_HEADER;\r | |
804 | \r | |
427987f5 | 805 | ///\r |
806 | /// Legacy ROM Header Extensions\r | |
807 | /// Section 6.3.3.1, PCI Local Bus Specification, 2.2\r | |
808 | ///\r | |
bc14bdb3 | 809 | typedef struct {\r |
810 | UINT16 Signature; ///< 0xaa55\r | |
811 | UINT8 Size512;\r | |
812 | UINT8 InitEntryPoint[3];\r | |
813 | UINT8 Reserved[0x12];\r | |
814 | UINT16 PcirOffset;\r | |
815 | } EFI_LEGACY_EXPANSION_ROM_HEADER;\r | |
816 | \r | |
427987f5 | 817 | ///\r |
818 | /// PCI Data Structure Format\r | |
819 | /// Section 6.3.1.2, PCI Local Bus Specification, 2.2\r | |
820 | ///\r | |
bc14bdb3 | 821 | typedef struct {\r |
822 | UINT32 Signature; ///< "PCIR"\r | |
823 | UINT16 VendorId;\r | |
824 | UINT16 DeviceId;\r | |
825 | UINT16 Reserved0;\r | |
826 | UINT16 Length;\r | |
827 | UINT8 Revision;\r | |
828 | UINT8 ClassCode[3];\r | |
829 | UINT16 ImageLength;\r | |
830 | UINT16 CodeRevision;\r | |
831 | UINT8 CodeType;\r | |
832 | UINT8 Indicator;\r | |
833 | UINT16 Reserved1;\r | |
834 | } PCI_DATA_STRUCTURE;\r | |
835 | \r | |
836 | ///\r | |
427987f5 | 837 | /// EFI PCI Expansion ROM Header\r |
838 | /// Section 13.4.2, Unified Extensible Firmware Interface Specification, Version 2.1\r | |
bc14bdb3 | 839 | ///\r |
afcf4907 | 840 | typedef struct {\r |
bc14bdb3 | 841 | UINT16 Signature; ///< 0xaa55\r |
afcf4907 | 842 | UINT16 InitializationSize;\r |
bc14bdb3 | 843 | UINT32 EfiSignature; ///< 0x0EF1\r |
afcf4907 | 844 | UINT16 EfiSubsystem;\r |
845 | UINT16 EfiMachineType;\r | |
846 | UINT16 CompressionType;\r | |
847 | UINT8 Reserved[8];\r | |
848 | UINT16 EfiImageHeaderOffset;\r | |
849 | UINT16 PcirOffset;\r | |
850 | } EFI_PCI_EXPANSION_ROM_HEADER;\r | |
851 | \r | |
852 | typedef union {\r | |
853 | UINT8 *Raw;\r | |
854 | PCI_EXPANSION_ROM_HEADER *Generic;\r | |
855 | EFI_PCI_EXPANSION_ROM_HEADER *Efi;\r | |
856 | EFI_LEGACY_EXPANSION_ROM_HEADER *PcAt;\r | |
857 | } EFI_PCI_ROM_HEADER;\r | |
858 | \r | |
766f4bc1 | 859 | #pragma pack()\r |
860 | \r | |
a7ed1e2e | 861 | #endif\r |