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fb3df220 | 1 | /** @file\r |
50a64e5b | 2 | Provides services to access PCI Configuration Space using the MMIO PCI Express window.\r |
9095d37b LG |
3 | \r |
4 | This library is identical to the PCI Library, except the access method for performing PCI\r | |
5c065855 MSB |
5 | configuration cycles must be through the PCI Express MMIO window whose base address\r |
6 | is defined by PcdPciExpressBaseAddress and size defined by PcdPciExpressBaseSize.\r | |
7 | \r | |
fb3df220 | 8 | \r |
5f354f6a | 9 | Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r |
9344f092 | 10 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
fb3df220 | 11 | \r |
fb3df220 | 12 | **/\r |
13 | \r | |
14 | #ifndef __PCI_EXPRESS_LIB_H__\r | |
15 | #define __PCI_EXPRESS_LIB_H__\r | |
16 | \r | |
5f354f6a RN |
17 | #include <IndustryStandard/PciExpress21.h>\r |
18 | \r | |
fb3df220 | 19 | /**\r |
20 | Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an\r | |
21 | address that can be passed to the PCI Library functions.\r | |
22 | \r | |
23 | Computes an address that is compatible with the PCI Library functions. The\r | |
24 | unused upper bits of Bus, Device, Function and Register are stripped prior to\r | |
25 | the generation of the address.\r | |
26 | \r | |
27 | @param Bus PCI Bus number. Range 0..255.\r | |
28 | @param Device PCI Device number. Range 0..31.\r | |
29 | @param Function PCI Function number. Range 0..7.\r | |
30 | @param Register PCI Register number. Range 0..4095.\r | |
31 | \r | |
32 | @return The encode PCI address.\r | |
33 | \r | |
34 | **/\r | |
2f88bd3a | 35 | #define PCI_EXPRESS_LIB_ADDRESS(Bus, Device, Function, Offset) PCI_ECAM_ADDRESS ((Bus), (Device), (Function), (Offset))\r |
fb3df220 | 36 | \r |
f926e538 | 37 | /**\r |
9095d37b | 38 | Registers a PCI device so PCI configuration registers may be accessed after\r |
f926e538 | 39 | SetVirtualAddressMap().\r |
9095d37b LG |
40 | \r |
41 | Registers the PCI device specified by Address so all the PCI configuration\r | |
42 | registers associated with that PCI device may be accessed after SetVirtualAddressMap()\r | |
d11195a3 | 43 | is called.\r |
9095d37b | 44 | \r |
f926e538 | 45 | If Address > 0x0FFFFFFF, then ASSERT().\r |
46 | \r | |
47 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
48 | Register.\r | |
9095d37b | 49 | \r |
f926e538 | 50 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r |
9095d37b | 51 | @retval RETURN_UNSUPPORTED An attempt was made to call this function\r |
f926e538 | 52 | after ExitBootServices().\r |
53 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r | |
54 | at runtime could not be mapped.\r | |
55 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r | |
56 | complete the registration.\r | |
57 | \r | |
58 | **/\r | |
59 | RETURN_STATUS\r | |
60 | EFIAPI\r | |
61 | PciExpressRegisterForRuntimeAccess (\r | |
62 | IN UINTN Address\r | |
63 | );\r | |
64 | \r | |
fb3df220 | 65 | /**\r |
66 | Reads an 8-bit PCI configuration register.\r | |
67 | \r | |
68 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
69 | This function must guarantee that all PCI read and write operations are\r | |
70 | serialized.\r | |
71 | \r | |
72 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
73 | \r | |
74 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
75 | Register.\r | |
76 | \r | |
77 | @return The read value from the PCI configuration register.\r | |
78 | \r | |
79 | **/\r | |
80 | UINT8\r | |
81 | EFIAPI\r | |
82 | PciExpressRead8 (\r | |
2f88bd3a | 83 | IN UINTN Address\r |
fb3df220 | 84 | );\r |
85 | \r | |
86 | /**\r | |
87 | Writes an 8-bit PCI configuration register.\r | |
88 | \r | |
89 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
90 | value specified by Value. Value is returned. This function must guarantee\r | |
91 | that all PCI read and write operations are serialized.\r | |
92 | \r | |
93 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
94 | \r | |
95 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
96 | Register.\r | |
97 | @param Value The value to write.\r | |
98 | \r | |
99 | @return The value written to the PCI configuration register.\r | |
100 | \r | |
101 | **/\r | |
102 | UINT8\r | |
103 | EFIAPI\r | |
104 | PciExpressWrite8 (\r | |
2f88bd3a MK |
105 | IN UINTN Address,\r |
106 | IN UINT8 Value\r | |
fb3df220 | 107 | );\r |
108 | \r | |
109 | /**\r | |
62991af2 | 110 | Performs a bitwise OR of an 8-bit PCI configuration register with\r |
fb3df220 | 111 | an 8-bit value.\r |
112 | \r | |
113 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 114 | bitwise OR between the read result and the value specified by\r |
fb3df220 | 115 | OrData, and writes the result to the 8-bit PCI configuration register\r |
116 | specified by Address. The value written to the PCI configuration register is\r | |
117 | returned. This function must guarantee that all PCI read and write operations\r | |
118 | are serialized.\r | |
119 | \r | |
120 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
121 | \r | |
122 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
123 | Register.\r | |
124 | @param OrData The value to OR with the PCI configuration register.\r | |
125 | \r | |
126 | @return The value written back to the PCI configuration register.\r | |
127 | \r | |
128 | **/\r | |
129 | UINT8\r | |
130 | EFIAPI\r | |
131 | PciExpressOr8 (\r | |
2f88bd3a MK |
132 | IN UINTN Address,\r |
133 | IN UINT8 OrData\r | |
fb3df220 | 134 | );\r |
135 | \r | |
136 | /**\r | |
137 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
138 | value.\r | |
139 | \r | |
140 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
141 | bitwise AND between the read result and the value specified by AndData, and\r | |
142 | writes the result to the 8-bit PCI configuration register specified by\r | |
143 | Address. The value written to the PCI configuration register is returned.\r | |
144 | This function must guarantee that all PCI read and write operations are\r | |
145 | serialized.\r | |
146 | \r | |
147 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
148 | \r | |
149 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
150 | Register.\r | |
151 | @param AndData The value to AND with the PCI configuration register.\r | |
152 | \r | |
153 | @return The value written back to the PCI configuration register.\r | |
154 | \r | |
155 | **/\r | |
156 | UINT8\r | |
157 | EFIAPI\r | |
158 | PciExpressAnd8 (\r | |
2f88bd3a MK |
159 | IN UINTN Address,\r |
160 | IN UINT8 AndData\r | |
fb3df220 | 161 | );\r |
162 | \r | |
163 | /**\r | |
164 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
62991af2 | 165 | value, followed a bitwise OR with another 8-bit value.\r |
fb3df220 | 166 | \r |
167 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
168 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 169 | performs a bitwise OR between the result of the AND operation and\r |
fb3df220 | 170 | the value specified by OrData, and writes the result to the 8-bit PCI\r |
171 | configuration register specified by Address. The value written to the PCI\r | |
172 | configuration register is returned. This function must guarantee that all PCI\r | |
173 | read and write operations are serialized.\r | |
174 | \r | |
175 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
176 | \r | |
177 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
178 | Register.\r | |
179 | @param AndData The value to AND with the PCI configuration register.\r | |
180 | @param OrData The value to OR with the result of the AND operation.\r | |
181 | \r | |
182 | @return The value written back to the PCI configuration register.\r | |
183 | \r | |
184 | **/\r | |
185 | UINT8\r | |
186 | EFIAPI\r | |
187 | PciExpressAndThenOr8 (\r | |
2f88bd3a MK |
188 | IN UINTN Address,\r |
189 | IN UINT8 AndData,\r | |
190 | IN UINT8 OrData\r | |
fb3df220 | 191 | );\r |
192 | \r | |
193 | /**\r | |
194 | Reads a bit field of a PCI configuration register.\r | |
195 | \r | |
196 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
197 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
198 | returned.\r | |
199 | \r | |
200 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
201 | If StartBit is greater than 7, then ASSERT().\r | |
202 | If EndBit is greater than 7, then ASSERT().\r | |
203 | If EndBit is less than StartBit, then ASSERT().\r | |
204 | \r | |
205 | @param Address PCI configuration register to read.\r | |
206 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
207 | Range 0..7.\r | |
208 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
209 | Range 0..7.\r | |
210 | \r | |
211 | @return The value of the bit field read from the PCI configuration register.\r | |
212 | \r | |
213 | **/\r | |
214 | UINT8\r | |
215 | EFIAPI\r | |
216 | PciExpressBitFieldRead8 (\r | |
2f88bd3a MK |
217 | IN UINTN Address,\r |
218 | IN UINTN StartBit,\r | |
219 | IN UINTN EndBit\r | |
fb3df220 | 220 | );\r |
221 | \r | |
222 | /**\r | |
223 | Writes a bit field to a PCI configuration register.\r | |
224 | \r | |
225 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
226 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
227 | destination PCI configuration register are preserved. The new value of the\r | |
228 | 8-bit register is returned.\r | |
229 | \r | |
230 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
231 | If StartBit is greater than 7, then ASSERT().\r | |
232 | If EndBit is greater than 7, then ASSERT().\r | |
233 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 234 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fb3df220 | 235 | \r |
236 | @param Address PCI configuration register to write.\r | |
237 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
238 | Range 0..7.\r | |
239 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
240 | Range 0..7.\r | |
241 | @param Value New value of the bit field.\r | |
242 | \r | |
243 | @return The value written back to the PCI configuration register.\r | |
244 | \r | |
245 | **/\r | |
246 | UINT8\r | |
247 | EFIAPI\r | |
248 | PciExpressBitFieldWrite8 (\r | |
2f88bd3a MK |
249 | IN UINTN Address,\r |
250 | IN UINTN StartBit,\r | |
251 | IN UINTN EndBit,\r | |
252 | IN UINT8 Value\r | |
fb3df220 | 253 | );\r |
254 | \r | |
255 | /**\r | |
256 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
257 | writes the result back to the bit field in the 8-bit port.\r | |
258 | \r | |
259 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 260 | bitwise OR between the read result and the value specified by\r |
fb3df220 | 261 | OrData, and writes the result to the 8-bit PCI configuration register\r |
262 | specified by Address. The value written to the PCI configuration register is\r | |
263 | returned. This function must guarantee that all PCI read and write operations\r | |
264 | are serialized. Extra left bits in OrData are stripped.\r | |
265 | \r | |
266 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
267 | If StartBit is greater than 7, then ASSERT().\r | |
268 | If EndBit is greater than 7, then ASSERT().\r | |
269 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 270 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fb3df220 | 271 | \r |
272 | @param Address PCI configuration register to write.\r | |
273 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
274 | Range 0..7.\r | |
275 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
276 | Range 0..7.\r | |
277 | @param OrData The value to OR with the PCI configuration register.\r | |
278 | \r | |
279 | @return The value written back to the PCI configuration register.\r | |
280 | \r | |
281 | **/\r | |
282 | UINT8\r | |
283 | EFIAPI\r | |
284 | PciExpressBitFieldOr8 (\r | |
2f88bd3a MK |
285 | IN UINTN Address,\r |
286 | IN UINTN StartBit,\r | |
287 | IN UINTN EndBit,\r | |
288 | IN UINT8 OrData\r | |
fb3df220 | 289 | );\r |
290 | \r | |
291 | /**\r | |
292 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
293 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
294 | \r | |
295 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
296 | bitwise AND between the read result and the value specified by AndData, and\r | |
297 | writes the result to the 8-bit PCI configuration register specified by\r | |
298 | Address. The value written to the PCI configuration register is returned.\r | |
299 | This function must guarantee that all PCI read and write operations are\r | |
300 | serialized. Extra left bits in AndData are stripped.\r | |
301 | \r | |
302 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
303 | If StartBit is greater than 7, then ASSERT().\r | |
304 | If EndBit is greater than 7, then ASSERT().\r | |
305 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 306 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fb3df220 | 307 | \r |
308 | @param Address PCI configuration register to write.\r | |
309 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
310 | Range 0..7.\r | |
311 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
312 | Range 0..7.\r | |
313 | @param AndData The value to AND with the PCI configuration register.\r | |
314 | \r | |
315 | @return The value written back to the PCI configuration register.\r | |
316 | \r | |
317 | **/\r | |
318 | UINT8\r | |
319 | EFIAPI\r | |
320 | PciExpressBitFieldAnd8 (\r | |
2f88bd3a MK |
321 | IN UINTN Address,\r |
322 | IN UINTN StartBit,\r | |
323 | IN UINTN EndBit,\r | |
324 | IN UINT8 AndData\r | |
fb3df220 | 325 | );\r |
326 | \r | |
327 | /**\r | |
328 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 329 | bitwise OR, and writes the result back to the bit field in the\r |
fb3df220 | 330 | 8-bit port.\r |
331 | \r | |
332 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 333 | bitwise AND followed by a bitwise OR between the read result and\r |
fb3df220 | 334 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
335 | configuration register specified by Address. The value written to the PCI\r | |
336 | configuration register is returned. This function must guarantee that all PCI\r | |
337 | read and write operations are serialized. Extra left bits in both AndData and\r | |
338 | OrData are stripped.\r | |
339 | \r | |
340 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
341 | If StartBit is greater than 7, then ASSERT().\r | |
342 | If EndBit is greater than 7, then ASSERT().\r | |
343 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
344 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
345 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
fb3df220 | 346 | \r |
347 | @param Address PCI configuration register to write.\r | |
348 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
349 | Range 0..7.\r | |
350 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
351 | Range 0..7.\r | |
352 | @param AndData The value to AND with the PCI configuration register.\r | |
353 | @param OrData The value to OR with the result of the AND operation.\r | |
354 | \r | |
355 | @return The value written back to the PCI configuration register.\r | |
356 | \r | |
357 | **/\r | |
358 | UINT8\r | |
359 | EFIAPI\r | |
360 | PciExpressBitFieldAndThenOr8 (\r | |
2f88bd3a MK |
361 | IN UINTN Address,\r |
362 | IN UINTN StartBit,\r | |
363 | IN UINTN EndBit,\r | |
364 | IN UINT8 AndData,\r | |
365 | IN UINT8 OrData\r | |
fb3df220 | 366 | );\r |
367 | \r | |
368 | /**\r | |
369 | Reads a 16-bit PCI configuration register.\r | |
370 | \r | |
371 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
372 | This function must guarantee that all PCI read and write operations are\r | |
373 | serialized.\r | |
374 | \r | |
375 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
376 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
377 | \r | |
378 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
379 | Register.\r | |
380 | \r | |
381 | @return The read value from the PCI configuration register.\r | |
382 | \r | |
383 | **/\r | |
384 | UINT16\r | |
385 | EFIAPI\r | |
386 | PciExpressRead16 (\r | |
2f88bd3a | 387 | IN UINTN Address\r |
fb3df220 | 388 | );\r |
389 | \r | |
390 | /**\r | |
391 | Writes a 16-bit PCI configuration register.\r | |
392 | \r | |
393 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
394 | value specified by Value. Value is returned. This function must guarantee\r | |
395 | that all PCI read and write operations are serialized.\r | |
396 | \r | |
397 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
398 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
399 | \r | |
400 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
401 | Register.\r | |
402 | @param Value The value to write.\r | |
403 | \r | |
404 | @return The value written to the PCI configuration register.\r | |
405 | \r | |
406 | **/\r | |
407 | UINT16\r | |
408 | EFIAPI\r | |
409 | PciExpressWrite16 (\r | |
2f88bd3a MK |
410 | IN UINTN Address,\r |
411 | IN UINT16 Value\r | |
fb3df220 | 412 | );\r |
413 | \r | |
414 | /**\r | |
62991af2 | 415 | Performs a bitwise OR of a 16-bit PCI configuration register with\r |
fb3df220 | 416 | a 16-bit value.\r |
417 | \r | |
418 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 419 | bitwise OR between the read result and the value specified by\r |
fb3df220 | 420 | OrData, and writes the result to the 16-bit PCI configuration register\r |
421 | specified by Address. The value written to the PCI configuration register is\r | |
422 | returned. This function must guarantee that all PCI read and write operations\r | |
423 | are serialized.\r | |
424 | \r | |
425 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
426 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
427 | \r | |
428 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
429 | Register.\r | |
430 | @param OrData The value to OR with the PCI configuration register.\r | |
431 | \r | |
432 | @return The value written back to the PCI configuration register.\r | |
433 | \r | |
434 | **/\r | |
435 | UINT16\r | |
436 | EFIAPI\r | |
437 | PciExpressOr16 (\r | |
2f88bd3a MK |
438 | IN UINTN Address,\r |
439 | IN UINT16 OrData\r | |
fb3df220 | 440 | );\r |
441 | \r | |
442 | /**\r | |
443 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
444 | value.\r | |
445 | \r | |
446 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
447 | bitwise AND between the read result and the value specified by AndData, and\r | |
448 | writes the result to the 16-bit PCI configuration register specified by\r | |
449 | Address. The value written to the PCI configuration register is returned.\r | |
450 | This function must guarantee that all PCI read and write operations are\r | |
451 | serialized.\r | |
452 | \r | |
453 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
454 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
455 | \r | |
456 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
457 | Register.\r | |
458 | @param AndData The value to AND with the PCI configuration register.\r | |
459 | \r | |
460 | @return The value written back to the PCI configuration register.\r | |
461 | \r | |
462 | **/\r | |
463 | UINT16\r | |
464 | EFIAPI\r | |
465 | PciExpressAnd16 (\r | |
2f88bd3a MK |
466 | IN UINTN Address,\r |
467 | IN UINT16 AndData\r | |
fb3df220 | 468 | );\r |
469 | \r | |
470 | /**\r | |
471 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
62991af2 | 472 | value, followed a bitwise OR with another 16-bit value.\r |
fb3df220 | 473 | \r |
474 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
475 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 476 | performs a bitwise OR between the result of the AND operation and\r |
fb3df220 | 477 | the value specified by OrData, and writes the result to the 16-bit PCI\r |
478 | configuration register specified by Address. The value written to the PCI\r | |
479 | configuration register is returned. This function must guarantee that all PCI\r | |
480 | read and write operations are serialized.\r | |
481 | \r | |
482 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
483 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
484 | \r | |
485 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
486 | Register.\r | |
487 | @param AndData The value to AND with the PCI configuration register.\r | |
488 | @param OrData The value to OR with the result of the AND operation.\r | |
489 | \r | |
490 | @return The value written back to the PCI configuration register.\r | |
491 | \r | |
492 | **/\r | |
493 | UINT16\r | |
494 | EFIAPI\r | |
495 | PciExpressAndThenOr16 (\r | |
2f88bd3a MK |
496 | IN UINTN Address,\r |
497 | IN UINT16 AndData,\r | |
498 | IN UINT16 OrData\r | |
fb3df220 | 499 | );\r |
500 | \r | |
501 | /**\r | |
502 | Reads a bit field of a PCI configuration register.\r | |
503 | \r | |
504 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
505 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
506 | returned.\r | |
507 | \r | |
508 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
509 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
510 | If StartBit is greater than 15, then ASSERT().\r | |
511 | If EndBit is greater than 15, then ASSERT().\r | |
512 | If EndBit is less than StartBit, then ASSERT().\r | |
513 | \r | |
514 | @param Address PCI configuration register to read.\r | |
515 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
516 | Range 0..15.\r | |
517 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
518 | Range 0..15.\r | |
519 | \r | |
520 | @return The value of the bit field read from the PCI configuration register.\r | |
521 | \r | |
522 | **/\r | |
523 | UINT16\r | |
524 | EFIAPI\r | |
525 | PciExpressBitFieldRead16 (\r | |
2f88bd3a MK |
526 | IN UINTN Address,\r |
527 | IN UINTN StartBit,\r | |
528 | IN UINTN EndBit\r | |
fb3df220 | 529 | );\r |
530 | \r | |
531 | /**\r | |
532 | Writes a bit field to a PCI configuration register.\r | |
533 | \r | |
534 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
535 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
536 | destination PCI configuration register are preserved. The new value of the\r | |
537 | 16-bit register is returned.\r | |
538 | \r | |
539 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
540 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
541 | If StartBit is greater than 15, then ASSERT().\r | |
542 | If EndBit is greater than 15, then ASSERT().\r | |
543 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 544 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fb3df220 | 545 | \r |
546 | @param Address PCI configuration register to write.\r | |
547 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
548 | Range 0..15.\r | |
549 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
550 | Range 0..15.\r | |
551 | @param Value New value of the bit field.\r | |
552 | \r | |
553 | @return The value written back to the PCI configuration register.\r | |
554 | \r | |
555 | **/\r | |
556 | UINT16\r | |
557 | EFIAPI\r | |
558 | PciExpressBitFieldWrite16 (\r | |
2f88bd3a MK |
559 | IN UINTN Address,\r |
560 | IN UINTN StartBit,\r | |
561 | IN UINTN EndBit,\r | |
562 | IN UINT16 Value\r | |
fb3df220 | 563 | );\r |
564 | \r | |
565 | /**\r | |
566 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
567 | writes the result back to the bit field in the 16-bit port.\r | |
568 | \r | |
569 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 570 | bitwise OR between the read result and the value specified by\r |
fb3df220 | 571 | OrData, and writes the result to the 16-bit PCI configuration register\r |
572 | specified by Address. The value written to the PCI configuration register is\r | |
573 | returned. This function must guarantee that all PCI read and write operations\r | |
574 | are serialized. Extra left bits in OrData are stripped.\r | |
575 | \r | |
576 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
577 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
578 | If StartBit is greater than 15, then ASSERT().\r | |
579 | If EndBit is greater than 15, then ASSERT().\r | |
580 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 581 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fb3df220 | 582 | \r |
583 | @param Address PCI configuration register to write.\r | |
584 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
585 | Range 0..15.\r | |
586 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
587 | Range 0..15.\r | |
588 | @param OrData The value to OR with the PCI configuration register.\r | |
589 | \r | |
590 | @return The value written back to the PCI configuration register.\r | |
591 | \r | |
592 | **/\r | |
593 | UINT16\r | |
594 | EFIAPI\r | |
595 | PciExpressBitFieldOr16 (\r | |
2f88bd3a MK |
596 | IN UINTN Address,\r |
597 | IN UINTN StartBit,\r | |
598 | IN UINTN EndBit,\r | |
599 | IN UINT16 OrData\r | |
fb3df220 | 600 | );\r |
601 | \r | |
602 | /**\r | |
603 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
604 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
605 | \r | |
606 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
607 | bitwise AND between the read result and the value specified by AndData, and\r | |
608 | writes the result to the 16-bit PCI configuration register specified by\r | |
609 | Address. The value written to the PCI configuration register is returned.\r | |
610 | This function must guarantee that all PCI read and write operations are\r | |
611 | serialized. Extra left bits in AndData are stripped.\r | |
612 | \r | |
613 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
614 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
615 | If StartBit is greater than 15, then ASSERT().\r | |
616 | If EndBit is greater than 15, then ASSERT().\r | |
617 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 618 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fb3df220 | 619 | \r |
620 | @param Address PCI configuration register to write.\r | |
621 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
622 | Range 0..15.\r | |
623 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
624 | Range 0..15.\r | |
625 | @param AndData The value to AND with the PCI configuration register.\r | |
626 | \r | |
627 | @return The value written back to the PCI configuration register.\r | |
628 | \r | |
629 | **/\r | |
630 | UINT16\r | |
631 | EFIAPI\r | |
632 | PciExpressBitFieldAnd16 (\r | |
2f88bd3a MK |
633 | IN UINTN Address,\r |
634 | IN UINTN StartBit,\r | |
635 | IN UINTN EndBit,\r | |
636 | IN UINT16 AndData\r | |
fb3df220 | 637 | );\r |
638 | \r | |
639 | /**\r | |
640 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 641 | bitwise OR, and writes the result back to the bit field in the\r |
fb3df220 | 642 | 16-bit port.\r |
643 | \r | |
644 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 645 | bitwise AND followed by a bitwise OR between the read result and\r |
fb3df220 | 646 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
647 | configuration register specified by Address. The value written to the PCI\r | |
648 | configuration register is returned. This function must guarantee that all PCI\r | |
649 | read and write operations are serialized. Extra left bits in both AndData and\r | |
650 | OrData are stripped.\r | |
651 | \r | |
652 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
653 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
654 | If StartBit is greater than 15, then ASSERT().\r | |
655 | If EndBit is greater than 15, then ASSERT().\r | |
656 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
657 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
658 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
fb3df220 | 659 | \r |
660 | @param Address PCI configuration register to write.\r | |
661 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
662 | Range 0..15.\r | |
663 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
664 | Range 0..15.\r | |
665 | @param AndData The value to AND with the PCI configuration register.\r | |
666 | @param OrData The value to OR with the result of the AND operation.\r | |
667 | \r | |
668 | @return The value written back to the PCI configuration register.\r | |
669 | \r | |
670 | **/\r | |
671 | UINT16\r | |
672 | EFIAPI\r | |
673 | PciExpressBitFieldAndThenOr16 (\r | |
2f88bd3a MK |
674 | IN UINTN Address,\r |
675 | IN UINTN StartBit,\r | |
676 | IN UINTN EndBit,\r | |
677 | IN UINT16 AndData,\r | |
678 | IN UINT16 OrData\r | |
fb3df220 | 679 | );\r |
680 | \r | |
681 | /**\r | |
682 | Reads a 32-bit PCI configuration register.\r | |
683 | \r | |
684 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
685 | This function must guarantee that all PCI read and write operations are\r | |
686 | serialized.\r | |
687 | \r | |
688 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
689 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
690 | \r | |
691 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
692 | Register.\r | |
693 | \r | |
694 | @return The read value from the PCI configuration register.\r | |
695 | \r | |
696 | **/\r | |
697 | UINT32\r | |
698 | EFIAPI\r | |
699 | PciExpressRead32 (\r | |
2f88bd3a | 700 | IN UINTN Address\r |
fb3df220 | 701 | );\r |
702 | \r | |
703 | /**\r | |
704 | Writes a 32-bit PCI configuration register.\r | |
705 | \r | |
706 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
707 | value specified by Value. Value is returned. This function must guarantee\r | |
708 | that all PCI read and write operations are serialized.\r | |
709 | \r | |
710 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
711 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
712 | \r | |
713 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
714 | Register.\r | |
715 | @param Value The value to write.\r | |
716 | \r | |
717 | @return The value written to the PCI configuration register.\r | |
718 | \r | |
719 | **/\r | |
720 | UINT32\r | |
721 | EFIAPI\r | |
722 | PciExpressWrite32 (\r | |
2f88bd3a MK |
723 | IN UINTN Address,\r |
724 | IN UINT32 Value\r | |
fb3df220 | 725 | );\r |
726 | \r | |
727 | /**\r | |
62991af2 | 728 | Performs a bitwise OR of a 32-bit PCI configuration register with\r |
fb3df220 | 729 | a 32-bit value.\r |
730 | \r | |
731 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 732 | bitwise OR between the read result and the value specified by\r |
fb3df220 | 733 | OrData, and writes the result to the 32-bit PCI configuration register\r |
734 | specified by Address. The value written to the PCI configuration register is\r | |
735 | returned. This function must guarantee that all PCI read and write operations\r | |
736 | are serialized.\r | |
737 | \r | |
738 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
739 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
740 | \r | |
741 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
742 | Register.\r | |
743 | @param OrData The value to OR with the PCI configuration register.\r | |
744 | \r | |
745 | @return The value written back to the PCI configuration register.\r | |
746 | \r | |
747 | **/\r | |
748 | UINT32\r | |
749 | EFIAPI\r | |
750 | PciExpressOr32 (\r | |
2f88bd3a MK |
751 | IN UINTN Address,\r |
752 | IN UINT32 OrData\r | |
fb3df220 | 753 | );\r |
754 | \r | |
755 | /**\r | |
756 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
757 | value.\r | |
758 | \r | |
759 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
760 | bitwise AND between the read result and the value specified by AndData, and\r | |
761 | writes the result to the 32-bit PCI configuration register specified by\r | |
762 | Address. The value written to the PCI configuration register is returned.\r | |
763 | This function must guarantee that all PCI read and write operations are\r | |
764 | serialized.\r | |
765 | \r | |
766 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
767 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
768 | \r | |
769 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
770 | Register.\r | |
771 | @param AndData The value to AND with the PCI configuration register.\r | |
772 | \r | |
773 | @return The value written back to the PCI configuration register.\r | |
774 | \r | |
775 | **/\r | |
776 | UINT32\r | |
777 | EFIAPI\r | |
778 | PciExpressAnd32 (\r | |
2f88bd3a MK |
779 | IN UINTN Address,\r |
780 | IN UINT32 AndData\r | |
fb3df220 | 781 | );\r |
782 | \r | |
783 | /**\r | |
784 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
62991af2 | 785 | value, followed a bitwise OR with another 32-bit value.\r |
fb3df220 | 786 | \r |
787 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
788 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 789 | performs a bitwise OR between the result of the AND operation and\r |
fb3df220 | 790 | the value specified by OrData, and writes the result to the 32-bit PCI\r |
791 | configuration register specified by Address. The value written to the PCI\r | |
792 | configuration register is returned. This function must guarantee that all PCI\r | |
793 | read and write operations are serialized.\r | |
794 | \r | |
795 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
796 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
797 | \r | |
798 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
799 | Register.\r | |
800 | @param AndData The value to AND with the PCI configuration register.\r | |
801 | @param OrData The value to OR with the result of the AND operation.\r | |
802 | \r | |
803 | @return The value written back to the PCI configuration register.\r | |
804 | \r | |
805 | **/\r | |
806 | UINT32\r | |
807 | EFIAPI\r | |
808 | PciExpressAndThenOr32 (\r | |
2f88bd3a MK |
809 | IN UINTN Address,\r |
810 | IN UINT32 AndData,\r | |
811 | IN UINT32 OrData\r | |
fb3df220 | 812 | );\r |
813 | \r | |
814 | /**\r | |
815 | Reads a bit field of a PCI configuration register.\r | |
816 | \r | |
817 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
818 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
819 | returned.\r | |
820 | \r | |
821 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
822 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
823 | If StartBit is greater than 31, then ASSERT().\r | |
824 | If EndBit is greater than 31, then ASSERT().\r | |
825 | If EndBit is less than StartBit, then ASSERT().\r | |
826 | \r | |
827 | @param Address PCI configuration register to read.\r | |
828 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
829 | Range 0..31.\r | |
830 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
831 | Range 0..31.\r | |
832 | \r | |
833 | @return The value of the bit field read from the PCI configuration register.\r | |
834 | \r | |
835 | **/\r | |
836 | UINT32\r | |
837 | EFIAPI\r | |
838 | PciExpressBitFieldRead32 (\r | |
2f88bd3a MK |
839 | IN UINTN Address,\r |
840 | IN UINTN StartBit,\r | |
841 | IN UINTN EndBit\r | |
fb3df220 | 842 | );\r |
843 | \r | |
844 | /**\r | |
845 | Writes a bit field to a PCI configuration register.\r | |
846 | \r | |
847 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
848 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
849 | destination PCI configuration register are preserved. The new value of the\r | |
850 | 32-bit register is returned.\r | |
851 | \r | |
852 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
853 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
854 | If StartBit is greater than 31, then ASSERT().\r | |
855 | If EndBit is greater than 31, then ASSERT().\r | |
856 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 857 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fb3df220 | 858 | \r |
859 | @param Address PCI configuration register to write.\r | |
860 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
861 | Range 0..31.\r | |
862 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
863 | Range 0..31.\r | |
864 | @param Value New value of the bit field.\r | |
865 | \r | |
866 | @return The value written back to the PCI configuration register.\r | |
867 | \r | |
868 | **/\r | |
869 | UINT32\r | |
870 | EFIAPI\r | |
871 | PciExpressBitFieldWrite32 (\r | |
2f88bd3a MK |
872 | IN UINTN Address,\r |
873 | IN UINTN StartBit,\r | |
874 | IN UINTN EndBit,\r | |
875 | IN UINT32 Value\r | |
fb3df220 | 876 | );\r |
877 | \r | |
878 | /**\r | |
879 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
880 | writes the result back to the bit field in the 32-bit port.\r | |
881 | \r | |
882 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 883 | bitwise OR between the read result and the value specified by\r |
fb3df220 | 884 | OrData, and writes the result to the 32-bit PCI configuration register\r |
885 | specified by Address. The value written to the PCI configuration register is\r | |
886 | returned. This function must guarantee that all PCI read and write operations\r | |
887 | are serialized. Extra left bits in OrData are stripped.\r | |
888 | \r | |
889 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
890 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
891 | If StartBit is greater than 31, then ASSERT().\r | |
892 | If EndBit is greater than 31, then ASSERT().\r | |
893 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 894 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fb3df220 | 895 | \r |
896 | @param Address PCI configuration register to write.\r | |
897 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
898 | Range 0..31.\r | |
899 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
900 | Range 0..31.\r | |
901 | @param OrData The value to OR with the PCI configuration register.\r | |
902 | \r | |
903 | @return The value written back to the PCI configuration register.\r | |
904 | \r | |
905 | **/\r | |
906 | UINT32\r | |
907 | EFIAPI\r | |
908 | PciExpressBitFieldOr32 (\r | |
2f88bd3a MK |
909 | IN UINTN Address,\r |
910 | IN UINTN StartBit,\r | |
911 | IN UINTN EndBit,\r | |
912 | IN UINT32 OrData\r | |
fb3df220 | 913 | );\r |
914 | \r | |
915 | /**\r | |
916 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
917 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
918 | \r | |
919 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
920 | bitwise AND between the read result and the value specified by AndData, and\r | |
921 | writes the result to the 32-bit PCI configuration register specified by\r | |
922 | Address. The value written to the PCI configuration register is returned.\r | |
923 | This function must guarantee that all PCI read and write operations are\r | |
924 | serialized. Extra left bits in AndData are stripped.\r | |
925 | \r | |
926 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
927 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
928 | If StartBit is greater than 31, then ASSERT().\r | |
929 | If EndBit is greater than 31, then ASSERT().\r | |
930 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 931 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fb3df220 | 932 | \r |
933 | @param Address PCI configuration register to write.\r | |
934 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
935 | Range 0..31.\r | |
936 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
937 | Range 0..31.\r | |
938 | @param AndData The value to AND with the PCI configuration register.\r | |
939 | \r | |
940 | @return The value written back to the PCI configuration register.\r | |
941 | \r | |
942 | **/\r | |
943 | UINT32\r | |
944 | EFIAPI\r | |
945 | PciExpressBitFieldAnd32 (\r | |
2f88bd3a MK |
946 | IN UINTN Address,\r |
947 | IN UINTN StartBit,\r | |
948 | IN UINTN EndBit,\r | |
949 | IN UINT32 AndData\r | |
fb3df220 | 950 | );\r |
951 | \r | |
952 | /**\r | |
953 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 954 | bitwise OR, and writes the result back to the bit field in the\r |
fb3df220 | 955 | 32-bit port.\r |
956 | \r | |
957 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 958 | bitwise AND followed by a bitwise OR between the read result and\r |
fb3df220 | 959 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
960 | configuration register specified by Address. The value written to the PCI\r | |
961 | configuration register is returned. This function must guarantee that all PCI\r | |
962 | read and write operations are serialized. Extra left bits in both AndData and\r | |
963 | OrData are stripped.\r | |
964 | \r | |
965 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
966 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
967 | If StartBit is greater than 31, then ASSERT().\r | |
968 | If EndBit is greater than 31, then ASSERT().\r | |
969 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
970 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
971 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
fb3df220 | 972 | \r |
973 | @param Address PCI configuration register to write.\r | |
974 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
975 | Range 0..31.\r | |
976 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
977 | Range 0..31.\r | |
978 | @param AndData The value to AND with the PCI configuration register.\r | |
979 | @param OrData The value to OR with the result of the AND operation.\r | |
980 | \r | |
981 | @return The value written back to the PCI configuration register.\r | |
982 | \r | |
983 | **/\r | |
984 | UINT32\r | |
985 | EFIAPI\r | |
986 | PciExpressBitFieldAndThenOr32 (\r | |
2f88bd3a MK |
987 | IN UINTN Address,\r |
988 | IN UINTN StartBit,\r | |
989 | IN UINTN EndBit,\r | |
990 | IN UINT32 AndData,\r | |
991 | IN UINT32 OrData\r | |
fb3df220 | 992 | );\r |
993 | \r | |
994 | /**\r | |
995 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
996 | \r | |
997 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
998 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
999 | configuration registers from a single PCI function to be read. Size is\r | |
1000 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
a8ecf980 | 1001 | from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit\r |
fb3df220 | 1002 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r |
1003 | end of the range.\r | |
1004 | \r | |
1005 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1006 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1007 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1008 | \r | |
1009 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
1010 | Function and Register.\r | |
1011 | @param Size Size in bytes of the transfer.\r | |
1012 | @param Buffer Pointer to a buffer receiving the data read.\r | |
1013 | \r | |
badcbfb2 | 1014 | @return Size read data from StartAddress.\r |
fb3df220 | 1015 | \r |
1016 | **/\r | |
1017 | UINTN\r | |
1018 | EFIAPI\r | |
1019 | PciExpressReadBuffer (\r | |
2f88bd3a MK |
1020 | IN UINTN StartAddress,\r |
1021 | IN UINTN Size,\r | |
1022 | OUT VOID *Buffer\r | |
fb3df220 | 1023 | );\r |
1024 | \r | |
1025 | /**\r | |
1026 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1027 | configuration space.\r | |
1028 | \r | |
1029 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1030 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1031 | configuration registers from a single PCI function to be written. Size is\r | |
1032 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
a8ecf980 | 1033 | write from StartAddress to StartAddress + Size. Due to alignment restrictions,\r |
fb3df220 | 1034 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r |
1035 | and the end of the range.\r | |
1036 | \r | |
1037 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1038 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1039 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1040 | \r | |
1041 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
1042 | Function and Register.\r | |
1043 | @param Size Size in bytes of the transfer.\r | |
1044 | @param Buffer Pointer to a buffer containing the data to write.\r | |
1045 | \r | |
9199040c | 1046 | @return Size written to StartAddress.\r |
fb3df220 | 1047 | \r |
1048 | **/\r | |
1049 | UINTN\r | |
1050 | EFIAPI\r | |
1051 | PciExpressWriteBuffer (\r | |
2f88bd3a MK |
1052 | IN UINTN StartAddress,\r |
1053 | IN UINTN Size,\r | |
1054 | IN VOID *Buffer\r | |
fb3df220 | 1055 | );\r |
1056 | \r | |
1057 | #endif\r |