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fb3df220 | 1 | /** @file\r |
50a64e5b | 2 | Provides services to access PCI Configuration Space on a platform with multiple PCI segments.\r |
badcbfb2 | 3 | \r |
4 | The PCI Segment Library function provide services to read, write, and modify the PCI configuration\r | |
5 | registers on PCI root bridges on any supported PCI segment. These library services take a single \r | |
6 | address parameter that encodes the PCI Segment, PCI Bus, PCI Device, PCI Function, and PCI Register. \r | |
7 | The layout of this address parameter is as follows:\r | |
8 | \r | |
40731047 | 9 | PCI Register: Bits 0..11\r |
10 | PCI Function Bits 12..14\r | |
11 | PCI Device Bits 15..19\r | |
12 | PCI Bus Bits 20..27\r | |
13 | Reserved Bits 28..31. Must be 0.\r | |
14 | PCI Segment Bits 32..47\r | |
15 | Reserved Bits 48..63. Must be 0.\r | |
badcbfb2 | 16 | \r |
17 | | Reserved (MBZ) | Segment | Reserved (MBZ) | Bus | Device | Function | Register |\r | |
18 | 63 48 47 32 31 28 27 20 19 15 14 12 11 0\r | |
19 | \r | |
20 | These functions perform PCI configuration cycles using the default PCI configuration access \r | |
21 | method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, or it \r | |
22 | may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some alternate \r | |
23 | access method. Modules will typically use the PCI Segment Library for its PCI configuration \r | |
24 | accesses when PCI Segments other than Segment #0 must be accessed. \r | |
fb3df220 | 25 | \r |
2b27b557 | 26 | Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r |
9df063a0 | 27 | This program and the accompanying materials\r |
50a64e5b | 28 | are licensed and made available under the terms and conditions of the BSD License\r |
29 | which accompanies this distribution. The full text of the license may be found at\r | |
30 | http://opensource.org/licenses/bsd-license.php\r | |
fb3df220 | 31 | \r |
50a64e5b | 32 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
33 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
fb3df220 | 34 | \r |
fb3df220 | 35 | **/\r |
36 | \r | |
37 | #ifndef __PCI_SEGMENT_LIB__\r | |
38 | #define __PCI_SEGMENT_LIB__\r | |
39 | \r | |
40 | \r | |
41 | /**\r | |
42 | Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,\r | |
43 | and PCI Register to an address that can be passed to the PCI Segment Library functions.\r | |
44 | \r | |
45 | Computes an address that is compatible with the PCI Segment Library functions.\r | |
46 | The unused upper bits of Segment, Bus, Device, Function,\r | |
47 | and Register are stripped prior to the generation of the address.\r | |
48 | \r | |
49 | @param Segment PCI Segment number. Range 0..65535.\r | |
50 | @param Bus PCI Bus number. Range 0..255.\r | |
51 | @param Device PCI Device number. Range 0..31.\r | |
52 | @param Function PCI Function number. Range 0..7.\r | |
53 | @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095 for PCI Express.\r | |
54 | \r | |
55 | @return The address that is compatible with the PCI Segment Library functions.\r | |
56 | \r | |
57 | **/\r | |
58 | #define PCI_SEGMENT_LIB_ADDRESS(Segment,Bus,Device,Function,Register) \\r | |
2b27b557 MK |
59 | ((Segment != 0) ? \\r |
60 | ( ((Register) & 0xfff) | \\r | |
61 | (((Function) & 0x07) << 12) | \\r | |
62 | (((Device) & 0x1f) << 15) | \\r | |
63 | (((Bus) & 0xff) << 20) | \\r | |
64 | (LShiftU64 ((Segment) & 0xffff, 32)) \\r | |
65 | ) : \\r | |
66 | ( ((Register) & 0xfff) | \\r | |
67 | (((Function) & 0x07) << 12) | \\r | |
68 | (((Device) & 0x1f) << 15) | \\r | |
69 | (((Bus) & 0xff) << 20) \\r | |
70 | ) \\r | |
fb3df220 | 71 | )\r |
72 | \r | |
f926e538 | 73 | /**\r |
74 | Register a PCI device so PCI configuration registers may be accessed after \r | |
75 | SetVirtualAddressMap().\r | |
76 | \r | |
59ceeabe | 77 | If any reserved bits in Address are set, then ASSERT().\r |
f926e538 | 78 | \r |
79 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
80 | Register.\r | |
81 | \r | |
82 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r | |
83 | @retval RETURN_UNSUPPORTED An attempt was made to call this function \r | |
84 | after ExitBootServices().\r | |
85 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r | |
86 | at runtime could not be mapped.\r | |
87 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r | |
88 | complete the registration.\r | |
89 | \r | |
90 | **/\r | |
91 | RETURN_STATUS\r | |
92 | EFIAPI\r | |
93 | PciSegmentRegisterForRuntimeAccess (\r | |
94 | IN UINTN Address\r | |
95 | );\r | |
96 | \r | |
fb3df220 | 97 | /**\r |
98 | Reads an 8-bit PCI configuration register.\r | |
99 | \r | |
100 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
101 | This function must guarantee that all PCI read and write operations are serialized.\r | |
badcbfb2 | 102 | \r |
fb3df220 | 103 | If any reserved bits in Address are set, then ASSERT().\r |
104 | \r | |
105 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
106 | \r | |
107 | @return The 8-bit PCI configuration register specified by Address.\r | |
108 | \r | |
109 | **/\r | |
110 | UINT8\r | |
111 | EFIAPI\r | |
112 | PciSegmentRead8 (\r | |
113 | IN UINT64 Address\r | |
ed66e1bc | 114 | );\r |
fb3df220 | 115 | \r |
116 | /**\r | |
117 | Writes an 8-bit PCI configuration register.\r | |
118 | \r | |
119 | Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r | |
120 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
badcbfb2 | 121 | \r |
59ceeabe | 122 | If any reserved bits in Address are set, then ASSERT().\r |
fb3df220 | 123 | \r |
124 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
125 | @param Value The value to write.\r | |
126 | \r | |
d5979dc0 | 127 | @return The value written to the PCI configuration register.\r |
fb3df220 | 128 | \r |
129 | **/\r | |
130 | UINT8\r | |
131 | EFIAPI\r | |
132 | PciSegmentWrite8 (\r | |
133 | IN UINT64 Address,\r | |
134 | IN UINT8 Value\r | |
ed66e1bc | 135 | );\r |
fb3df220 | 136 | \r |
137 | /**\r | |
62991af2 | 138 | Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.\r |
fb3df220 | 139 | \r |
140 | Reads the 8-bit PCI configuration register specified by Address,\r | |
62991af2 | 141 | performs a bitwise OR between the read result and the value specified by OrData,\r |
fb3df220 | 142 | and writes the result to the 8-bit PCI configuration register specified by Address.\r |
143 | The value written to the PCI configuration register is returned.\r | |
144 | This function must guarantee that all PCI read and write operations are serialized.\r | |
badcbfb2 | 145 | \r |
fb3df220 | 146 | If any reserved bits in Address are set, then ASSERT().\r |
147 | \r | |
148 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
149 | @param OrData The value to OR with the PCI configuration register.\r | |
150 | \r | |
151 | @return The value written to the PCI configuration register.\r | |
152 | \r | |
153 | **/\r | |
154 | UINT8\r | |
155 | EFIAPI\r | |
156 | PciSegmentOr8 (\r | |
157 | IN UINT64 Address,\r | |
158 | IN UINT8 OrData\r | |
ed66e1bc | 159 | );\r |
fb3df220 | 160 | \r |
161 | /**\r | |
162 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.\r | |
163 | \r | |
164 | Reads the 8-bit PCI configuration register specified by Address,\r | |
165 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
166 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
167 | The value written to the PCI configuration register is returned.\r | |
168 | This function must guarantee that all PCI read and write operations are serialized.\r | |
169 | If any reserved bits in Address are set, then ASSERT().\r | |
170 | \r | |
171 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
7d9333a9 | 172 | @param AndData The value to AND with the PCI configuration register.\r |
fb3df220 | 173 | \r |
174 | @return The value written to the PCI configuration register.\r | |
175 | \r | |
176 | **/\r | |
177 | UINT8\r | |
178 | EFIAPI\r | |
179 | PciSegmentAnd8 (\r | |
180 | IN UINT64 Address,\r | |
181 | IN UINT8 AndData\r | |
ed66e1bc | 182 | );\r |
fb3df220 | 183 | \r |
184 | /**\r | |
185 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,\r | |
62991af2 | 186 | followed a bitwise OR with another 8-bit value.\r |
fb3df220 | 187 | \r |
188 | Reads the 8-bit PCI configuration register specified by Address,\r | |
189 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 190 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r |
fb3df220 | 191 | and writes the result to the 8-bit PCI configuration register specified by Address.\r |
192 | The value written to the PCI configuration register is returned.\r | |
193 | This function must guarantee that all PCI read and write operations are serialized.\r | |
badcbfb2 | 194 | \r |
fb3df220 | 195 | If any reserved bits in Address are set, then ASSERT().\r |
196 | \r | |
197 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
42eedea9 | 198 | @param AndData The value to AND with the PCI configuration register.\r |
fb3df220 | 199 | @param OrData The value to OR with the PCI configuration register.\r |
200 | \r | |
201 | @return The value written to the PCI configuration register.\r | |
202 | \r | |
203 | **/\r | |
204 | UINT8\r | |
205 | EFIAPI\r | |
206 | PciSegmentAndThenOr8 (\r | |
207 | IN UINT64 Address,\r | |
208 | IN UINT8 AndData,\r | |
209 | IN UINT8 OrData\r | |
ed66e1bc | 210 | );\r |
fb3df220 | 211 | \r |
212 | /**\r | |
213 | Reads a bit field of a PCI configuration register.\r | |
214 | \r | |
d5979dc0 | 215 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r |
216 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
217 | returned.\r | |
218 | \r | |
fb3df220 | 219 | If any reserved bits in Address are set, then ASSERT().\r |
220 | If StartBit is greater than 7, then ASSERT().\r | |
221 | If EndBit is greater than 7, then ASSERT().\r | |
222 | If EndBit is less than StartBit, then ASSERT().\r | |
223 | \r | |
d5979dc0 | 224 | @param Address PCI configuration register to read.\r |
fb3df220 | 225 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
d5979dc0 | 226 | Range 0..7.\r |
fb3df220 | 227 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
d5979dc0 | 228 | Range 0..7.\r |
fb3df220 | 229 | \r |
d5979dc0 | 230 | @return The value of the bit field read from the PCI configuration register.\r |
fb3df220 | 231 | \r |
232 | **/\r | |
233 | UINT8\r | |
234 | EFIAPI\r | |
235 | PciSegmentBitFieldRead8 (\r | |
236 | IN UINT64 Address,\r | |
237 | IN UINTN StartBit,\r | |
238 | IN UINTN EndBit\r | |
ed66e1bc | 239 | );\r |
fb3df220 | 240 | \r |
241 | /**\r | |
242 | Writes a bit field to a PCI configuration register.\r | |
243 | \r | |
d5979dc0 | 244 | Writes Value to the bit field of the PCI configuration register. The bit\r |
245 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
246 | destination PCI configuration register are preserved. The new value of the\r | |
247 | 8-bit register is returned.\r | |
248 | \r | |
fb3df220 | 249 | If any reserved bits in Address are set, then ASSERT().\r |
250 | If StartBit is greater than 7, then ASSERT().\r | |
251 | If EndBit is greater than 7, then ASSERT().\r | |
252 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 253 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fb3df220 | 254 | \r |
d5979dc0 | 255 | @param Address PCI configuration register to write.\r |
fb3df220 | 256 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
d5979dc0 | 257 | Range 0..7.\r |
fb3df220 | 258 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
d5979dc0 | 259 | Range 0..7.\r |
fb3df220 | 260 | @param Value New value of the bit field.\r |
261 | \r | |
d5979dc0 | 262 | @return The value written back to the PCI configuration register.\r |
fb3df220 | 263 | \r |
264 | **/\r | |
265 | UINT8\r | |
266 | EFIAPI\r | |
267 | PciSegmentBitFieldWrite8 (\r | |
268 | IN UINT64 Address,\r | |
269 | IN UINTN StartBit,\r | |
270 | IN UINTN EndBit,\r | |
271 | IN UINT8 Value\r | |
ed66e1bc | 272 | );\r |
fb3df220 | 273 | \r |
274 | /**\r | |
d5979dc0 | 275 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r |
276 | writes the result back to the bit field in the 8-bit port.\r | |
277 | \r | |
278 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 279 | bitwise OR between the read result and the value specified by\r |
d5979dc0 | 280 | OrData, and writes the result to the 8-bit PCI configuration register\r |
281 | specified by Address. The value written to the PCI configuration register is\r | |
282 | returned. This function must guarantee that all PCI read and write operations\r | |
283 | are serialized. Extra left bits in OrData are stripped.\r | |
284 | \r | |
badcbfb2 | 285 | If any reserved bits in Address are set, then ASSERT().\r |
286 | If StartBit is greater than 7, then ASSERT().\r | |
287 | If EndBit is greater than 7, then ASSERT().\r | |
288 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 289 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fb3df220 | 290 | \r |
d5979dc0 | 291 | @param Address PCI configuration register to write.\r |
fb3df220 | 292 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
d5979dc0 | 293 | Range 0..7.\r |
fb3df220 | 294 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
d5979dc0 | 295 | Range 0..7.\r |
296 | @param OrData The value to OR with the PCI configuration register.\r | |
fb3df220 | 297 | \r |
d5979dc0 | 298 | @return The value written back to the PCI configuration register.\r |
fb3df220 | 299 | \r |
300 | **/\r | |
301 | UINT8\r | |
302 | EFIAPI\r | |
303 | PciSegmentBitFieldOr8 (\r | |
304 | IN UINT64 Address,\r | |
305 | IN UINTN StartBit,\r | |
306 | IN UINTN EndBit,\r | |
307 | IN UINT8 OrData\r | |
ed66e1bc | 308 | );\r |
fb3df220 | 309 | \r |
310 | /**\r | |
d5979dc0 | 311 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r |
312 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
313 | \r | |
314 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
315 | bitwise AND between the read result and the value specified by AndData, and\r | |
316 | writes the result to the 8-bit PCI configuration register specified by\r | |
317 | Address. The value written to the PCI configuration register is returned.\r | |
318 | This function must guarantee that all PCI read and write operations are\r | |
319 | serialized. Extra left bits in AndData are stripped.\r | |
fb3df220 | 320 | \r |
fb3df220 | 321 | If any reserved bits in Address are set, then ASSERT().\r |
322 | If StartBit is greater than 7, then ASSERT().\r | |
323 | If EndBit is greater than 7, then ASSERT().\r | |
324 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 325 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fb3df220 | 326 | \r |
d5979dc0 | 327 | @param Address PCI configuration register to write.\r |
fb3df220 | 328 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
d5979dc0 | 329 | Range 0..7.\r |
fb3df220 | 330 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
d5979dc0 | 331 | Range 0..7.\r |
332 | @param AndData The value to AND with the PCI configuration register.\r | |
fb3df220 | 333 | \r |
d5979dc0 | 334 | @return The value written back to the PCI configuration register.\r |
fb3df220 | 335 | \r |
336 | **/\r | |
337 | UINT8\r | |
338 | EFIAPI\r | |
339 | PciSegmentBitFieldAnd8 (\r | |
340 | IN UINT64 Address,\r | |
341 | IN UINTN StartBit,\r | |
342 | IN UINTN EndBit,\r | |
343 | IN UINT8 AndData\r | |
ed66e1bc | 344 | );\r |
fb3df220 | 345 | \r |
346 | /**\r | |
d5979dc0 | 347 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r |
62991af2 | 348 | bitwise OR, and writes the result back to the bit field in the\r |
d5979dc0 | 349 | 8-bit port.\r |
350 | \r | |
351 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 352 | bitwise AND followed by a bitwise OR between the read result and\r |
d5979dc0 | 353 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
354 | configuration register specified by Address. The value written to the PCI\r | |
355 | configuration register is returned. This function must guarantee that all PCI\r | |
356 | read and write operations are serialized. Extra left bits in both AndData and\r | |
357 | OrData are stripped.\r | |
358 | \r | |
fb3df220 | 359 | If any reserved bits in Address are set, then ASSERT().\r |
360 | If StartBit is greater than 7, then ASSERT().\r | |
361 | If EndBit is greater than 7, then ASSERT().\r | |
362 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
363 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
364 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
fb3df220 | 365 | \r |
d5979dc0 | 366 | @param Address PCI configuration register to write.\r |
fb3df220 | 367 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
d5979dc0 | 368 | Range 0..7.\r |
fb3df220 | 369 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
d5979dc0 | 370 | Range 0..7.\r |
371 | @param AndData The value to AND with the PCI configuration register.\r | |
372 | @param OrData The value to OR with the result of the AND operation.\r | |
fb3df220 | 373 | \r |
d5979dc0 | 374 | @return The value written back to the PCI configuration register.\r |
fb3df220 | 375 | \r |
376 | **/\r | |
377 | UINT8\r | |
378 | EFIAPI\r | |
379 | PciSegmentBitFieldAndThenOr8 (\r | |
380 | IN UINT64 Address,\r | |
381 | IN UINTN StartBit,\r | |
382 | IN UINTN EndBit,\r | |
383 | IN UINT8 AndData,\r | |
384 | IN UINT8 OrData\r | |
ed66e1bc | 385 | );\r |
fb3df220 | 386 | \r |
387 | /**\r | |
388 | Reads a 16-bit PCI configuration register.\r | |
389 | \r | |
390 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
391 | This function must guarantee that all PCI read and write operations are serialized.\r | |
badcbfb2 | 392 | \r |
fb3df220 | 393 | If any reserved bits in Address are set, then ASSERT().\r |
badcbfb2 | 394 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
fb3df220 | 395 | \r |
396 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
397 | \r | |
398 | @return The 16-bit PCI configuration register specified by Address.\r | |
399 | \r | |
400 | **/\r | |
401 | UINT16\r | |
402 | EFIAPI\r | |
403 | PciSegmentRead16 (\r | |
404 | IN UINT64 Address\r | |
ed66e1bc | 405 | );\r |
fb3df220 | 406 | \r |
407 | /**\r | |
408 | Writes a 16-bit PCI configuration register.\r | |
409 | \r | |
410 | Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.\r | |
411 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
badcbfb2 | 412 | \r |
413 | If any reserved bits in Address are set, then ASSERT().\r | |
414 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
fb3df220 | 415 | \r |
416 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
417 | @param Value The value to write.\r | |
418 | \r | |
419 | @return The parameter of Value.\r | |
420 | \r | |
421 | **/\r | |
422 | UINT16\r | |
423 | EFIAPI\r | |
424 | PciSegmentWrite16 (\r | |
425 | IN UINT64 Address,\r | |
426 | IN UINT16 Value\r | |
ed66e1bc | 427 | );\r |
fb3df220 | 428 | \r |
429 | /**\r | |
62991af2 | 430 | Performs a bitwise OR of a 16-bit PCI configuration register with\r |
d5979dc0 | 431 | a 16-bit value.\r |
432 | \r | |
433 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 434 | bitwise OR between the read result and the value specified by\r |
d5979dc0 | 435 | OrData, and writes the result to the 16-bit PCI configuration register\r |
436 | specified by Address. The value written to the PCI configuration register is\r | |
437 | returned. This function must guarantee that all PCI read and write operations\r | |
438 | are serialized.\r | |
fb3df220 | 439 | \r |
fb3df220 | 440 | If any reserved bits in Address are set, then ASSERT().\r |
badcbfb2 | 441 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
fb3df220 | 442 | \r |
d5979dc0 | 443 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r |
444 | Register.\r | |
445 | @param OrData The value to OR with the PCI configuration register.\r | |
fb3df220 | 446 | \r |
d5979dc0 | 447 | @return The value written back to the PCI configuration register.\r |
fb3df220 | 448 | \r |
449 | **/\r | |
450 | UINT16\r | |
451 | EFIAPI\r | |
452 | PciSegmentOr16 (\r | |
453 | IN UINT64 Address,\r | |
454 | IN UINT16 OrData\r | |
ed66e1bc | 455 | );\r |
fb3df220 | 456 | \r |
457 | /**\r | |
458 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.\r | |
459 | \r | |
460 | Reads the 16-bit PCI configuration register specified by Address,\r | |
461 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
462 | and writes the result to the 16-bit PCI configuration register specified by Address.\r | |
463 | The value written to the PCI configuration register is returned.\r | |
464 | This function must guarantee that all PCI read and write operations are serialized.\r | |
badcbfb2 | 465 | \r |
fb3df220 | 466 | If any reserved bits in Address are set, then ASSERT().\r |
badcbfb2 | 467 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
468 | \r | |
fb3df220 | 469 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
7d9333a9 | 470 | @param AndData The value to AND with the PCI configuration register.\r |
fb3df220 | 471 | \r |
472 | @return The value written to the PCI configuration register.\r | |
473 | \r | |
474 | **/\r | |
475 | UINT16\r | |
476 | EFIAPI\r | |
477 | PciSegmentAnd16 (\r | |
478 | IN UINT64 Address,\r | |
479 | IN UINT16 AndData\r | |
ed66e1bc | 480 | );\r |
fb3df220 | 481 | \r |
482 | /**\r | |
483 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,\r | |
62991af2 | 484 | followed a bitwise OR with another 16-bit value.\r |
fb3df220 | 485 | \r |
486 | Reads the 16-bit PCI configuration register specified by Address,\r | |
487 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 488 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r |
fb3df220 | 489 | and writes the result to the 16-bit PCI configuration register specified by Address.\r |
490 | The value written to the PCI configuration register is returned.\r | |
491 | This function must guarantee that all PCI read and write operations are serialized.\r | |
badcbfb2 | 492 | \r |
fb3df220 | 493 | If any reserved bits in Address are set, then ASSERT().\r |
badcbfb2 | 494 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
fb3df220 | 495 | \r |
496 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
42eedea9 | 497 | @param AndData The value to AND with the PCI configuration register.\r |
fb3df220 | 498 | @param OrData The value to OR with the PCI configuration register.\r |
499 | \r | |
500 | @return The value written to the PCI configuration register.\r | |
501 | \r | |
502 | **/\r | |
503 | UINT16\r | |
504 | EFIAPI\r | |
505 | PciSegmentAndThenOr16 (\r | |
506 | IN UINT64 Address,\r | |
507 | IN UINT16 AndData,\r | |
508 | IN UINT16 OrData\r | |
ed66e1bc | 509 | );\r |
fb3df220 | 510 | \r |
511 | /**\r | |
512 | Reads a bit field of a PCI configuration register.\r | |
513 | \r | |
d5979dc0 | 514 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r |
515 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
516 | returned.\r | |
517 | \r | |
fb3df220 | 518 | If any reserved bits in Address are set, then ASSERT().\r |
badcbfb2 | 519 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
d5979dc0 | 520 | If StartBit is greater than 15, then ASSERT().\r |
521 | If EndBit is greater than 15, then ASSERT().\r | |
fb3df220 | 522 | If EndBit is less than StartBit, then ASSERT().\r |
523 | \r | |
d5979dc0 | 524 | @param Address PCI configuration register to read.\r |
fb3df220 | 525 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
d5979dc0 | 526 | Range 0..15.\r |
fb3df220 | 527 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
d5979dc0 | 528 | Range 0..15.\r |
fb3df220 | 529 | \r |
d5979dc0 | 530 | @return The value of the bit field read from the PCI configuration register.\r |
fb3df220 | 531 | \r |
532 | **/\r | |
533 | UINT16\r | |
534 | EFIAPI\r | |
535 | PciSegmentBitFieldRead16 (\r | |
536 | IN UINT64 Address,\r | |
537 | IN UINTN StartBit,\r | |
538 | IN UINTN EndBit\r | |
ed66e1bc | 539 | );\r |
fb3df220 | 540 | \r |
541 | /**\r | |
542 | Writes a bit field to a PCI configuration register.\r | |
543 | \r | |
d5979dc0 | 544 | Writes Value to the bit field of the PCI configuration register. The bit\r |
545 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
546 | destination PCI configuration register are preserved. The new value of the\r | |
547 | 16-bit register is returned.\r | |
548 | \r | |
fb3df220 | 549 | If any reserved bits in Address are set, then ASSERT().\r |
badcbfb2 | 550 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
d5979dc0 | 551 | If StartBit is greater than 15, then ASSERT().\r |
552 | If EndBit is greater than 15, then ASSERT().\r | |
fb3df220 | 553 | If EndBit is less than StartBit, then ASSERT().\r |
94952554 | 554 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fb3df220 | 555 | \r |
d5979dc0 | 556 | @param Address PCI configuration register to write.\r |
fb3df220 | 557 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
d5979dc0 | 558 | Range 0..15.\r |
fb3df220 | 559 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
d5979dc0 | 560 | Range 0..15.\r |
fb3df220 | 561 | @param Value New value of the bit field.\r |
562 | \r | |
d5979dc0 | 563 | @return The value written back to the PCI configuration register.\r |
fb3df220 | 564 | \r |
565 | **/\r | |
566 | UINT16\r | |
567 | EFIAPI\r | |
568 | PciSegmentBitFieldWrite16 (\r | |
569 | IN UINT64 Address,\r | |
570 | IN UINTN StartBit,\r | |
571 | IN UINTN EndBit,\r | |
572 | IN UINT16 Value\r | |
ed66e1bc | 573 | );\r |
fb3df220 | 574 | \r |
575 | /**\r | |
576 | Reads the 16-bit PCI configuration register specified by Address,\r | |
62991af2 | 577 | performs a bitwise OR between the read result and the value specified by OrData,\r |
fb3df220 | 578 | and writes the result to the 16-bit PCI configuration register specified by Address. \r |
579 | \r | |
badcbfb2 | 580 | If any reserved bits in Address are set, then ASSERT().\r |
581 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
582 | If StartBit is greater than 15, then ASSERT().\r | |
583 | If EndBit is greater than 15, then ASSERT().\r | |
584 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 585 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
badcbfb2 | 586 | \r |
d5979dc0 | 587 | @param Address PCI configuration register to write.\r |
fb3df220 | 588 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
d5979dc0 | 589 | Range 0..15.\r |
fb3df220 | 590 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
d5979dc0 | 591 | Range 0..15.\r |
592 | @param OrData The value to OR with the PCI configuration register.\r | |
fb3df220 | 593 | \r |
d5979dc0 | 594 | @return The value written back to the PCI configuration register.\r |
fb3df220 | 595 | \r |
596 | **/\r | |
597 | UINT16\r | |
598 | EFIAPI\r | |
599 | PciSegmentBitFieldOr16 (\r | |
600 | IN UINT64 Address,\r | |
601 | IN UINTN StartBit,\r | |
602 | IN UINTN EndBit,\r | |
603 | IN UINT16 OrData\r | |
ed66e1bc | 604 | );\r |
fb3df220 | 605 | \r |
606 | /**\r | |
607 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,\r | |
608 | and writes the result back to the bit field in the 16-bit port.\r | |
609 | \r | |
610 | Reads the 16-bit PCI configuration register specified by Address,\r | |
62991af2 | 611 | performs a bitwise OR between the read result and the value specified by OrData,\r |
fb3df220 | 612 | and writes the result to the 16-bit PCI configuration register specified by Address.\r |
613 | The value written to the PCI configuration register is returned.\r | |
614 | This function must guarantee that all PCI read and write operations are serialized.\r | |
615 | Extra left bits in OrData are stripped.\r | |
badcbfb2 | 616 | \r |
fb3df220 | 617 | If any reserved bits in Address are set, then ASSERT().\r |
badcbfb2 | 618 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
fb3df220 | 619 | If StartBit is greater than 7, then ASSERT().\r |
620 | If EndBit is greater than 7, then ASSERT().\r | |
621 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 622 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fb3df220 | 623 | \r |
624 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
625 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
626 | The ordinal of the least significant bit in a byte is bit 0.\r | |
627 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
628 | The ordinal of the most significant bit in a byte is bit 7.\r | |
629 | @param AndData The value to AND with the read value from the PCI configuration register.\r | |
630 | \r | |
631 | @return The value written to the PCI configuration register.\r | |
632 | \r | |
633 | **/\r | |
634 | UINT16\r | |
635 | EFIAPI\r | |
636 | PciSegmentBitFieldAnd16 (\r | |
637 | IN UINT64 Address,\r | |
638 | IN UINTN StartBit,\r | |
639 | IN UINTN EndBit,\r | |
640 | IN UINT16 AndData\r | |
ed66e1bc | 641 | );\r |
fb3df220 | 642 | \r |
643 | /**\r | |
d5979dc0 | 644 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r |
62991af2 | 645 | bitwise OR, and writes the result back to the bit field in the\r |
d5979dc0 | 646 | 16-bit port.\r |
647 | \r | |
648 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 649 | bitwise AND followed by a bitwise OR between the read result and\r |
d5979dc0 | 650 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
651 | configuration register specified by Address. The value written to the PCI\r | |
652 | configuration register is returned. This function must guarantee that all PCI\r | |
653 | read and write operations are serialized. Extra left bits in both AndData and\r | |
654 | OrData are stripped.\r | |
655 | \r | |
fb3df220 | 656 | If any reserved bits in Address are set, then ASSERT().\r |
d5979dc0 | 657 | If StartBit is greater than 15, then ASSERT().\r |
658 | If EndBit is greater than 15, then ASSERT().\r | |
fb3df220 | 659 | If EndBit is less than StartBit, then ASSERT().\r |
94952554 LG |
660 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
661 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
fb3df220 | 662 | \r |
d5979dc0 | 663 | @param Address PCI configuration register to write.\r |
fb3df220 | 664 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
d5979dc0 | 665 | Range 0..15.\r |
fb3df220 | 666 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
d5979dc0 | 667 | Range 0..15.\r |
668 | @param AndData The value to AND with the PCI configuration register.\r | |
669 | @param OrData The value to OR with the result of the AND operation.\r | |
fb3df220 | 670 | \r |
d5979dc0 | 671 | @return The value written back to the PCI configuration register.\r |
fb3df220 | 672 | \r |
673 | **/\r | |
674 | UINT16\r | |
675 | EFIAPI\r | |
676 | PciSegmentBitFieldAndThenOr16 (\r | |
677 | IN UINT64 Address,\r | |
678 | IN UINTN StartBit,\r | |
679 | IN UINTN EndBit,\r | |
680 | IN UINT16 AndData,\r | |
681 | IN UINT16 OrData\r | |
ed66e1bc | 682 | );\r |
fb3df220 | 683 | \r |
684 | /**\r | |
685 | Reads a 32-bit PCI configuration register.\r | |
686 | \r | |
687 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
688 | This function must guarantee that all PCI read and write operations are serialized.\r | |
fb3df220 | 689 | \r |
badcbfb2 | 690 | If any reserved bits in Address are set, then ASSERT().\r |
691 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
692 | \r | |
fb3df220 | 693 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
694 | \r | |
695 | @return The 32-bit PCI configuration register specified by Address.\r | |
696 | \r | |
697 | **/\r | |
698 | UINT32\r | |
699 | EFIAPI\r | |
700 | PciSegmentRead32 (\r | |
701 | IN UINT64 Address\r | |
ed66e1bc | 702 | );\r |
fb3df220 | 703 | \r |
704 | /**\r | |
705 | Writes a 32-bit PCI configuration register.\r | |
706 | \r | |
707 | Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.\r | |
708 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
badcbfb2 | 709 | \r |
710 | If any reserved bits in Address are set, then ASSERT().\r | |
711 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
fb3df220 | 712 | \r |
713 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
714 | @param Value The value to write.\r | |
715 | \r | |
716 | @return The parameter of Value.\r | |
717 | \r | |
718 | **/\r | |
719 | UINT32\r | |
720 | EFIAPI\r | |
721 | PciSegmentWrite32 (\r | |
722 | IN UINT64 Address,\r | |
723 | IN UINT32 Value\r | |
ed66e1bc | 724 | );\r |
fb3df220 | 725 | \r |
726 | /**\r | |
62991af2 | 727 | Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.\r |
fb3df220 | 728 | \r |
729 | Reads the 32-bit PCI configuration register specified by Address,\r | |
62991af2 | 730 | performs a bitwise OR between the read result and the value specified by OrData,\r |
fb3df220 | 731 | and writes the result to the 32-bit PCI configuration register specified by Address.\r |
732 | The value written to the PCI configuration register is returned.\r | |
733 | This function must guarantee that all PCI read and write operations are serialized.\r | |
badcbfb2 | 734 | \r |
fb3df220 | 735 | If any reserved bits in Address are set, then ASSERT().\r |
badcbfb2 | 736 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
fb3df220 | 737 | \r |
738 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
739 | @param OrData The value to OR with the PCI configuration register.\r | |
740 | \r | |
741 | @return The value written to the PCI configuration register.\r | |
742 | \r | |
743 | **/\r | |
744 | UINT32\r | |
745 | EFIAPI\r | |
746 | PciSegmentOr32 (\r | |
747 | IN UINT64 Address,\r | |
748 | IN UINT32 OrData\r | |
ed66e1bc | 749 | );\r |
fb3df220 | 750 | \r |
751 | /**\r | |
752 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.\r | |
753 | \r | |
754 | Reads the 32-bit PCI configuration register specified by Address,\r | |
755 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
756 | and writes the result to the 32-bit PCI configuration register specified by Address.\r | |
757 | The value written to the PCI configuration register is returned.\r | |
758 | This function must guarantee that all PCI read and write operations are serialized.\r | |
badcbfb2 | 759 | \r |
fb3df220 | 760 | If any reserved bits in Address are set, then ASSERT().\r |
badcbfb2 | 761 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
fb3df220 | 762 | \r |
763 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
7d9333a9 | 764 | @param AndData The value to AND with the PCI configuration register.\r |
fb3df220 | 765 | \r |
766 | @return The value written to the PCI configuration register.\r | |
767 | \r | |
768 | **/\r | |
769 | UINT32\r | |
770 | EFIAPI\r | |
771 | PciSegmentAnd32 (\r | |
772 | IN UINT64 Address,\r | |
773 | IN UINT32 AndData\r | |
ed66e1bc | 774 | );\r |
fb3df220 | 775 | \r |
776 | /**\r | |
777 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,\r | |
62991af2 | 778 | followed a bitwise OR with another 32-bit value.\r |
fb3df220 | 779 | \r |
780 | Reads the 32-bit PCI configuration register specified by Address,\r | |
781 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 782 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r |
fb3df220 | 783 | and writes the result to the 32-bit PCI configuration register specified by Address.\r |
784 | The value written to the PCI configuration register is returned.\r | |
785 | This function must guarantee that all PCI read and write operations are serialized.\r | |
badcbfb2 | 786 | \r |
fb3df220 | 787 | If any reserved bits in Address are set, then ASSERT().\r |
badcbfb2 | 788 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
fb3df220 | 789 | \r |
790 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
7d9333a9 | 791 | @param AndData The value to AND with the PCI configuration register.\r |
fb3df220 | 792 | @param OrData The value to OR with the PCI configuration register.\r |
793 | \r | |
794 | @return The value written to the PCI configuration register.\r | |
795 | \r | |
796 | **/\r | |
797 | UINT32\r | |
798 | EFIAPI\r | |
799 | PciSegmentAndThenOr32 (\r | |
800 | IN UINT64 Address,\r | |
801 | IN UINT32 AndData,\r | |
802 | IN UINT32 OrData\r | |
ed66e1bc | 803 | );\r |
fb3df220 | 804 | \r |
805 | /**\r | |
806 | Reads a bit field of a PCI configuration register.\r | |
807 | \r | |
d5979dc0 | 808 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r |
809 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
810 | returned.\r | |
811 | \r | |
fb3df220 | 812 | If any reserved bits in Address are set, then ASSERT().\r |
badcbfb2 | 813 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
d5979dc0 | 814 | If StartBit is greater than 31, then ASSERT().\r |
815 | If EndBit is greater than 31, then ASSERT().\r | |
fb3df220 | 816 | If EndBit is less than StartBit, then ASSERT().\r |
817 | \r | |
d5979dc0 | 818 | @param Address PCI configuration register to read.\r |
fb3df220 | 819 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
d5979dc0 | 820 | Range 0..31.\r |
fb3df220 | 821 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
d5979dc0 | 822 | Range 0..31.\r |
fb3df220 | 823 | \r |
d5979dc0 | 824 | @return The value of the bit field read from the PCI configuration register.\r |
fb3df220 | 825 | \r |
826 | **/\r | |
827 | UINT32\r | |
828 | EFIAPI\r | |
829 | PciSegmentBitFieldRead32 (\r | |
830 | IN UINT64 Address,\r | |
831 | IN UINTN StartBit,\r | |
832 | IN UINTN EndBit\r | |
ed66e1bc | 833 | );\r |
fb3df220 | 834 | \r |
835 | /**\r | |
836 | Writes a bit field to a PCI configuration register.\r | |
837 | \r | |
d5979dc0 | 838 | Writes Value to the bit field of the PCI configuration register. The bit\r |
839 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
840 | destination PCI configuration register are preserved. The new value of the\r | |
841 | 32-bit register is returned.\r | |
842 | \r | |
fb3df220 | 843 | If any reserved bits in Address are set, then ASSERT().\r |
badcbfb2 | 844 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
d5979dc0 | 845 | If StartBit is greater than 31, then ASSERT().\r |
846 | If EndBit is greater than 31, then ASSERT().\r | |
fb3df220 | 847 | If EndBit is less than StartBit, then ASSERT().\r |
94952554 | 848 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fb3df220 | 849 | \r |
d5979dc0 | 850 | @param Address PCI configuration register to write.\r |
fb3df220 | 851 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
d5979dc0 | 852 | Range 0..31.\r |
fb3df220 | 853 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
d5979dc0 | 854 | Range 0..31.\r |
fb3df220 | 855 | @param Value New value of the bit field.\r |
856 | \r | |
d5979dc0 | 857 | @return The value written back to the PCI configuration register.\r |
fb3df220 | 858 | \r |
859 | **/\r | |
860 | UINT32\r | |
861 | EFIAPI\r | |
862 | PciSegmentBitFieldWrite32 (\r | |
863 | IN UINT64 Address,\r | |
864 | IN UINTN StartBit,\r | |
865 | IN UINTN EndBit,\r | |
866 | IN UINT32 Value\r | |
ed66e1bc | 867 | );\r |
fb3df220 | 868 | \r |
869 | /**\r | |
d5979dc0 | 870 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r |
871 | writes the result back to the bit field in the 32-bit port.\r | |
872 | \r | |
873 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 874 | bitwise OR between the read result and the value specified by\r |
d5979dc0 | 875 | OrData, and writes the result to the 32-bit PCI configuration register\r |
876 | specified by Address. The value written to the PCI configuration register is\r | |
877 | returned. This function must guarantee that all PCI read and write operations\r | |
878 | are serialized. Extra left bits in OrData are stripped.\r | |
879 | \r | |
badcbfb2 | 880 | If any reserved bits in Address are set, then ASSERT().\r |
d5979dc0 | 881 | If StartBit is greater than 31, then ASSERT().\r |
882 | If EndBit is greater than 31, then ASSERT().\r | |
badcbfb2 | 883 | If EndBit is less than StartBit, then ASSERT().\r |
94952554 | 884 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
d5979dc0 | 885 | \r |
886 | @param Address PCI configuration register to write.\r | |
fb3df220 | 887 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
d5979dc0 | 888 | Range 0..31.\r |
fb3df220 | 889 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
d5979dc0 | 890 | Range 0..31.\r |
891 | @param OrData The value to OR with the PCI configuration register.\r | |
fb3df220 | 892 | \r |
d5979dc0 | 893 | @return The value written back to the PCI configuration register.\r |
fb3df220 | 894 | \r |
895 | **/\r | |
896 | UINT32\r | |
897 | EFIAPI\r | |
898 | PciSegmentBitFieldOr32 (\r | |
899 | IN UINT64 Address,\r | |
900 | IN UINTN StartBit,\r | |
901 | IN UINTN EndBit,\r | |
902 | IN UINT32 OrData\r | |
ed66e1bc | 903 | );\r |
fb3df220 | 904 | \r |
905 | /**\r | |
d5979dc0 | 906 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r |
907 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
fb3df220 | 908 | \r |
badcbfb2 | 909 | \r |
d5979dc0 | 910 | Reads the 32-bit PCI configuration register specified by Address, performs a bitwise\r |
911 | AND between the read result and the value specified by AndData, and writes the result\r | |
912 | to the 32-bit PCI configuration register specified by Address. The value written to\r | |
913 | the PCI configuration register is returned. This function must guarantee that all PCI\r | |
914 | read and write operations are serialized. Extra left bits in AndData are stripped.\r | |
fb3df220 | 915 | If any reserved bits in Address are set, then ASSERT().\r |
badcbfb2 | 916 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
d5979dc0 | 917 | If StartBit is greater than 31, then ASSERT().\r |
918 | If EndBit is greater than 31, then ASSERT().\r | |
fb3df220 | 919 | If EndBit is less than StartBit, then ASSERT().\r |
94952554 | 920 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fb3df220 | 921 | \r |
d5979dc0 | 922 | @param Address PCI configuration register to write.\r |
fb3df220 | 923 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
d5979dc0 | 924 | Range 0..31.\r |
fb3df220 | 925 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
d5979dc0 | 926 | Range 0..31.\r |
927 | @param AndData The value to AND with the PCI configuration register.\r | |
fb3df220 | 928 | \r |
d5979dc0 | 929 | @return The value written back to the PCI configuration register.\r |
fb3df220 | 930 | \r |
931 | **/\r | |
932 | UINT32\r | |
933 | EFIAPI\r | |
934 | PciSegmentBitFieldAnd32 (\r | |
935 | IN UINT64 Address,\r | |
936 | IN UINTN StartBit,\r | |
937 | IN UINTN EndBit,\r | |
938 | IN UINT32 AndData\r | |
ed66e1bc | 939 | );\r |
fb3df220 | 940 | \r |
941 | /**\r | |
d5979dc0 | 942 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r |
62991af2 | 943 | bitwise OR, and writes the result back to the bit field in the\r |
d5979dc0 | 944 | 32-bit port.\r |
945 | \r | |
946 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 947 | bitwise AND followed by a bitwise OR between the read result and\r |
d5979dc0 | 948 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
949 | configuration register specified by Address. The value written to the PCI\r | |
950 | configuration register is returned. This function must guarantee that all PCI\r | |
951 | read and write operations are serialized. Extra left bits in both AndData and\r | |
952 | OrData are stripped.\r | |
953 | \r | |
fb3df220 | 954 | If any reserved bits in Address are set, then ASSERT().\r |
d5979dc0 | 955 | If StartBit is greater than 31, then ASSERT().\r |
956 | If EndBit is greater than 31, then ASSERT().\r | |
fb3df220 | 957 | If EndBit is less than StartBit, then ASSERT().\r |
94952554 LG |
958 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
959 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
fb3df220 | 960 | \r |
d5979dc0 | 961 | @param Address PCI configuration register to write.\r |
fb3df220 | 962 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
d5979dc0 | 963 | Range 0..31.\r |
fb3df220 | 964 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
d5979dc0 | 965 | Range 0..31.\r |
966 | @param AndData The value to AND with the PCI configuration register.\r | |
967 | @param OrData The value to OR with the result of the AND operation.\r | |
fb3df220 | 968 | \r |
d5979dc0 | 969 | @return The value written back to the PCI configuration register.\r |
fb3df220 | 970 | \r |
971 | **/\r | |
972 | UINT32\r | |
973 | EFIAPI\r | |
974 | PciSegmentBitFieldAndThenOr32 (\r | |
975 | IN UINT64 Address,\r | |
976 | IN UINTN StartBit,\r | |
977 | IN UINTN EndBit,\r | |
978 | IN UINT32 AndData,\r | |
979 | IN UINT32 OrData\r | |
ed66e1bc | 980 | );\r |
fb3df220 | 981 | \r |
982 | /**\r | |
983 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
984 | \r | |
d5979dc0 | 985 | Reads the range of PCI configuration registers specified by StartAddress and\r |
986 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
987 | configuration registers from a single PCI function to be read. Size is\r | |
988 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
989 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
990 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
991 | end of the range.\r | |
992 | \r | |
59ceeabe | 993 | If any reserved bits in StartAddress are set, then ASSERT().\r |
fb3df220 | 994 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
badcbfb2 | 995 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
fb3df220 | 996 | \r |
d5979dc0 | 997 | @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r |
998 | Function and Register.\r | |
fb3df220 | 999 | @param Size Size in bytes of the transfer.\r |
1000 | @param Buffer Pointer to a buffer receiving the data read.\r | |
1001 | \r | |
d5979dc0 | 1002 | @return Size\r |
fb3df220 | 1003 | \r |
1004 | **/\r | |
1005 | UINTN\r | |
1006 | EFIAPI\r | |
1007 | PciSegmentReadBuffer (\r | |
1008 | IN UINT64 StartAddress,\r | |
1009 | IN UINTN Size,\r | |
1010 | OUT VOID *Buffer\r | |
ed66e1bc | 1011 | );\r |
fb3df220 | 1012 | \r |
1013 | /**\r | |
d5979dc0 | 1014 | Copies the data in a caller supplied buffer to a specified range of PCI\r |
1015 | configuration space.\r | |
1016 | \r | |
1017 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1018 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1019 | configuration registers from a single PCI function to be written. Size is\r | |
1020 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1021 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1022 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1023 | and the end of the range.\r | |
1024 | \r | |
59ceeabe | 1025 | If any reserved bits in StartAddress are set, then ASSERT().\r |
fb3df220 | 1026 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
d5979dc0 | 1027 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
fb3df220 | 1028 | \r |
d5979dc0 | 1029 | @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r |
1030 | Function and Register.\r | |
fb3df220 | 1031 | @param Size Size in bytes of the transfer.\r |
1032 | @param Buffer Pointer to a buffer containing the data to write.\r | |
1033 | \r | |
badcbfb2 | 1034 | @return The parameter of Size.\r |
fb3df220 | 1035 | \r |
1036 | **/\r | |
1037 | UINTN\r | |
1038 | EFIAPI\r | |
1039 | PciSegmentWriteBuffer (\r | |
1040 | IN UINT64 StartAddress,\r | |
1041 | IN UINTN Size,\r | |
1042 | IN VOID *Buffer\r | |
ed66e1bc | 1043 | );\r |
fb3df220 | 1044 | \r |
1045 | #endif\r |