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fe69ac84 | 1 | /** @file\r |
2 | The PCI configuration Library Services that carry out PCI configuration and enable\r | |
3 | the PCI operations to be replayed during an S3 resume. This library class\r | |
4 | maps directly on top of the PciLib class. \r | |
5 | \r | |
94952554 | 6 | Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r |
fe69ac84 | 7 | \r |
8 | This program and the accompanying materials\r | |
9 | are licensed and made available under the terms and conditions\r | |
10 | of the BSD License which accompanies this distribution. The\r | |
11 | full text of the license may be found at\r | |
12 | http://opensource.org/licenses/bsd-license.php\r | |
13 | \r | |
14 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
15 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
16 | \r | |
17 | **/\r | |
18 | \r | |
19 | #ifndef __S3_PCI_LIB_H__\r | |
20 | #define __S3_PCI_LIB_H__\r | |
21 | \r | |
22 | /**\r | |
23 | Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an\r | |
24 | address that can be passed to the S3 PCI Library functions.\r | |
25 | \r | |
26 | @param Bus The PCI Bus number. Range 0..255.\r | |
27 | @param Device The PCI Device number. Range 0..31.\r | |
28 | @param Function The PCI Function number. Range 0..7.\r | |
29 | @param Register The PCI Register number. Range 0..255 for PCI. Range 0..4095\r | |
30 | for PCI Express.\r | |
31 | \r | |
32 | @return The encoded PCI address.\r | |
33 | \r | |
34 | **/\r | |
35 | #define S3_PCI_LIB_ADDRESS(Bus,Device,Function,Register) \\r | |
36 | (((Register) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))\r | |
37 | \r | |
38 | /**\r | |
39 | \r | |
40 | Reads and returns the 8-bit PCI configuration register specified by Address, \r | |
41 | and saves the value in the S3 script to be replayed on S3 resume.\r | |
42 | This function must guarantee that all PCI read and write operations are\r | |
43 | serialized.\r | |
44 | \r | |
45 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
46 | \r | |
47 | @param[in] Address The address that encodes the PCI Bus, Device, Function and\r | |
48 | Register.\r | |
49 | \r | |
50 | @return The value read from the PCI configuration register.\r | |
51 | \r | |
52 | **/\r | |
53 | UINT8\r | |
54 | EFIAPI\r | |
55 | S3PciRead8 (\r | |
56 | IN UINTN Address\r | |
57 | );\r | |
58 | \r | |
59 | /**\r | |
60 | Writes an 8-bit PCI configuration register, and saves the value in the S3\r | |
61 | script to be replayed on S3 resume.\r | |
62 | \r | |
63 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
64 | value specified by Value. Value is returned. This function must guarantee\r | |
65 | that all PCI read and write operations are serialized.\r | |
66 | \r | |
67 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
68 | \r | |
69 | @param[in] Address The address that encodes the PCI Bus, Device, Function and\r | |
70 | Register.\r | |
71 | @param[in] Value The value to write.\r | |
72 | \r | |
73 | @return The value written to the PCI configuration register.\r | |
74 | \r | |
75 | **/\r | |
76 | UINT8\r | |
77 | EFIAPI\r | |
78 | S3PciWrite8 (\r | |
79 | IN UINTN Address,\r | |
80 | IN UINT8 Value\r | |
81 | );\r | |
82 | \r | |
83 | /**\r | |
84 | Performs a bitwise OR of an 8-bit PCI configuration register with\r | |
85 | an 8-bit value, and saves the value in the S3 script to be replayed on S3 resume.\r | |
86 | \r | |
87 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
88 | bitwise OR between the read result and the value specified by\r | |
89 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
90 | specified by Address. The value written to the PCI configuration register is\r | |
91 | returned. This function must guarantee that all PCI read and write operations\r | |
92 | are serialized.\r | |
93 | \r | |
94 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
95 | \r | |
96 | @param[in] Address The address that encodes the PCI Bus, Device, Function and\r | |
97 | Register.\r | |
98 | @param[in] OrData The value to OR with the PCI configuration register.\r | |
99 | \r | |
100 | @return The value written back to the PCI configuration register.\r | |
101 | \r | |
102 | **/\r | |
103 | UINT8\r | |
104 | EFIAPI\r | |
105 | S3PciOr8 (\r | |
106 | IN UINTN Address,\r | |
107 | IN UINT8 OrData\r | |
108 | );\r | |
109 | \r | |
110 | /**\r | |
111 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
112 | value, and saves the value in the S3 script to be replayed on S3 resume.\r | |
113 | \r | |
114 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
115 | bitwise AND between the read result and the value specified by AndData, and\r | |
116 | writes the result to the 8-bit PCI configuration register specified by\r | |
117 | Address. The value written to the PCI configuration register is returned.\r | |
118 | This function must guarantee that all PCI read and write operations are\r | |
119 | serialized.\r | |
120 | \r | |
121 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
122 | \r | |
123 | @param[in] Address The address that encodes the PCI Bus, Device, Function and\r | |
124 | Register.\r | |
125 | @param[in] AndData The value to AND with the PCI configuration register.\r | |
126 | \r | |
127 | @return The value written back to the PCI configuration register.\r | |
128 | \r | |
129 | **/\r | |
130 | UINT8\r | |
131 | EFIAPI\r | |
132 | S3PciAnd8 (\r | |
133 | IN UINTN Address,\r | |
134 | IN UINT8 AndData\r | |
135 | );\r | |
136 | \r | |
137 | /**\r | |
138 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
139 | value, followed a bitwise OR with another 8-bit value, and saves\r | |
140 | the value in the S3 script to be replayed on S3 resume.\r | |
141 | \r | |
142 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
143 | bitwise AND between the read result and the value specified by AndData,\r | |
144 | performs a bitwise OR between the result of the AND operation and\r | |
145 | the value specified by OrData, and writes the result to the 8-bit PCI\r | |
146 | configuration register specified by Address. The value written to the PCI\r | |
147 | configuration register is returned. This function must guarantee that all PCI\r | |
148 | read and write operations are serialized.\r | |
149 | \r | |
150 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
151 | \r | |
152 | @param[in] Address The address that encodes the PCI Bus, Device, Function and\r | |
153 | Register.\r | |
154 | @param[in] AndData The value to AND with the PCI configuration register.\r | |
155 | @param[in] OrData The value to OR with the result of the AND operation.\r | |
156 | \r | |
157 | @return The value written back to the PCI configuration register.\r | |
158 | \r | |
159 | **/\r | |
160 | UINT8\r | |
161 | EFIAPI\r | |
162 | S3PciAndThenOr8 (\r | |
163 | IN UINTN Address,\r | |
164 | IN UINT8 AndData,\r | |
165 | IN UINT8 OrData\r | |
166 | );\r | |
167 | \r | |
168 | /**\r | |
169 | Reads a bit field of a PCI configuration register, and saves the value in\r | |
170 | the S3 script to be replayed on S3 resume.\r | |
171 | \r | |
172 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
173 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
174 | returned.\r | |
175 | \r | |
176 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
177 | If StartBit is greater than 7, then ASSERT().\r | |
178 | If EndBit is greater than 7, then ASSERT().\r | |
179 | If EndBit is less than StartBit, then ASSERT().\r | |
180 | \r | |
181 | @param[in] Address The PCI configuration register to read.\r | |
182 | @param[in] StartBit The ordinal of the least significant bit in the bit field.\r | |
183 | Range 0..7.\r | |
184 | @param[in] EndBit The ordinal of the most significant bit in the bit field.\r | |
185 | Range 0..7.\r | |
186 | \r | |
187 | @return The value of the bit field read from the PCI configuration register.\r | |
188 | \r | |
189 | **/\r | |
190 | UINT8\r | |
191 | EFIAPI\r | |
192 | S3PciBitFieldRead8 (\r | |
193 | IN UINTN Address,\r | |
194 | IN UINTN StartBit,\r | |
195 | IN UINTN EndBit\r | |
196 | );\r | |
197 | \r | |
198 | /**\r | |
199 | Writes a bit field to a PCI configuration register, and saves the value in\r | |
200 | the S3 script to be replayed on S3 resume.\r | |
201 | \r | |
202 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
203 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
204 | destination PCI configuration register are preserved. The new value of the\r | |
205 | 8-bit register is returned.\r | |
206 | \r | |
207 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
208 | If StartBit is greater than 7, then ASSERT().\r | |
209 | If EndBit is greater than 7, then ASSERT().\r | |
210 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 211 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fe69ac84 | 212 | \r |
213 | @param[in] Address The PCI configuration register to write.\r | |
214 | @param[in] StartBit The ordinal of the least significant bit in the bit field.\r | |
215 | Range 0..7.\r | |
216 | @param[in] EndBit The ordinal of the most significant bit in the bit field.\r | |
217 | Range 0..7.\r | |
218 | @param[in] Value New value of the bit field.\r | |
219 | \r | |
220 | @return The value written back to the PCI configuration register.\r | |
221 | \r | |
222 | **/\r | |
223 | UINT8\r | |
224 | EFIAPI\r | |
225 | S3PciBitFieldWrite8 (\r | |
226 | IN UINTN Address,\r | |
227 | IN UINTN StartBit,\r | |
228 | IN UINTN EndBit,\r | |
229 | IN UINT8 Value\r | |
230 | );\r | |
231 | \r | |
232 | /**\r | |
233 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
234 | writes the result back to the bit field in the 8-bit port, and saves the value\r | |
235 | in the S3 script to be replayed on S3 resume.\r | |
236 | \r | |
237 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
238 | bitwise OR between the read result and the value specified by\r | |
239 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
240 | specified by Address. The value written to the PCI configuration register is\r | |
241 | returned. This function must guarantee that all PCI read and write operations\r | |
242 | are serialized. Extra left bits in OrData are stripped.\r | |
243 | \r | |
244 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
245 | If StartBit is greater than 7, then ASSERT().\r | |
246 | If EndBit is greater than 7, then ASSERT().\r | |
247 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 248 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fe69ac84 | 249 | \r |
250 | @param[in] Address The PCI configuration register to write.\r | |
251 | @param[in] StartBit The ordinal of the least significant bit in the bit field.\r | |
252 | Range 0..7.\r | |
253 | @param[in] EndBit The ordinal of the most significant bit in the bit field.\r | |
254 | Range 0..7.\r | |
255 | @param[in] OrData The value to OR with the PCI configuration register.\r | |
256 | \r | |
257 | @return The value written back to the PCI configuration register.\r | |
258 | \r | |
259 | **/\r | |
260 | UINT8\r | |
261 | EFIAPI\r | |
262 | S3PciBitFieldOr8 (\r | |
263 | IN UINTN Address,\r | |
264 | IN UINTN StartBit,\r | |
265 | IN UINTN EndBit,\r | |
266 | IN UINT8 OrData\r | |
267 | );\r | |
268 | \r | |
269 | /**\r | |
270 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
271 | AND, and writes the result back to the bit field in the 8-bit register and\r | |
272 | saves the value in the S3 script to be replayed on S3 resume.\r | |
273 | \r | |
274 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
275 | bitwise AND between the read result and the value specified by AndData, and\r | |
276 | writes the result to the 8-bit PCI configuration register specified by\r | |
277 | Address. The value written to the PCI configuration register is returned.\r | |
278 | This function must guarantee that all PCI read and write operations are\r | |
279 | serialized. Extra left bits in AndData are stripped.\r | |
280 | \r | |
281 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
282 | If StartBit is greater than 7, then ASSERT().\r | |
283 | If EndBit is greater than 7, then ASSERT().\r | |
284 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 285 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fe69ac84 | 286 | \r |
287 | @param[in] Address The PCI configuration register to write.\r | |
288 | @param[in] StartBit The ordinal of the least significant bit in the bit field.\r | |
289 | Range 0..7.\r | |
290 | @param[in] EndBit The ordinal of the most significant bit in the bit field.\r | |
291 | Range 0..7.\r | |
292 | @param[in] AndData The value to AND with the PCI configuration register.\r | |
293 | \r | |
294 | @return The value written back to the PCI configuration register.\r | |
295 | \r | |
296 | **/\r | |
297 | UINT8\r | |
298 | EFIAPI\r | |
299 | S3PciBitFieldAnd8 (\r | |
300 | IN UINTN Address,\r | |
301 | IN UINTN StartBit,\r | |
302 | IN UINTN EndBit,\r | |
303 | IN UINT8 AndData\r | |
304 | );\r | |
305 | \r | |
306 | /**\r | |
307 | Reads a bit field in an 8-bit Address, performs a bitwise AND followed by a\r | |
308 | bitwise OR, and writes the result back to the bit field in the\r | |
309 | 8-bit port, and saves the value in the S3 script to be replayed on S3 resume.\r | |
310 | \r | |
311 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
312 | bitwise AND followed by a bitwise OR between the read result and\r | |
313 | the value specified by AndData, and writes the result to the 8-bit PCI\r | |
314 | configuration register specified by Address. The value written to the PCI\r | |
315 | configuration register is returned. This function must guarantee that all PCI\r | |
316 | read and write operations are serialized. Extra left bits in both AndData and\r | |
317 | OrData are stripped.\r | |
318 | \r | |
319 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
320 | If StartBit is greater than 7, then ASSERT().\r | |
321 | If EndBit is greater than 7, then ASSERT().\r | |
322 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
323 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
324 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
fe69ac84 | 325 | \r |
326 | @param[in] Address The PCI configuration register to write.\r | |
327 | @param[in] StartBit The ordinal of the least significant bit in the bit field.\r | |
328 | Range 0..7.\r | |
329 | @param[in] EndBit The ordinal of the most significant bit in the bit field.\r | |
330 | Range 0..7.\r | |
331 | @param[in] AndData The value to AND with the PCI configuration register.\r | |
332 | @param[in] OrData The value to OR with the result of the AND operation.\r | |
333 | \r | |
334 | @return The value written back to the PCI configuration register.\r | |
335 | \r | |
336 | **/\r | |
337 | UINT8\r | |
338 | EFIAPI\r | |
339 | S3PciBitFieldAndThenOr8 (\r | |
340 | IN UINTN Address,\r | |
341 | IN UINTN StartBit,\r | |
342 | IN UINTN EndBit,\r | |
343 | IN UINT8 AndData,\r | |
344 | IN UINT8 OrData\r | |
345 | );\r | |
346 | \r | |
347 | /**\r | |
348 | Reads a 16-bit PCI configuration register, and saves the value in the S3\r | |
349 | script to be replayed on S3 resume.\r | |
350 | \r | |
351 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
352 | This function must guarantee that all PCI read and write operations are\r | |
353 | serialized.\r | |
354 | \r | |
355 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
356 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
357 | \r | |
358 | @param[in] Address The address that encodes the PCI Bus, Device, Function and\r | |
359 | Register.\r | |
360 | \r | |
361 | @return The read value from the PCI configuration register.\r | |
362 | \r | |
363 | **/\r | |
364 | UINT16\r | |
365 | EFIAPI\r | |
366 | S3PciRead16 (\r | |
367 | IN UINTN Address\r | |
368 | );\r | |
369 | \r | |
370 | /**\r | |
371 | Writes a 16-bit PCI configuration register, and saves the value in the S3\r | |
372 | script to be replayed on S3 resume.\r | |
373 | \r | |
374 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
375 | value specified by Value. Value is returned. This function must guarantee\r | |
376 | that all PCI read and write operations are serialized.\r | |
377 | \r | |
378 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
379 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
380 | \r | |
381 | @param[in] Address The address that encodes the PCI Bus, Device, Function and\r | |
382 | Register.\r | |
383 | @param[in] Value The value to write.\r | |
384 | \r | |
385 | @return The value written to the PCI configuration register.\r | |
386 | \r | |
387 | **/\r | |
388 | UINT16\r | |
389 | EFIAPI\r | |
390 | S3PciWrite16 (\r | |
391 | IN UINTN Address,\r | |
392 | IN UINT16 Value\r | |
393 | );\r | |
394 | \r | |
395 | /**\r | |
396 | Performs a bitwise OR of a 16-bit PCI configuration register with\r | |
397 | a 16-bit value, and saves the value in the S3 script to be replayed on S3 resume.\r | |
398 | \r | |
399 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
400 | bitwise OR between the read result and the value specified by\r | |
401 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
402 | specified by Address. The value written to the PCI configuration register is\r | |
403 | returned. This function must guarantee that all PCI read and write operations\r | |
404 | are serialized.\r | |
405 | \r | |
406 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
407 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
408 | \r | |
409 | @param[in] Address The address that encodes the PCI Bus, Device, Function and\r | |
410 | Register.\r | |
411 | @param[in] OrData The value to OR with the PCI configuration register.\r | |
412 | \r | |
413 | @return The value written back to the PCI configuration register.\r | |
414 | \r | |
415 | **/\r | |
416 | UINT16\r | |
417 | EFIAPI\r | |
418 | S3PciOr16 (\r | |
419 | IN UINTN Address,\r | |
420 | IN UINT16 OrData\r | |
421 | );\r | |
422 | \r | |
423 | /**\r | |
424 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
425 | value, and saves the value in the S3 script to be replayed on S3 resume.\r | |
426 | \r | |
427 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
428 | bitwise AND between the read result and the value specified by AndData, and\r | |
429 | writes the result to the 16-bit PCI configuration register specified by\r | |
430 | Address. The value written to the PCI configuration register is returned.\r | |
431 | This function must guarantee that all PCI read and write operations are\r | |
432 | serialized.\r | |
433 | \r | |
434 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
435 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
436 | \r | |
437 | @param[in] Address The address that encodes the PCI Bus, Device, Function and\r | |
438 | Register.\r | |
439 | @param[in] AndData The value to AND with the PCI configuration register.\r | |
440 | \r | |
441 | @return The value written back to the PCI configuration register.\r | |
442 | \r | |
443 | **/\r | |
444 | UINT16\r | |
445 | EFIAPI\r | |
446 | S3PciAnd16 (\r | |
447 | IN UINTN Address,\r | |
448 | IN UINT16 AndData\r | |
449 | );\r | |
450 | \r | |
451 | /**\r | |
452 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
453 | value, followed a bitwise OR with another 16-bit value, and saves\r | |
454 | the value in the S3 script to be replayed on S3 resume.\r | |
455 | \r | |
456 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
457 | bitwise AND between the read result and the value specified by AndData,\r | |
458 | performs a bitwise OR between the result of the AND operation and\r | |
459 | the value specified by OrData, and writes the result to the 16-bit PCI\r | |
460 | configuration register specified by Address. The value written to the PCI\r | |
461 | configuration register is returned. This function must guarantee that all PCI\r | |
462 | read and write operations are serialized.\r | |
463 | \r | |
464 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
465 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
466 | \r | |
467 | @param[in] Address The address that encodes the PCI Bus, Device, Function and\r | |
468 | Register.\r | |
469 | @param[in] AndData The value to AND with the PCI configuration register.\r | |
470 | @param[in] OrData The value to OR with the result of the AND operation.\r | |
471 | \r | |
472 | @return The value written back to the PCI configuration register.\r | |
473 | \r | |
474 | **/\r | |
475 | UINT16\r | |
476 | EFIAPI\r | |
477 | S3PciAndThenOr16 (\r | |
478 | IN UINTN Address,\r | |
479 | IN UINT16 AndData,\r | |
480 | IN UINT16 OrData\r | |
481 | );\r | |
482 | \r | |
483 | /**\r | |
484 | Reads a bit field of a PCI configuration register, and saves the value in\r | |
485 | the S3 script to be replayed on S3 resume.\r | |
486 | \r | |
487 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
488 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
489 | returned.\r | |
490 | \r | |
491 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
492 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
493 | If StartBit is greater than 15, then ASSERT().\r | |
494 | If EndBit is greater than 15, then ASSERT().\r | |
495 | If EndBit is less than StartBit, then ASSERT().\r | |
496 | \r | |
497 | @param[in] Address The PCI configuration register to read.\r | |
498 | @param[in] StartBit The ordinal of the least significant bit in the bit field.\r | |
499 | Range 0..15.\r | |
500 | @param[in] EndBit The ordinal of the most significant bit in the bit field.\r | |
501 | Range 0..15.\r | |
502 | \r | |
503 | @return The value of the bit field read from the PCI configuration register.\r | |
504 | \r | |
505 | **/\r | |
506 | UINT16\r | |
507 | EFIAPI\r | |
508 | S3PciBitFieldRead16 (\r | |
509 | IN UINTN Address,\r | |
510 | IN UINTN StartBit,\r | |
511 | IN UINTN EndBit\r | |
512 | );\r | |
513 | \r | |
514 | /**\r | |
515 | Writes a bit field to a PCI configuration register, and saves the value in\r | |
516 | the S3 script to be replayed on S3 resume.\r | |
517 | \r | |
518 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
519 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
520 | destination PCI configuration register are preserved. The new value of the\r | |
521 | 16-bit register is returned.\r | |
522 | \r | |
523 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
524 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
525 | If StartBit is greater than 15, then ASSERT().\r | |
526 | If EndBit is greater than 15, then ASSERT().\r | |
527 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 528 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fe69ac84 | 529 | \r |
530 | @param[in] Address The PCI configuration register to write.\r | |
531 | @param[in] StartBit The ordinal of the least significant bit in the bit field.\r | |
532 | Range 0..15.\r | |
533 | @param[in] EndBit The ordinal of the most significant bit in the bit field.\r | |
534 | Range 0..15.\r | |
535 | @param[in] Value New value of the bit field.\r | |
536 | \r | |
537 | @return The value written back to the PCI configuration register.\r | |
538 | \r | |
539 | **/\r | |
540 | UINT16\r | |
541 | EFIAPI\r | |
542 | S3PciBitFieldWrite16 (\r | |
543 | IN UINTN Address,\r | |
544 | IN UINTN StartBit,\r | |
545 | IN UINTN EndBit,\r | |
546 | IN UINT16 Value\r | |
547 | );\r | |
548 | \r | |
549 | /**\r | |
550 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
551 | writes the result back to the bit field in the 16-bit port, and saves the value\r | |
552 | in the S3 script to be replayed on S3 resume.\r | |
553 | \r | |
554 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
555 | bitwise OR between the read result and the value specified by\r | |
556 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
557 | specified by Address. The value written to the PCI configuration register is\r | |
558 | returned. This function must guarantee that all PCI read and write operations\r | |
559 | are serialized. Extra left bits in OrData are stripped.\r | |
560 | \r | |
561 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
562 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
563 | If StartBit is greater than 15, then ASSERT().\r | |
564 | If EndBit is greater than 15, then ASSERT().\r | |
565 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 566 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fe69ac84 | 567 | \r |
568 | @param[in] Address The PCI configuration register to write.\r | |
569 | @param[in] StartBit The ordinal of the least significant bit in the bit field.\r | |
570 | Range 0..15.\r | |
571 | @param[in] EndBit The ordinal of the most significant bit in the bit field.\r | |
572 | Range 0..15.\r | |
573 | @param[in] OrData The value to OR with the PCI configuration register.\r | |
574 | \r | |
575 | @return The value written back to the PCI configuration register.\r | |
576 | \r | |
577 | **/\r | |
578 | UINT16\r | |
579 | EFIAPI\r | |
580 | S3PciBitFieldOr16 (\r | |
581 | IN UINTN Address,\r | |
582 | IN UINTN StartBit,\r | |
583 | IN UINTN EndBit,\r | |
584 | IN UINT16 OrData\r | |
585 | );\r | |
586 | \r | |
587 | /**\r | |
588 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
589 | AND, and writes the result back to the bit field in the 16-bit register and\r | |
590 | saves the value in the S3 script to be replayed on S3 resume.\r | |
591 | \r | |
592 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
593 | bitwise AND between the read result and the value specified by AndData, and\r | |
594 | writes the result to the 16-bit PCI configuration register specified by\r | |
595 | Address. The value written to the PCI configuration register is returned.\r | |
596 | This function must guarantee that all PCI read and write operations are\r | |
597 | serialized. Extra left bits in AndData are stripped.\r | |
598 | \r | |
599 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
600 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
601 | If StartBit is greater than 15, then ASSERT().\r | |
602 | If EndBit is greater than 15, then ASSERT().\r | |
603 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 604 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fe69ac84 | 605 | \r |
606 | @param[in] Address The PCI configuration register to write.\r | |
607 | @param[in] StartBit The ordinal of the least significant bit in the bit field.\r | |
608 | Range 0..15.\r | |
609 | @param[in] EndBit The ordinal of the most significant bit in the bit field.\r | |
610 | Range 0..15.\r | |
611 | @param[in] AndData The value to AND with the PCI configuration register.\r | |
612 | \r | |
613 | @return The value written back to the PCI configuration register.\r | |
614 | \r | |
615 | **/\r | |
616 | UINT16\r | |
617 | EFIAPI\r | |
618 | S3PciBitFieldAnd16 (\r | |
619 | IN UINTN Address,\r | |
620 | IN UINTN StartBit,\r | |
621 | IN UINTN EndBit,\r | |
622 | IN UINT16 AndData\r | |
623 | );\r | |
624 | \r | |
625 | /**\r | |
626 | Reads a bit field in a 16-bit Address, performs a bitwise AND followed by a\r | |
627 | bitwise OR, and writes the result back to the bit field in the\r | |
628 | 16-bit port, and saves the value in the S3 script to be replayed on S3 resume.\r | |
629 | \r | |
630 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
631 | bitwise AND followed by a bitwise OR between the read result and\r | |
632 | the value specified by AndData, and writes the result to the 16-bit PCI\r | |
633 | configuration register specified by Address. The value written to the PCI\r | |
634 | configuration register is returned. This function must guarantee that all PCI\r | |
635 | read and write operations are serialized. Extra left bits in both AndData and\r | |
636 | OrData are stripped.\r | |
637 | \r | |
638 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
639 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
640 | If StartBit is greater than 15, then ASSERT().\r | |
641 | If EndBit is greater than 15, then ASSERT().\r | |
642 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
643 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
644 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
fe69ac84 | 645 | \r |
646 | @param[in] Address The PCI configuration register to write.\r | |
647 | @param[in] StartBit The ordinal of the least significant bit in the bit field.\r | |
648 | Range 0..15.\r | |
649 | @param[in] EndBit The ordinal of the most significant bit in the bit field.\r | |
650 | Range 0..15.\r | |
651 | @param[in] AndData The value to AND with the PCI configuration register.\r | |
652 | @param[in] OrData The value to OR with the result of the AND operation.\r | |
653 | \r | |
654 | @return The value written back to the PCI configuration register.\r | |
655 | \r | |
656 | **/\r | |
657 | UINT16\r | |
658 | EFIAPI\r | |
659 | S3PciBitFieldAndThenOr16 (\r | |
660 | IN UINTN Address,\r | |
661 | IN UINTN StartBit,\r | |
662 | IN UINTN EndBit,\r | |
663 | IN UINT16 AndData,\r | |
664 | IN UINT16 OrData\r | |
665 | );\r | |
666 | \r | |
667 | /**\r | |
668 | Reads a 32-bit PCI configuration register, and saves the value in the S3\r | |
669 | script to be replayed on S3 resume.\r | |
670 | \r | |
671 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
672 | This function must guarantee that all PCI read and write operations are\r | |
673 | serialized.\r | |
674 | \r | |
675 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
676 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
677 | \r | |
678 | @param[in] Address The address that encodes the PCI Bus, Device, Function and\r | |
679 | Register.\r | |
680 | \r | |
681 | @return The read value from the PCI configuration register.\r | |
682 | \r | |
683 | **/\r | |
684 | UINT32\r | |
685 | EFIAPI\r | |
686 | S3PciRead32 (\r | |
687 | IN UINTN Address\r | |
688 | );\r | |
689 | \r | |
690 | /**\r | |
691 | Writes a 32-bit PCI configuration register, and saves the value in the S3\r | |
692 | script to be replayed on S3 resume.\r | |
693 | \r | |
694 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
695 | value specified by Value. Value is returned. This function must guarantee\r | |
696 | that all PCI read and write operations are serialized.\r | |
697 | \r | |
698 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
699 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
700 | \r | |
701 | @param[in] Address The address that encodes the PCI Bus, Device, Function and\r | |
702 | Register.\r | |
703 | @param[in] Value The value to write.\r | |
704 | \r | |
705 | @return The value written to the PCI configuration register.\r | |
706 | \r | |
707 | **/\r | |
708 | UINT32\r | |
709 | EFIAPI\r | |
710 | S3PciWrite32 (\r | |
711 | IN UINTN Address,\r | |
712 | IN UINT32 Value\r | |
713 | );\r | |
714 | \r | |
715 | /**\r | |
716 | Performs a bitwise OR of a 32-bit PCI configuration register with\r | |
717 | a 32-bit value, and saves the value in the S3 script to be replayed on S3 resume.\r | |
718 | \r | |
719 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
720 | bitwise OR between the read result and the value specified by\r | |
721 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
722 | specified by Address. The value written to the PCI configuration register is\r | |
723 | returned. This function must guarantee that all PCI read and write operations\r | |
724 | are serialized.\r | |
725 | \r | |
726 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
727 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
728 | \r | |
729 | @param[in] Address The address that encodes the PCI Bus, Device, Function and\r | |
730 | Register.\r | |
731 | @param[in] OrData The value to OR with the PCI configuration register.\r | |
732 | \r | |
733 | @return The value written back to the PCI configuration register.\r | |
734 | \r | |
735 | **/\r | |
736 | UINT32\r | |
737 | EFIAPI\r | |
738 | S3PciOr32 (\r | |
739 | IN UINTN Address,\r | |
740 | IN UINT32 OrData\r | |
741 | );\r | |
742 | \r | |
743 | /**\r | |
744 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
745 | value, and saves the value in the S3 script to be replayed on S3 resume.\r | |
746 | \r | |
747 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
748 | bitwise AND between the read result and the value specified by AndData, and\r | |
749 | writes the result to the 32-bit PCI configuration register specified by\r | |
750 | Address. The value written to the PCI configuration register is returned.\r | |
751 | This function must guarantee that all PCI read and write operations are\r | |
752 | serialized.\r | |
753 | \r | |
754 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
755 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
756 | \r | |
757 | @param[in] Address The address that encodes the PCI Bus, Device, Function and\r | |
758 | Register.\r | |
759 | @param[in] AndData The value to AND with the PCI configuration register.\r | |
760 | \r | |
761 | @return The value written back to the PCI configuration register.\r | |
762 | \r | |
763 | **/\r | |
764 | UINT32\r | |
765 | EFIAPI\r | |
766 | S3PciAnd32 (\r | |
767 | IN UINTN Address,\r | |
768 | IN UINT32 AndData\r | |
769 | );\r | |
770 | \r | |
771 | /**\r | |
772 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
773 | value, followed a bitwise OR with another 32-bit value, and saves\r | |
774 | the value in the S3 script to be replayed on S3 resume.\r | |
775 | \r | |
776 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
777 | bitwise AND between the read result and the value specified by AndData,\r | |
778 | performs a bitwise OR between the result of the AND operation and\r | |
779 | the value specified by OrData, and writes the result to the 32-bit PCI\r | |
780 | configuration register specified by Address. The value written to the PCI\r | |
781 | configuration register is returned. This function must guarantee that all PCI\r | |
782 | read and write operations are serialized.\r | |
783 | \r | |
784 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
785 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
786 | \r | |
787 | @param[in] Address The address that encodes the PCI Bus, Device, Function and\r | |
788 | Register.\r | |
789 | @param[in] AndData The value to AND with the PCI configuration register.\r | |
790 | @param[in] OrData The value to OR with the result of the AND operation.\r | |
791 | \r | |
792 | @return The value written back to the PCI configuration register.\r | |
793 | \r | |
794 | **/\r | |
795 | UINT32\r | |
796 | EFIAPI\r | |
797 | S3PciAndThenOr32 (\r | |
798 | IN UINTN Address,\r | |
799 | IN UINT32 AndData,\r | |
800 | IN UINT32 OrData\r | |
801 | );\r | |
802 | \r | |
803 | /**\r | |
804 | Reads a bit field of a PCI configuration register, and saves the value in\r | |
805 | the S3 script to be replayed on S3 resume.\r | |
806 | \r | |
807 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
808 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
809 | returned.\r | |
810 | \r | |
811 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
812 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
813 | If StartBit is greater than 31, then ASSERT().\r | |
814 | If EndBit is greater than 31, then ASSERT().\r | |
815 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 816 | \r |
fe69ac84 | 817 | @param[in] Address The PCI configuration register to read.\r |
818 | @param[in] StartBit The ordinal of the least significant bit in the bit field.\r | |
819 | Range 0..31.\r | |
820 | @param[in] EndBit The ordinal of the most significant bit in the bit field.\r | |
821 | Range 0..31.\r | |
822 | \r | |
823 | @return The value of the bit field read from the PCI configuration register.\r | |
824 | \r | |
825 | **/\r | |
826 | UINT32\r | |
827 | EFIAPI\r | |
828 | S3PciBitFieldRead32 (\r | |
829 | IN UINTN Address,\r | |
830 | IN UINTN StartBit,\r | |
831 | IN UINTN EndBit\r | |
832 | );\r | |
833 | \r | |
834 | /**\r | |
835 | Writes a bit field to a PCI configuration register, and saves the value in\r | |
836 | the S3 script to be replayed on S3 resume.\r | |
837 | \r | |
838 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
839 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
840 | destination PCI configuration register are preserved. The new value of the\r | |
841 | 32-bit register is returned.\r | |
842 | \r | |
843 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
844 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
845 | If StartBit is greater than 31, then ASSERT().\r | |
846 | If EndBit is greater than 31, then ASSERT().\r | |
847 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 848 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fe69ac84 | 849 | \r |
850 | @param[in] Address The PCI configuration register to write.\r | |
851 | @param[in] StartBit The ordinal of the least significant bit in the bit field.\r | |
852 | Range 0..31.\r | |
853 | @param[in] EndBit The ordinal of the most significant bit in the bit field.\r | |
854 | Range 0..31.\r | |
855 | @param[in] Value New value of the bit field.\r | |
856 | \r | |
857 | @return The value written back to the PCI configuration register.\r | |
858 | \r | |
859 | **/\r | |
860 | UINT32\r | |
861 | EFIAPI\r | |
862 | S3PciBitFieldWrite32 (\r | |
863 | IN UINTN Address,\r | |
864 | IN UINTN StartBit,\r | |
865 | IN UINTN EndBit,\r | |
866 | IN UINT32 Value\r | |
867 | );\r | |
868 | \r | |
869 | /**\r | |
870 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
871 | writes the result back to the bit field in the 32-bit port, and saves the value\r | |
872 | in the S3 script to be replayed on S3 resume.\r | |
873 | \r | |
874 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
875 | bitwise OR between the read result and the value specified by\r | |
876 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
877 | specified by Address. The value written to the PCI configuration register is\r | |
878 | returned. This function must guarantee that all PCI read and write operations\r | |
879 | are serialized. Extra left bits in OrData are stripped.\r | |
880 | \r | |
881 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
882 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
883 | If StartBit is greater than 31, then ASSERT().\r | |
884 | If EndBit is greater than 31, then ASSERT().\r | |
885 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 886 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fe69ac84 | 887 | \r |
888 | @param[in] Address The PCI configuration register to write.\r | |
889 | @param[in] StartBit The ordinal of the least significant bit in the bit field.\r | |
890 | Range 0..31.\r | |
891 | @param[in] EndBit The ordinal of the most significant bit in the bit field.\r | |
892 | Range 0..31.\r | |
893 | @param[in] OrData The value to OR with the PCI configuration register.\r | |
894 | \r | |
895 | @return The value written back to the PCI configuration register.\r | |
896 | \r | |
897 | **/\r | |
898 | UINT32\r | |
899 | EFIAPI\r | |
900 | S3PciBitFieldOr32 (\r | |
901 | IN UINTN Address,\r | |
902 | IN UINTN StartBit,\r | |
903 | IN UINTN EndBit,\r | |
904 | IN UINT32 OrData\r | |
905 | );\r | |
906 | \r | |
907 | /**\r | |
908 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
909 | AND, and writes the result back to the bit field in the 32-bit register and\r | |
910 | saves the value in the S3 script to be replayed on S3 resume.\r | |
911 | \r | |
912 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
913 | bitwise AND between the read result and the value specified by AndData, and\r | |
914 | writes the result to the 32-bit PCI configuration register specified by\r | |
915 | Address. The value written to the PCI configuration register is returned.\r | |
916 | This function must guarantee that all PCI read and write operations are\r | |
917 | serialized. Extra left bits in AndData are stripped.\r | |
918 | \r | |
919 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
920 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
921 | If StartBit is greater than 31, then ASSERT().\r | |
922 | If EndBit is greater than 31, then ASSERT().\r | |
923 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 924 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fe69ac84 | 925 | \r |
926 | @param[in] Address The PCI configuration register to write.\r | |
927 | @param[in] StartBit The ordinal of the least significant bit in the bit field.\r | |
928 | Range 0..31.\r | |
929 | @param[in] EndBit The ordinal of the most significant bit in the bit field.\r | |
930 | Range 0..31.\r | |
931 | @param[in] AndData The value to AND with the PCI configuration register.\r | |
932 | \r | |
933 | @return The value written back to the PCI configuration register.\r | |
934 | \r | |
935 | **/\r | |
936 | UINT32\r | |
937 | EFIAPI\r | |
938 | S3PciBitFieldAnd32 (\r | |
939 | IN UINTN Address,\r | |
940 | IN UINTN StartBit,\r | |
941 | IN UINTN EndBit,\r | |
942 | IN UINT32 AndData\r | |
943 | );\r | |
944 | \r | |
945 | /**\r | |
946 | Reads a bit field in a 32-bit Address, performs a bitwise AND followed by a\r | |
947 | bitwise OR, and writes the result back to the bit field in the\r | |
948 | 32-bit port, and saves the value in the S3 script to be replayed on S3 resume.\r | |
949 | \r | |
950 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
951 | bitwise AND followed by a bitwise OR between the read result and\r | |
952 | the value specified by AndData, and writes the result to the 32-bit PCI\r | |
953 | configuration register specified by Address. The value written to the PCI\r | |
954 | configuration register is returned. This function must guarantee that all PCI\r | |
955 | read and write operations are serialized. Extra left bits in both AndData and\r | |
956 | OrData are stripped.\r | |
957 | \r | |
958 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
959 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
960 | If StartBit is greater than 31, then ASSERT().\r | |
961 | If EndBit is greater than 31, then ASSERT().\r | |
962 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
963 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
964 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
fe69ac84 | 965 | \r |
966 | @param[in] Address The PCI configuration register to write.\r | |
967 | @param[in] StartBit The ordinal of the least significant bit in the bit field.\r | |
968 | Range 0..31.\r | |
969 | @param[in] EndBit The ordinal of the most significant bit in the bit field.\r | |
970 | Range 0..31.\r | |
971 | @param[in] AndData The value to AND with the PCI configuration register.\r | |
972 | @param[in] OrData The value to OR with the result of the AND operation.\r | |
973 | \r | |
974 | @return The value written back to the PCI configuration register.\r | |
975 | \r | |
976 | **/\r | |
977 | UINT32\r | |
978 | EFIAPI\r | |
979 | S3PciBitFieldAndThenOr32 (\r | |
980 | IN UINTN Address,\r | |
981 | IN UINTN StartBit,\r | |
982 | IN UINTN EndBit,\r | |
983 | IN UINT32 AndData,\r | |
984 | IN UINT32 OrData\r | |
985 | );\r | |
986 | \r | |
987 | /**\r | |
988 | Reads a range of PCI configuration registers into a caller supplied buffer,\r | |
989 | and saves the value in the S3 script to be replayed on S3 resume.\r | |
990 | \r | |
991 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
992 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
993 | configuration registers from a single PCI function to be read. Size is\r | |
994 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
995 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
996 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
997 | end of the range.\r | |
998 | \r | |
999 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1000 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1001 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1002 | \r | |
1003 | @param[in] StartAddress Starting address that encodes the PCI Bus, Device,\r | |
1004 | Function and Register.\r | |
1005 | @param[in] Size Size in bytes of the transfer.\r | |
1006 | @param[out] Buffer The pointer to a buffer receiving the data read.\r | |
1007 | \r | |
1008 | @return Size.\r | |
1009 | \r | |
1010 | **/\r | |
1011 | UINTN\r | |
1012 | EFIAPI\r | |
1013 | S3PciReadBuffer (\r | |
1014 | IN UINTN StartAddress,\r | |
1015 | IN UINTN Size,\r | |
1016 | OUT VOID *Buffer\r | |
1017 | );\r | |
1018 | \r | |
1019 | /**\r | |
1020 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1021 | configuration space, and saves the value in the S3 script to be replayed on S3\r | |
1022 | resume.\r | |
1023 | \r | |
1024 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1025 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1026 | configuration registers from a single PCI function to be written. Size is\r | |
1027 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1028 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1029 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1030 | and the end of the range.\r | |
1031 | \r | |
1032 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1033 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1034 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1035 | \r | |
1036 | @param[in] StartAddress Starting address that encodes the PCI Bus, Device,\r | |
1037 | Function and Register.\r | |
1038 | @param[in] Size Size in bytes of the transfer.\r | |
1039 | @param[in] Buffer The pointer to a buffer containing the data to write.\r | |
1040 | \r | |
1041 | @return Size.\r | |
1042 | \r | |
1043 | **/\r | |
1044 | UINTN\r | |
1045 | EFIAPI\r | |
1046 | S3PciWriteBuffer (\r | |
1047 | IN UINTN StartAddress,\r | |
1048 | IN UINTN Size,\r | |
1049 | IN VOID *Buffer\r | |
1050 | );\r | |
1051 | \r | |
1052 | #endif\r |