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d1f95000 | 1 | /** @file\r |
b4319afb | 2 | DebugSupport protocol and supporting definitions as defined in the UEFI2.4\r |
d1f95000 | 3 | specification.\r |
4 | \r | |
5 | The DebugSupport protocol is used by source level debuggers to abstract the\r | |
6 | processor and handle context save and restore operations.\r | |
7 | \r | |
9095d37b | 8 | Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r |
b4319afb HL |
9 | Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>\r |
10 | \r | |
9344f092 | 11 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
d1f95000 | 12 | \r |
d1f95000 | 13 | **/\r |
14 | \r | |
15 | #ifndef __DEBUG_SUPPORT_H__\r | |
16 | #define __DEBUG_SUPPORT_H__\r | |
17 | \r | |
18 | #include <IndustryStandard/PeImage.h>\r | |
19 | \r | |
20 | typedef struct _EFI_DEBUG_SUPPORT_PROTOCOL EFI_DEBUG_SUPPORT_PROTOCOL;\r | |
21 | \r | |
99e8ed21 | 22 | ///\r |
af2dc6a7 | 23 | /// Debug Support protocol {2755590C-6F3C-42FA-9EA4-A3BA543CDA25}.\r |
99e8ed21 | 24 | ///\r |
d1f95000 | 25 | #define EFI_DEBUG_SUPPORT_PROTOCOL_GUID \\r |
26 | { \\r | |
27 | 0x2755590C, 0x6F3C, 0x42FA, {0x9E, 0xA4, 0xA3, 0xBA, 0x54, 0x3C, 0xDA, 0x25 } \\r | |
28 | }\r | |
29 | \r | |
99e8ed21 | 30 | ///\r |
9319d2c2 LG |
31 | /// Processor exception to be hooked.\r |
32 | /// All exception types for IA32, X64, Itanium and EBC processors are defined.\r | |
99e8ed21 | 33 | ///\r |
d1f95000 | 34 | typedef INTN EFI_EXCEPTION_TYPE;\r |
35 | \r | |
9319d2c2 | 36 | ///\r |
af2dc6a7 | 37 | /// IA-32 processor exception types.\r |
9319d2c2 | 38 | ///\r |
d1f95000 | 39 | #define EXCEPT_IA32_DIVIDE_ERROR 0\r |
40 | #define EXCEPT_IA32_DEBUG 1\r | |
41 | #define EXCEPT_IA32_NMI 2\r | |
42 | #define EXCEPT_IA32_BREAKPOINT 3\r | |
43 | #define EXCEPT_IA32_OVERFLOW 4\r | |
44 | #define EXCEPT_IA32_BOUND 5\r | |
45 | #define EXCEPT_IA32_INVALID_OPCODE 6\r | |
46 | #define EXCEPT_IA32_DOUBLE_FAULT 8\r | |
47 | #define EXCEPT_IA32_INVALID_TSS 10\r | |
48 | #define EXCEPT_IA32_SEG_NOT_PRESENT 11\r | |
49 | #define EXCEPT_IA32_STACK_FAULT 12\r | |
50 | #define EXCEPT_IA32_GP_FAULT 13\r | |
51 | #define EXCEPT_IA32_PAGE_FAULT 14\r | |
52 | #define EXCEPT_IA32_FP_ERROR 16\r | |
53 | #define EXCEPT_IA32_ALIGNMENT_CHECK 17\r | |
54 | #define EXCEPT_IA32_MACHINE_CHECK 18\r | |
55 | #define EXCEPT_IA32_SIMD 19\r | |
56 | \r | |
8b6c989b | 57 | ///\r |
af2dc6a7 | 58 | /// FXSAVE_STATE.\r |
59 | /// FP / MMX / XMM registers (see fxrstor instruction definition).\r | |
8b6c989b | 60 | ///\r |
d1f95000 | 61 | typedef struct {\r |
62 | UINT16 Fcw;\r | |
63 | UINT16 Fsw;\r | |
64 | UINT16 Ftw;\r | |
65 | UINT16 Opcode;\r | |
66 | UINT32 Eip;\r | |
67 | UINT16 Cs;\r | |
68 | UINT16 Reserved1;\r | |
69 | UINT32 DataOffset;\r | |
70 | UINT16 Ds;\r | |
71 | UINT8 Reserved2[10];\r | |
d1f95000 | 72 | UINT8 St0Mm0[10], Reserved3[6];\r |
73 | UINT8 St1Mm1[10], Reserved4[6];\r | |
74 | UINT8 St2Mm2[10], Reserved5[6];\r | |
75 | UINT8 St3Mm3[10], Reserved6[6];\r | |
76 | UINT8 St4Mm4[10], Reserved7[6];\r | |
77 | UINT8 St5Mm5[10], Reserved8[6];\r | |
78 | UINT8 St6Mm6[10], Reserved9[6];\r | |
79 | UINT8 St7Mm7[10], Reserved10[6];\r | |
80 | UINT8 Xmm0[16];\r | |
81 | UINT8 Xmm1[16];\r | |
82 | UINT8 Xmm2[16];\r | |
83 | UINT8 Xmm3[16];\r | |
84 | UINT8 Xmm4[16];\r | |
85 | UINT8 Xmm5[16];\r | |
86 | UINT8 Xmm6[16];\r | |
87 | UINT8 Xmm7[16];\r | |
88 | UINT8 Reserved11[14 * 16];\r | |
89 | } EFI_FX_SAVE_STATE_IA32;\r | |
d1f95000 | 90 | \r |
9319d2c2 | 91 | ///\r |
af2dc6a7 | 92 | /// IA-32 processor context definition.\r |
9319d2c2 | 93 | ///\r |
d1f95000 | 94 | typedef struct {\r |
95 | UINT32 ExceptionData;\r | |
d1f95000 | 96 | EFI_FX_SAVE_STATE_IA32 FxSaveState;\r |
d1f95000 | 97 | UINT32 Dr0;\r |
98 | UINT32 Dr1;\r | |
99 | UINT32 Dr2;\r | |
100 | UINT32 Dr3;\r | |
101 | UINT32 Dr6;\r | |
102 | UINT32 Dr7;\r | |
103 | UINT32 Cr0;\r | |
104 | UINT32 Cr1; /* Reserved */\r | |
105 | UINT32 Cr2;\r | |
106 | UINT32 Cr3;\r | |
107 | UINT32 Cr4;\r | |
108 | UINT32 Eflags;\r | |
109 | UINT32 Ldtr;\r | |
110 | UINT32 Tr;\r | |
111 | UINT32 Gdtr[2];\r | |
112 | UINT32 Idtr[2];\r | |
113 | UINT32 Eip;\r | |
114 | UINT32 Gs;\r | |
115 | UINT32 Fs;\r | |
116 | UINT32 Es;\r | |
117 | UINT32 Ds;\r | |
118 | UINT32 Cs;\r | |
119 | UINT32 Ss;\r | |
120 | UINT32 Edi;\r | |
121 | UINT32 Esi;\r | |
122 | UINT32 Ebp;\r | |
123 | UINT32 Esp;\r | |
124 | UINT32 Ebx;\r | |
125 | UINT32 Edx;\r | |
126 | UINT32 Ecx;\r | |
127 | UINT32 Eax;\r | |
128 | } EFI_SYSTEM_CONTEXT_IA32;\r | |
129 | \r | |
9319d2c2 | 130 | ///\r |
af2dc6a7 | 131 | /// x64 processor exception types.\r |
9319d2c2 | 132 | ///\r |
d1f95000 | 133 | #define EXCEPT_X64_DIVIDE_ERROR 0\r |
134 | #define EXCEPT_X64_DEBUG 1\r | |
135 | #define EXCEPT_X64_NMI 2\r | |
136 | #define EXCEPT_X64_BREAKPOINT 3\r | |
137 | #define EXCEPT_X64_OVERFLOW 4\r | |
138 | #define EXCEPT_X64_BOUND 5\r | |
139 | #define EXCEPT_X64_INVALID_OPCODE 6\r | |
140 | #define EXCEPT_X64_DOUBLE_FAULT 8\r | |
141 | #define EXCEPT_X64_INVALID_TSS 10\r | |
142 | #define EXCEPT_X64_SEG_NOT_PRESENT 11\r | |
143 | #define EXCEPT_X64_STACK_FAULT 12\r | |
144 | #define EXCEPT_X64_GP_FAULT 13\r | |
145 | #define EXCEPT_X64_PAGE_FAULT 14\r | |
146 | #define EXCEPT_X64_FP_ERROR 16\r | |
147 | #define EXCEPT_X64_ALIGNMENT_CHECK 17\r | |
148 | #define EXCEPT_X64_MACHINE_CHECK 18\r | |
149 | #define EXCEPT_X64_SIMD 19\r | |
150 | \r | |
8b6c989b | 151 | ///\r |
af2dc6a7 | 152 | /// FXSAVE_STATE.\r |
153 | /// FP / MMX / XMM registers (see fxrstor instruction definition).\r | |
8b6c989b | 154 | ///\r |
d1f95000 | 155 | typedef struct {\r |
156 | UINT16 Fcw;\r | |
157 | UINT16 Fsw;\r | |
158 | UINT16 Ftw;\r | |
159 | UINT16 Opcode;\r | |
160 | UINT64 Rip;\r | |
161 | UINT64 DataOffset;\r | |
162 | UINT8 Reserved1[8];\r | |
163 | UINT8 St0Mm0[10], Reserved2[6];\r | |
164 | UINT8 St1Mm1[10], Reserved3[6];\r | |
165 | UINT8 St2Mm2[10], Reserved4[6];\r | |
166 | UINT8 St3Mm3[10], Reserved5[6];\r | |
167 | UINT8 St4Mm4[10], Reserved6[6];\r | |
168 | UINT8 St5Mm5[10], Reserved7[6];\r | |
169 | UINT8 St6Mm6[10], Reserved8[6];\r | |
170 | UINT8 St7Mm7[10], Reserved9[6];\r | |
171 | UINT8 Xmm0[16];\r | |
172 | UINT8 Xmm1[16];\r | |
173 | UINT8 Xmm2[16];\r | |
174 | UINT8 Xmm3[16];\r | |
175 | UINT8 Xmm4[16];\r | |
176 | UINT8 Xmm5[16];\r | |
177 | UINT8 Xmm6[16];\r | |
178 | UINT8 Xmm7[16];\r | |
d1f95000 | 179 | //\r |
9095d37b | 180 | // NOTE: UEFI 2.0 spec definition as follows.\r |
d1f95000 | 181 | //\r |
182 | UINT8 Reserved11[14 * 16];\r | |
d1f95000 | 183 | } EFI_FX_SAVE_STATE_X64;\r |
184 | \r | |
9319d2c2 | 185 | ///\r |
af2dc6a7 | 186 | /// x64 processor context definition.\r |
9319d2c2 | 187 | ///\r |
d1f95000 | 188 | typedef struct {\r |
189 | UINT64 ExceptionData;\r | |
190 | EFI_FX_SAVE_STATE_X64 FxSaveState;\r | |
191 | UINT64 Dr0;\r | |
192 | UINT64 Dr1;\r | |
193 | UINT64 Dr2;\r | |
194 | UINT64 Dr3;\r | |
195 | UINT64 Dr6;\r | |
196 | UINT64 Dr7;\r | |
197 | UINT64 Cr0;\r | |
198 | UINT64 Cr1; /* Reserved */\r | |
199 | UINT64 Cr2;\r | |
200 | UINT64 Cr3;\r | |
201 | UINT64 Cr4;\r | |
202 | UINT64 Cr8;\r | |
203 | UINT64 Rflags;\r | |
204 | UINT64 Ldtr;\r | |
205 | UINT64 Tr;\r | |
206 | UINT64 Gdtr[2];\r | |
207 | UINT64 Idtr[2];\r | |
208 | UINT64 Rip;\r | |
209 | UINT64 Gs;\r | |
210 | UINT64 Fs;\r | |
211 | UINT64 Es;\r | |
212 | UINT64 Ds;\r | |
213 | UINT64 Cs;\r | |
214 | UINT64 Ss;\r | |
215 | UINT64 Rdi;\r | |
216 | UINT64 Rsi;\r | |
217 | UINT64 Rbp;\r | |
218 | UINT64 Rsp;\r | |
219 | UINT64 Rbx;\r | |
220 | UINT64 Rdx;\r | |
221 | UINT64 Rcx;\r | |
222 | UINT64 Rax;\r | |
223 | UINT64 R8;\r | |
224 | UINT64 R9;\r | |
225 | UINT64 R10;\r | |
226 | UINT64 R11;\r | |
227 | UINT64 R12;\r | |
228 | UINT64 R13;\r | |
229 | UINT64 R14;\r | |
230 | UINT64 R15;\r | |
231 | } EFI_SYSTEM_CONTEXT_X64;\r | |
232 | \r | |
9319d2c2 | 233 | ///\r |
af2dc6a7 | 234 | /// Itanium Processor Family Exception types.\r |
9319d2c2 | 235 | ///\r |
d1f95000 | 236 | #define EXCEPT_IPF_VHTP_TRANSLATION 0\r |
237 | #define EXCEPT_IPF_INSTRUCTION_TLB 1\r | |
238 | #define EXCEPT_IPF_DATA_TLB 2\r | |
239 | #define EXCEPT_IPF_ALT_INSTRUCTION_TLB 3\r | |
240 | #define EXCEPT_IPF_ALT_DATA_TLB 4\r | |
241 | #define EXCEPT_IPF_DATA_NESTED_TLB 5\r | |
242 | #define EXCEPT_IPF_INSTRUCTION_KEY_MISSED 6\r | |
243 | #define EXCEPT_IPF_DATA_KEY_MISSED 7\r | |
244 | #define EXCEPT_IPF_DIRTY_BIT 8\r | |
245 | #define EXCEPT_IPF_INSTRUCTION_ACCESS_BIT 9\r | |
246 | #define EXCEPT_IPF_DATA_ACCESS_BIT 10\r | |
247 | #define EXCEPT_IPF_BREAKPOINT 11\r | |
248 | #define EXCEPT_IPF_EXTERNAL_INTERRUPT 12\r | |
249 | //\r | |
250 | // 13 - 19 reserved\r | |
251 | //\r | |
252 | #define EXCEPT_IPF_PAGE_NOT_PRESENT 20\r | |
253 | #define EXCEPT_IPF_KEY_PERMISSION 21\r | |
254 | #define EXCEPT_IPF_INSTRUCTION_ACCESS_RIGHTS 22\r | |
255 | #define EXCEPT_IPF_DATA_ACCESS_RIGHTS 23\r | |
256 | #define EXCEPT_IPF_GENERAL_EXCEPTION 24\r | |
257 | #define EXCEPT_IPF_DISABLED_FP_REGISTER 25\r | |
258 | #define EXCEPT_IPF_NAT_CONSUMPTION 26\r | |
259 | #define EXCEPT_IPF_SPECULATION 27\r | |
260 | //\r | |
261 | // 28 reserved\r | |
262 | //\r | |
263 | #define EXCEPT_IPF_DEBUG 29\r | |
264 | #define EXCEPT_IPF_UNALIGNED_REFERENCE 30\r | |
265 | #define EXCEPT_IPF_UNSUPPORTED_DATA_REFERENCE 31\r | |
266 | #define EXCEPT_IPF_FP_FAULT 32\r | |
267 | #define EXCEPT_IPF_FP_TRAP 33\r | |
268 | #define EXCEPT_IPF_LOWER_PRIVILEGE_TRANSFER_TRAP 34\r | |
269 | #define EXCEPT_IPF_TAKEN_BRANCH 35\r | |
270 | #define EXCEPT_IPF_SINGLE_STEP 36\r | |
271 | //\r | |
272 | // 37 - 44 reserved\r | |
273 | //\r | |
274 | #define EXCEPT_IPF_IA32_EXCEPTION 45\r | |
275 | #define EXCEPT_IPF_IA32_INTERCEPT 46\r | |
276 | #define EXCEPT_IPF_IA32_INTERRUPT 47\r | |
277 | \r | |
8b6c989b | 278 | ///\r |
af2dc6a7 | 279 | /// IPF processor context definition.\r |
8b6c989b | 280 | ///\r |
d1f95000 | 281 | typedef struct {\r |
282 | //\r | |
283 | // The first reserved field is necessary to preserve alignment for the correct\r | |
630b4187 | 284 | // bits in UNAT and to insure F2 is 16 byte aligned.\r |
d1f95000 | 285 | //\r |
286 | UINT64 Reserved;\r | |
287 | UINT64 R1;\r | |
288 | UINT64 R2;\r | |
289 | UINT64 R3;\r | |
290 | UINT64 R4;\r | |
291 | UINT64 R5;\r | |
292 | UINT64 R6;\r | |
293 | UINT64 R7;\r | |
294 | UINT64 R8;\r | |
295 | UINT64 R9;\r | |
296 | UINT64 R10;\r | |
297 | UINT64 R11;\r | |
298 | UINT64 R12;\r | |
299 | UINT64 R13;\r | |
300 | UINT64 R14;\r | |
301 | UINT64 R15;\r | |
302 | UINT64 R16;\r | |
303 | UINT64 R17;\r | |
304 | UINT64 R18;\r | |
305 | UINT64 R19;\r | |
306 | UINT64 R20;\r | |
307 | UINT64 R21;\r | |
308 | UINT64 R22;\r | |
309 | UINT64 R23;\r | |
310 | UINT64 R24;\r | |
311 | UINT64 R25;\r | |
312 | UINT64 R26;\r | |
313 | UINT64 R27;\r | |
314 | UINT64 R28;\r | |
315 | UINT64 R29;\r | |
316 | UINT64 R30;\r | |
317 | UINT64 R31;\r | |
318 | \r | |
319 | UINT64 F2[2];\r | |
320 | UINT64 F3[2];\r | |
321 | UINT64 F4[2];\r | |
322 | UINT64 F5[2];\r | |
323 | UINT64 F6[2];\r | |
324 | UINT64 F7[2];\r | |
325 | UINT64 F8[2];\r | |
326 | UINT64 F9[2];\r | |
327 | UINT64 F10[2];\r | |
328 | UINT64 F11[2];\r | |
329 | UINT64 F12[2];\r | |
330 | UINT64 F13[2];\r | |
331 | UINT64 F14[2];\r | |
332 | UINT64 F15[2];\r | |
333 | UINT64 F16[2];\r | |
334 | UINT64 F17[2];\r | |
335 | UINT64 F18[2];\r | |
336 | UINT64 F19[2];\r | |
337 | UINT64 F20[2];\r | |
338 | UINT64 F21[2];\r | |
339 | UINT64 F22[2];\r | |
340 | UINT64 F23[2];\r | |
341 | UINT64 F24[2];\r | |
342 | UINT64 F25[2];\r | |
343 | UINT64 F26[2];\r | |
344 | UINT64 F27[2];\r | |
345 | UINT64 F28[2];\r | |
346 | UINT64 F29[2];\r | |
347 | UINT64 F30[2];\r | |
348 | UINT64 F31[2];\r | |
349 | \r | |
350 | UINT64 Pr;\r | |
351 | \r | |
352 | UINT64 B0;\r | |
353 | UINT64 B1;\r | |
354 | UINT64 B2;\r | |
355 | UINT64 B3;\r | |
356 | UINT64 B4;\r | |
357 | UINT64 B5;\r | |
358 | UINT64 B6;\r | |
359 | UINT64 B7;\r | |
360 | \r | |
361 | //\r | |
362 | // application registers\r | |
363 | //\r | |
364 | UINT64 ArRsc;\r | |
365 | UINT64 ArBsp;\r | |
366 | UINT64 ArBspstore;\r | |
367 | UINT64 ArRnat;\r | |
368 | \r | |
369 | UINT64 ArFcr;\r | |
370 | \r | |
371 | UINT64 ArEflag;\r | |
372 | UINT64 ArCsd;\r | |
373 | UINT64 ArSsd;\r | |
374 | UINT64 ArCflg;\r | |
375 | UINT64 ArFsr;\r | |
376 | UINT64 ArFir;\r | |
377 | UINT64 ArFdr;\r | |
378 | \r | |
379 | UINT64 ArCcv;\r | |
380 | \r | |
381 | UINT64 ArUnat;\r | |
382 | \r | |
383 | UINT64 ArFpsr;\r | |
384 | \r | |
385 | UINT64 ArPfs;\r | |
386 | UINT64 ArLc;\r | |
387 | UINT64 ArEc;\r | |
388 | \r | |
389 | //\r | |
390 | // control registers\r | |
391 | //\r | |
392 | UINT64 CrDcr;\r | |
393 | UINT64 CrItm;\r | |
394 | UINT64 CrIva;\r | |
395 | UINT64 CrPta;\r | |
396 | UINT64 CrIpsr;\r | |
397 | UINT64 CrIsr;\r | |
398 | UINT64 CrIip;\r | |
399 | UINT64 CrIfa;\r | |
400 | UINT64 CrItir;\r | |
401 | UINT64 CrIipa;\r | |
402 | UINT64 CrIfs;\r | |
403 | UINT64 CrIim;\r | |
404 | UINT64 CrIha;\r | |
405 | \r | |
406 | //\r | |
407 | // debug registers\r | |
408 | //\r | |
409 | UINT64 Dbr0;\r | |
410 | UINT64 Dbr1;\r | |
411 | UINT64 Dbr2;\r | |
412 | UINT64 Dbr3;\r | |
413 | UINT64 Dbr4;\r | |
414 | UINT64 Dbr5;\r | |
415 | UINT64 Dbr6;\r | |
416 | UINT64 Dbr7;\r | |
417 | \r | |
418 | UINT64 Ibr0;\r | |
419 | UINT64 Ibr1;\r | |
420 | UINT64 Ibr2;\r | |
421 | UINT64 Ibr3;\r | |
422 | UINT64 Ibr4;\r | |
423 | UINT64 Ibr5;\r | |
424 | UINT64 Ibr6;\r | |
425 | UINT64 Ibr7;\r | |
426 | \r | |
427 | //\r | |
428 | // virtual registers - nat bits for R1-R31\r | |
429 | //\r | |
430 | UINT64 IntNat;\r | |
431 | \r | |
432 | } EFI_SYSTEM_CONTEXT_IPF;\r | |
433 | \r | |
9319d2c2 | 434 | ///\r |
af2dc6a7 | 435 | /// EBC processor exception types.\r |
9319d2c2 | 436 | ///\r |
d1f95000 | 437 | #define EXCEPT_EBC_UNDEFINED 0\r |
438 | #define EXCEPT_EBC_DIVIDE_ERROR 1\r | |
439 | #define EXCEPT_EBC_DEBUG 2\r | |
440 | #define EXCEPT_EBC_BREAKPOINT 3\r | |
441 | #define EXCEPT_EBC_OVERFLOW 4\r | |
af2dc6a7 | 442 | #define EXCEPT_EBC_INVALID_OPCODE 5 ///< Opcode out of range.\r |
d1f95000 | 443 | #define EXCEPT_EBC_STACK_FAULT 6\r |
444 | #define EXCEPT_EBC_ALIGNMENT_CHECK 7\r | |
af2dc6a7 | 445 | #define EXCEPT_EBC_INSTRUCTION_ENCODING 8 ///< Malformed instruction.\r |
446 | #define EXCEPT_EBC_BAD_BREAK 9 ///< BREAK 0 or undefined BREAK.\r | |
447 | #define EXCEPT_EBC_STEP 10 ///< To support debug stepping.\r | |
99e8ed21 | 448 | ///\r |
449 | /// For coding convenience, define the maximum valid EBC exception.\r | |
450 | ///\r | |
d1f95000 | 451 | #define MAX_EBC_EXCEPTION EXCEPT_EBC_STEP\r |
452 | \r | |
99e8ed21 | 453 | ///\r |
af2dc6a7 | 454 | /// EBC processor context definition.\r |
99e8ed21 | 455 | ///\r |
d1f95000 | 456 | typedef struct {\r |
457 | UINT64 R0;\r | |
458 | UINT64 R1;\r | |
459 | UINT64 R2;\r | |
460 | UINT64 R3;\r | |
461 | UINT64 R4;\r | |
462 | UINT64 R5;\r | |
463 | UINT64 R6;\r | |
464 | UINT64 R7;\r | |
465 | UINT64 Flags;\r | |
466 | UINT64 ControlFlags;\r | |
467 | UINT64 Ip;\r | |
468 | } EFI_SYSTEM_CONTEXT_EBC;\r | |
469 | \r | |
ebd04fc2 | 470 | \r |
471 | \r | |
472 | ///\r | |
af2dc6a7 | 473 | /// ARM processor exception types.\r |
ebd04fc2 | 474 | ///\r |
475 | #define EXCEPT_ARM_RESET 0\r | |
476 | #define EXCEPT_ARM_UNDEFINED_INSTRUCTION 1\r | |
477 | #define EXCEPT_ARM_SOFTWARE_INTERRUPT 2\r | |
478 | #define EXCEPT_ARM_PREFETCH_ABORT 3\r | |
479 | #define EXCEPT_ARM_DATA_ABORT 4\r | |
480 | #define EXCEPT_ARM_RESERVED 5\r | |
481 | #define EXCEPT_ARM_IRQ 6\r | |
482 | #define EXCEPT_ARM_FIQ 7\r | |
483 | \r | |
484 | ///\r | |
485 | /// For coding convenience, define the maximum valid ARM exception.\r | |
486 | ///\r | |
487 | #define MAX_ARM_EXCEPTION EXCEPT_ARM_FIQ\r | |
488 | \r | |
489 | ///\r | |
af2dc6a7 | 490 | /// ARM processor context definition.\r |
ebd04fc2 | 491 | ///\r |
492 | typedef struct {\r | |
493 | UINT32 R0;\r | |
494 | UINT32 R1;\r | |
495 | UINT32 R2;\r | |
496 | UINT32 R3;\r | |
497 | UINT32 R4;\r | |
498 | UINT32 R5;\r | |
499 | UINT32 R6;\r | |
500 | UINT32 R7;\r | |
501 | UINT32 R8;\r | |
502 | UINT32 R9;\r | |
503 | UINT32 R10;\r | |
504 | UINT32 R11;\r | |
505 | UINT32 R12;\r | |
506 | UINT32 SP;\r | |
507 | UINT32 LR;\r | |
508 | UINT32 PC;\r | |
509 | UINT32 CPSR;\r | |
510 | UINT32 DFSR;\r | |
511 | UINT32 DFAR;\r | |
512 | UINT32 IFSR;\r | |
513 | UINT32 IFAR;\r | |
514 | } EFI_SYSTEM_CONTEXT_ARM;\r | |
515 | \r | |
b4319afb HL |
516 | \r |
517 | ///\r | |
518 | /// AARCH64 processor exception types.\r | |
519 | ///\r | |
520 | #define EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS 0\r | |
521 | #define EXCEPT_AARCH64_IRQ 1\r | |
522 | #define EXCEPT_AARCH64_FIQ 2\r | |
523 | #define EXCEPT_AARCH64_SERROR 3\r | |
524 | \r | |
525 | ///\r | |
526 | /// For coding convenience, define the maximum valid ARM exception.\r | |
527 | ///\r | |
528 | #define MAX_AARCH64_EXCEPTION EXCEPT_AARCH64_SERROR\r | |
529 | \r | |
530 | typedef struct {\r | |
531 | // General Purpose Registers\r | |
532 | UINT64 X0;\r | |
533 | UINT64 X1;\r | |
534 | UINT64 X2;\r | |
535 | UINT64 X3;\r | |
536 | UINT64 X4;\r | |
537 | UINT64 X5;\r | |
538 | UINT64 X6;\r | |
539 | UINT64 X7;\r | |
540 | UINT64 X8;\r | |
541 | UINT64 X9;\r | |
542 | UINT64 X10;\r | |
543 | UINT64 X11;\r | |
544 | UINT64 X12;\r | |
545 | UINT64 X13;\r | |
546 | UINT64 X14;\r | |
547 | UINT64 X15;\r | |
548 | UINT64 X16;\r | |
549 | UINT64 X17;\r | |
550 | UINT64 X18;\r | |
551 | UINT64 X19;\r | |
552 | UINT64 X20;\r | |
553 | UINT64 X21;\r | |
554 | UINT64 X22;\r | |
555 | UINT64 X23;\r | |
556 | UINT64 X24;\r | |
557 | UINT64 X25;\r | |
558 | UINT64 X26;\r | |
559 | UINT64 X27;\r | |
560 | UINT64 X28;\r | |
561 | UINT64 FP; // x29 - Frame pointer\r | |
562 | UINT64 LR; // x30 - Link Register\r | |
563 | UINT64 SP; // x31 - Stack pointer\r | |
564 | \r | |
565 | // FP/SIMD Registers\r | |
566 | UINT64 V0[2];\r | |
567 | UINT64 V1[2];\r | |
568 | UINT64 V2[2];\r | |
569 | UINT64 V3[2];\r | |
570 | UINT64 V4[2];\r | |
571 | UINT64 V5[2];\r | |
572 | UINT64 V6[2];\r | |
573 | UINT64 V7[2];\r | |
574 | UINT64 V8[2];\r | |
575 | UINT64 V9[2];\r | |
576 | UINT64 V10[2];\r | |
577 | UINT64 V11[2];\r | |
578 | UINT64 V12[2];\r | |
579 | UINT64 V13[2];\r | |
580 | UINT64 V14[2];\r | |
581 | UINT64 V15[2];\r | |
582 | UINT64 V16[2];\r | |
583 | UINT64 V17[2];\r | |
584 | UINT64 V18[2];\r | |
585 | UINT64 V19[2];\r | |
586 | UINT64 V20[2];\r | |
587 | UINT64 V21[2];\r | |
588 | UINT64 V22[2];\r | |
589 | UINT64 V23[2];\r | |
590 | UINT64 V24[2];\r | |
591 | UINT64 V25[2];\r | |
592 | UINT64 V26[2];\r | |
593 | UINT64 V27[2];\r | |
594 | UINT64 V28[2];\r | |
595 | UINT64 V29[2];\r | |
596 | UINT64 V30[2];\r | |
597 | UINT64 V31[2];\r | |
598 | \r | |
599 | UINT64 ELR; // Exception Link Register\r | |
600 | UINT64 SPSR; // Saved Processor Status Register\r | |
601 | UINT64 FPSR; // Floating Point Status Register\r | |
602 | UINT64 ESR; // Exception syndrome register\r | |
603 | UINT64 FAR; // Fault Address Register\r | |
604 | } EFI_SYSTEM_CONTEXT_AARCH64;\r | |
605 | \r | |
606 | \r | |
ebd04fc2 | 607 | ///\r |
af2dc6a7 | 608 | /// Universal EFI_SYSTEM_CONTEXT definition.\r |
ebd04fc2 | 609 | ///\r |
d1f95000 | 610 | typedef union {\r |
611 | EFI_SYSTEM_CONTEXT_EBC *SystemContextEbc;\r | |
612 | EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32;\r | |
613 | EFI_SYSTEM_CONTEXT_X64 *SystemContextX64;\r | |
614 | EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;\r | |
ebd04fc2 | 615 | EFI_SYSTEM_CONTEXT_ARM *SystemContextArm;\r |
b4319afb | 616 | EFI_SYSTEM_CONTEXT_AARCH64 *SystemContextAArch64;\r |
d1f95000 | 617 | } EFI_SYSTEM_CONTEXT;\r |
618 | \r | |
619 | //\r | |
620 | // DebugSupport callback function prototypes\r | |
621 | //\r | |
622 | \r | |
9095d37b | 623 | /**\r |
d1f95000 | 624 | Registers and enables an exception callback function for the specified exception.\r |
9095d37b | 625 | \r |
af2dc6a7 | 626 | @param ExceptionType Exception types in EBC, IA-32, x64, or IPF.\r |
d1f95000 | 627 | @param SystemContext Exception content.\r |
9095d37b | 628 | \r |
d1f95000 | 629 | **/\r |
630 | typedef\r | |
631 | VOID\r | |
6d3ea23f | 632 | (EFIAPI *EFI_EXCEPTION_CALLBACK)(\r |
d1f95000 | 633 | IN EFI_EXCEPTION_TYPE ExceptionType,\r |
634 | IN OUT EFI_SYSTEM_CONTEXT SystemContext\r | |
635 | );\r | |
636 | \r | |
9095d37b | 637 | /**\r |
d1f95000 | 638 | Registers and enables the on-target debug agent's periodic entry point.\r |
9095d37b | 639 | \r |
d1f95000 | 640 | @param SystemContext Exception content.\r |
9095d37b | 641 | \r |
d1f95000 | 642 | **/\r |
643 | typedef\r | |
644 | VOID\r | |
6d3ea23f | 645 | (EFIAPI *EFI_PERIODIC_CALLBACK)(\r |
d1f95000 | 646 | IN OUT EFI_SYSTEM_CONTEXT SystemContext\r |
647 | );\r | |
648 | \r | |
8b6c989b | 649 | ///\r |
650 | /// Machine type definition\r | |
651 | ///\r | |
d1f95000 | 652 | typedef enum {\r |
05e3c7cc | 653 | IsaIa32 = IMAGE_FILE_MACHINE_I386, ///< 0x014C\r |
654 | IsaX64 = IMAGE_FILE_MACHINE_X64, ///< 0x8664\r | |
655 | IsaIpf = IMAGE_FILE_MACHINE_IA64, ///< 0x0200\r | |
ebd04fc2 | 656 | IsaEbc = IMAGE_FILE_MACHINE_EBC, ///< 0x0EBC\r |
b4319afb HL |
657 | IsaArm = IMAGE_FILE_MACHINE_ARMTHUMB_MIXED, ///< 0x01c2\r |
658 | IsaAArch64 = IMAGE_FILE_MACHINE_ARM64 ///< 0xAA64\r | |
d1f95000 | 659 | } EFI_INSTRUCTION_SET_ARCHITECTURE;\r |
660 | \r | |
661 | \r | |
662 | //\r | |
663 | // DebugSupport member function definitions\r | |
664 | //\r | |
665 | \r | |
9095d37b | 666 | /**\r |
d1f95000 | 667 | Returns the maximum value that may be used for the ProcessorIndex parameter in\r |
9095d37b LG |
668 | RegisterPeriodicCallback() and RegisterExceptionCallback().\r |
669 | \r | |
d1f95000 | 670 | @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r |
671 | @param MaxProcessorIndex Pointer to a caller-allocated UINTN in which the maximum supported\r | |
9095d37b LG |
672 | processor index is returned.\r |
673 | \r | |
674 | @retval EFI_SUCCESS The function completed successfully.\r | |
675 | \r | |
d1f95000 | 676 | **/\r |
677 | typedef\r | |
678 | EFI_STATUS\r | |
8b13229b | 679 | (EFIAPI *EFI_GET_MAXIMUM_PROCESSOR_INDEX)(\r |
d1f95000 | 680 | IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r |
681 | OUT UINTN *MaxProcessorIndex\r | |
682 | );\r | |
683 | \r | |
9095d37b | 684 | /**\r |
d1f95000 | 685 | Registers a function to be called back periodically in interrupt context.\r |
9095d37b | 686 | \r |
d1f95000 | 687 | @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r |
688 | @param ProcessorIndex Specifies which processor the callback function applies to.\r | |
689 | @param PeriodicCallback A pointer to a function of type PERIODIC_CALLBACK that is the main\r | |
690 | periodic entry point of the debug agent.\r | |
9095d37b LG |
691 | \r |
692 | @retval EFI_SUCCESS The function completed successfully.\r | |
d1f95000 | 693 | @retval EFI_ALREADY_STARTED Non-NULL PeriodicCallback parameter when a callback\r |
9095d37b LG |
694 | function was previously registered.\r |
695 | @retval EFI_OUT_OF_RESOURCES System has insufficient memory resources to register new callback\r | |
696 | function.\r | |
697 | \r | |
d1f95000 | 698 | **/\r |
699 | typedef\r | |
700 | EFI_STATUS\r | |
8b13229b | 701 | (EFIAPI *EFI_REGISTER_PERIODIC_CALLBACK)(\r |
d1f95000 | 702 | IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r |
703 | IN UINTN ProcessorIndex,\r | |
704 | IN EFI_PERIODIC_CALLBACK PeriodicCallback\r | |
705 | );\r | |
706 | \r | |
9095d37b | 707 | /**\r |
d1f95000 | 708 | Registers a function to be called when a given processor exception occurs.\r |
9095d37b | 709 | \r |
d1f95000 | 710 | @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r |
711 | @param ProcessorIndex Specifies which processor the callback function applies to.\r | |
89df7f9d | 712 | @param ExceptionCallback A pointer to a function of type EXCEPTION_CALLBACK that is called\r |
9095d37b LG |
713 | when the processor exception specified by ExceptionType occurs.\r |
714 | @param ExceptionType Specifies which processor exception to hook.\r | |
715 | \r | |
716 | @retval EFI_SUCCESS The function completed successfully.\r | |
d1f95000 | 717 | @retval EFI_ALREADY_STARTED Non-NULL PeriodicCallback parameter when a callback\r |
9095d37b LG |
718 | function was previously registered.\r |
719 | @retval EFI_OUT_OF_RESOURCES System has insufficient memory resources to register new callback\r | |
720 | function.\r | |
721 | \r | |
d1f95000 | 722 | **/\r |
723 | typedef\r | |
724 | EFI_STATUS\r | |
8b13229b | 725 | (EFIAPI *EFI_REGISTER_EXCEPTION_CALLBACK)(\r |
d1f95000 | 726 | IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r |
727 | IN UINTN ProcessorIndex,\r | |
728 | IN EFI_EXCEPTION_CALLBACK ExceptionCallback,\r | |
729 | IN EFI_EXCEPTION_TYPE ExceptionType\r | |
730 | );\r | |
731 | \r | |
9095d37b | 732 | /**\r |
d1f95000 | 733 | Invalidates processor instruction cache for a memory range. Subsequent execution in this range\r |
9095d37b LG |
734 | causes a fresh memory fetch to retrieve code to be executed.\r |
735 | \r | |
d1f95000 | 736 | @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.\r |
737 | @param ProcessorIndex Specifies which processor's instruction cache is to be invalidated.\r | |
9095d37b | 738 | @param Start Specifies the physical base of the memory range to be invalidated.\r |
d1f95000 | 739 | @param Length Specifies the minimum number of bytes in the processor's instruction\r |
9095d37b LG |
740 | cache to invalidate.\r |
741 | \r | |
742 | @retval EFI_SUCCESS The function completed successfully.\r | |
743 | \r | |
d1f95000 | 744 | **/\r |
745 | typedef\r | |
746 | EFI_STATUS\r | |
8b13229b | 747 | (EFIAPI *EFI_INVALIDATE_INSTRUCTION_CACHE)(\r |
d1f95000 | 748 | IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r |
749 | IN UINTN ProcessorIndex,\r | |
750 | IN VOID *Start,\r | |
751 | IN UINT64 Length\r | |
752 | );\r | |
753 | \r | |
44717a39 | 754 | ///\r |
9095d37b LG |
755 | /// This protocol provides the services to allow the debug agent to register\r |
756 | /// callback functions that are called either periodically or when specific\r | |
44717a39 | 757 | /// processor exceptions occur.\r |
758 | ///\r | |
d1f95000 | 759 | struct _EFI_DEBUG_SUPPORT_PROTOCOL {\r |
44717a39 | 760 | ///\r |
761 | /// Declares the processor architecture for this instance of the EFI Debug Support protocol.\r | |
762 | ///\r | |
d1f95000 | 763 | EFI_INSTRUCTION_SET_ARCHITECTURE Isa;\r |
764 | EFI_GET_MAXIMUM_PROCESSOR_INDEX GetMaximumProcessorIndex;\r | |
765 | EFI_REGISTER_PERIODIC_CALLBACK RegisterPeriodicCallback;\r | |
766 | EFI_REGISTER_EXCEPTION_CALLBACK RegisterExceptionCallback;\r | |
767 | EFI_INVALIDATE_INSTRUCTION_CACHE InvalidateInstructionCache;\r | |
768 | };\r | |
769 | \r | |
770 | extern EFI_GUID gEfiDebugSupportProtocolGuid;\r | |
771 | \r | |
9095d37b | 772 | #endif\r |