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1 | /** @file\r |
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2 | PCI Library functions that use the 256 MB PCI Express MMIO window to perform PCI\r |
| 3 | Configuration cycles. Layers on PCI Express Library.\r |
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4 | \r |
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5 | Copyright (c) 2006 - 2008, Intel Corporation<BR>\r |
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6 | All rights reserved. This program and the accompanying materials\r |
| 7 | are licensed and made available under the terms and conditions of the BSD License\r |
| 8 | which accompanies this distribution. The full text of the license may be found at\r |
| 9 | http://opensource.org/licenses/bsd-license.php\r |
| 10 | \r |
| 11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| 13 | \r |
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14 | **/\r |
| 15 | \r |
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16 | \r |
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17 | #include <Base.h>\r |
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18 | \r |
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19 | #include <Library/PciLib.h>\r |
| 20 | #include <Library/PciExpressLib.h>\r |
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21 | \r |
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22 | /**\r |
| 23 | Register a PCI device so PCI configuration registers may be accessed after \r |
| 24 | SetVirtualAddressMap().\r |
| 25 | \r |
| 26 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 27 | \r |
| 28 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 29 | Register.\r |
| 30 | \r |
| 31 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r |
| 32 | @retval RETURN_UNSUPPORTED An attempt was made to call this function \r |
| 33 | after ExitBootServices().\r |
| 34 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r |
| 35 | at runtime could not be mapped.\r |
| 36 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r |
| 37 | complete the registration.\r |
| 38 | \r |
| 39 | **/\r |
| 40 | RETURN_STATUS\r |
| 41 | EFIAPI\r |
| 42 | PciRegisterForRuntimeAccess (\r |
| 43 | IN UINTN Address\r |
| 44 | )\r |
| 45 | {\r |
| 46 | return PciExpressRegisterForRuntimeAccess (Address);\r |
| 47 | }\r |
| 48 | \r |
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49 | /**\r |
| 50 | Reads an 8-bit PCI configuration register.\r |
| 51 | \r |
| 52 | Reads and returns the 8-bit PCI configuration register specified by Address.\r |
| 53 | This function must guarantee that all PCI read and write operations are\r |
| 54 | serialized.\r |
| 55 | \r |
| 56 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 57 | \r |
| 58 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 59 | Register.\r |
| 60 | \r |
| 61 | @return The read value from the PCI configuration register.\r |
| 62 | \r |
| 63 | **/\r |
| 64 | UINT8\r |
| 65 | EFIAPI\r |
| 66 | PciRead8 (\r |
| 67 | IN UINTN Address\r |
| 68 | )\r |
| 69 | {\r |
| 70 | return PciExpressRead8 (Address);\r |
| 71 | }\r |
| 72 | \r |
| 73 | /**\r |
| 74 | Writes an 8-bit PCI configuration register.\r |
| 75 | \r |
| 76 | Writes the 8-bit PCI configuration register specified by Address with the\r |
| 77 | value specified by Value. Value is returned. This function must guarantee\r |
| 78 | that all PCI read and write operations are serialized.\r |
| 79 | \r |
| 80 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 81 | \r |
| 82 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 83 | Register.\r |
| 7612cbf0 |
84 | @param Value The value to write.\r |
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85 | \r |
| 86 | @return The value written to the PCI configuration register.\r |
| 87 | \r |
| 88 | **/\r |
| 89 | UINT8\r |
| 90 | EFIAPI\r |
| 91 | PciWrite8 (\r |
| 92 | IN UINTN Address,\r |
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93 | IN UINT8 Value\r |
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94 | )\r |
| 95 | {\r |
| 94646ec0 |
96 | return PciExpressWrite8 (Address, Value);\r |
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97 | }\r |
| 98 | \r |
| 99 | /**\r |
| 100 | Performs a bitwise inclusive OR of an 8-bit PCI configuration register with\r |
| 101 | an 8-bit value.\r |
| 102 | \r |
| 103 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 104 | bitwise inclusive OR between the read result and the value specified by\r |
| 105 | OrData, and writes the result to the 8-bit PCI configuration register\r |
| 106 | specified by Address. The value written to the PCI configuration register is\r |
| 107 | returned. This function must guarantee that all PCI read and write operations\r |
| 108 | are serialized.\r |
| 109 | \r |
| 110 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 111 | \r |
| 112 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 113 | Register.\r |
| 114 | @param OrData The value to OR with the PCI configuration register.\r |
| 115 | \r |
| 116 | @return The value written back to the PCI configuration register.\r |
| 117 | \r |
| 118 | **/\r |
| 119 | UINT8\r |
| 120 | EFIAPI\r |
| 121 | PciOr8 (\r |
| 122 | IN UINTN Address,\r |
| 123 | IN UINT8 OrData\r |
| 124 | )\r |
| 125 | {\r |
| 126 | return PciExpressOr8 (Address, OrData);\r |
| 127 | }\r |
| 128 | \r |
| 129 | /**\r |
| 130 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r |
| 131 | value.\r |
| 132 | \r |
| 133 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 134 | bitwise AND between the read result and the value specified by AndData, and\r |
| 135 | writes the result to the 8-bit PCI configuration register specified by\r |
| 136 | Address. The value written to the PCI configuration register is returned.\r |
| 137 | This function must guarantee that all PCI read and write operations are\r |
| 138 | serialized.\r |
| 139 | \r |
| 140 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 141 | \r |
| 142 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 143 | Register.\r |
| 144 | @param AndData The value to AND with the PCI configuration register.\r |
| 145 | \r |
| 146 | @return The value written back to the PCI configuration register.\r |
| 147 | \r |
| 148 | **/\r |
| 149 | UINT8\r |
| 150 | EFIAPI\r |
| 151 | PciAnd8 (\r |
| 152 | IN UINTN Address,\r |
| 153 | IN UINT8 AndData\r |
| 154 | )\r |
| 155 | {\r |
| 156 | return PciExpressAnd8 (Address, AndData);\r |
| 157 | }\r |
| 158 | \r |
| 159 | /**\r |
| 160 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r |
| 161 | value, followed a bitwise inclusive OR with another 8-bit value.\r |
| 162 | \r |
| 163 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 164 | bitwise AND between the read result and the value specified by AndData,\r |
| 165 | performs a bitwise inclusive OR between the result of the AND operation and\r |
| 166 | the value specified by OrData, and writes the result to the 8-bit PCI\r |
| 167 | configuration register specified by Address. The value written to the PCI\r |
| 168 | configuration register is returned. This function must guarantee that all PCI\r |
| 169 | read and write operations are serialized.\r |
| 170 | \r |
| 171 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 172 | \r |
| 173 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 174 | Register.\r |
| 175 | @param AndData The value to AND with the PCI configuration register.\r |
| 176 | @param OrData The value to OR with the result of the AND operation.\r |
| 177 | \r |
| 178 | @return The value written back to the PCI configuration register.\r |
| 179 | \r |
| 180 | **/\r |
| 181 | UINT8\r |
| 182 | EFIAPI\r |
| 183 | PciAndThenOr8 (\r |
| 184 | IN UINTN Address,\r |
| 185 | IN UINT8 AndData,\r |
| 186 | IN UINT8 OrData\r |
| 187 | )\r |
| 188 | {\r |
| 189 | return PciExpressAndThenOr8 (Address, AndData, OrData);\r |
| 190 | }\r |
| 191 | \r |
| 192 | /**\r |
| 193 | Reads a bit field of a PCI configuration register.\r |
| 194 | \r |
| 195 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r |
| 196 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 197 | returned.\r |
| 198 | \r |
| 199 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 200 | If StartBit is greater than 7, then ASSERT().\r |
| 201 | If EndBit is greater than 7, then ASSERT().\r |
| 202 | If EndBit is less than StartBit, then ASSERT().\r |
| 203 | \r |
| 204 | @param Address PCI configuration register to read.\r |
| 205 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 206 | Range 0..7.\r |
| 207 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 208 | Range 0..7.\r |
| 209 | \r |
| 210 | @return The value of the bit field read from the PCI configuration register.\r |
| 211 | \r |
| 212 | **/\r |
| 213 | UINT8\r |
| 214 | EFIAPI\r |
| 215 | PciBitFieldRead8 (\r |
| 216 | IN UINTN Address,\r |
| 217 | IN UINTN StartBit,\r |
| 218 | IN UINTN EndBit\r |
| 219 | )\r |
| 220 | {\r |
| 221 | return PciExpressBitFieldRead8 (Address, StartBit, EndBit);\r |
| 222 | }\r |
| 223 | \r |
| 224 | /**\r |
| 225 | Writes a bit field to a PCI configuration register.\r |
| 226 | \r |
| 227 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 228 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 229 | destination PCI configuration register are preserved. The new value of the\r |
| 230 | 8-bit register is returned.\r |
| 231 | \r |
| 232 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 233 | If StartBit is greater than 7, then ASSERT().\r |
| 234 | If EndBit is greater than 7, then ASSERT().\r |
| 235 | If EndBit is less than StartBit, then ASSERT().\r |
| 236 | \r |
| 237 | @param Address PCI configuration register to write.\r |
| 238 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 239 | Range 0..7.\r |
| 240 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 241 | Range 0..7.\r |
| 242 | @param Value New value of the bit field.\r |
| 243 | \r |
| 244 | @return The value written back to the PCI configuration register.\r |
| 245 | \r |
| 246 | **/\r |
| 247 | UINT8\r |
| 248 | EFIAPI\r |
| 249 | PciBitFieldWrite8 (\r |
| 250 | IN UINTN Address,\r |
| 251 | IN UINTN StartBit,\r |
| 252 | IN UINTN EndBit,\r |
| 253 | IN UINT8 Value\r |
| 254 | )\r |
| 255 | {\r |
| 256 | return PciExpressBitFieldWrite8 (Address, StartBit, EndBit, Value);\r |
| 257 | }\r |
| 258 | \r |
| 259 | /**\r |
| 260 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r |
| 261 | writes the result back to the bit field in the 8-bit port.\r |
| 262 | \r |
| 263 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 264 | bitwise inclusive OR between the read result and the value specified by\r |
| 265 | OrData, and writes the result to the 8-bit PCI configuration register\r |
| 266 | specified by Address. The value written to the PCI configuration register is\r |
| 267 | returned. This function must guarantee that all PCI read and write operations\r |
| 268 | are serialized. Extra left bits in OrData are stripped.\r |
| 269 | \r |
| 270 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 271 | If StartBit is greater than 7, then ASSERT().\r |
| 272 | If EndBit is greater than 7, then ASSERT().\r |
| 273 | If EndBit is less than StartBit, then ASSERT().\r |
| 274 | \r |
| 275 | @param Address PCI configuration register to write.\r |
| 276 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 277 | Range 0..7.\r |
| 278 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 279 | Range 0..7.\r |
| 280 | @param OrData The value to OR with the PCI configuration register.\r |
| 281 | \r |
| 282 | @return The value written back to the PCI configuration register.\r |
| 283 | \r |
| 284 | **/\r |
| 285 | UINT8\r |
| 286 | EFIAPI\r |
| 287 | PciBitFieldOr8 (\r |
| 288 | IN UINTN Address,\r |
| 289 | IN UINTN StartBit,\r |
| 290 | IN UINTN EndBit,\r |
| 291 | IN UINT8 OrData\r |
| 292 | )\r |
| 293 | {\r |
| 294 | return PciExpressBitFieldOr8 (Address, StartBit, EndBit, OrData);\r |
| 295 | }\r |
| 296 | \r |
| 297 | /**\r |
| 298 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r |
| 299 | AND, and writes the result back to the bit field in the 8-bit register.\r |
| 300 | \r |
| 301 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 302 | bitwise AND between the read result and the value specified by AndData, and\r |
| 303 | writes the result to the 8-bit PCI configuration register specified by\r |
| 304 | Address. The value written to the PCI configuration register is returned.\r |
| 305 | This function must guarantee that all PCI read and write operations are\r |
| 306 | serialized. Extra left bits in AndData are stripped.\r |
| 307 | \r |
| 308 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 309 | If StartBit is greater than 7, then ASSERT().\r |
| 310 | If EndBit is greater than 7, then ASSERT().\r |
| 311 | If EndBit is less than StartBit, then ASSERT().\r |
| 312 | \r |
| 313 | @param Address PCI configuration register to write.\r |
| 314 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 315 | Range 0..7.\r |
| 316 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 317 | Range 0..7.\r |
| 318 | @param AndData The value to AND with the PCI configuration register.\r |
| 319 | \r |
| 320 | @return The value written back to the PCI configuration register.\r |
| 321 | \r |
| 322 | **/\r |
| 323 | UINT8\r |
| 324 | EFIAPI\r |
| 325 | PciBitFieldAnd8 (\r |
| 326 | IN UINTN Address,\r |
| 327 | IN UINTN StartBit,\r |
| 328 | IN UINTN EndBit,\r |
| 329 | IN UINT8 AndData\r |
| 330 | )\r |
| 331 | {\r |
| 332 | return PciExpressBitFieldAnd8 (Address, StartBit, EndBit, AndData);\r |
| 333 | }\r |
| 334 | \r |
| 335 | /**\r |
| 336 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r |
| 337 | bitwise inclusive OR, and writes the result back to the bit field in the\r |
| 338 | 8-bit port.\r |
| 339 | \r |
| 340 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 341 | bitwise AND followed by a bitwise inclusive OR between the read result and\r |
| 342 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
| 343 | configuration register specified by Address. The value written to the PCI\r |
| 344 | configuration register is returned. This function must guarantee that all PCI\r |
| 345 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 346 | OrData are stripped.\r |
| 347 | \r |
| 348 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 349 | If StartBit is greater than 7, then ASSERT().\r |
| 350 | If EndBit is greater than 7, then ASSERT().\r |
| 351 | If EndBit is less than StartBit, then ASSERT().\r |
| 352 | \r |
| 353 | @param Address PCI configuration register to write.\r |
| 354 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 355 | Range 0..7.\r |
| 356 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 357 | Range 0..7.\r |
| 358 | @param AndData The value to AND with the PCI configuration register.\r |
| 359 | @param OrData The value to OR with the result of the AND operation.\r |
| 360 | \r |
| 361 | @return The value written back to the PCI configuration register.\r |
| 362 | \r |
| 363 | **/\r |
| 364 | UINT8\r |
| 365 | EFIAPI\r |
| 366 | PciBitFieldAndThenOr8 (\r |
| 367 | IN UINTN Address,\r |
| 368 | IN UINTN StartBit,\r |
| 369 | IN UINTN EndBit,\r |
| 370 | IN UINT8 AndData,\r |
| 371 | IN UINT8 OrData\r |
| 372 | )\r |
| 373 | {\r |
| 374 | return PciExpressBitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData);\r |
| 375 | }\r |
| 376 | \r |
| 377 | /**\r |
| 378 | Reads a 16-bit PCI configuration register.\r |
| 379 | \r |
| 380 | Reads and returns the 16-bit PCI configuration register specified by Address.\r |
| 381 | This function must guarantee that all PCI read and write operations are\r |
| 382 | serialized.\r |
| 383 | \r |
| 384 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 385 | \r |
| 386 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 387 | Register.\r |
| 388 | \r |
| 389 | @return The read value from the PCI configuration register.\r |
| 390 | \r |
| 391 | **/\r |
| 392 | UINT16\r |
| 393 | EFIAPI\r |
| 394 | PciRead16 (\r |
| 395 | IN UINTN Address\r |
| 396 | )\r |
| 397 | {\r |
| 398 | return PciExpressRead16 (Address);\r |
| 399 | }\r |
| 400 | \r |
| 401 | /**\r |
| 402 | Writes a 16-bit PCI configuration register.\r |
| 403 | \r |
| 404 | Writes the 16-bit PCI configuration register specified by Address with the\r |
| 405 | value specified by Value. Value is returned. This function must guarantee\r |
| 406 | that all PCI read and write operations are serialized.\r |
| 407 | \r |
| 408 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 409 | \r |
| 410 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 411 | Register.\r |
| 7612cbf0 |
412 | @param Value The value to write.\r |
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413 | \r |
| 414 | @return The value written to the PCI configuration register.\r |
| 415 | \r |
| 416 | **/\r |
| 417 | UINT16\r |
| 418 | EFIAPI\r |
| 419 | PciWrite16 (\r |
| 420 | IN UINTN Address,\r |
| 94646ec0 |
421 | IN UINT16 Value\r |
| e1f414b6 |
422 | )\r |
| 423 | {\r |
| 94646ec0 |
424 | return PciExpressWrite16 (Address, Value);\r |
| e1f414b6 |
425 | }\r |
| 426 | \r |
| 427 | /**\r |
| 428 | Performs a bitwise inclusive OR of a 16-bit PCI configuration register with\r |
| 429 | a 16-bit value.\r |
| 430 | \r |
| 431 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 432 | bitwise inclusive OR between the read result and the value specified by\r |
| 433 | OrData, and writes the result to the 16-bit PCI configuration register\r |
| 434 | specified by Address. The value written to the PCI configuration register is\r |
| 435 | returned. This function must guarantee that all PCI read and write operations\r |
| 436 | are serialized.\r |
| 437 | \r |
| 438 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 439 | \r |
| 440 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 441 | Register.\r |
| 442 | @param OrData The value to OR with the PCI configuration register.\r |
| 443 | \r |
| 444 | @return The value written back to the PCI configuration register.\r |
| 445 | \r |
| 446 | **/\r |
| 447 | UINT16\r |
| 448 | EFIAPI\r |
| 449 | PciOr16 (\r |
| 450 | IN UINTN Address,\r |
| 451 | IN UINT16 OrData\r |
| 452 | )\r |
| 453 | {\r |
| 454 | return PciExpressOr16 (Address, OrData);\r |
| 455 | }\r |
| 456 | \r |
| 457 | /**\r |
| 458 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r |
| 459 | value.\r |
| 460 | \r |
| 461 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 462 | bitwise AND between the read result and the value specified by AndData, and\r |
| 463 | writes the result to the 16-bit PCI configuration register specified by\r |
| 464 | Address. The value written to the PCI configuration register is returned.\r |
| 465 | This function must guarantee that all PCI read and write operations are\r |
| 466 | serialized.\r |
| 467 | \r |
| 468 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 469 | \r |
| 470 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 471 | Register.\r |
| 472 | @param AndData The value to AND with the PCI configuration register.\r |
| 473 | \r |
| 474 | @return The value written back to the PCI configuration register.\r |
| 475 | \r |
| 476 | **/\r |
| 477 | UINT16\r |
| 478 | EFIAPI\r |
| 479 | PciAnd16 (\r |
| 480 | IN UINTN Address,\r |
| 481 | IN UINT16 AndData\r |
| 482 | )\r |
| 483 | {\r |
| 484 | return PciExpressAnd16 (Address, AndData);\r |
| 485 | }\r |
| 486 | \r |
| 487 | /**\r |
| 488 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r |
| 489 | value, followed a bitwise inclusive OR with another 16-bit value.\r |
| 490 | \r |
| 491 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 492 | bitwise AND between the read result and the value specified by AndData,\r |
| 493 | performs a bitwise inclusive OR between the result of the AND operation and\r |
| 494 | the value specified by OrData, and writes the result to the 16-bit PCI\r |
| 495 | configuration register specified by Address. The value written to the PCI\r |
| 496 | configuration register is returned. This function must guarantee that all PCI\r |
| 497 | read and write operations are serialized.\r |
| 498 | \r |
| 499 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 500 | \r |
| 501 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 502 | Register.\r |
| 503 | @param AndData The value to AND with the PCI configuration register.\r |
| 504 | @param OrData The value to OR with the result of the AND operation.\r |
| 505 | \r |
| 506 | @return The value written back to the PCI configuration register.\r |
| 507 | \r |
| 508 | **/\r |
| 509 | UINT16\r |
| 510 | EFIAPI\r |
| 511 | PciAndThenOr16 (\r |
| 512 | IN UINTN Address,\r |
| 513 | IN UINT16 AndData,\r |
| 514 | IN UINT16 OrData\r |
| 515 | )\r |
| 516 | {\r |
| 517 | return PciExpressAndThenOr16 (Address, AndData, OrData);\r |
| 518 | }\r |
| 519 | \r |
| 520 | /**\r |
| 521 | Reads a bit field of a PCI configuration register.\r |
| 522 | \r |
| 523 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r |
| 524 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 525 | returned.\r |
| 526 | \r |
| 527 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 528 | If StartBit is greater than 15, then ASSERT().\r |
| 529 | If EndBit is greater than 15, then ASSERT().\r |
| 530 | If EndBit is less than StartBit, then ASSERT().\r |
| 531 | \r |
| 532 | @param Address PCI configuration register to read.\r |
| 533 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 534 | Range 0..15.\r |
| 535 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 536 | Range 0..15.\r |
| 537 | \r |
| 538 | @return The value of the bit field read from the PCI configuration register.\r |
| 539 | \r |
| 540 | **/\r |
| 541 | UINT16\r |
| 542 | EFIAPI\r |
| 543 | PciBitFieldRead16 (\r |
| 544 | IN UINTN Address,\r |
| 545 | IN UINTN StartBit,\r |
| 546 | IN UINTN EndBit\r |
| 547 | )\r |
| 548 | {\r |
| 549 | return PciExpressBitFieldRead16 (Address, StartBit, EndBit);\r |
| 550 | }\r |
| 551 | \r |
| 552 | /**\r |
| 553 | Writes a bit field to a PCI configuration register.\r |
| 554 | \r |
| 555 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 556 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 557 | destination PCI configuration register are preserved. The new value of the\r |
| 558 | 16-bit register is returned.\r |
| 559 | \r |
| 560 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 561 | If StartBit is greater than 15, then ASSERT().\r |
| 562 | If EndBit is greater than 15, then ASSERT().\r |
| 563 | If EndBit is less than StartBit, then ASSERT().\r |
| 564 | \r |
| 565 | @param Address PCI configuration register to write.\r |
| 566 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 567 | Range 0..15.\r |
| 568 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 569 | Range 0..15.\r |
| 570 | @param Value New value of the bit field.\r |
| 571 | \r |
| 572 | @return The value written back to the PCI configuration register.\r |
| 573 | \r |
| 574 | **/\r |
| 575 | UINT16\r |
| 576 | EFIAPI\r |
| 577 | PciBitFieldWrite16 (\r |
| 578 | IN UINTN Address,\r |
| 579 | IN UINTN StartBit,\r |
| 580 | IN UINTN EndBit,\r |
| 581 | IN UINT16 Value\r |
| 582 | )\r |
| 583 | {\r |
| 584 | return PciExpressBitFieldWrite16 (Address, StartBit, EndBit, Value);\r |
| 585 | }\r |
| 586 | \r |
| 587 | /**\r |
| 588 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r |
| 589 | writes the result back to the bit field in the 16-bit port.\r |
| 590 | \r |
| 591 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 592 | bitwise inclusive OR between the read result and the value specified by\r |
| 593 | OrData, and writes the result to the 16-bit PCI configuration register\r |
| 594 | specified by Address. The value written to the PCI configuration register is\r |
| 595 | returned. This function must guarantee that all PCI read and write operations\r |
| 596 | are serialized. Extra left bits in OrData are stripped.\r |
| 597 | \r |
| 598 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 599 | If StartBit is greater than 15, then ASSERT().\r |
| 600 | If EndBit is greater than 15, then ASSERT().\r |
| 601 | If EndBit is less than StartBit, then ASSERT().\r |
| 602 | \r |
| 603 | @param Address PCI configuration register to write.\r |
| 604 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 605 | Range 0..15.\r |
| 606 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 607 | Range 0..15.\r |
| 608 | @param OrData The value to OR with the PCI configuration register.\r |
| 609 | \r |
| 610 | @return The value written back to the PCI configuration register.\r |
| 611 | \r |
| 612 | **/\r |
| 613 | UINT16\r |
| 614 | EFIAPI\r |
| 615 | PciBitFieldOr16 (\r |
| 616 | IN UINTN Address,\r |
| 617 | IN UINTN StartBit,\r |
| 618 | IN UINTN EndBit,\r |
| 619 | IN UINT16 OrData\r |
| 620 | )\r |
| 621 | {\r |
| 622 | return PciExpressBitFieldOr16 (Address, StartBit, EndBit, OrData);\r |
| 623 | }\r |
| 624 | \r |
| 625 | /**\r |
| 626 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r |
| 627 | AND, and writes the result back to the bit field in the 16-bit register.\r |
| 628 | \r |
| 629 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 630 | bitwise AND between the read result and the value specified by AndData, and\r |
| 631 | writes the result to the 16-bit PCI configuration register specified by\r |
| 632 | Address. The value written to the PCI configuration register is returned.\r |
| 633 | This function must guarantee that all PCI read and write operations are\r |
| 634 | serialized. Extra left bits in AndData are stripped.\r |
| 635 | \r |
| 636 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 637 | If StartBit is greater than 15, then ASSERT().\r |
| 638 | If EndBit is greater than 15, then ASSERT().\r |
| 639 | If EndBit is less than StartBit, then ASSERT().\r |
| 640 | \r |
| 641 | @param Address PCI configuration register to write.\r |
| 642 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 643 | Range 0..15.\r |
| 644 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 645 | Range 0..15.\r |
| 646 | @param AndData The value to AND with the PCI configuration register.\r |
| 647 | \r |
| 648 | @return The value written back to the PCI configuration register.\r |
| 649 | \r |
| 650 | **/\r |
| 651 | UINT16\r |
| 652 | EFIAPI\r |
| 653 | PciBitFieldAnd16 (\r |
| 654 | IN UINTN Address,\r |
| 655 | IN UINTN StartBit,\r |
| 656 | IN UINTN EndBit,\r |
| 657 | IN UINT16 AndData\r |
| 658 | )\r |
| 659 | {\r |
| 660 | return PciExpressBitFieldAnd16 (Address, StartBit, EndBit, AndData);\r |
| 661 | }\r |
| 662 | \r |
| 663 | /**\r |
| 664 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r |
| 665 | bitwise inclusive OR, and writes the result back to the bit field in the\r |
| 666 | 16-bit port.\r |
| 667 | \r |
| 668 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 669 | bitwise AND followed by a bitwise inclusive OR between the read result and\r |
| 670 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
| 671 | configuration register specified by Address. The value written to the PCI\r |
| 672 | configuration register is returned. This function must guarantee that all PCI\r |
| 673 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 674 | OrData are stripped.\r |
| 675 | \r |
| 676 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 677 | If StartBit is greater than 15, then ASSERT().\r |
| 678 | If EndBit is greater than 15, then ASSERT().\r |
| 679 | If EndBit is less than StartBit, then ASSERT().\r |
| 680 | \r |
| 681 | @param Address PCI configuration register to write.\r |
| 682 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 683 | Range 0..15.\r |
| 684 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 685 | Range 0..15.\r |
| 686 | @param AndData The value to AND with the PCI configuration register.\r |
| 687 | @param OrData The value to OR with the result of the AND operation.\r |
| 688 | \r |
| 689 | @return The value written back to the PCI configuration register.\r |
| 690 | \r |
| 691 | **/\r |
| 692 | UINT16\r |
| 693 | EFIAPI\r |
| 694 | PciBitFieldAndThenOr16 (\r |
| 695 | IN UINTN Address,\r |
| 696 | IN UINTN StartBit,\r |
| 697 | IN UINTN EndBit,\r |
| 698 | IN UINT16 AndData,\r |
| 699 | IN UINT16 OrData\r |
| 700 | )\r |
| 701 | {\r |
| 702 | return PciExpressBitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData);\r |
| 703 | }\r |
| 704 | \r |
| 705 | /**\r |
| 706 | Reads a 32-bit PCI configuration register.\r |
| 707 | \r |
| 708 | Reads and returns the 32-bit PCI configuration register specified by Address.\r |
| 709 | This function must guarantee that all PCI read and write operations are\r |
| 710 | serialized.\r |
| 711 | \r |
| 712 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 713 | \r |
| 714 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 715 | Register.\r |
| 716 | \r |
| 717 | @return The read value from the PCI configuration register.\r |
| 718 | \r |
| 719 | **/\r |
| 720 | UINT32\r |
| 721 | EFIAPI\r |
| 722 | PciRead32 (\r |
| 723 | IN UINTN Address\r |
| 724 | )\r |
| 725 | {\r |
| 726 | return PciExpressRead32 (Address);\r |
| 727 | }\r |
| 728 | \r |
| 729 | /**\r |
| 730 | Writes a 32-bit PCI configuration register.\r |
| 731 | \r |
| 732 | Writes the 32-bit PCI configuration register specified by Address with the\r |
| 733 | value specified by Value. Value is returned. This function must guarantee\r |
| 734 | that all PCI read and write operations are serialized.\r |
| 735 | \r |
| 736 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 737 | \r |
| 738 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 739 | Register.\r |
| 7612cbf0 |
740 | @param Value The value to write.\r |
| e1f414b6 |
741 | \r |
| 742 | @return The value written to the PCI configuration register.\r |
| 743 | \r |
| 744 | **/\r |
| 745 | UINT32\r |
| 746 | EFIAPI\r |
| 747 | PciWrite32 (\r |
| 748 | IN UINTN Address,\r |
| 94646ec0 |
749 | IN UINT32 Value\r |
| e1f414b6 |
750 | )\r |
| 751 | {\r |
| 94646ec0 |
752 | return PciExpressWrite32 (Address, Value);\r |
| e1f414b6 |
753 | }\r |
| 754 | \r |
| 755 | /**\r |
| 756 | Performs a bitwise inclusive OR of a 32-bit PCI configuration register with\r |
| 757 | a 32-bit value.\r |
| 758 | \r |
| 759 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 760 | bitwise inclusive OR between the read result and the value specified by\r |
| 761 | OrData, and writes the result to the 32-bit PCI configuration register\r |
| 762 | specified by Address. The value written to the PCI configuration register is\r |
| 763 | returned. This function must guarantee that all PCI read and write operations\r |
| 764 | are serialized.\r |
| 765 | \r |
| 766 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 767 | \r |
| 768 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 769 | Register.\r |
| 770 | @param OrData The value to OR with the PCI configuration register.\r |
| 771 | \r |
| 772 | @return The value written back to the PCI configuration register.\r |
| 773 | \r |
| 774 | **/\r |
| 775 | UINT32\r |
| 776 | EFIAPI\r |
| 777 | PciOr32 (\r |
| 778 | IN UINTN Address,\r |
| 779 | IN UINT32 OrData\r |
| 780 | )\r |
| 781 | {\r |
| 782 | return PciExpressOr32 (Address, OrData);\r |
| 783 | }\r |
| 784 | \r |
| 785 | /**\r |
| 786 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r |
| 787 | value.\r |
| 788 | \r |
| 789 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 790 | bitwise AND between the read result and the value specified by AndData, and\r |
| 791 | writes the result to the 32-bit PCI configuration register specified by\r |
| 792 | Address. The value written to the PCI configuration register is returned.\r |
| 793 | This function must guarantee that all PCI read and write operations are\r |
| 794 | serialized.\r |
| 795 | \r |
| 796 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 797 | \r |
| 798 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 799 | Register.\r |
| 800 | @param AndData The value to AND with the PCI configuration register.\r |
| 801 | \r |
| 802 | @return The value written back to the PCI configuration register.\r |
| 803 | \r |
| 804 | **/\r |
| 805 | UINT32\r |
| 806 | EFIAPI\r |
| 807 | PciAnd32 (\r |
| 808 | IN UINTN Address,\r |
| 809 | IN UINT32 AndData\r |
| 810 | )\r |
| 811 | {\r |
| 812 | return PciExpressAnd32 (Address, AndData);\r |
| 813 | }\r |
| 814 | \r |
| 815 | /**\r |
| 816 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r |
| 817 | value, followed a bitwise inclusive OR with another 32-bit value.\r |
| 818 | \r |
| 819 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 820 | bitwise AND between the read result and the value specified by AndData,\r |
| 821 | performs a bitwise inclusive OR between the result of the AND operation and\r |
| 822 | the value specified by OrData, and writes the result to the 32-bit PCI\r |
| 823 | configuration register specified by Address. The value written to the PCI\r |
| 824 | configuration register is returned. This function must guarantee that all PCI\r |
| 825 | read and write operations are serialized.\r |
| 826 | \r |
| 827 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 828 | \r |
| 829 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 830 | Register.\r |
| 831 | @param AndData The value to AND with the PCI configuration register.\r |
| 832 | @param OrData The value to OR with the result of the AND operation.\r |
| 833 | \r |
| 834 | @return The value written back to the PCI configuration register.\r |
| 835 | \r |
| 836 | **/\r |
| 837 | UINT32\r |
| 838 | EFIAPI\r |
| 839 | PciAndThenOr32 (\r |
| 840 | IN UINTN Address,\r |
| 841 | IN UINT32 AndData,\r |
| 842 | IN UINT32 OrData\r |
| 843 | )\r |
| 844 | {\r |
| 845 | return PciExpressAndThenOr32 (Address, AndData, OrData);\r |
| 846 | }\r |
| 847 | \r |
| 848 | /**\r |
| 849 | Reads a bit field of a PCI configuration register.\r |
| 850 | \r |
| 851 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r |
| 852 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 853 | returned.\r |
| 854 | \r |
| 855 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 856 | If StartBit is greater than 31, then ASSERT().\r |
| 857 | If EndBit is greater than 31, then ASSERT().\r |
| 858 | If EndBit is less than StartBit, then ASSERT().\r |
| 859 | \r |
| 860 | @param Address PCI configuration register to read.\r |
| 861 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 862 | Range 0..31.\r |
| 863 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 864 | Range 0..31.\r |
| 865 | \r |
| 866 | @return The value of the bit field read from the PCI configuration register.\r |
| 867 | \r |
| 868 | **/\r |
| 869 | UINT32\r |
| 870 | EFIAPI\r |
| 871 | PciBitFieldRead32 (\r |
| 872 | IN UINTN Address,\r |
| 873 | IN UINTN StartBit,\r |
| 874 | IN UINTN EndBit\r |
| 875 | )\r |
| 876 | {\r |
| 877 | return PciExpressBitFieldRead32 (Address, StartBit, EndBit);\r |
| 878 | }\r |
| 879 | \r |
| 880 | /**\r |
| 881 | Writes a bit field to a PCI configuration register.\r |
| 882 | \r |
| 883 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 884 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 885 | destination PCI configuration register are preserved. The new value of the\r |
| 886 | 32-bit register is returned.\r |
| 887 | \r |
| 888 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 889 | If StartBit is greater than 31, then ASSERT().\r |
| 890 | If EndBit is greater than 31, then ASSERT().\r |
| 891 | If EndBit is less than StartBit, then ASSERT().\r |
| 892 | \r |
| 893 | @param Address PCI configuration register to write.\r |
| 894 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 895 | Range 0..31.\r |
| 896 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 897 | Range 0..31.\r |
| 898 | @param Value New value of the bit field.\r |
| 899 | \r |
| 900 | @return The value written back to the PCI configuration register.\r |
| 901 | \r |
| 902 | **/\r |
| 903 | UINT32\r |
| 904 | EFIAPI\r |
| 905 | PciBitFieldWrite32 (\r |
| 906 | IN UINTN Address,\r |
| 907 | IN UINTN StartBit,\r |
| 908 | IN UINTN EndBit,\r |
| 909 | IN UINT32 Value\r |
| 910 | )\r |
| 911 | {\r |
| 912 | return PciExpressBitFieldWrite32 (Address, StartBit, EndBit, Value);\r |
| 913 | }\r |
| 914 | \r |
| 915 | /**\r |
| 916 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r |
| 917 | writes the result back to the bit field in the 32-bit port.\r |
| 918 | \r |
| 919 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 920 | bitwise inclusive OR between the read result and the value specified by\r |
| 921 | OrData, and writes the result to the 32-bit PCI configuration register\r |
| 922 | specified by Address. The value written to the PCI configuration register is\r |
| 923 | returned. This function must guarantee that all PCI read and write operations\r |
| 924 | are serialized. Extra left bits in OrData are stripped.\r |
| 925 | \r |
| 926 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 927 | If StartBit is greater than 31, then ASSERT().\r |
| 928 | If EndBit is greater than 31, then ASSERT().\r |
| 929 | If EndBit is less than StartBit, then ASSERT().\r |
| 930 | \r |
| 931 | @param Address PCI configuration register to write.\r |
| 932 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 933 | Range 0..31.\r |
| 934 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 935 | Range 0..31.\r |
| 936 | @param OrData The value to OR with the PCI configuration register.\r |
| 937 | \r |
| 938 | @return The value written back to the PCI configuration register.\r |
| 939 | \r |
| 940 | **/\r |
| 941 | UINT32\r |
| 942 | EFIAPI\r |
| 943 | PciBitFieldOr32 (\r |
| 944 | IN UINTN Address,\r |
| 945 | IN UINTN StartBit,\r |
| 946 | IN UINTN EndBit,\r |
| 947 | IN UINT32 OrData\r |
| 948 | )\r |
| 949 | {\r |
| 950 | return PciExpressBitFieldOr32 (Address, StartBit, EndBit, OrData);\r |
| 951 | }\r |
| 952 | \r |
| 953 | /**\r |
| 954 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r |
| 955 | AND, and writes the result back to the bit field in the 32-bit register.\r |
| 956 | \r |
| 957 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 958 | bitwise AND between the read result and the value specified by AndData, and\r |
| 959 | writes the result to the 32-bit PCI configuration register specified by\r |
| 960 | Address. The value written to the PCI configuration register is returned.\r |
| 961 | This function must guarantee that all PCI read and write operations are\r |
| 962 | serialized. Extra left bits in AndData are stripped.\r |
| 963 | \r |
| 964 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 965 | If StartBit is greater than 31, then ASSERT().\r |
| 966 | If EndBit is greater than 31, then ASSERT().\r |
| 967 | If EndBit is less than StartBit, then ASSERT().\r |
| 968 | \r |
| 969 | @param Address PCI configuration register to write.\r |
| 970 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 971 | Range 0..31.\r |
| 972 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 973 | Range 0..31.\r |
| 974 | @param AndData The value to AND with the PCI configuration register.\r |
| 975 | \r |
| 976 | @return The value written back to the PCI configuration register.\r |
| 977 | \r |
| 978 | **/\r |
| 979 | UINT32\r |
| 980 | EFIAPI\r |
| 981 | PciBitFieldAnd32 (\r |
| 982 | IN UINTN Address,\r |
| 983 | IN UINTN StartBit,\r |
| 984 | IN UINTN EndBit,\r |
| 985 | IN UINT32 AndData\r |
| 986 | )\r |
| 987 | {\r |
| 988 | return PciExpressBitFieldAnd32 (Address, StartBit, EndBit, AndData);\r |
| 989 | }\r |
| 990 | \r |
| 991 | /**\r |
| 992 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r |
| 993 | bitwise inclusive OR, and writes the result back to the bit field in the\r |
| 994 | 32-bit port.\r |
| 995 | \r |
| 996 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 997 | bitwise AND followed by a bitwise inclusive OR between the read result and\r |
| 998 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
| 999 | configuration register specified by Address. The value written to the PCI\r |
| 1000 | configuration register is returned. This function must guarantee that all PCI\r |
| 1001 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 1002 | OrData are stripped.\r |
| 1003 | \r |
| 1004 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 1005 | If StartBit is greater than 31, then ASSERT().\r |
| 1006 | If EndBit is greater than 31, then ASSERT().\r |
| 1007 | If EndBit is less than StartBit, then ASSERT().\r |
| 1008 | \r |
| 1009 | @param Address PCI configuration register to write.\r |
| 1010 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 1011 | Range 0..31.\r |
| 1012 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 1013 | Range 0..31.\r |
| 1014 | @param AndData The value to AND with the PCI configuration register.\r |
| 1015 | @param OrData The value to OR with the result of the AND operation.\r |
| 1016 | \r |
| 1017 | @return The value written back to the PCI configuration register.\r |
| 1018 | \r |
| 1019 | **/\r |
| 1020 | UINT32\r |
| 1021 | EFIAPI\r |
| 1022 | PciBitFieldAndThenOr32 (\r |
| 1023 | IN UINTN Address,\r |
| 1024 | IN UINTN StartBit,\r |
| 1025 | IN UINTN EndBit,\r |
| 1026 | IN UINT32 AndData,\r |
| 1027 | IN UINT32 OrData\r |
| 1028 | )\r |
| 1029 | {\r |
| 1030 | return PciExpressBitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData);\r |
| 1031 | }\r |
| 1032 | \r |
| 1033 | /**\r |
| 1034 | Reads a range of PCI configuration registers into a caller supplied buffer.\r |
| 1035 | \r |
| 1036 | Reads the range of PCI configuration registers specified by StartAddress and\r |
| 1037 | Size into the buffer specified by Buffer. This function only allows the PCI\r |
| 1038 | configuration registers from a single PCI function to be read. Size is\r |
| 1039 | returned. When possible 32-bit PCI configuration read cycles are used to read\r |
| 1040 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r |
| 1041 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r |
| 1042 | end of the range.\r |
| 1043 | \r |
| 1044 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r |
| 1045 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
| 1046 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
| 1047 | \r |
| 1048 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r |
| 1049 | Function and Register.\r |
| 1050 | @param Size Size in bytes of the transfer.\r |
| 1051 | @param Buffer Pointer to a buffer receiving the data read.\r |
| 1052 | \r |
| 1053 | @return Size\r |
| 1054 | \r |
| 1055 | **/\r |
| 1056 | UINTN\r |
| 1057 | EFIAPI\r |
| 1058 | PciReadBuffer (\r |
| 1059 | IN UINTN StartAddress,\r |
| 1060 | IN UINTN Size,\r |
| 1061 | OUT VOID *Buffer\r |
| 1062 | )\r |
| 1063 | {\r |
| 1064 | return PciExpressReadBuffer (StartAddress, Size, Buffer);\r |
| 1065 | }\r |
| 1066 | \r |
| 1067 | /**\r |
| 1068 | Copies the data in a caller supplied buffer to a specified range of PCI\r |
| 1069 | configuration space.\r |
| 1070 | \r |
| 1071 | Writes the range of PCI configuration registers specified by StartAddress and\r |
| 1072 | Size from the buffer specified by Buffer. This function only allows the PCI\r |
| 1073 | configuration registers from a single PCI function to be written. Size is\r |
| 1074 | returned. When possible 32-bit PCI configuration write cycles are used to\r |
| 1075 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r |
| 1076 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r |
| 1077 | and the end of the range.\r |
| 1078 | \r |
| 1079 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r |
| 1080 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
| 1081 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
| 1082 | \r |
| 1083 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r |
| 1084 | Function and Register.\r |
| 1085 | @param Size Size in bytes of the transfer.\r |
| 1086 | @param Buffer Pointer to a buffer containing the data to write.\r |
| 1087 | \r |
| 1088 | @return Size\r |
| 1089 | \r |
| 1090 | **/\r |
| 1091 | UINTN\r |
| 1092 | EFIAPI\r |
| 1093 | PciWriteBuffer (\r |
| 1094 | IN UINTN StartAddress,\r |
| 1095 | IN UINTN Size,\r |
| 1096 | IN VOID *Buffer\r |
| 1097 | )\r |
| 1098 | {\r |
| 1099 | return PciExpressWriteBuffer (StartAddress, Size, Buffer);\r |
| 1100 | }\r |
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