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e1f414b6 | 1 | /** @file\r |
5c57f3ea | 2 | PCI Library functions that use the 256 MB PCI Express MMIO window to perform PCI\r |
3 | Configuration cycles. Layers on PCI Express Library.\r | |
e1f414b6 | 4 | \r |
94646ec0 | 5 | Copyright (c) 2006 - 2008, Intel Corporation<BR>\r |
e1f414b6 | 6 | All rights reserved. This program and the accompanying materials\r |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
e1f414b6 | 14 | **/\r |
15 | \r | |
c892d846 | 16 | \r |
c7d265a9 | 17 | #include <Base.h>\r |
c892d846 | 18 | \r |
c7d265a9 | 19 | #include <Library/PciLib.h>\r |
20 | #include <Library/PciExpressLib.h>\r | |
e1f414b6 | 21 | \r |
3e3ae634 | 22 | /**\r |
23 | Register a PCI device so PCI configuration registers may be accessed after \r | |
24 | SetVirtualAddressMap().\r | |
25 | \r | |
26 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
27 | \r | |
28 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
29 | Register.\r | |
30 | \r | |
31 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r | |
32 | @retval RETURN_UNSUPPORTED An attempt was made to call this function \r | |
33 | after ExitBootServices().\r | |
34 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r | |
35 | at runtime could not be mapped.\r | |
36 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r | |
37 | complete the registration.\r | |
38 | \r | |
39 | **/\r | |
40 | RETURN_STATUS\r | |
41 | EFIAPI\r | |
42 | PciRegisterForRuntimeAccess (\r | |
43 | IN UINTN Address\r | |
44 | )\r | |
45 | {\r | |
46 | return PciExpressRegisterForRuntimeAccess (Address);\r | |
47 | }\r | |
48 | \r | |
e1f414b6 | 49 | /**\r |
50 | Reads an 8-bit PCI configuration register.\r | |
51 | \r | |
52 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
53 | This function must guarantee that all PCI read and write operations are\r | |
54 | serialized.\r | |
55 | \r | |
56 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
57 | \r | |
58 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
59 | Register.\r | |
60 | \r | |
61 | @return The read value from the PCI configuration register.\r | |
62 | \r | |
63 | **/\r | |
64 | UINT8\r | |
65 | EFIAPI\r | |
66 | PciRead8 (\r | |
67 | IN UINTN Address\r | |
68 | )\r | |
69 | {\r | |
70 | return PciExpressRead8 (Address);\r | |
71 | }\r | |
72 | \r | |
73 | /**\r | |
74 | Writes an 8-bit PCI configuration register.\r | |
75 | \r | |
76 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
77 | value specified by Value. Value is returned. This function must guarantee\r | |
78 | that all PCI read and write operations are serialized.\r | |
79 | \r | |
80 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
81 | \r | |
82 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
83 | Register.\r | |
7612cbf0 | 84 | @param Value The value to write.\r |
e1f414b6 | 85 | \r |
86 | @return The value written to the PCI configuration register.\r | |
87 | \r | |
88 | **/\r | |
89 | UINT8\r | |
90 | EFIAPI\r | |
91 | PciWrite8 (\r | |
92 | IN UINTN Address,\r | |
94646ec0 | 93 | IN UINT8 Value\r |
e1f414b6 | 94 | )\r |
95 | {\r | |
94646ec0 | 96 | return PciExpressWrite8 (Address, Value);\r |
e1f414b6 | 97 | }\r |
98 | \r | |
99 | /**\r | |
100 | Performs a bitwise inclusive OR of an 8-bit PCI configuration register with\r | |
101 | an 8-bit value.\r | |
102 | \r | |
103 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
104 | bitwise inclusive OR between the read result and the value specified by\r | |
105 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
106 | specified by Address. The value written to the PCI configuration register is\r | |
107 | returned. This function must guarantee that all PCI read and write operations\r | |
108 | are serialized.\r | |
109 | \r | |
110 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
111 | \r | |
112 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
113 | Register.\r | |
114 | @param OrData The value to OR with the PCI configuration register.\r | |
115 | \r | |
116 | @return The value written back to the PCI configuration register.\r | |
117 | \r | |
118 | **/\r | |
119 | UINT8\r | |
120 | EFIAPI\r | |
121 | PciOr8 (\r | |
122 | IN UINTN Address,\r | |
123 | IN UINT8 OrData\r | |
124 | )\r | |
125 | {\r | |
126 | return PciExpressOr8 (Address, OrData);\r | |
127 | }\r | |
128 | \r | |
129 | /**\r | |
130 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
131 | value.\r | |
132 | \r | |
133 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
134 | bitwise AND between the read result and the value specified by AndData, and\r | |
135 | writes the result to the 8-bit PCI configuration register specified by\r | |
136 | Address. The value written to the PCI configuration register is returned.\r | |
137 | This function must guarantee that all PCI read and write operations are\r | |
138 | serialized.\r | |
139 | \r | |
140 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
141 | \r | |
142 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
143 | Register.\r | |
144 | @param AndData The value to AND with the PCI configuration register.\r | |
145 | \r | |
146 | @return The value written back to the PCI configuration register.\r | |
147 | \r | |
148 | **/\r | |
149 | UINT8\r | |
150 | EFIAPI\r | |
151 | PciAnd8 (\r | |
152 | IN UINTN Address,\r | |
153 | IN UINT8 AndData\r | |
154 | )\r | |
155 | {\r | |
156 | return PciExpressAnd8 (Address, AndData);\r | |
157 | }\r | |
158 | \r | |
159 | /**\r | |
160 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
161 | value, followed a bitwise inclusive OR with another 8-bit value.\r | |
162 | \r | |
163 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
164 | bitwise AND between the read result and the value specified by AndData,\r | |
165 | performs a bitwise inclusive OR between the result of the AND operation and\r | |
166 | the value specified by OrData, and writes the result to the 8-bit PCI\r | |
167 | configuration register specified by Address. The value written to the PCI\r | |
168 | configuration register is returned. This function must guarantee that all PCI\r | |
169 | read and write operations are serialized.\r | |
170 | \r | |
171 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
172 | \r | |
173 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
174 | Register.\r | |
175 | @param AndData The value to AND with the PCI configuration register.\r | |
176 | @param OrData The value to OR with the result of the AND operation.\r | |
177 | \r | |
178 | @return The value written back to the PCI configuration register.\r | |
179 | \r | |
180 | **/\r | |
181 | UINT8\r | |
182 | EFIAPI\r | |
183 | PciAndThenOr8 (\r | |
184 | IN UINTN Address,\r | |
185 | IN UINT8 AndData,\r | |
186 | IN UINT8 OrData\r | |
187 | )\r | |
188 | {\r | |
189 | return PciExpressAndThenOr8 (Address, AndData, OrData);\r | |
190 | }\r | |
191 | \r | |
192 | /**\r | |
193 | Reads a bit field of a PCI configuration register.\r | |
194 | \r | |
195 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
196 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
197 | returned.\r | |
198 | \r | |
199 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
200 | If StartBit is greater than 7, then ASSERT().\r | |
201 | If EndBit is greater than 7, then ASSERT().\r | |
202 | If EndBit is less than StartBit, then ASSERT().\r | |
203 | \r | |
204 | @param Address PCI configuration register to read.\r | |
205 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
206 | Range 0..7.\r | |
207 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
208 | Range 0..7.\r | |
209 | \r | |
210 | @return The value of the bit field read from the PCI configuration register.\r | |
211 | \r | |
212 | **/\r | |
213 | UINT8\r | |
214 | EFIAPI\r | |
215 | PciBitFieldRead8 (\r | |
216 | IN UINTN Address,\r | |
217 | IN UINTN StartBit,\r | |
218 | IN UINTN EndBit\r | |
219 | )\r | |
220 | {\r | |
221 | return PciExpressBitFieldRead8 (Address, StartBit, EndBit);\r | |
222 | }\r | |
223 | \r | |
224 | /**\r | |
225 | Writes a bit field to a PCI configuration register.\r | |
226 | \r | |
227 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
228 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
229 | destination PCI configuration register are preserved. The new value of the\r | |
230 | 8-bit register is returned.\r | |
231 | \r | |
232 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
233 | If StartBit is greater than 7, then ASSERT().\r | |
234 | If EndBit is greater than 7, then ASSERT().\r | |
235 | If EndBit is less than StartBit, then ASSERT().\r | |
236 | \r | |
237 | @param Address PCI configuration register to write.\r | |
238 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
239 | Range 0..7.\r | |
240 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
241 | Range 0..7.\r | |
242 | @param Value New value of the bit field.\r | |
243 | \r | |
244 | @return The value written back to the PCI configuration register.\r | |
245 | \r | |
246 | **/\r | |
247 | UINT8\r | |
248 | EFIAPI\r | |
249 | PciBitFieldWrite8 (\r | |
250 | IN UINTN Address,\r | |
251 | IN UINTN StartBit,\r | |
252 | IN UINTN EndBit,\r | |
253 | IN UINT8 Value\r | |
254 | )\r | |
255 | {\r | |
256 | return PciExpressBitFieldWrite8 (Address, StartBit, EndBit, Value);\r | |
257 | }\r | |
258 | \r | |
259 | /**\r | |
260 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
261 | writes the result back to the bit field in the 8-bit port.\r | |
262 | \r | |
263 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
264 | bitwise inclusive OR between the read result and the value specified by\r | |
265 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
266 | specified by Address. The value written to the PCI configuration register is\r | |
267 | returned. This function must guarantee that all PCI read and write operations\r | |
268 | are serialized. Extra left bits in OrData are stripped.\r | |
269 | \r | |
270 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
271 | If StartBit is greater than 7, then ASSERT().\r | |
272 | If EndBit is greater than 7, then ASSERT().\r | |
273 | If EndBit is less than StartBit, then ASSERT().\r | |
274 | \r | |
275 | @param Address PCI configuration register to write.\r | |
276 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
277 | Range 0..7.\r | |
278 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
279 | Range 0..7.\r | |
280 | @param OrData The value to OR with the PCI configuration register.\r | |
281 | \r | |
282 | @return The value written back to the PCI configuration register.\r | |
283 | \r | |
284 | **/\r | |
285 | UINT8\r | |
286 | EFIAPI\r | |
287 | PciBitFieldOr8 (\r | |
288 | IN UINTN Address,\r | |
289 | IN UINTN StartBit,\r | |
290 | IN UINTN EndBit,\r | |
291 | IN UINT8 OrData\r | |
292 | )\r | |
293 | {\r | |
294 | return PciExpressBitFieldOr8 (Address, StartBit, EndBit, OrData);\r | |
295 | }\r | |
296 | \r | |
297 | /**\r | |
298 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
299 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
300 | \r | |
301 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
302 | bitwise AND between the read result and the value specified by AndData, and\r | |
303 | writes the result to the 8-bit PCI configuration register specified by\r | |
304 | Address. The value written to the PCI configuration register is returned.\r | |
305 | This function must guarantee that all PCI read and write operations are\r | |
306 | serialized. Extra left bits in AndData are stripped.\r | |
307 | \r | |
308 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
309 | If StartBit is greater than 7, then ASSERT().\r | |
310 | If EndBit is greater than 7, then ASSERT().\r | |
311 | If EndBit is less than StartBit, then ASSERT().\r | |
312 | \r | |
313 | @param Address PCI configuration register to write.\r | |
314 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
315 | Range 0..7.\r | |
316 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
317 | Range 0..7.\r | |
318 | @param AndData The value to AND with the PCI configuration register.\r | |
319 | \r | |
320 | @return The value written back to the PCI configuration register.\r | |
321 | \r | |
322 | **/\r | |
323 | UINT8\r | |
324 | EFIAPI\r | |
325 | PciBitFieldAnd8 (\r | |
326 | IN UINTN Address,\r | |
327 | IN UINTN StartBit,\r | |
328 | IN UINTN EndBit,\r | |
329 | IN UINT8 AndData\r | |
330 | )\r | |
331 | {\r | |
332 | return PciExpressBitFieldAnd8 (Address, StartBit, EndBit, AndData);\r | |
333 | }\r | |
334 | \r | |
335 | /**\r | |
336 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
337 | bitwise inclusive OR, and writes the result back to the bit field in the\r | |
338 | 8-bit port.\r | |
339 | \r | |
340 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
341 | bitwise AND followed by a bitwise inclusive OR between the read result and\r | |
342 | the value specified by AndData, and writes the result to the 8-bit PCI\r | |
343 | configuration register specified by Address. The value written to the PCI\r | |
344 | configuration register is returned. This function must guarantee that all PCI\r | |
345 | read and write operations are serialized. Extra left bits in both AndData and\r | |
346 | OrData are stripped.\r | |
347 | \r | |
348 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
349 | If StartBit is greater than 7, then ASSERT().\r | |
350 | If EndBit is greater than 7, then ASSERT().\r | |
351 | If EndBit is less than StartBit, then ASSERT().\r | |
352 | \r | |
353 | @param Address PCI configuration register to write.\r | |
354 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
355 | Range 0..7.\r | |
356 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
357 | Range 0..7.\r | |
358 | @param AndData The value to AND with the PCI configuration register.\r | |
359 | @param OrData The value to OR with the result of the AND operation.\r | |
360 | \r | |
361 | @return The value written back to the PCI configuration register.\r | |
362 | \r | |
363 | **/\r | |
364 | UINT8\r | |
365 | EFIAPI\r | |
366 | PciBitFieldAndThenOr8 (\r | |
367 | IN UINTN Address,\r | |
368 | IN UINTN StartBit,\r | |
369 | IN UINTN EndBit,\r | |
370 | IN UINT8 AndData,\r | |
371 | IN UINT8 OrData\r | |
372 | )\r | |
373 | {\r | |
374 | return PciExpressBitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData);\r | |
375 | }\r | |
376 | \r | |
377 | /**\r | |
378 | Reads a 16-bit PCI configuration register.\r | |
379 | \r | |
380 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
381 | This function must guarantee that all PCI read and write operations are\r | |
382 | serialized.\r | |
383 | \r | |
384 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 385 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 386 | \r |
387 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
388 | Register.\r | |
389 | \r | |
390 | @return The read value from the PCI configuration register.\r | |
391 | \r | |
392 | **/\r | |
393 | UINT16\r | |
394 | EFIAPI\r | |
395 | PciRead16 (\r | |
396 | IN UINTN Address\r | |
397 | )\r | |
398 | {\r | |
399 | return PciExpressRead16 (Address);\r | |
400 | }\r | |
401 | \r | |
402 | /**\r | |
403 | Writes a 16-bit PCI configuration register.\r | |
404 | \r | |
405 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
406 | value specified by Value. Value is returned. This function must guarantee\r | |
407 | that all PCI read and write operations are serialized.\r | |
408 | \r | |
409 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 410 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 411 | \r |
412 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
413 | Register.\r | |
9638ba6d | 414 | @param Value The value to write.\r |
e1f414b6 | 415 | \r |
416 | @return The value written to the PCI configuration register.\r | |
417 | \r | |
418 | **/\r | |
419 | UINT16\r | |
420 | EFIAPI\r | |
421 | PciWrite16 (\r | |
422 | IN UINTN Address,\r | |
94646ec0 | 423 | IN UINT16 Value\r |
e1f414b6 | 424 | )\r |
425 | {\r | |
94646ec0 | 426 | return PciExpressWrite16 (Address, Value);\r |
e1f414b6 | 427 | }\r |
428 | \r | |
429 | /**\r | |
430 | Performs a bitwise inclusive OR of a 16-bit PCI configuration register with\r | |
431 | a 16-bit value.\r | |
432 | \r | |
433 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
434 | bitwise inclusive OR between the read result and the value specified by\r | |
435 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
436 | specified by Address. The value written to the PCI configuration register is\r | |
437 | returned. This function must guarantee that all PCI read and write operations\r | |
438 | are serialized.\r | |
439 | \r | |
440 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 441 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 442 | \r |
443 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
444 | Register.\r | |
445 | @param OrData The value to OR with the PCI configuration register.\r | |
446 | \r | |
447 | @return The value written back to the PCI configuration register.\r | |
448 | \r | |
449 | **/\r | |
450 | UINT16\r | |
451 | EFIAPI\r | |
452 | PciOr16 (\r | |
453 | IN UINTN Address,\r | |
454 | IN UINT16 OrData\r | |
455 | )\r | |
456 | {\r | |
457 | return PciExpressOr16 (Address, OrData);\r | |
458 | }\r | |
459 | \r | |
460 | /**\r | |
461 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
462 | value.\r | |
463 | \r | |
464 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
465 | bitwise AND between the read result and the value specified by AndData, and\r | |
466 | writes the result to the 16-bit PCI configuration register specified by\r | |
467 | Address. The value written to the PCI configuration register is returned.\r | |
468 | This function must guarantee that all PCI read and write operations are\r | |
469 | serialized.\r | |
470 | \r | |
471 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 472 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 473 | \r |
474 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
475 | Register.\r | |
476 | @param AndData The value to AND with the PCI configuration register.\r | |
477 | \r | |
478 | @return The value written back to the PCI configuration register.\r | |
479 | \r | |
480 | **/\r | |
481 | UINT16\r | |
482 | EFIAPI\r | |
483 | PciAnd16 (\r | |
484 | IN UINTN Address,\r | |
485 | IN UINT16 AndData\r | |
486 | )\r | |
487 | {\r | |
488 | return PciExpressAnd16 (Address, AndData);\r | |
489 | }\r | |
490 | \r | |
491 | /**\r | |
492 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
493 | value, followed a bitwise inclusive OR with another 16-bit value.\r | |
494 | \r | |
495 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
496 | bitwise AND between the read result and the value specified by AndData,\r | |
497 | performs a bitwise inclusive OR between the result of the AND operation and\r | |
498 | the value specified by OrData, and writes the result to the 16-bit PCI\r | |
499 | configuration register specified by Address. The value written to the PCI\r | |
500 | configuration register is returned. This function must guarantee that all PCI\r | |
501 | read and write operations are serialized.\r | |
502 | \r | |
503 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 504 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 505 | \r |
506 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
507 | Register.\r | |
508 | @param AndData The value to AND with the PCI configuration register.\r | |
509 | @param OrData The value to OR with the result of the AND operation.\r | |
510 | \r | |
511 | @return The value written back to the PCI configuration register.\r | |
512 | \r | |
513 | **/\r | |
514 | UINT16\r | |
515 | EFIAPI\r | |
516 | PciAndThenOr16 (\r | |
517 | IN UINTN Address,\r | |
518 | IN UINT16 AndData,\r | |
519 | IN UINT16 OrData\r | |
520 | )\r | |
521 | {\r | |
522 | return PciExpressAndThenOr16 (Address, AndData, OrData);\r | |
523 | }\r | |
524 | \r | |
525 | /**\r | |
526 | Reads a bit field of a PCI configuration register.\r | |
527 | \r | |
528 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
529 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
530 | returned.\r | |
531 | \r | |
532 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 533 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 534 | If StartBit is greater than 15, then ASSERT().\r |
535 | If EndBit is greater than 15, then ASSERT().\r | |
536 | If EndBit is less than StartBit, then ASSERT().\r | |
537 | \r | |
538 | @param Address PCI configuration register to read.\r | |
539 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
540 | Range 0..15.\r | |
541 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
542 | Range 0..15.\r | |
543 | \r | |
544 | @return The value of the bit field read from the PCI configuration register.\r | |
545 | \r | |
546 | **/\r | |
547 | UINT16\r | |
548 | EFIAPI\r | |
549 | PciBitFieldRead16 (\r | |
550 | IN UINTN Address,\r | |
551 | IN UINTN StartBit,\r | |
552 | IN UINTN EndBit\r | |
553 | )\r | |
554 | {\r | |
555 | return PciExpressBitFieldRead16 (Address, StartBit, EndBit);\r | |
556 | }\r | |
557 | \r | |
558 | /**\r | |
559 | Writes a bit field to a PCI configuration register.\r | |
560 | \r | |
561 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
562 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
563 | destination PCI configuration register are preserved. The new value of the\r | |
564 | 16-bit register is returned.\r | |
565 | \r | |
566 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 567 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 568 | If StartBit is greater than 15, then ASSERT().\r |
569 | If EndBit is greater than 15, then ASSERT().\r | |
570 | If EndBit is less than StartBit, then ASSERT().\r | |
571 | \r | |
572 | @param Address PCI configuration register to write.\r | |
573 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
574 | Range 0..15.\r | |
575 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
576 | Range 0..15.\r | |
577 | @param Value New value of the bit field.\r | |
578 | \r | |
579 | @return The value written back to the PCI configuration register.\r | |
580 | \r | |
581 | **/\r | |
582 | UINT16\r | |
583 | EFIAPI\r | |
584 | PciBitFieldWrite16 (\r | |
585 | IN UINTN Address,\r | |
586 | IN UINTN StartBit,\r | |
587 | IN UINTN EndBit,\r | |
588 | IN UINT16 Value\r | |
589 | )\r | |
590 | {\r | |
591 | return PciExpressBitFieldWrite16 (Address, StartBit, EndBit, Value);\r | |
592 | }\r | |
593 | \r | |
594 | /**\r | |
595 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
596 | writes the result back to the bit field in the 16-bit port.\r | |
597 | \r | |
598 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
599 | bitwise inclusive OR between the read result and the value specified by\r | |
600 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
601 | specified by Address. The value written to the PCI configuration register is\r | |
602 | returned. This function must guarantee that all PCI read and write operations\r | |
603 | are serialized. Extra left bits in OrData are stripped.\r | |
604 | \r | |
605 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 606 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 607 | If StartBit is greater than 15, then ASSERT().\r |
608 | If EndBit is greater than 15, then ASSERT().\r | |
609 | If EndBit is less than StartBit, then ASSERT().\r | |
610 | \r | |
611 | @param Address PCI configuration register to write.\r | |
612 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
613 | Range 0..15.\r | |
614 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
615 | Range 0..15.\r | |
616 | @param OrData The value to OR with the PCI configuration register.\r | |
617 | \r | |
618 | @return The value written back to the PCI configuration register.\r | |
619 | \r | |
620 | **/\r | |
621 | UINT16\r | |
622 | EFIAPI\r | |
623 | PciBitFieldOr16 (\r | |
624 | IN UINTN Address,\r | |
625 | IN UINTN StartBit,\r | |
626 | IN UINTN EndBit,\r | |
627 | IN UINT16 OrData\r | |
628 | )\r | |
629 | {\r | |
630 | return PciExpressBitFieldOr16 (Address, StartBit, EndBit, OrData);\r | |
631 | }\r | |
632 | \r | |
633 | /**\r | |
634 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
635 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
636 | \r | |
637 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
638 | bitwise AND between the read result and the value specified by AndData, and\r | |
639 | writes the result to the 16-bit PCI configuration register specified by\r | |
640 | Address. The value written to the PCI configuration register is returned.\r | |
641 | This function must guarantee that all PCI read and write operations are\r | |
642 | serialized. Extra left bits in AndData are stripped.\r | |
643 | \r | |
644 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 645 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 646 | If StartBit is greater than 15, then ASSERT().\r |
647 | If EndBit is greater than 15, then ASSERT().\r | |
648 | If EndBit is less than StartBit, then ASSERT().\r | |
649 | \r | |
650 | @param Address PCI configuration register to write.\r | |
651 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
652 | Range 0..15.\r | |
653 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
654 | Range 0..15.\r | |
655 | @param AndData The value to AND with the PCI configuration register.\r | |
656 | \r | |
657 | @return The value written back to the PCI configuration register.\r | |
658 | \r | |
659 | **/\r | |
660 | UINT16\r | |
661 | EFIAPI\r | |
662 | PciBitFieldAnd16 (\r | |
663 | IN UINTN Address,\r | |
664 | IN UINTN StartBit,\r | |
665 | IN UINTN EndBit,\r | |
666 | IN UINT16 AndData\r | |
667 | )\r | |
668 | {\r | |
669 | return PciExpressBitFieldAnd16 (Address, StartBit, EndBit, AndData);\r | |
670 | }\r | |
671 | \r | |
672 | /**\r | |
673 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
674 | bitwise inclusive OR, and writes the result back to the bit field in the\r | |
675 | 16-bit port.\r | |
676 | \r | |
677 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
678 | bitwise AND followed by a bitwise inclusive OR between the read result and\r | |
679 | the value specified by AndData, and writes the result to the 16-bit PCI\r | |
680 | configuration register specified by Address. The value written to the PCI\r | |
681 | configuration register is returned. This function must guarantee that all PCI\r | |
682 | read and write operations are serialized. Extra left bits in both AndData and\r | |
683 | OrData are stripped.\r | |
684 | \r | |
685 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 686 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
e1f414b6 | 687 | If StartBit is greater than 15, then ASSERT().\r |
688 | If EndBit is greater than 15, then ASSERT().\r | |
689 | If EndBit is less than StartBit, then ASSERT().\r | |
690 | \r | |
691 | @param Address PCI configuration register to write.\r | |
692 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
693 | Range 0..15.\r | |
694 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
695 | Range 0..15.\r | |
696 | @param AndData The value to AND with the PCI configuration register.\r | |
697 | @param OrData The value to OR with the result of the AND operation.\r | |
698 | \r | |
699 | @return The value written back to the PCI configuration register.\r | |
700 | \r | |
701 | **/\r | |
702 | UINT16\r | |
703 | EFIAPI\r | |
704 | PciBitFieldAndThenOr16 (\r | |
705 | IN UINTN Address,\r | |
706 | IN UINTN StartBit,\r | |
707 | IN UINTN EndBit,\r | |
708 | IN UINT16 AndData,\r | |
709 | IN UINT16 OrData\r | |
710 | )\r | |
711 | {\r | |
712 | return PciExpressBitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData);\r | |
713 | }\r | |
714 | \r | |
715 | /**\r | |
716 | Reads a 32-bit PCI configuration register.\r | |
717 | \r | |
718 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
719 | This function must guarantee that all PCI read and write operations are\r | |
720 | serialized.\r | |
721 | \r | |
722 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 723 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 724 | \r |
725 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
726 | Register.\r | |
727 | \r | |
728 | @return The read value from the PCI configuration register.\r | |
729 | \r | |
730 | **/\r | |
731 | UINT32\r | |
732 | EFIAPI\r | |
733 | PciRead32 (\r | |
734 | IN UINTN Address\r | |
735 | )\r | |
736 | {\r | |
737 | return PciExpressRead32 (Address);\r | |
738 | }\r | |
739 | \r | |
740 | /**\r | |
741 | Writes a 32-bit PCI configuration register.\r | |
742 | \r | |
743 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
744 | value specified by Value. Value is returned. This function must guarantee\r | |
745 | that all PCI read and write operations are serialized.\r | |
746 | \r | |
747 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 748 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 749 | \r |
750 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
751 | Register.\r | |
7612cbf0 | 752 | @param Value The value to write.\r |
e1f414b6 | 753 | \r |
754 | @return The value written to the PCI configuration register.\r | |
755 | \r | |
756 | **/\r | |
757 | UINT32\r | |
758 | EFIAPI\r | |
759 | PciWrite32 (\r | |
760 | IN UINTN Address,\r | |
94646ec0 | 761 | IN UINT32 Value\r |
e1f414b6 | 762 | )\r |
763 | {\r | |
94646ec0 | 764 | return PciExpressWrite32 (Address, Value);\r |
e1f414b6 | 765 | }\r |
766 | \r | |
767 | /**\r | |
768 | Performs a bitwise inclusive OR of a 32-bit PCI configuration register with\r | |
769 | a 32-bit value.\r | |
770 | \r | |
771 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
772 | bitwise inclusive OR between the read result and the value specified by\r | |
773 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
774 | specified by Address. The value written to the PCI configuration register is\r | |
775 | returned. This function must guarantee that all PCI read and write operations\r | |
776 | are serialized.\r | |
777 | \r | |
778 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 779 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 780 | \r |
781 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
782 | Register.\r | |
783 | @param OrData The value to OR with the PCI configuration register.\r | |
784 | \r | |
785 | @return The value written back to the PCI configuration register.\r | |
786 | \r | |
787 | **/\r | |
788 | UINT32\r | |
789 | EFIAPI\r | |
790 | PciOr32 (\r | |
791 | IN UINTN Address,\r | |
792 | IN UINT32 OrData\r | |
793 | )\r | |
794 | {\r | |
795 | return PciExpressOr32 (Address, OrData);\r | |
796 | }\r | |
797 | \r | |
798 | /**\r | |
799 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
800 | value.\r | |
801 | \r | |
802 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
803 | bitwise AND between the read result and the value specified by AndData, and\r | |
804 | writes the result to the 32-bit PCI configuration register specified by\r | |
805 | Address. The value written to the PCI configuration register is returned.\r | |
806 | This function must guarantee that all PCI read and write operations are\r | |
807 | serialized.\r | |
808 | \r | |
809 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 810 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 811 | \r |
812 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
813 | Register.\r | |
814 | @param AndData The value to AND with the PCI configuration register.\r | |
815 | \r | |
816 | @return The value written back to the PCI configuration register.\r | |
817 | \r | |
818 | **/\r | |
819 | UINT32\r | |
820 | EFIAPI\r | |
821 | PciAnd32 (\r | |
822 | IN UINTN Address,\r | |
823 | IN UINT32 AndData\r | |
824 | )\r | |
825 | {\r | |
826 | return PciExpressAnd32 (Address, AndData);\r | |
827 | }\r | |
828 | \r | |
829 | /**\r | |
830 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
831 | value, followed a bitwise inclusive OR with another 32-bit value.\r | |
832 | \r | |
833 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
834 | bitwise AND between the read result and the value specified by AndData,\r | |
835 | performs a bitwise inclusive OR between the result of the AND operation and\r | |
836 | the value specified by OrData, and writes the result to the 32-bit PCI\r | |
837 | configuration register specified by Address. The value written to the PCI\r | |
838 | configuration register is returned. This function must guarantee that all PCI\r | |
839 | read and write operations are serialized.\r | |
840 | \r | |
841 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 842 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 843 | \r |
844 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
845 | Register.\r | |
846 | @param AndData The value to AND with the PCI configuration register.\r | |
847 | @param OrData The value to OR with the result of the AND operation.\r | |
848 | \r | |
849 | @return The value written back to the PCI configuration register.\r | |
850 | \r | |
851 | **/\r | |
852 | UINT32\r | |
853 | EFIAPI\r | |
854 | PciAndThenOr32 (\r | |
855 | IN UINTN Address,\r | |
856 | IN UINT32 AndData,\r | |
857 | IN UINT32 OrData\r | |
858 | )\r | |
859 | {\r | |
860 | return PciExpressAndThenOr32 (Address, AndData, OrData);\r | |
861 | }\r | |
862 | \r | |
863 | /**\r | |
864 | Reads a bit field of a PCI configuration register.\r | |
865 | \r | |
866 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
867 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
868 | returned.\r | |
869 | \r | |
870 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 871 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 872 | If StartBit is greater than 31, then ASSERT().\r |
873 | If EndBit is greater than 31, then ASSERT().\r | |
874 | If EndBit is less than StartBit, then ASSERT().\r | |
875 | \r | |
876 | @param Address PCI configuration register to read.\r | |
877 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
878 | Range 0..31.\r | |
879 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
880 | Range 0..31.\r | |
881 | \r | |
882 | @return The value of the bit field read from the PCI configuration register.\r | |
883 | \r | |
884 | **/\r | |
885 | UINT32\r | |
886 | EFIAPI\r | |
887 | PciBitFieldRead32 (\r | |
888 | IN UINTN Address,\r | |
889 | IN UINTN StartBit,\r | |
890 | IN UINTN EndBit\r | |
891 | )\r | |
892 | {\r | |
893 | return PciExpressBitFieldRead32 (Address, StartBit, EndBit);\r | |
894 | }\r | |
895 | \r | |
896 | /**\r | |
897 | Writes a bit field to a PCI configuration register.\r | |
898 | \r | |
899 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
900 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
901 | destination PCI configuration register are preserved. The new value of the\r | |
902 | 32-bit register is returned.\r | |
903 | \r | |
904 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 905 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 906 | If StartBit is greater than 31, then ASSERT().\r |
907 | If EndBit is greater than 31, then ASSERT().\r | |
908 | If EndBit is less than StartBit, then ASSERT().\r | |
909 | \r | |
910 | @param Address PCI configuration register to write.\r | |
911 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
912 | Range 0..31.\r | |
913 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
914 | Range 0..31.\r | |
915 | @param Value New value of the bit field.\r | |
916 | \r | |
917 | @return The value written back to the PCI configuration register.\r | |
918 | \r | |
919 | **/\r | |
920 | UINT32\r | |
921 | EFIAPI\r | |
922 | PciBitFieldWrite32 (\r | |
923 | IN UINTN Address,\r | |
924 | IN UINTN StartBit,\r | |
925 | IN UINTN EndBit,\r | |
926 | IN UINT32 Value\r | |
927 | )\r | |
928 | {\r | |
929 | return PciExpressBitFieldWrite32 (Address, StartBit, EndBit, Value);\r | |
930 | }\r | |
931 | \r | |
932 | /**\r | |
933 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
934 | writes the result back to the bit field in the 32-bit port.\r | |
935 | \r | |
936 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
937 | bitwise inclusive OR between the read result and the value specified by\r | |
938 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
939 | specified by Address. The value written to the PCI configuration register is\r | |
940 | returned. This function must guarantee that all PCI read and write operations\r | |
941 | are serialized. Extra left bits in OrData are stripped.\r | |
942 | \r | |
943 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 944 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 945 | If StartBit is greater than 31, then ASSERT().\r |
946 | If EndBit is greater than 31, then ASSERT().\r | |
947 | If EndBit is less than StartBit, then ASSERT().\r | |
948 | \r | |
949 | @param Address PCI configuration register to write.\r | |
950 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
951 | Range 0..31.\r | |
952 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
953 | Range 0..31.\r | |
954 | @param OrData The value to OR with the PCI configuration register.\r | |
955 | \r | |
956 | @return The value written back to the PCI configuration register.\r | |
957 | \r | |
958 | **/\r | |
959 | UINT32\r | |
960 | EFIAPI\r | |
961 | PciBitFieldOr32 (\r | |
962 | IN UINTN Address,\r | |
963 | IN UINTN StartBit,\r | |
964 | IN UINTN EndBit,\r | |
965 | IN UINT32 OrData\r | |
966 | )\r | |
967 | {\r | |
968 | return PciExpressBitFieldOr32 (Address, StartBit, EndBit, OrData);\r | |
969 | }\r | |
970 | \r | |
971 | /**\r | |
972 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
973 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
974 | \r | |
975 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
976 | bitwise AND between the read result and the value specified by AndData, and\r | |
977 | writes the result to the 32-bit PCI configuration register specified by\r | |
978 | Address. The value written to the PCI configuration register is returned.\r | |
979 | This function must guarantee that all PCI read and write operations are\r | |
980 | serialized. Extra left bits in AndData are stripped.\r | |
981 | \r | |
982 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 983 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 984 | If StartBit is greater than 31, then ASSERT().\r |
985 | If EndBit is greater than 31, then ASSERT().\r | |
986 | If EndBit is less than StartBit, then ASSERT().\r | |
987 | \r | |
988 | @param Address PCI configuration register to write.\r | |
989 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
990 | Range 0..31.\r | |
991 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
992 | Range 0..31.\r | |
993 | @param AndData The value to AND with the PCI configuration register.\r | |
994 | \r | |
995 | @return The value written back to the PCI configuration register.\r | |
996 | \r | |
997 | **/\r | |
998 | UINT32\r | |
999 | EFIAPI\r | |
1000 | PciBitFieldAnd32 (\r | |
1001 | IN UINTN Address,\r | |
1002 | IN UINTN StartBit,\r | |
1003 | IN UINTN EndBit,\r | |
1004 | IN UINT32 AndData\r | |
1005 | )\r | |
1006 | {\r | |
1007 | return PciExpressBitFieldAnd32 (Address, StartBit, EndBit, AndData);\r | |
1008 | }\r | |
1009 | \r | |
1010 | /**\r | |
1011 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
1012 | bitwise inclusive OR, and writes the result back to the bit field in the\r | |
1013 | 32-bit port.\r | |
1014 | \r | |
1015 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1016 | bitwise AND followed by a bitwise inclusive OR between the read result and\r | |
1017 | the value specified by AndData, and writes the result to the 32-bit PCI\r | |
1018 | configuration register specified by Address. The value written to the PCI\r | |
1019 | configuration register is returned. This function must guarantee that all PCI\r | |
1020 | read and write operations are serialized. Extra left bits in both AndData and\r | |
1021 | OrData are stripped.\r | |
1022 | \r | |
1023 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
9638ba6d | 1024 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
e1f414b6 | 1025 | If StartBit is greater than 31, then ASSERT().\r |
1026 | If EndBit is greater than 31, then ASSERT().\r | |
1027 | If EndBit is less than StartBit, then ASSERT().\r | |
1028 | \r | |
1029 | @param Address PCI configuration register to write.\r | |
1030 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1031 | Range 0..31.\r | |
1032 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1033 | Range 0..31.\r | |
1034 | @param AndData The value to AND with the PCI configuration register.\r | |
1035 | @param OrData The value to OR with the result of the AND operation.\r | |
1036 | \r | |
1037 | @return The value written back to the PCI configuration register.\r | |
1038 | \r | |
1039 | **/\r | |
1040 | UINT32\r | |
1041 | EFIAPI\r | |
1042 | PciBitFieldAndThenOr32 (\r | |
1043 | IN UINTN Address,\r | |
1044 | IN UINTN StartBit,\r | |
1045 | IN UINTN EndBit,\r | |
1046 | IN UINT32 AndData,\r | |
1047 | IN UINT32 OrData\r | |
1048 | )\r | |
1049 | {\r | |
1050 | return PciExpressBitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData);\r | |
1051 | }\r | |
1052 | \r | |
1053 | /**\r | |
1054 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
1055 | \r | |
1056 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
1057 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
1058 | configuration registers from a single PCI function to be read. Size is\r | |
1059 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
1060 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
1061 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
1062 | end of the range.\r | |
1063 | \r | |
1064 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1065 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1066 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1067 | \r | |
1068 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
1069 | Function and Register.\r | |
1070 | @param Size Size in bytes of the transfer.\r | |
1071 | @param Buffer Pointer to a buffer receiving the data read.\r | |
1072 | \r | |
1073 | @return Size\r | |
1074 | \r | |
1075 | **/\r | |
1076 | UINTN\r | |
1077 | EFIAPI\r | |
1078 | PciReadBuffer (\r | |
1079 | IN UINTN StartAddress,\r | |
1080 | IN UINTN Size,\r | |
1081 | OUT VOID *Buffer\r | |
1082 | )\r | |
1083 | {\r | |
1084 | return PciExpressReadBuffer (StartAddress, Size, Buffer);\r | |
1085 | }\r | |
1086 | \r | |
1087 | /**\r | |
1088 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1089 | configuration space.\r | |
1090 | \r | |
1091 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1092 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1093 | configuration registers from a single PCI function to be written. Size is\r | |
1094 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1095 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1096 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1097 | and the end of the range.\r | |
1098 | \r | |
1099 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1100 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1101 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1102 | \r | |
1103 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
1104 | Function and Register.\r | |
1105 | @param Size Size in bytes of the transfer.\r | |
1106 | @param Buffer Pointer to a buffer containing the data to write.\r | |
1107 | \r | |
1108 | @return Size\r | |
1109 | \r | |
1110 | **/\r | |
1111 | UINTN\r | |
1112 | EFIAPI\r | |
1113 | PciWriteBuffer (\r | |
1114 | IN UINTN StartAddress,\r | |
1115 | IN UINTN Size,\r | |
1116 | IN VOID *Buffer\r | |
1117 | )\r | |
1118 | {\r | |
1119 | return PciExpressWriteBuffer (StartAddress, Size, Buffer);\r | |
1120 | }\r |