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1a3eaf06 | 1 | /** @file\r |
2 | PCI Segment Library implementation using PCI CFG2 PPI.\r | |
3 | \r | |
19388d29 HT |
4 | Copyright (c) 2007 - 2009, Intel Corporation. All rights reserved.<BR>\r |
5 | This program and the accompanying materials are\r | |
1a3eaf06 | 6 | licensed and made available under the terms and conditions of\r |
7 | the BSD License which accompanies this distribution. The full\r | |
8 | text of the license may be found at\r | |
2fc59a00 | 9 | http://opensource.org/licenses/bsd-license.php.\r |
1a3eaf06 | 10 | \r |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #include <PiPei.h>\r | |
17 | \r | |
18 | #include <Ppi/PciCfg2.h>\r | |
19 | \r | |
20 | #include <Library/PciSegmentLib.h>\r | |
21 | #include <Library/BaseLib.h>\r | |
22 | #include <Library/PeiServicesTablePointerLib.h>\r | |
23 | #include <Library/DebugLib.h>\r | |
24 | #include <Library/PeiServicesLib.h>\r | |
25 | \r | |
26 | /**\r | |
27 | Assert the validity of a PCI Segment address.\r | |
59ceeabe | 28 | A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63\r |
1a3eaf06 | 29 | \r |
30 | @param A The address to validate.\r | |
31 | @param M Additional bits to assert to be zero.\r | |
32 | \r | |
33 | **/\r | |
34 | #define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \\r | |
59ceeabe | 35 | ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)\r |
1a3eaf06 | 36 | \r |
37 | /**\r | |
38 | Translate PCI Lib address into format of PCI CFG2 PPI.\r | |
39 | \r | |
2fc59a00 | 40 | @param A The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 41 | Register.\r |
42 | \r | |
43 | **/\r | |
44 | #define PCI_TO_PCICFG2_ADDRESS(A) \\r | |
f5305d5a | 45 | ((((UINT32)(A) << 4) & 0xff000000) | (((UINT32)(A) >> 4) & 0x00000700) | (((UINT32)(A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))\r |
1a3eaf06 | 46 | \r |
47 | /**\r | |
48 | Gets PCI CFG2 PPI.\r | |
49 | \r | |
50 | This internal function retrieves PCI CFG2 PPI from PPI database.\r | |
51 | \r | |
58380e9c | 52 | @param Address The address that encodes the PCI Segment, Bus, Device, \r |
53 | Function and Register.\r | |
1a3eaf06 | 54 | \r |
55 | @return The pointer to PCI CFG2 PPI.\r | |
56 | \r | |
57 | **/\r | |
58 | EFI_PEI_PCI_CFG2_PPI *\r | |
59 | InternalGetPciCfg2Ppi (\r | |
60 | IN UINT64 Address\r | |
61 | )\r | |
62 | {\r | |
63 | EFI_STATUS Status;\r | |
64 | UINTN Instance;\r | |
65 | EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r | |
66 | UINT64 SegmentNumber;\r | |
67 | \r | |
68 | Instance = 0;\r | |
69 | PciCfg2Ppi = NULL;\r | |
70 | SegmentNumber = BitFieldRead64 (Address, 32, 63);\r | |
71 | \r | |
72 | //\r | |
73 | // Loop through all instances of the PPI and match segment number\r | |
74 | //\r | |
75 | do {\r | |
76 | Status = PeiServicesLocatePpi(\r | |
77 | &gEfiPciCfg2PpiGuid,\r | |
78 | Instance,\r | |
79 | NULL,\r | |
80 | (VOID**) &PciCfg2Ppi\r | |
81 | );\r | |
82 | ASSERT_EFI_ERROR (Status);\r | |
83 | Instance++;\r | |
84 | } while (PciCfg2Ppi->Segment != SegmentNumber);\r | |
85 | \r | |
86 | return PciCfg2Ppi;\r | |
87 | }\r | |
88 | \r | |
89 | /**\r | |
90 | Internal worker function to read a PCI configuration register.\r | |
91 | \r | |
92 | This function wraps EFI_PEI_PCI_CFG2_PPI.Read() service.\r | |
93 | It reads and returns the PCI configuration register specified by Address,\r | |
94 | the width of data is specified by Width.\r | |
95 | \r | |
2fc59a00 | 96 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 97 | Register.\r |
58380e9c | 98 | @param Width The width of data to read\r |
1a3eaf06 | 99 | \r |
100 | @return The value read from the PCI configuration register.\r | |
101 | \r | |
102 | **/\r | |
103 | UINT32\r | |
104 | PeiPciSegmentLibPciCfg2ReadWorker (\r | |
105 | IN UINT64 Address,\r | |
106 | IN EFI_PEI_PCI_CFG_PPI_WIDTH Width\r | |
107 | )\r | |
108 | {\r | |
109 | UINT32 Data;\r | |
110 | CONST EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r | |
43fe5cdc | 111 | UINT64 PciCfg2Address;\r |
1a3eaf06 | 112 | \r |
113 | PciCfg2Ppi = InternalGetPciCfg2Ppi (Address);\r | |
43fe5cdc | 114 | PciCfg2Address = PCI_TO_PCICFG2_ADDRESS (Address);\r |
1a3eaf06 | 115 | PciCfg2Ppi->Read (\r |
116 | GetPeiServicesTablePointer (),\r | |
117 | PciCfg2Ppi,\r | |
118 | Width,\r | |
43fe5cdc | 119 | PciCfg2Address,\r |
1a3eaf06 | 120 | &Data\r |
121 | );\r | |
122 | \r | |
123 | return Data;\r | |
124 | }\r | |
125 | \r | |
126 | /**\r | |
127 | Internal worker function to writes a PCI configuration register.\r | |
128 | \r | |
129 | This function wraps EFI_PEI_PCI_CFG2_PPI.Write() service.\r | |
130 | It writes the PCI configuration register specified by Address with the\r | |
131 | value specified by Data. The width of data is specifed by Width.\r | |
132 | Data is returned.\r | |
133 | \r | |
2fc59a00 | 134 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 135 | Register.\r |
58380e9c | 136 | @param Width The width of data to write\r |
1a3eaf06 | 137 | @param Data The value to write.\r |
138 | \r | |
139 | @return The value written to the PCI configuration register.\r | |
140 | \r | |
141 | **/\r | |
142 | UINT32\r | |
143 | PeiPciSegmentLibPciCfg2WriteWorker (\r | |
144 | IN UINT64 Address,\r | |
145 | IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r | |
146 | IN UINT32 Data\r | |
147 | )\r | |
148 | {\r | |
149 | CONST EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r | |
43fe5cdc | 150 | UINT64 PciCfg2Address;\r |
1a3eaf06 | 151 | \r |
152 | PciCfg2Ppi = InternalGetPciCfg2Ppi (Address);\r | |
43fe5cdc | 153 | PciCfg2Address = PCI_TO_PCICFG2_ADDRESS (Address);\r |
1a3eaf06 | 154 | PciCfg2Ppi->Write (\r |
155 | GetPeiServicesTablePointer (),\r | |
156 | PciCfg2Ppi,\r | |
157 | Width,\r | |
43fe5cdc | 158 | PciCfg2Address,\r |
1a3eaf06 | 159 | &Data\r |
160 | );\r | |
161 | \r | |
162 | return Data;\r | |
163 | }\r | |
164 | \r | |
3e3ae634 | 165 | /**\r |
166 | Register a PCI device so PCI configuration registers may be accessed after \r | |
167 | SetVirtualAddressMap().\r | |
168 | \r | |
59ceeabe | 169 | If any reserved bits in Address are set, then ASSERT().\r |
3e3ae634 | 170 | \r |
2fc59a00 | 171 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
3e3ae634 | 172 | Register.\r |
173 | \r | |
174 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r | |
175 | @retval RETURN_UNSUPPORTED An attempt was made to call this function \r | |
176 | after ExitBootServices().\r | |
177 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r | |
178 | at runtime could not be mapped.\r | |
179 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r | |
180 | complete the registration.\r | |
181 | \r | |
182 | **/\r | |
183 | RETURN_STATUS\r | |
184 | EFIAPI\r | |
185 | PciSegmentRegisterForRuntimeAccess (\r | |
186 | IN UINTN Address\r | |
187 | )\r | |
188 | {\r | |
59ceeabe | 189 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r |
3e3ae634 | 190 | return RETURN_UNSUPPORTED;\r |
191 | }\r | |
192 | \r | |
1a3eaf06 | 193 | /**\r |
194 | Reads an 8-bit PCI configuration register.\r | |
195 | \r | |
196 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
d5979dc0 | 197 | This function must guarantee that all PCI read and write operations are serialized.\r |
198 | \r | |
1a3eaf06 | 199 | If any reserved bits in Address are set, then ASSERT().\r |
d5979dc0 | 200 | \r |
58380e9c | 201 | @param Address The address that encodes the PCI Segment, Bus, Device, Function, \r |
202 | and Register.\r | |
1a3eaf06 | 203 | \r |
d5979dc0 | 204 | @return The 8-bit PCI configuration register specified by Address.\r |
1a3eaf06 | 205 | \r |
206 | **/\r | |
207 | UINT8\r | |
208 | EFIAPI\r | |
209 | PciSegmentRead8 (\r | |
0c3437e0 | 210 | IN UINT64 Address\r |
1a3eaf06 | 211 | )\r |
212 | {\r | |
213 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r | |
214 | \r | |
215 | return (UINT8) PeiPciSegmentLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint8);\r | |
216 | }\r | |
217 | \r | |
218 | /**\r | |
219 | Writes an 8-bit PCI configuration register.\r | |
220 | \r | |
d5979dc0 | 221 | Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r |
222 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
223 | \r | |
59ceeabe | 224 | If any reserved bits in Address are set, then ASSERT().\r |
1a3eaf06 | 225 | \r |
2fc59a00 | 226 | @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
d5979dc0 | 227 | @param Value The value to write.\r |
1a3eaf06 | 228 | \r |
229 | @return The value written to the PCI configuration register.\r | |
230 | \r | |
231 | **/\r | |
232 | UINT8\r | |
233 | EFIAPI\r | |
234 | PciSegmentWrite8 (\r | |
0c3437e0 | 235 | IN UINT64 Address,\r |
236 | IN UINT8 Value\r | |
1a3eaf06 | 237 | )\r |
238 | {\r | |
239 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r | |
240 | \r | |
d5979dc0 | 241 | return (UINT8) PeiPciSegmentLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint8, Value);\r |
1a3eaf06 | 242 | }\r |
243 | \r | |
244 | /**\r | |
62991af2 | 245 | Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.\r |
1a3eaf06 | 246 | \r |
d5979dc0 | 247 | Reads the 8-bit PCI configuration register specified by Address,\r |
62991af2 | 248 | performs a bitwise OR between the read result and the value specified by OrData,\r |
d5979dc0 | 249 | and writes the result to the 8-bit PCI configuration register specified by Address.\r |
250 | The value written to the PCI configuration register is returned.\r | |
251 | This function must guarantee that all PCI read and write operations are serialized.\r | |
252 | \r | |
1a3eaf06 | 253 | If any reserved bits in Address are set, then ASSERT().\r |
254 | \r | |
2fc59a00 | 255 | @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
d5979dc0 | 256 | @param OrData The value to OR with the PCI configuration register.\r |
1a3eaf06 | 257 | \r |
d5979dc0 | 258 | @return The value written to the PCI configuration register.\r |
1a3eaf06 | 259 | \r |
260 | **/\r | |
261 | UINT8\r | |
262 | EFIAPI\r | |
263 | PciSegmentOr8 (\r | |
0c3437e0 | 264 | IN UINT64 Address,\r |
265 | IN UINT8 OrData\r | |
1a3eaf06 | 266 | )\r |
267 | {\r | |
268 | return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) | OrData));\r | |
269 | }\r | |
270 | \r | |
271 | /**\r | |
122e2191 | 272 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.\r |
1a3eaf06 | 273 | \r |
122e2191 | 274 | Reads the 8-bit PCI configuration register specified by Address,\r |
275 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
276 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
277 | The value written to the PCI configuration register is returned.\r | |
278 | This function must guarantee that all PCI read and write operations are serialized.\r | |
1a3eaf06 | 279 | If any reserved bits in Address are set, then ASSERT().\r |
280 | \r | |
2fc59a00 | 281 | @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
122e2191 | 282 | @param AndData The value to AND with the PCI configuration register.\r |
1a3eaf06 | 283 | \r |
122e2191 | 284 | @return The value written to the PCI configuration register.\r |
1a3eaf06 | 285 | \r |
286 | **/\r | |
287 | UINT8\r | |
288 | EFIAPI\r | |
289 | PciSegmentAnd8 (\r | |
0c3437e0 | 290 | IN UINT64 Address,\r |
291 | IN UINT8 AndData\r | |
1a3eaf06 | 292 | )\r |
293 | {\r | |
294 | return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & AndData));\r | |
295 | }\r | |
296 | \r | |
297 | /**\r | |
122e2191 | 298 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,\r |
62991af2 | 299 | followed a bitwise OR with another 8-bit value.\r |
122e2191 | 300 | \r |
301 | Reads the 8-bit PCI configuration register specified by Address,\r | |
302 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 303 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r |
122e2191 | 304 | and writes the result to the 8-bit PCI configuration register specified by Address.\r |
305 | The value written to the PCI configuration register is returned.\r | |
306 | This function must guarantee that all PCI read and write operations are serialized.\r | |
307 | \r | |
1a3eaf06 | 308 | If any reserved bits in Address are set, then ASSERT().\r |
309 | \r | |
2fc59a00 | 310 | @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
122e2191 | 311 | @param AndData The value to AND with the PCI configuration register.\r |
312 | @param OrData The value to OR with the PCI configuration register.\r | |
1a3eaf06 | 313 | \r |
122e2191 | 314 | @return The value written to the PCI configuration register.\r |
1a3eaf06 | 315 | \r |
316 | **/\r | |
317 | UINT8\r | |
318 | EFIAPI\r | |
319 | PciSegmentAndThenOr8 (\r | |
0c3437e0 | 320 | IN UINT64 Address,\r |
321 | IN UINT8 AndData,\r | |
322 | IN UINT8 OrData\r | |
1a3eaf06 | 323 | )\r |
324 | {\r | |
325 | return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & AndData) | OrData));\r | |
326 | }\r | |
327 | \r | |
328 | /**\r | |
329 | Reads a bit field of a PCI configuration register.\r | |
330 | \r | |
331 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
332 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
333 | returned.\r | |
334 | \r | |
335 | If any reserved bits in Address are set, then ASSERT().\r | |
336 | If StartBit is greater than 7, then ASSERT().\r | |
337 | If EndBit is greater than 7, then ASSERT().\r | |
338 | If EndBit is less than StartBit, then ASSERT().\r | |
339 | \r | |
2fc59a00 | 340 | @param Address The PCI configuration register to read.\r |
1a3eaf06 | 341 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
342 | Range 0..7.\r | |
343 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
344 | Range 0..7.\r | |
345 | \r | |
346 | @return The value of the bit field read from the PCI configuration register.\r | |
347 | \r | |
348 | **/\r | |
349 | UINT8\r | |
350 | EFIAPI\r | |
351 | PciSegmentBitFieldRead8 (\r | |
0c3437e0 | 352 | IN UINT64 Address,\r |
353 | IN UINTN StartBit,\r | |
354 | IN UINTN EndBit\r | |
1a3eaf06 | 355 | )\r |
356 | {\r | |
357 | return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);\r | |
358 | }\r | |
359 | \r | |
360 | /**\r | |
361 | Writes a bit field to a PCI configuration register.\r | |
362 | \r | |
363 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
364 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
365 | destination PCI configuration register are preserved. The new value of the\r | |
366 | 8-bit register is returned.\r | |
367 | \r | |
368 | If any reserved bits in Address are set, then ASSERT().\r | |
369 | If StartBit is greater than 7, then ASSERT().\r | |
370 | If EndBit is greater than 7, then ASSERT().\r | |
371 | If EndBit is less than StartBit, then ASSERT().\r | |
372 | \r | |
2fc59a00 | 373 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 374 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
375 | Range 0..7.\r | |
376 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
377 | Range 0..7.\r | |
2fc59a00 | 378 | @param Value The new value of the bit field.\r |
1a3eaf06 | 379 | \r |
380 | @return The value written back to the PCI configuration register.\r | |
381 | \r | |
382 | **/\r | |
383 | UINT8\r | |
384 | EFIAPI\r | |
385 | PciSegmentBitFieldWrite8 (\r | |
0c3437e0 | 386 | IN UINT64 Address,\r |
387 | IN UINTN StartBit,\r | |
388 | IN UINTN EndBit,\r | |
389 | IN UINT8 Value\r | |
1a3eaf06 | 390 | )\r |
391 | {\r | |
392 | return PciSegmentWrite8 (\r | |
393 | Address,\r | |
394 | BitFieldWrite8 (PciSegmentRead8 (Address), StartBit, EndBit, Value)\r | |
395 | );\r | |
396 | }\r | |
397 | \r | |
398 | /**\r | |
399 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
400 | writes the result back to the bit field in the 8-bit port.\r | |
401 | \r | |
402 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 403 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 404 | OrData, and writes the result to the 8-bit PCI configuration register\r |
405 | specified by Address. The value written to the PCI configuration register is\r | |
406 | returned. This function must guarantee that all PCI read and write operations\r | |
407 | are serialized. Extra left bits in OrData are stripped.\r | |
408 | \r | |
409 | If any reserved bits in Address are set, then ASSERT().\r | |
410 | If StartBit is greater than 7, then ASSERT().\r | |
411 | If EndBit is greater than 7, then ASSERT().\r | |
412 | If EndBit is less than StartBit, then ASSERT().\r | |
413 | \r | |
2fc59a00 | 414 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 415 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
416 | Range 0..7.\r | |
417 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
418 | Range 0..7.\r | |
419 | @param OrData The value to OR with the PCI configuration register.\r | |
420 | \r | |
421 | @return The value written back to the PCI configuration register.\r | |
422 | \r | |
423 | **/\r | |
424 | UINT8\r | |
425 | EFIAPI\r | |
426 | PciSegmentBitFieldOr8 (\r | |
0c3437e0 | 427 | IN UINT64 Address,\r |
428 | IN UINTN StartBit,\r | |
429 | IN UINTN EndBit,\r | |
430 | IN UINT8 OrData\r | |
1a3eaf06 | 431 | )\r |
432 | {\r | |
433 | return PciSegmentWrite8 (\r | |
434 | Address,\r | |
435 | BitFieldOr8 (PciSegmentRead8 (Address), StartBit, EndBit, OrData)\r | |
436 | );\r | |
437 | }\r | |
438 | \r | |
439 | /**\r | |
440 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
441 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
442 | \r | |
443 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
444 | bitwise AND between the read result and the value specified by AndData, and\r | |
445 | writes the result to the 8-bit PCI configuration register specified by\r | |
446 | Address. The value written to the PCI configuration register is returned.\r | |
447 | This function must guarantee that all PCI read and write operations are\r | |
448 | serialized. Extra left bits in AndData are stripped.\r | |
449 | \r | |
450 | If any reserved bits in Address are set, then ASSERT().\r | |
451 | If StartBit is greater than 7, then ASSERT().\r | |
452 | If EndBit is greater than 7, then ASSERT().\r | |
453 | If EndBit is less than StartBit, then ASSERT().\r | |
454 | \r | |
2fc59a00 | 455 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 456 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
457 | Range 0..7.\r | |
458 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
459 | Range 0..7.\r | |
460 | @param AndData The value to AND with the PCI configuration register.\r | |
461 | \r | |
462 | @return The value written back to the PCI configuration register.\r | |
463 | \r | |
464 | **/\r | |
465 | UINT8\r | |
466 | EFIAPI\r | |
467 | PciSegmentBitFieldAnd8 (\r | |
0c3437e0 | 468 | IN UINT64 Address,\r |
469 | IN UINTN StartBit,\r | |
470 | IN UINTN EndBit,\r | |
471 | IN UINT8 AndData\r | |
1a3eaf06 | 472 | )\r |
473 | {\r | |
474 | return PciSegmentWrite8 (\r | |
475 | Address,\r | |
476 | BitFieldAnd8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData)\r | |
477 | );\r | |
478 | }\r | |
479 | \r | |
480 | /**\r | |
481 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 482 | bitwise OR, and writes the result back to the bit field in the\r |
1a3eaf06 | 483 | 8-bit port.\r |
484 | \r | |
485 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 486 | bitwise AND followed by a bitwise OR between the read result and\r |
1a3eaf06 | 487 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
488 | configuration register specified by Address. The value written to the PCI\r | |
489 | configuration register is returned. This function must guarantee that all PCI\r | |
490 | read and write operations are serialized. Extra left bits in both AndData and\r | |
491 | OrData are stripped.\r | |
492 | \r | |
493 | If any reserved bits in Address are set, then ASSERT().\r | |
494 | If StartBit is greater than 7, then ASSERT().\r | |
495 | If EndBit is greater than 7, then ASSERT().\r | |
496 | If EndBit is less than StartBit, then ASSERT().\r | |
497 | \r | |
2fc59a00 | 498 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 499 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
500 | Range 0..7.\r | |
501 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
502 | Range 0..7.\r | |
503 | @param AndData The value to AND with the PCI configuration register.\r | |
504 | @param OrData The value to OR with the result of the AND operation.\r | |
505 | \r | |
506 | @return The value written back to the PCI configuration register.\r | |
507 | \r | |
508 | **/\r | |
509 | UINT8\r | |
510 | EFIAPI\r | |
511 | PciSegmentBitFieldAndThenOr8 (\r | |
0c3437e0 | 512 | IN UINT64 Address,\r |
513 | IN UINTN StartBit,\r | |
514 | IN UINTN EndBit,\r | |
515 | IN UINT8 AndData,\r | |
516 | IN UINT8 OrData\r | |
1a3eaf06 | 517 | )\r |
518 | {\r | |
519 | return PciSegmentWrite8 (\r | |
520 | Address,\r | |
521 | BitFieldAndThenOr8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData, OrData)\r | |
522 | );\r | |
523 | }\r | |
524 | \r | |
525 | /**\r | |
526 | Reads a 16-bit PCI configuration register.\r | |
527 | \r | |
528 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
d5979dc0 | 529 | This function must guarantee that all PCI read and write operations are serialized.\r |
530 | \r | |
1a3eaf06 | 531 | If any reserved bits in Address are set, then ASSERT().\r |
d5979dc0 | 532 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
533 | \r | |
2fc59a00 | 534 | @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
1a3eaf06 | 535 | \r |
d5979dc0 | 536 | @return The 16-bit PCI configuration register specified by Address.\r |
1a3eaf06 | 537 | \r |
538 | **/\r | |
539 | UINT16\r | |
540 | EFIAPI\r | |
541 | PciSegmentRead16 (\r | |
0c3437e0 | 542 | IN UINT64 Address\r |
1a3eaf06 | 543 | )\r |
544 | {\r | |
545 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);\r | |
546 | \r | |
547 | return (UINT16) PeiPciSegmentLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint16);\r | |
548 | }\r | |
549 | \r | |
550 | /**\r | |
551 | Writes a 16-bit PCI configuration register.\r | |
552 | \r | |
d5979dc0 | 553 | Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.\r |
554 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
555 | \r | |
1a3eaf06 | 556 | If any reserved bits in Address are set, then ASSERT().\r |
d5979dc0 | 557 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
1a3eaf06 | 558 | \r |
2fc59a00 | 559 | @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
d5979dc0 | 560 | @param Value The value to write.\r |
1a3eaf06 | 561 | \r |
d5979dc0 | 562 | @return The parameter of Value.\r |
1a3eaf06 | 563 | \r |
564 | **/\r | |
565 | UINT16\r | |
566 | EFIAPI\r | |
567 | PciSegmentWrite16 (\r | |
0c3437e0 | 568 | IN UINT64 Address,\r |
569 | IN UINT16 Value\r | |
1a3eaf06 | 570 | )\r |
571 | {\r | |
572 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);\r | |
573 | \r | |
d5979dc0 | 574 | return (UINT16) PeiPciSegmentLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint16, Value);\r |
1a3eaf06 | 575 | }\r |
576 | \r | |
577 | /**\r | |
62991af2 | 578 | Performs a bitwise OR of a 16-bit PCI configuration register with\r |
1a3eaf06 | 579 | a 16-bit value.\r |
580 | \r | |
581 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 582 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 583 | OrData, and writes the result to the 16-bit PCI configuration register\r |
584 | specified by Address. The value written to the PCI configuration register is\r | |
585 | returned. This function must guarantee that all PCI read and write operations\r | |
586 | are serialized.\r | |
587 | \r | |
588 | If any reserved bits in Address are set, then ASSERT().\r | |
d5979dc0 | 589 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
1a3eaf06 | 590 | \r |
2fc59a00 | 591 | @param Address The address that encodes the PCI Segment, Bus, Device, Function and\r |
1a3eaf06 | 592 | Register.\r |
593 | @param OrData The value to OR with the PCI configuration register.\r | |
594 | \r | |
595 | @return The value written back to the PCI configuration register.\r | |
596 | \r | |
597 | **/\r | |
598 | UINT16\r | |
599 | EFIAPI\r | |
600 | PciSegmentOr16 (\r | |
0c3437e0 | 601 | IN UINT64 Address,\r |
602 | IN UINT16 OrData\r | |
1a3eaf06 | 603 | )\r |
604 | {\r | |
605 | return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData));\r | |
606 | }\r | |
607 | \r | |
608 | /**\r | |
122e2191 | 609 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.\r |
1a3eaf06 | 610 | \r |
122e2191 | 611 | Reads the 16-bit PCI configuration register specified by Address,\r |
612 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
613 | and writes the result to the 16-bit PCI configuration register specified by Address.\r | |
614 | The value written to the PCI configuration register is returned.\r | |
615 | This function must guarantee that all PCI read and write operations are serialized.\r | |
616 | \r | |
1a3eaf06 | 617 | If any reserved bits in Address are set, then ASSERT().\r |
122e2191 | 618 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
619 | \r | |
2fc59a00 | 620 | @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
122e2191 | 621 | @param AndData The value to AND with the PCI configuration register.\r |
1a3eaf06 | 622 | \r |
122e2191 | 623 | @return The value written to the PCI configuration register.\r |
1a3eaf06 | 624 | \r |
625 | **/\r | |
626 | UINT16\r | |
627 | EFIAPI\r | |
628 | PciSegmentAnd16 (\r | |
0c3437e0 | 629 | IN UINT64 Address,\r |
630 | IN UINT16 AndData\r | |
1a3eaf06 | 631 | )\r |
632 | {\r | |
633 | return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData));\r | |
634 | }\r | |
635 | \r | |
636 | /**\r | |
d5979dc0 | 637 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,\r |
62991af2 | 638 | followed a bitwise OR with another 16-bit value.\r |
d5979dc0 | 639 | \r |
640 | Reads the 16-bit PCI configuration register specified by Address,\r | |
641 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 642 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r |
d5979dc0 | 643 | and writes the result to the 16-bit PCI configuration register specified by Address.\r |
644 | The value written to the PCI configuration register is returned.\r | |
645 | This function must guarantee that all PCI read and write operations are serialized.\r | |
646 | \r | |
1a3eaf06 | 647 | If any reserved bits in Address are set, then ASSERT().\r |
d5979dc0 | 648 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
1a3eaf06 | 649 | \r |
2fc59a00 | 650 | @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
58380e9c | 651 | @param AndData The value to AND with the PCI configuration register.\r |
d5979dc0 | 652 | @param OrData The value to OR with the PCI configuration register.\r |
1a3eaf06 | 653 | \r |
d5979dc0 | 654 | @return The value written to the PCI configuration register.\r |
1a3eaf06 | 655 | \r |
656 | **/\r | |
657 | UINT16\r | |
658 | EFIAPI\r | |
659 | PciSegmentAndThenOr16 (\r | |
0c3437e0 | 660 | IN UINT64 Address,\r |
661 | IN UINT16 AndData,\r | |
662 | IN UINT16 OrData\r | |
1a3eaf06 | 663 | )\r |
664 | {\r | |
665 | return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData));\r | |
666 | }\r | |
667 | \r | |
668 | /**\r | |
669 | Reads a bit field of a PCI configuration register.\r | |
670 | \r | |
671 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
672 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
673 | returned.\r | |
674 | \r | |
675 | If any reserved bits in Address are set, then ASSERT().\r | |
d5979dc0 | 676 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
1a3eaf06 | 677 | If StartBit is greater than 15, then ASSERT().\r |
678 | If EndBit is greater than 15, then ASSERT().\r | |
679 | If EndBit is less than StartBit, then ASSERT().\r | |
680 | \r | |
2fc59a00 | 681 | @param Address The PCI configuration register to read.\r |
1a3eaf06 | 682 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
683 | Range 0..15.\r | |
684 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
685 | Range 0..15.\r | |
686 | \r | |
687 | @return The value of the bit field read from the PCI configuration register.\r | |
688 | \r | |
689 | **/\r | |
690 | UINT16\r | |
691 | EFIAPI\r | |
692 | PciSegmentBitFieldRead16 (\r | |
0c3437e0 | 693 | IN UINT64 Address,\r |
694 | IN UINTN StartBit,\r | |
695 | IN UINTN EndBit\r | |
1a3eaf06 | 696 | )\r |
697 | {\r | |
698 | return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);\r | |
699 | }\r | |
700 | \r | |
701 | /**\r | |
702 | Writes a bit field to a PCI configuration register.\r | |
703 | \r | |
704 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
705 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
706 | destination PCI configuration register are preserved. The new value of the\r | |
707 | 16-bit register is returned.\r | |
708 | \r | |
709 | If any reserved bits in Address are set, then ASSERT().\r | |
d5979dc0 | 710 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
1a3eaf06 | 711 | If StartBit is greater than 15, then ASSERT().\r |
712 | If EndBit is greater than 15, then ASSERT().\r | |
713 | If EndBit is less than StartBit, then ASSERT().\r | |
714 | \r | |
2fc59a00 | 715 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 716 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
717 | Range 0..15.\r | |
718 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
719 | Range 0..15.\r | |
2fc59a00 | 720 | @param Value The new value of the bit field.\r |
1a3eaf06 | 721 | \r |
722 | @return The value written back to the PCI configuration register.\r | |
723 | \r | |
724 | **/\r | |
725 | UINT16\r | |
726 | EFIAPI\r | |
727 | PciSegmentBitFieldWrite16 (\r | |
0c3437e0 | 728 | IN UINT64 Address,\r |
729 | IN UINTN StartBit,\r | |
730 | IN UINTN EndBit,\r | |
731 | IN UINT16 Value\r | |
1a3eaf06 | 732 | )\r |
733 | {\r | |
734 | return PciSegmentWrite16 (\r | |
735 | Address,\r | |
736 | BitFieldWrite16 (PciSegmentRead16 (Address), StartBit, EndBit, Value)\r | |
737 | );\r | |
738 | }\r | |
739 | \r | |
740 | /**\r | |
d5979dc0 | 741 | Reads the 16-bit PCI configuration register specified by Address,\r |
62991af2 | 742 | performs a bitwise OR between the read result and the value specified by OrData,\r |
d5979dc0 | 743 | and writes the result to the 16-bit PCI configuration register specified by Address. \r |
1a3eaf06 | 744 | \r |
745 | If any reserved bits in Address are set, then ASSERT().\r | |
d5979dc0 | 746 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
1a3eaf06 | 747 | If StartBit is greater than 15, then ASSERT().\r |
748 | If EndBit is greater than 15, then ASSERT().\r | |
749 | If EndBit is less than StartBit, then ASSERT().\r | |
750 | \r | |
2fc59a00 | 751 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 752 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
753 | Range 0..15.\r | |
754 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
755 | Range 0..15.\r | |
756 | @param OrData The value to OR with the PCI configuration register.\r | |
757 | \r | |
758 | @return The value written back to the PCI configuration register.\r | |
759 | \r | |
760 | **/\r | |
761 | UINT16\r | |
762 | EFIAPI\r | |
763 | PciSegmentBitFieldOr16 (\r | |
0c3437e0 | 764 | IN UINT64 Address,\r |
765 | IN UINTN StartBit,\r | |
766 | IN UINTN EndBit,\r | |
767 | IN UINT16 OrData\r | |
1a3eaf06 | 768 | )\r |
769 | {\r | |
770 | return PciSegmentWrite16 (\r | |
771 | Address,\r | |
772 | BitFieldOr16 (PciSegmentRead16 (Address), StartBit, EndBit, OrData)\r | |
773 | );\r | |
774 | }\r | |
775 | \r | |
776 | /**\r | |
0c3437e0 | 777 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,\r |
778 | and writes the result back to the bit field in the 16-bit port.\r | |
1a3eaf06 | 779 | \r |
0c3437e0 | 780 | Reads the 16-bit PCI configuration register specified by Address,\r |
781 | performs a bitwise OR between the read result and the value specified by OrData,\r | |
782 | and writes the result to the 16-bit PCI configuration register specified by Address.\r | |
783 | The value written to the PCI configuration register is returned.\r | |
784 | This function must guarantee that all PCI read and write operations are serialized.\r | |
785 | Extra left bits in OrData are stripped.\r | |
786 | \r | |
1a3eaf06 | 787 | If any reserved bits in Address are set, then ASSERT().\r |
0c3437e0 | 788 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
789 | If StartBit is greater than 7, then ASSERT().\r | |
790 | If EndBit is greater than 7, then ASSERT().\r | |
1a3eaf06 | 791 | If EndBit is less than StartBit, then ASSERT().\r |
792 | \r | |
2fc59a00 | 793 | @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
1a3eaf06 | 794 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
0c3437e0 | 795 | The ordinal of the least significant bit in a byte is bit 0.\r |
1a3eaf06 | 796 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
0c3437e0 | 797 | The ordinal of the most significant bit in a byte is bit 7.\r |
798 | @param AndData The value to AND with the read value from the PCI configuration register.\r | |
1a3eaf06 | 799 | \r |
0c3437e0 | 800 | @return The value written to the PCI configuration register.\r |
1a3eaf06 | 801 | \r |
802 | **/\r | |
803 | UINT16\r | |
804 | EFIAPI\r | |
805 | PciSegmentBitFieldAnd16 (\r | |
0c3437e0 | 806 | IN UINT64 Address,\r |
807 | IN UINTN StartBit,\r | |
808 | IN UINTN EndBit,\r | |
809 | IN UINT16 AndData\r | |
1a3eaf06 | 810 | )\r |
811 | {\r | |
812 | return PciSegmentWrite16 (\r | |
813 | Address,\r | |
814 | BitFieldAnd16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData)\r | |
815 | );\r | |
816 | }\r | |
817 | \r | |
818 | /**\r | |
819 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 820 | bitwise OR, and writes the result back to the bit field in the\r |
1a3eaf06 | 821 | 16-bit port.\r |
822 | \r | |
823 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 824 | bitwise AND followed by a bitwise OR between the read result and\r |
1a3eaf06 | 825 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
826 | configuration register specified by Address. The value written to the PCI\r | |
827 | configuration register is returned. This function must guarantee that all PCI\r | |
828 | read and write operations are serialized. Extra left bits in both AndData and\r | |
829 | OrData are stripped.\r | |
830 | \r | |
831 | If any reserved bits in Address are set, then ASSERT().\r | |
832 | If StartBit is greater than 15, then ASSERT().\r | |
833 | If EndBit is greater than 15, then ASSERT().\r | |
834 | If EndBit is less than StartBit, then ASSERT().\r | |
835 | \r | |
2fc59a00 | 836 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 837 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
838 | Range 0..15.\r | |
839 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
840 | Range 0..15.\r | |
841 | @param AndData The value to AND with the PCI configuration register.\r | |
842 | @param OrData The value to OR with the result of the AND operation.\r | |
843 | \r | |
844 | @return The value written back to the PCI configuration register.\r | |
845 | \r | |
846 | **/\r | |
847 | UINT16\r | |
848 | EFIAPI\r | |
849 | PciSegmentBitFieldAndThenOr16 (\r | |
0c3437e0 | 850 | IN UINT64 Address,\r |
851 | IN UINTN StartBit,\r | |
852 | IN UINTN EndBit,\r | |
853 | IN UINT16 AndData,\r | |
854 | IN UINT16 OrData\r | |
1a3eaf06 | 855 | )\r |
856 | {\r | |
857 | return PciSegmentWrite16 (\r | |
858 | Address,\r | |
859 | BitFieldAndThenOr16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData, OrData)\r | |
860 | );\r | |
861 | }\r | |
862 | \r | |
863 | /**\r | |
864 | Reads a 32-bit PCI configuration register.\r | |
865 | \r | |
866 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
d5979dc0 | 867 | This function must guarantee that all PCI read and write operations are serialized.\r |
868 | \r | |
1a3eaf06 | 869 | If any reserved bits in Address are set, then ASSERT().\r |
d5979dc0 | 870 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
1a3eaf06 | 871 | \r |
58380e9c | 872 | @param Address The address that encodes the PCI Segment, Bus, Device, Function, \r |
873 | and Register.\r | |
1a3eaf06 | 874 | \r |
d5979dc0 | 875 | @return The 32-bit PCI configuration register specified by Address.\r |
1a3eaf06 | 876 | \r |
877 | **/\r | |
878 | UINT32\r | |
879 | EFIAPI\r | |
880 | PciSegmentRead32 (\r | |
0c3437e0 | 881 | IN UINT64 Address\r |
1a3eaf06 | 882 | )\r |
883 | {\r | |
884 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);\r | |
885 | \r | |
886 | return PeiPciSegmentLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint32);\r | |
887 | }\r | |
888 | \r | |
889 | /**\r | |
890 | Writes a 32-bit PCI configuration register.\r | |
891 | \r | |
d5979dc0 | 892 | Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.\r |
893 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
894 | \r | |
1a3eaf06 | 895 | If any reserved bits in Address are set, then ASSERT().\r |
d5979dc0 | 896 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
1a3eaf06 | 897 | \r |
58380e9c | 898 | @param Address The address that encodes the PCI Segment, Bus, Device, \r |
899 | Function, and Register.\r | |
d5979dc0 | 900 | @param Value The value to write.\r |
1a3eaf06 | 901 | \r |
d5979dc0 | 902 | @return The parameter of Value.\r |
1a3eaf06 | 903 | \r |
904 | **/\r | |
905 | UINT32\r | |
906 | EFIAPI\r | |
907 | PciSegmentWrite32 (\r | |
0c3437e0 | 908 | IN UINT64 Address,\r |
909 | IN UINT32 Value\r | |
1a3eaf06 | 910 | )\r |
911 | {\r | |
912 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);\r | |
913 | \r | |
d5979dc0 | 914 | return PeiPciSegmentLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint32, Value);\r |
1a3eaf06 | 915 | }\r |
916 | \r | |
917 | /**\r | |
62991af2 | 918 | Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.\r |
1a3eaf06 | 919 | \r |
d5979dc0 | 920 | Reads the 32-bit PCI configuration register specified by Address,\r |
62991af2 | 921 | performs a bitwise OR between the read result and the value specified by OrData,\r |
d5979dc0 | 922 | and writes the result to the 32-bit PCI configuration register specified by Address.\r |
923 | The value written to the PCI configuration register is returned.\r | |
924 | This function must guarantee that all PCI read and write operations are serialized.\r | |
925 | \r | |
1a3eaf06 | 926 | If any reserved bits in Address are set, then ASSERT().\r |
d5979dc0 | 927 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
1a3eaf06 | 928 | \r |
2fc59a00 | 929 | @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
d5979dc0 | 930 | @param OrData The value to OR with the PCI configuration register.\r |
1a3eaf06 | 931 | \r |
d5979dc0 | 932 | @return The value written to the PCI configuration register.\r |
1a3eaf06 | 933 | \r |
934 | **/\r | |
935 | UINT32\r | |
936 | EFIAPI\r | |
937 | PciSegmentOr32 (\r | |
0c3437e0 | 938 | IN UINT64 Address,\r |
939 | IN UINT32 OrData\r | |
1a3eaf06 | 940 | )\r |
941 | {\r | |
942 | return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);\r | |
943 | }\r | |
944 | \r | |
945 | /**\r | |
122e2191 | 946 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.\r |
1a3eaf06 | 947 | \r |
122e2191 | 948 | Reads the 32-bit PCI configuration register specified by Address,\r |
949 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
950 | and writes the result to the 32-bit PCI configuration register specified by Address.\r | |
951 | The value written to the PCI configuration register is returned.\r | |
952 | This function must guarantee that all PCI read and write operations are serialized.\r | |
953 | \r | |
1a3eaf06 | 954 | If any reserved bits in Address are set, then ASSERT().\r |
122e2191 | 955 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
1a3eaf06 | 956 | \r |
58380e9c | 957 | @param Address The address that encodes the PCI Segment, Bus, Device, Function, \r |
958 | and Register.\r | |
122e2191 | 959 | @param AndData The value to AND with the PCI configuration register.\r |
1a3eaf06 | 960 | \r |
122e2191 | 961 | @return The value written to the PCI configuration register.\r |
1a3eaf06 | 962 | \r |
963 | **/\r | |
964 | UINT32\r | |
965 | EFIAPI\r | |
966 | PciSegmentAnd32 (\r | |
0c3437e0 | 967 | IN UINT64 Address,\r |
968 | IN UINT32 AndData\r | |
1a3eaf06 | 969 | )\r |
970 | {\r | |
971 | return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData);\r | |
972 | }\r | |
973 | \r | |
974 | /**\r | |
122e2191 | 975 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,\r |
62991af2 | 976 | followed a bitwise OR with another 32-bit value.\r |
122e2191 | 977 | \r |
978 | Reads the 32-bit PCI configuration register specified by Address,\r | |
979 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 980 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r |
122e2191 | 981 | and writes the result to the 32-bit PCI configuration register specified by Address.\r |
982 | The value written to the PCI configuration register is returned.\r | |
983 | This function must guarantee that all PCI read and write operations are serialized.\r | |
984 | \r | |
1a3eaf06 | 985 | If any reserved bits in Address are set, then ASSERT().\r |
122e2191 | 986 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
1a3eaf06 | 987 | \r |
58380e9c | 988 | @param Address The address that encodes the PCI Segment, Bus, Device, Function,\r |
989 | and Register.\r | |
122e2191 | 990 | @param AndData The value to AND with the PCI configuration register.\r |
991 | @param OrData The value to OR with the PCI configuration register.\r | |
1a3eaf06 | 992 | \r |
122e2191 | 993 | @return The value written to the PCI configuration register.\r |
1a3eaf06 | 994 | \r |
995 | **/\r | |
996 | UINT32\r | |
997 | EFIAPI\r | |
998 | PciSegmentAndThenOr32 (\r | |
0c3437e0 | 999 | IN UINT64 Address,\r |
1000 | IN UINT32 AndData,\r | |
1001 | IN UINT32 OrData\r | |
1a3eaf06 | 1002 | )\r |
1003 | {\r | |
1004 | return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData);\r | |
1005 | }\r | |
1006 | \r | |
1007 | /**\r | |
1008 | Reads a bit field of a PCI configuration register.\r | |
1009 | \r | |
1010 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
1011 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
1012 | returned.\r | |
1013 | \r | |
1014 | If any reserved bits in Address are set, then ASSERT().\r | |
d5979dc0 | 1015 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
1a3eaf06 | 1016 | If StartBit is greater than 31, then ASSERT().\r |
1017 | If EndBit is greater than 31, then ASSERT().\r | |
1018 | If EndBit is less than StartBit, then ASSERT().\r | |
1019 | \r | |
2fc59a00 | 1020 | @param Address The PCI configuration register to read.\r |
1a3eaf06 | 1021 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1022 | Range 0..31.\r | |
1023 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1024 | Range 0..31.\r | |
1025 | \r | |
1026 | @return The value of the bit field read from the PCI configuration register.\r | |
1027 | \r | |
1028 | **/\r | |
1029 | UINT32\r | |
1030 | EFIAPI\r | |
1031 | PciSegmentBitFieldRead32 (\r | |
0c3437e0 | 1032 | IN UINT64 Address,\r |
1033 | IN UINTN StartBit,\r | |
1034 | IN UINTN EndBit\r | |
1a3eaf06 | 1035 | )\r |
1036 | {\r | |
1037 | return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);\r | |
1038 | }\r | |
1039 | \r | |
1040 | /**\r | |
1041 | Writes a bit field to a PCI configuration register.\r | |
1042 | \r | |
1043 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
1044 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
1045 | destination PCI configuration register are preserved. The new value of the\r | |
1046 | 32-bit register is returned.\r | |
1047 | \r | |
1048 | If any reserved bits in Address are set, then ASSERT().\r | |
d5979dc0 | 1049 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
1a3eaf06 | 1050 | If StartBit is greater than 31, then ASSERT().\r |
1051 | If EndBit is greater than 31, then ASSERT().\r | |
1052 | If EndBit is less than StartBit, then ASSERT().\r | |
1053 | \r | |
2fc59a00 | 1054 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 1055 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1056 | Range 0..31.\r | |
1057 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1058 | Range 0..31.\r | |
2fc59a00 | 1059 | @param Value The new value of the bit field.\r |
1a3eaf06 | 1060 | \r |
1061 | @return The value written back to the PCI configuration register.\r | |
1062 | \r | |
1063 | **/\r | |
1064 | UINT32\r | |
1065 | EFIAPI\r | |
1066 | PciSegmentBitFieldWrite32 (\r | |
0c3437e0 | 1067 | IN UINT64 Address,\r |
1068 | IN UINTN StartBit,\r | |
1069 | IN UINTN EndBit,\r | |
1070 | IN UINT32 Value\r | |
1a3eaf06 | 1071 | )\r |
1072 | {\r | |
1073 | return PciSegmentWrite32 (\r | |
1074 | Address,\r | |
1075 | BitFieldWrite32 (PciSegmentRead32 (Address), StartBit, EndBit, Value)\r | |
1076 | );\r | |
1077 | }\r | |
1078 | \r | |
1079 | /**\r | |
1080 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
1081 | writes the result back to the bit field in the 32-bit port.\r | |
1082 | \r | |
1083 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 1084 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 1085 | OrData, and writes the result to the 32-bit PCI configuration register\r |
1086 | specified by Address. The value written to the PCI configuration register is\r | |
1087 | returned. This function must guarantee that all PCI read and write operations\r | |
1088 | are serialized. Extra left bits in OrData are stripped.\r | |
1089 | \r | |
1090 | If any reserved bits in Address are set, then ASSERT().\r | |
1091 | If StartBit is greater than 31, then ASSERT().\r | |
1092 | If EndBit is greater than 31, then ASSERT().\r | |
1093 | If EndBit is less than StartBit, then ASSERT().\r | |
1094 | \r | |
2fc59a00 | 1095 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 1096 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1097 | Range 0..31.\r | |
1098 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1099 | Range 0..31.\r | |
1100 | @param OrData The value to OR with the PCI configuration register.\r | |
1101 | \r | |
1102 | @return The value written back to the PCI configuration register.\r | |
1103 | \r | |
1104 | **/\r | |
1105 | UINT32\r | |
1106 | EFIAPI\r | |
1107 | PciSegmentBitFieldOr32 (\r | |
0c3437e0 | 1108 | IN UINT64 Address,\r |
1109 | IN UINTN StartBit,\r | |
1110 | IN UINTN EndBit,\r | |
1111 | IN UINT32 OrData\r | |
1a3eaf06 | 1112 | )\r |
1113 | {\r | |
1114 | return PciSegmentWrite32 (\r | |
1115 | Address,\r | |
1116 | BitFieldOr32 (PciSegmentRead32 (Address), StartBit, EndBit, OrData)\r | |
1117 | );\r | |
1118 | }\r | |
1119 | \r | |
1120 | /**\r | |
1121 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
1122 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
1123 | \r | |
0c3437e0 | 1124 | \r |
1125 | Reads the 32-bit PCI configuration register specified by Address, performs a bitwise\r | |
1126 | AND between the read result and the value specified by AndData, and writes the result\r | |
1127 | to the 32-bit PCI configuration register specified by Address. The value written to\r | |
1128 | the PCI configuration register is returned. This function must guarantee that all PCI\r | |
1129 | read and write operations are serialized. Extra left bits in AndData are stripped.\r | |
1a3eaf06 | 1130 | If any reserved bits in Address are set, then ASSERT().\r |
0c3437e0 | 1131 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
1a3eaf06 | 1132 | If StartBit is greater than 31, then ASSERT().\r |
1133 | If EndBit is greater than 31, then ASSERT().\r | |
1134 | If EndBit is less than StartBit, then ASSERT().\r | |
0c3437e0 | 1135 | \r |
1a3eaf06 | 1136 | \r |
2fc59a00 | 1137 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 1138 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1139 | Range 0..31.\r | |
1140 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1141 | Range 0..31.\r | |
1142 | @param AndData The value to AND with the PCI configuration register.\r | |
1143 | \r | |
1144 | @return The value written back to the PCI configuration register.\r | |
1145 | \r | |
1146 | **/\r | |
1147 | UINT32\r | |
1148 | EFIAPI\r | |
1149 | PciSegmentBitFieldAnd32 (\r | |
0c3437e0 | 1150 | IN UINT64 Address,\r |
1151 | IN UINTN StartBit,\r | |
1152 | IN UINTN EndBit,\r | |
1153 | IN UINT32 AndData\r | |
1a3eaf06 | 1154 | )\r |
1155 | {\r | |
1156 | return PciSegmentWrite32 (\r | |
1157 | Address,\r | |
1158 | BitFieldAnd32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData)\r | |
1159 | );\r | |
1160 | }\r | |
1161 | \r | |
1162 | /**\r | |
1163 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 1164 | bitwise OR, and writes the result back to the bit field in the\r |
1a3eaf06 | 1165 | 32-bit port.\r |
1166 | \r | |
1167 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 1168 | bitwise AND followed by a bitwise OR between the read result and\r |
1a3eaf06 | 1169 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
1170 | configuration register specified by Address. The value written to the PCI\r | |
1171 | configuration register is returned. This function must guarantee that all PCI\r | |
1172 | read and write operations are serialized. Extra left bits in both AndData and\r | |
1173 | OrData are stripped.\r | |
1174 | \r | |
1175 | If any reserved bits in Address are set, then ASSERT().\r | |
1176 | If StartBit is greater than 31, then ASSERT().\r | |
1177 | If EndBit is greater than 31, then ASSERT().\r | |
1178 | If EndBit is less than StartBit, then ASSERT().\r | |
1179 | \r | |
2fc59a00 | 1180 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 1181 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1182 | Range 0..31.\r | |
1183 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1184 | Range 0..31.\r | |
1185 | @param AndData The value to AND with the PCI configuration register.\r | |
1186 | @param OrData The value to OR with the result of the AND operation.\r | |
1187 | \r | |
1188 | @return The value written back to the PCI configuration register.\r | |
1189 | \r | |
1190 | **/\r | |
1191 | UINT32\r | |
1192 | EFIAPI\r | |
1193 | PciSegmentBitFieldAndThenOr32 (\r | |
0c3437e0 | 1194 | IN UINT64 Address,\r |
1195 | IN UINTN StartBit,\r | |
1196 | IN UINTN EndBit,\r | |
1197 | IN UINT32 AndData,\r | |
1198 | IN UINT32 OrData\r | |
1a3eaf06 | 1199 | )\r |
1200 | {\r | |
1201 | return PciSegmentWrite32 (\r | |
1202 | Address,\r | |
1203 | BitFieldAndThenOr32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData, OrData)\r | |
1204 | );\r | |
1205 | }\r | |
1206 | \r | |
1207 | /**\r | |
1208 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
1209 | \r | |
0c3437e0 | 1210 | Reads the range of PCI configuration registers specified by StartAddress and\r |
1211 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
1212 | configuration registers from a single PCI function to be read. Size is\r | |
1213 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
1214 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
1215 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
1216 | end of the range.\r | |
1217 | \r | |
59ceeabe | 1218 | If any reserved bits in StartAddress are set, then ASSERT().\r |
1a3eaf06 | 1219 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
1220 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1221 | \r | |
58380e9c | 1222 | @param StartAddress The starting address that encodes the PCI Segment, Bus, \r |
1223 | Device, Function and Register.\r | |
2fc59a00 | 1224 | @param Size The size in bytes of the transfer.\r |
1225 | @param Buffer The pointer to a buffer receiving the data read.\r | |
1a3eaf06 | 1226 | \r |
0c3437e0 | 1227 | @return Size\r |
1a3eaf06 | 1228 | \r |
1229 | **/\r | |
1230 | UINTN\r | |
1231 | EFIAPI\r | |
1232 | PciSegmentReadBuffer (\r | |
0c3437e0 | 1233 | IN UINT64 StartAddress,\r |
1234 | IN UINTN Size,\r | |
1235 | OUT VOID *Buffer\r | |
1a3eaf06 | 1236 | )\r |
1237 | {\r | |
1238 | UINTN ReturnValue;\r | |
1239 | \r | |
1240 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);\r | |
1241 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r | |
1242 | \r | |
1243 | if (Size == 0) {\r | |
1244 | return Size;\r | |
1245 | }\r | |
1246 | \r | |
1247 | ASSERT (Buffer != NULL);\r | |
1248 | \r | |
1249 | //\r | |
1250 | // Save Size for return\r | |
1251 | //\r | |
1252 | ReturnValue = Size;\r | |
1253 | \r | |
e43e4b3e | 1254 | if ((StartAddress & BIT0) != 0) {\r |
1a3eaf06 | 1255 | //\r |
1256 | // Read a byte if StartAddress is byte aligned\r | |
1257 | //\r | |
1258 | *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);\r | |
1259 | StartAddress += sizeof (UINT8);\r | |
1260 | Size -= sizeof (UINT8);\r | |
1261 | Buffer = (UINT8*)Buffer + 1;\r | |
1262 | }\r | |
1263 | \r | |
e43e4b3e | 1264 | if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r |
1a3eaf06 | 1265 | //\r |
1266 | // Read a word if StartAddress is word aligned\r | |
1267 | //\r | |
5dc4fd78 | 1268 | WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));\r |
1a3eaf06 | 1269 | StartAddress += sizeof (UINT16);\r |
1270 | Size -= sizeof (UINT16);\r | |
1271 | Buffer = (UINT16*)Buffer + 1;\r | |
1272 | }\r | |
1273 | \r | |
1274 | while (Size >= sizeof (UINT32)) {\r | |
1275 | //\r | |
1276 | // Read as many double words as possible\r | |
1277 | //\r | |
5dc4fd78 | 1278 | WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress));\r |
1a3eaf06 | 1279 | StartAddress += sizeof (UINT32);\r |
1280 | Size -= sizeof (UINT32);\r | |
1281 | Buffer = (UINT32*)Buffer + 1;\r | |
1282 | }\r | |
1283 | \r | |
1284 | if (Size >= sizeof (UINT16)) {\r | |
1285 | //\r | |
1286 | // Read the last remaining word if exist\r | |
1287 | //\r | |
5dc4fd78 | 1288 | WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));\r |
1a3eaf06 | 1289 | StartAddress += sizeof (UINT16);\r |
1290 | Size -= sizeof (UINT16);\r | |
1291 | Buffer = (UINT16*)Buffer + 1;\r | |
1292 | }\r | |
1293 | \r | |
1294 | if (Size >= sizeof (UINT8)) {\r | |
1295 | //\r | |
1296 | // Read the last remaining byte if exist\r | |
1297 | //\r | |
1298 | *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);\r | |
1299 | }\r | |
1300 | \r | |
1301 | return ReturnValue;\r | |
1302 | }\r | |
1303 | \r | |
d5979dc0 | 1304 | \r |
1a3eaf06 | 1305 | /**\r |
0c3437e0 | 1306 | Copies the data in a caller supplied buffer to a specified range of PCI\r |
1307 | configuration space.\r | |
1308 | \r | |
1309 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1310 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1311 | configuration registers from a single PCI function to be written. Size is\r | |
1312 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1313 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1314 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1315 | and the end of the range.\r | |
1316 | \r | |
59ceeabe | 1317 | If any reserved bits in StartAddress are set, then ASSERT().\r |
1a3eaf06 | 1318 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
1319 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1320 | \r | |
58380e9c | 1321 | @param StartAddress The starting address that encodes the PCI Segment, Bus, \r |
1322 | Device, Function and Register.\r | |
2fc59a00 | 1323 | @param Size The size in bytes of the transfer.\r |
1324 | @param Buffer The pointer to a buffer containing the data to write.\r | |
1a3eaf06 | 1325 | \r |
d5979dc0 | 1326 | @return The parameter of Size.\r |
1a3eaf06 | 1327 | \r |
1328 | **/\r | |
1329 | UINTN\r | |
1330 | EFIAPI\r | |
1331 | PciSegmentWriteBuffer (\r | |
0c3437e0 | 1332 | IN UINT64 StartAddress,\r |
1333 | IN UINTN Size,\r | |
1334 | IN VOID *Buffer\r | |
1a3eaf06 | 1335 | )\r |
1336 | {\r | |
1337 | UINTN ReturnValue;\r | |
1338 | \r | |
1339 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);\r | |
1340 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r | |
1341 | \r | |
1342 | if (Size == 0) {\r | |
1343 | return 0;\r | |
1344 | }\r | |
1345 | \r | |
1346 | ASSERT (Buffer != NULL);\r | |
1347 | \r | |
1348 | //\r | |
1349 | // Save Size for return\r | |
1350 | //\r | |
1351 | ReturnValue = Size;\r | |
1352 | \r | |
e43e4b3e | 1353 | if ((StartAddress & BIT0) != 0) {\r |
1a3eaf06 | 1354 | //\r |
1355 | // Write a byte if StartAddress is byte aligned\r | |
1356 | //\r | |
1357 | PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);\r | |
1358 | StartAddress += sizeof (UINT8);\r | |
1359 | Size -= sizeof (UINT8);\r | |
1360 | Buffer = (UINT8*)Buffer + 1;\r | |
1361 | }\r | |
1362 | \r | |
e43e4b3e | 1363 | if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r |
1a3eaf06 | 1364 | //\r |
1365 | // Write a word if StartAddress is word aligned\r | |
1366 | //\r | |
5dc4fd78 | 1367 | PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r |
1a3eaf06 | 1368 | StartAddress += sizeof (UINT16);\r |
1369 | Size -= sizeof (UINT16);\r | |
1370 | Buffer = (UINT16*)Buffer + 1;\r | |
1371 | }\r | |
1372 | \r | |
1373 | while (Size >= sizeof (UINT32)) {\r | |
1374 | //\r | |
1375 | // Write as many double words as possible\r | |
1376 | //\r | |
5dc4fd78 | 1377 | PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer));\r |
1a3eaf06 | 1378 | StartAddress += sizeof (UINT32);\r |
1379 | Size -= sizeof (UINT32);\r | |
1380 | Buffer = (UINT32*)Buffer + 1;\r | |
1381 | }\r | |
1382 | \r | |
1383 | if (Size >= sizeof (UINT16)) {\r | |
1384 | //\r | |
1385 | // Write the last remaining word if exist\r | |
1386 | //\r | |
5dc4fd78 | 1387 | PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r |
1a3eaf06 | 1388 | StartAddress += sizeof (UINT16);\r |
1389 | Size -= sizeof (UINT16);\r | |
1390 | Buffer = (UINT16*)Buffer + 1;\r | |
1391 | }\r | |
1392 | \r | |
1393 | if (Size >= sizeof (UINT8)) {\r | |
1394 | //\r | |
1395 | // Write the last remaining byte if exist\r | |
1396 | //\r | |
1397 | PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);\r | |
1398 | }\r | |
1399 | \r | |
1400 | return ReturnValue;\r | |
1401 | }\r |