]>
Commit | Line | Data |
---|---|---|
4e48c72c GS |
1 | /** @file\r |
2 | OVMF Platform definitions\r | |
3 | \r | |
cb2e3007 | 4 | Copyright (C) 2015, Red Hat, Inc.\r |
4e48c72c GS |
5 | Copyright (c) 2014, Gabriel L. Somlo <somlo@cmu.edu>\r |
6 | \r | |
b26f0cf9 | 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
4e48c72c GS |
8 | **/\r |
9 | \r | |
10 | #ifndef __OVMF_PLATFORMS_H__\r | |
11 | #define __OVMF_PLATFORMS_H__\r | |
12 | \r | |
13 | #include <Library/PciLib.h>\r | |
14 | #include <IndustryStandard/Pci22.h>\r | |
cb2e3007 LE |
15 | #include <IndustryStandard/Q35MchIch9.h>\r |
16 | #include <IndustryStandard/I440FxPiix4.h>\r | |
4e48c72c GS |
17 | \r |
18 | //\r | |
19 | // OVMF Host Bridge DID Address\r | |
20 | //\r | |
21 | #define OVMF_HOSTBRIDGE_DID \\r | |
22 | PCI_LIB_ADDRESS (0, 0, 0, PCI_DEVICE_ID_OFFSET)\r | |
23 | \r | |
b2f4da39 LE |
24 | //\r |
25 | // Values we program into the PM base address registers\r | |
26 | //\r | |
27 | #define PIIX4_PMBA_VALUE 0xB000\r | |
b97af6d4 | 28 | #define ICH9_PMBASE_VALUE 0x0600\r |
b2f4da39 | 29 | \r |
cc5e0aa9 LE |
30 | //\r |
31 | // Common bits in same-purpose registers\r | |
32 | //\r | |
33 | #define PMBA_RTE BIT0\r | |
34 | \r | |
35 | //\r | |
36 | // Common IO ports relative to the Power Management Base Address\r | |
37 | //\r | |
38 | #define ACPI_TIMER_OFFSET 0x8\r | |
39 | \r | |
4e48c72c | 40 | #endif\r |