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Commit | Line | Data |
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7b202cb0 | 1 | ## @file\r |
49ba9447 | 2 | # EFI/Framework Open Virtual Machine Firmware (OVMF) platform\r |
3 | #\r | |
e557442e | 4 | # Copyright (c) 2020, Rebecca Cran <rebecca@bsdio.com>\r |
10fa47e5 | 5 | # Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r |
e557442e | 6 | # Copyright (c) 2014, Pluribus Networks, Inc.\r |
49ba9447 | 7 | #\r |
b26f0cf9 | 8 | # SPDX-License-Identifier: BSD-2-Clause-Patent\r |
49ba9447 | 9 | #\r |
7b202cb0 | 10 | ##\r |
49ba9447 | 11 | \r |
12 | [Defines]\r | |
46293a42 | 13 | DEC_SPECIFICATION = 0x00010005\r |
49ba9447 | 14 | PACKAGE_NAME = OvmfPkg\r |
15 | PACKAGE_GUID = 2daf5f34-50e5-4b9d-b8e3-5562334d87e5\r | |
16 | PACKAGE_VERSION = 0.1\r | |
17 | \r | |
50944545 | 18 | [Includes]\r |
19 | Include\r | |
eb7cad3f | 20 | Csm/Include\r |
50944545 | 21 | \r |
28b29a70 | 22 | [LibraryClasses]\r |
e557442e LE |
23 | ## @libraryclass Access bhyve's firmware control interface.\r |
24 | BhyveFwCtlLib|Include/Library/BhyveFwCtlLib.h\r | |
0cb48007 DM |
25 | \r |
26 | ## @libraryclass Verify blobs read from the VMM\r | |
27 | BlobVerifierLib|Include/Library/BlobVerifierLib.h\r | |
e557442e | 28 | \r |
f6c6c020 | 29 | ## @libraryclass Loads and boots a Linux kernel image\r |
30 | #\r | |
31 | LoadLinuxLib|Include/Library/LoadLinuxLib.h\r | |
32 | \r | |
7cfc48fe LE |
33 | ## @libraryclass Declares helper functions for Secure Encrypted\r |
34 | # Virtualization (SEV) guests.\r | |
35 | MemEncryptSevLib|Include/Library/MemEncryptSevLib.h\r | |
36 | \r | |
28b29a70 | 37 | ## @libraryclass Save and restore variables using a file\r |
38 | #\r | |
39 | NvVarsFileLib|Include/Library/NvVarsFileLib.h\r | |
40 | \r | |
392a3146 LE |
41 | ## @libraryclass Provides services to work with PCI capabilities in PCI\r |
42 | # config space.\r | |
43 | PciCapLib|Include/Library/PciCapLib.h\r | |
44 | \r | |
02b9a834 LE |
45 | ## @libraryclass Layered on top of PciCapLib, allows clients to plug an\r |
46 | # EFI_PCI_IO_PROTOCOL backend into PciCapLib, for config\r | |
47 | # space access.\r | |
48 | PciCapPciIoLib|Include/Library/PciCapPciIoLib.h\r | |
49 | \r | |
6a744d40 LE |
50 | ## @libraryclass Layered on top of PciCapLib, allows clients to plug a\r |
51 | # PciSegmentLib backend into PciCapLib, for config space\r | |
52 | # access.\r | |
53 | PciCapPciSegmentLib|Include/Library/PciCapPciSegmentLib.h\r | |
54 | \r | |
7a6172f8 JC |
55 | ## @libraryclass Provide common utility functions to PciHostBridgeLib\r |
56 | # instances in ArmVirtPkg and OvmfPkg.\r | |
57 | PciHostBridgeUtilityLib|Include/Library/PciHostBridgeUtilityLib.h\r | |
58 | \r | |
77874cee LE |
59 | ## @libraryclass Register a status code handler for printing the Boot\r |
60 | # Manager's LoadImage() and StartImage() preparations, and\r | |
61 | # return codes, to the UEFI console.\r | |
62 | PlatformBmPrintScLib|Include/Library/PlatformBmPrintScLib.h\r | |
63 | \r | |
7cfc48fe LE |
64 | ## @libraryclass Customize FVB2 protocol member functions for a platform.\r |
65 | PlatformFvbLib|Include/Library/PlatformFvbLib.h\r | |
66 | \r | |
f1ec65ba | 67 | ## @libraryclass Access QEMU's firmware configuration interface\r |
68 | #\r | |
69 | QemuFwCfgLib|Include/Library/QemuFwCfgLib.h\r | |
70 | \r | |
f70b071e LE |
71 | ## @libraryclass S3 support for QEMU fw_cfg\r |
72 | #\r | |
73 | QemuFwCfgS3Lib|Include/Library/QemuFwCfgS3Lib.h\r | |
74 | \r | |
611c7f11 LE |
75 | ## @libraryclass Parse the contents of named fw_cfg files as simple\r |
76 | # (scalar) data types.\r | |
77 | QemuFwCfgSimpleParserLib|Include/Library/QemuFwCfgSimpleParserLib.h\r | |
78 | \r | |
cca7475b LE |
79 | ## @libraryclass Rewrite the BootOrder NvVar based on QEMU's "bootorder"\r |
80 | # fw_cfg file.\r | |
81 | #\r | |
82 | QemuBootOrderLib|Include/Library/QemuBootOrderLib.h\r | |
83 | \r | |
28de1a55 AB |
84 | ## @libraryclass Load a kernel image and command line passed to QEMU via\r |
85 | # the command line\r | |
86 | #\r | |
87 | QemuLoadImageLib|Include/Library/QemuLoadImageLib.h\r | |
88 | \r | |
28b29a70 | 89 | ## @libraryclass Serialize (and deserialize) variables\r |
90 | #\r | |
91 | SerializeVariablesLib|Include/Library/SerializeVariablesLib.h\r | |
92 | \r | |
7cfc48fe LE |
93 | ## @libraryclass Declares utility functions for virtio device drivers.\r |
94 | VirtioLib|Include/Library/VirtioLib.h\r | |
95 | \r | |
96 | ## @libraryclass Install Virtio Device Protocol instances on virtio-mmio\r | |
97 | # transports.\r | |
98 | VirtioMmioDeviceLib|Include/Library/VirtioMmioDeviceLib.h\r | |
99 | \r | |
cd8ff8fd AB |
100 | ## @libraryclass Invoke Xen hypercalls\r |
101 | #\r | |
102 | XenHypercallLib|Include/Library/XenHypercallLib.h\r | |
103 | \r | |
0169352e AB |
104 | ## @libraryclass Manage XenBus device path and I/O handles\r |
105 | #\r | |
106 | XenIoMmioLib|Include/Library/XenIoMmioLib.h\r | |
107 | \r | |
f496443e AP |
108 | ## @libraryclass Get information about Xen\r |
109 | #\r | |
110 | XenPlatformLib|Include/Library/XenPlatformLib.h\r | |
111 | \r | |
7b202cb0 | 112 | [Guids]\r |
1dc875a7 AB |
113 | gUefiOvmfPkgTokenSpaceGuid = {0x93bb96af, 0xb9f2, 0x4eb8, {0x94, 0x62, 0xe0, 0xba, 0x74, 0x56, 0x42, 0x36}}\r |
114 | gEfiXenInfoGuid = {0xd3b46f3b, 0xd441, 0x1244, {0x9a, 0x12, 0x0, 0x12, 0x27, 0x3f, 0xc1, 0x4d}}\r | |
115 | gOvmfPkKek1AppPrefixGuid = {0x4e32566d, 0x8e9e, 0x4f52, {0x81, 0xd3, 0x5b, 0xb9, 0x71, 0x5f, 0x97, 0x27}}\r | |
116 | gOvmfPlatformConfigGuid = {0x7235c51c, 0x0c80, 0x4cab, {0x87, 0xac, 0x3b, 0x08, 0x4a, 0x63, 0x04, 0xb1}}\r | |
117 | gVirtioMmioTransportGuid = {0x837dca9e, 0xe874, 0x4d82, {0xb2, 0x9a, 0x23, 0xfe, 0x0e, 0x23, 0xd1, 0xe2}}\r | |
118 | gQemuRamfbGuid = {0x557423a1, 0x63ab, 0x406c, {0xbe, 0x7e, 0x91, 0xcd, 0xbc, 0x08, 0xc4, 0x57}}\r | |
119 | gXenBusRootDeviceGuid = {0xa732241f, 0x383d, 0x4d9c, {0x8a, 0xe1, 0x8e, 0x09, 0x83, 0x75, 0x89, 0xd7}}\r | |
120 | gRootBridgesConnectedEventGroupGuid = {0x24a2d66f, 0xeedd, 0x4086, {0x90, 0x42, 0xf2, 0x6e, 0x47, 0x97, 0xee, 0x69}}\r | |
121 | gMicrosoftVendorGuid = {0x77fa9abd, 0x0359, 0x4d32, {0xbd, 0x60, 0x28, 0xf4, 0xe7, 0x8f, 0x78, 0x4b}}\r | |
122 | gEfiLegacyBiosGuid = {0x2E3044AC, 0x879F, 0x490F, {0x97, 0x60, 0xBB, 0xDF, 0xAF, 0x69, 0x5F, 0x50}}\r | |
123 | gEfiLegacyDevOrderVariableGuid = {0xa56074db, 0x65fe, 0x45f7, {0xbd, 0x21, 0x2d, 0x2b, 0xdd, 0x8e, 0x96, 0x52}}\r | |
1dc875a7 | 124 | gQemuKernelLoaderFsMediaGuid = {0x1428f772, 0xb64a, 0x441e, {0xb8, 0xc3, 0x9e, 0xbd, 0xd7, 0xf8, 0x93, 0xc7}}\r |
b261a30c | 125 | gGrubFileGuid = {0xb5ae312c, 0xbc8a, 0x43b1, {0x9c, 0x62, 0xeb, 0xb8, 0x26, 0xdd, 0x5d, 0x07}}\r |
96201ae7 | 126 | gConfidentialComputingSecretGuid = {0xadf956ad, 0xe98c, 0x484c, {0xae, 0x11, 0xb5, 0x1c, 0x7d, 0x33, 0x64, 0x47}}\r |
49ba9447 | 127 | \r |
6b3d196a AB |
128 | [Ppis]\r |
129 | # PPI whose presence in the PPI database signals that the TPM base address\r | |
130 | # has been discovered and recorded\r | |
1dc875a7 | 131 | gOvmfTpmDiscoveredPpiGuid = {0xb9a61ad0, 0x2802, 0x41f3, {0xb5, 0x13, 0x96, 0x51, 0xce, 0x6b, 0xd5, 0x75}}\r |
6b3d196a | 132 | \r |
a3f12cd4 TL |
133 | # This PPI signals that accessing the MMIO range of the TPM is possible in\r |
134 | # the PEI phase, regardless of memory encryption\r | |
135 | gOvmfTpmMmioAccessiblePpiGuid = {0x35c84ff2, 0x7bfe, 0x453d, {0x84, 0x5f, 0x68, 0x3a, 0x49, 0x2c, 0xf7, 0xb7}}\r | |
136 | \r | |
b0f51446 | 137 | [Protocols]\r |
1dc875a7 AB |
138 | gVirtioDeviceProtocolGuid = {0xfa920010, 0x6785, 0x4941, {0xb6, 0xec, 0x49, 0x8c, 0x57, 0x9f, 0x16, 0x0a}}\r |
139 | gXenBusProtocolGuid = {0x3d3ca290, 0xb9a5, 0x11e3, {0xb7, 0x5d, 0xb8, 0xac, 0x6f, 0x7d, 0x65, 0xe6}}\r | |
140 | gXenIoProtocolGuid = {0x6efac84f, 0x0ab0, 0x4747, {0x81, 0xbe, 0x85, 0x55, 0x62, 0x59, 0x04, 0x49}}\r | |
141 | gIoMmuAbsentProtocolGuid = {0xf8775d50, 0x8abd, 0x4adf, {0x92, 0xac, 0x85, 0x3e, 0x51, 0xf6, 0xc8, 0xdc}}\r | |
142 | gEfiLegacy8259ProtocolGuid = {0x38321dba, 0x4fe0, 0x4e17, {0x8a, 0xec, 0x41, 0x30, 0x55, 0xea, 0xed, 0xc1}}\r | |
143 | gEfiFirmwareVolumeProtocolGuid = {0x389F751F, 0x1838, 0x4388, {0x83, 0x90, 0xcd, 0x81, 0x54, 0xbd, 0x27, 0xf8}}\r | |
144 | gEfiIsaAcpiProtocolGuid = {0x64a892dc, 0x5561, 0x4536, {0x92, 0xc7, 0x79, 0x9b, 0xfc, 0x18, 0x33, 0x55}}\r | |
145 | gEfiIsaIoProtocolGuid = {0x7ee2bd44, 0x3da0, 0x11d4, {0x9a, 0x38, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d}}\r | |
146 | gEfiLegacyBiosProtocolGuid = {0xdb9a1e3d, 0x45cb, 0x4abb, {0x85, 0x3b, 0xe5, 0x38, 0x7f, 0xdb, 0x2e, 0x2d}}\r | |
147 | gEfiLegacyBiosPlatformProtocolGuid = {0x783658a3, 0x4172, 0x4421, {0xa2, 0x99, 0xe0, 0x09, 0x07, 0x9c, 0x0c, 0xb4}}\r | |
148 | gEfiLegacyInterruptProtocolGuid = {0x31ce593d, 0x108a, 0x485d, {0xad, 0xb2, 0x78, 0xf2, 0x1f, 0x29, 0x66, 0xbe}}\r | |
149 | gEfiVgaMiniPortProtocolGuid = {0xc7735a2f, 0x88f5, 0x4882, {0xae, 0x63, 0xfa, 0xac, 0x8c, 0x8b, 0x86, 0xb3}}\r | |
150 | gOvmfLoadedX86LinuxKernelProtocolGuid = {0xa3edc05d, 0xb618, 0x4ff6, {0x95, 0x52, 0x76, 0xd7, 0x88, 0x63, 0x43, 0xc8}}\r | |
b0f51446 | 151 | \r |
61069836 | 152 | [PcdsFixedAtBuild]\r |
b36f701d JJ |
153 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase|0x0|UINT32|0\r |
154 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvSize|0x0|UINT32|1\r | |
155 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase|0x0|UINT32|0x15\r | |
156 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize|0x0|UINT32|0x16\r | |
61069836 | 157 | \r |
b90aefa9 | 158 | ## This flag is used to control the destination port for PlatformDebugLibIoPort\r |
159 | gUefiOvmfPkgTokenSpaceGuid.PcdDebugIoPort|0x402|UINT16|4\r | |
160 | \r | |
37078a63 | 161 | ## When VirtioScsiDxe is instantiated for a HBA, the numbers of targets and\r |
162 | # LUNs are retrieved from the host during virtio-scsi setup.\r | |
163 | # MdeModulePkg/Bus/Scsi/ScsiBusDxe then scans all MaxTarget * MaxLun\r | |
164 | # possible devices. This can take extremely long, for example with\r | |
165 | # MaxTarget=255 and MaxLun=16383. The *inclusive* constants below limit\r | |
166 | # MaxTarget and MaxLun, independently, should the host report higher values,\r | |
167 | # so that scanning the number of devices given by their product is still\r | |
168 | # acceptably fast.\r | |
169 | gUefiOvmfPkgTokenSpaceGuid.PcdVirtioScsiMaxTargetLimit|31|UINT16|6\r | |
170 | gUefiOvmfPkgTokenSpaceGuid.PcdVirtioScsiMaxLunLimit|7|UINT32|7\r | |
171 | \r | |
7efce2e5 LA |
172 | ## Sets the *inclusive* number of targets and LUNs that PvScsi exposes for\r |
173 | # scan by ScsiBusDxe.\r | |
174 | # As specified above for VirtioScsi, ScsiBusDxe scans all MaxTarget * MaxLun\r | |
175 | # possible devices, which can take extremely long. Thus, the below constants\r | |
176 | # are used so that scanning the number of devices given by their product\r | |
177 | # is still acceptably fast.\r | |
178 | gUefiOvmfPkgTokenSpaceGuid.PcdPvScsiMaxTargetLimit|64|UINT8|0x36\r | |
179 | gUefiOvmfPkgTokenSpaceGuid.PcdPvScsiMaxLunLimit|0|UINT8|0x37\r | |
180 | \r | |
c4c15b87 LA |
181 | ## After PvScsiDxe sends a SCSI request to the device, it waits for\r |
182 | # the request completion in a polling loop.\r | |
183 | # This constant defines how many micro-seconds to wait between each\r | |
184 | # polling loop iteration.\r | |
185 | gUefiOvmfPkgTokenSpaceGuid.PcdPvScsiWaitForCmpStallInUsecs|5|UINT32|0x38\r | |
186 | \r | |
093cceaf NL |
187 | ## Set the *inclusive* number of targets that MptScsi exposes for scan\r |
188 | # by ScsiBusDxe.\r | |
189 | gUefiOvmfPkgTokenSpaceGuid.PcdMptScsiMaxTargetLimit|7|UINT8|0x39\r | |
190 | \r | |
505812ae | 191 | ## Microseconds to stall between polling for MptScsi request result\r |
d9269d69 | 192 | gUefiOvmfPkgTokenSpaceGuid.PcdMptScsiStallPerPollUsec|5|UINT32|0x3a\r |
505812ae | 193 | \r |
12d99b8f GL |
194 | ## Set the *inclusive* number of targets and LUNs that LsiScsi exposes for\r |
195 | # scan by ScsiBusDxe.\r | |
196 | gUefiOvmfPkgTokenSpaceGuid.PcdLsiScsiMaxTargetLimit|7|UINT8|0x3b\r | |
197 | gUefiOvmfPkgTokenSpaceGuid.PcdLsiScsiMaxLunLimit|0|UINT8|0x3c\r | |
198 | \r | |
31830b07 GL |
199 | ## Microseconds to stall between polling for LsiScsi request result\r |
200 | gUefiOvmfPkgTokenSpaceGuid.PcdLsiScsiStallPerPollUsec|5|UINT32|0x3d\r | |
201 | \r | |
501e08fc JJ |
202 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogBase|0x0|UINT32|0x8\r |
203 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogSize|0x0|UINT32|0x9\r | |
204 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize|0x0|UINT32|0xa\r | |
205 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareBlockSize|0|UINT32|0xb\r | |
206 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageVariableBase|0x0|UINT32|0xc\r | |
207 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwSpareBase|0x0|UINT32|0xd\r | |
208 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwWorkingBase|0x0|UINT32|0xe\r | |
209 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress|0x0|UINT32|0xf\r | |
b382ede3 JJ |
210 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesBase|0x0|UINT32|0x11\r |
211 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesSize|0x0|UINT32|0x12\r | |
7cb6b0e0 JJ |
212 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase|0x0|UINT32|0x13\r |
213 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize|0x0|UINT32|0x14\r | |
6a7cba79 LE |
214 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageBase|0x0|UINT32|0x18\r |
215 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageSize|0x0|UINT32|0x19\r | |
ad43bc6b | 216 | gUefiOvmfPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize|0x0|UINT32|0x1a\r |
9beac0d8 | 217 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDecompressionScratchEnd|0x0|UINT32|0x1f\r |
501e08fc | 218 | \r |
460ffed2 HW |
219 | ## Pcd8259LegacyModeMask defines the default mask value for platform. This\r |
220 | # value is determined.\r | |
221 | # 1) If platform only support pure UEFI, value should be set to 0xFFFF or\r | |
222 | # 0xFFFE; Because only clock interrupt is allowed in legacy mode in pure\r | |
223 | # UEFI platform.\r | |
224 | # 2) If platform install CSM and use thunk module:\r | |
225 | # a) If thunk call provided by CSM binary requires some legacy interrupt\r | |
226 | # support, the corresponding bit should be opened as 0.\r | |
227 | # For example, if keyboard interfaces provided CSM binary use legacy\r | |
228 | # keyboard interrupt in 8259 bit 1, then the value should be set to\r | |
229 | # 0xFFFC.\r | |
230 | # b) If all thunk call provied by CSM binary do not require legacy\r | |
231 | # interrupt support, value should be set to 0xFFFF or 0xFFFE.\r | |
232 | #\r | |
233 | # The default value of legacy mode mask could be changed by\r | |
234 | # EFI_LEGACY_8259_PROTOCOL->SetMask(). But it is rarely need change it\r | |
235 | # except some special cases such as when initializing the CSM binary, it\r | |
236 | # should be set to 0xFFFF to mask all legacy interrupt. Please restore the\r | |
237 | # original legacy mask value if changing is made for these special case.\r | |
238 | gUefiOvmfPkgTokenSpaceGuid.Pcd8259LegacyModeMask|0xFFFF|UINT16|0x3\r | |
239 | \r | |
240 | ## Pcd8259LegacyModeEdgeLevel defines the default edge level for legacy\r | |
241 | # mode's interrrupt controller.\r | |
242 | # For the corresponding bits, 0 = Edge triggered and 1 = Level triggered.\r | |
243 | gUefiOvmfPkgTokenSpaceGuid.Pcd8259LegacyModeEdgeLevel|0x0000|UINT16|0x5\r | |
244 | \r | |
51e55d81 HW |
245 | ## Indicates if BiosVideo driver will switch to 80x25 Text VGA Mode when\r |
246 | # exiting boot service.\r | |
247 | # TRUE - Switch to Text VGA Mode.\r | |
248 | # FALSE - Does not switch to Text VGA Mode.\r | |
249 | gUefiOvmfPkgTokenSpaceGuid.PcdBiosVideoSetTextVgaModeEnable|FALSE|BOOLEAN|0x28\r | |
250 | \r | |
251 | ## Indicates if BiosVideo driver will check for VESA BIOS Extension service\r | |
252 | # support.\r | |
253 | # TRUE - Check for VESA BIOS Extension service.\r | |
254 | # FALSE - Does not check for VESA BIOS Extension service.\r | |
255 | gUefiOvmfPkgTokenSpaceGuid.PcdBiosVideoCheckVbeEnable|TRUE|BOOLEAN|0x29\r | |
256 | \r | |
257 | ## Indicates if BiosVideo driver will check for VGA service support.\r | |
258 | # NOTE: If both PcdBiosVideoCheckVbeEnable and PcdBiosVideoCheckVgaEnable\r | |
259 | # are set to FALSE, that means Graphics Output protocol will not be\r | |
260 | # installed, the VGA miniport protocol will be installed instead.\r | |
261 | # TRUE - Check for VGA service.<BR>\r | |
262 | # FALSE - Does not check for VGA service.<BR>\r | |
263 | gUefiOvmfPkgTokenSpaceGuid.PcdBiosVideoCheckVgaEnable|TRUE|BOOLEAN|0x2a\r | |
264 | \r | |
265 | ## Indicates if memory space for legacy region will be set as cacheable.\r | |
266 | # TRUE - Set cachebility for legacy region.\r | |
267 | # FALSE - Does not set cachebility for legacy region.\r | |
268 | gUefiOvmfPkgTokenSpaceGuid.PcdLegacyBiosCacheLegacyRegion|TRUE|BOOLEAN|0x2b\r | |
269 | \r | |
270 | ## Specify memory size with bytes to reserve EBDA below 640K for OPROM.\r | |
271 | # The value should be a multiple of 4KB.\r | |
272 | gUefiOvmfPkgTokenSpaceGuid.PcdEbdaReservedMemorySize|0x8000|UINT32|0x2c\r | |
273 | \r | |
274 | ## Specify memory base address for OPROM to find free memory.\r | |
275 | # Some OPROMs do not use EBDA or PMM to allocate memory for its usage,\r | |
276 | # instead they find the memory filled with zero from 0x20000.\r | |
277 | # The value should be a multiple of 4KB.\r | |
278 | # The range should be below the EBDA reserved range from\r | |
279 | # (CONVENTIONAL_MEMORY_TOP - Reserved EBDA Memory Size) to\r | |
280 | # CONVENTIONAL_MEMORY_TOP.\r | |
281 | gUefiOvmfPkgTokenSpaceGuid.PcdOpromReservedMemoryBase|0x60000|UINT32|0x2d\r | |
282 | \r | |
283 | ## Specify memory size with bytes for OPROM to find free memory.\r | |
284 | # The value should be a multiple of 4KB. And the range should be below the\r | |
285 | # EBDA reserved range from\r | |
286 | # (CONVENTIONAL_MEMORY_TOP - Reserved EBDA Memory Size) to\r | |
287 | # CONVENTIONAL_MEMORY_TOP.\r | |
288 | gUefiOvmfPkgTokenSpaceGuid.PcdOpromReservedMemorySize|0x28000|UINT32|0x2e\r | |
289 | \r | |
290 | ## Specify the end of address below 1MB for the OPROM.\r | |
291 | # The last shadowed OpROM should not exceed this address.\r | |
292 | gUefiOvmfPkgTokenSpaceGuid.PcdEndOpromShadowAddress|0xdffff|UINT32|0x2f\r | |
293 | \r | |
294 | ## Specify the low PMM (Post Memory Manager) size with bytes below 1MB.\r | |
295 | # The value should be a multiple of 4KB.\r | |
296 | # @Prompt Low PMM (Post Memory Manager) Size\r | |
297 | gUefiOvmfPkgTokenSpaceGuid.PcdLowPmmMemorySize|0x10000|UINT32|0x30\r | |
298 | \r | |
299 | ## Specify the high PMM (Post Memory Manager) size with bytes above 1MB.\r | |
300 | # The value should be a multiple of 4KB.\r | |
301 | gUefiOvmfPkgTokenSpaceGuid.PcdHighPmmMemorySize|0x400000|UINT32|0x31\r | |
302 | \r | |
93314ae5 AP |
303 | gUefiOvmfPkgTokenSpaceGuid.PcdXenPvhStartOfDayStructPtr|0x0|UINT32|0x17\r |
304 | gUefiOvmfPkgTokenSpaceGuid.PcdXenPvhStartOfDayStructPtrSize|0x0|UINT32|0x32\r | |
305 | \r | |
8f39d79d AP |
306 | ## Number of page frames to use for storing grant table entries.\r |
307 | gUefiOvmfPkgTokenSpaceGuid.PcdXenGrantFrames|4|UINT32|0x33\r | |
308 | \r | |
6995a1b7 TL |
309 | ## Specify the extra page table needed to mark the GHCB as unencrypted.\r |
310 | # The value should be a multiple of 4KB for each.\r | |
311 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableBase|0x0|UINT32|0x3e\r | |
312 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableSize|0x0|UINT32|0x3f\r | |
313 | \r | |
314 | ## The base address of the SEC GHCB page used by SEV-ES.\r | |
315 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBase|0|UINT32|0x40\r | |
316 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbSize|0|UINT32|0x41\r | |
5667dc43 TL |
317 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupBase|0|UINT32|0x44\r |
318 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupSize|0|UINT32|0x45\r | |
6995a1b7 | 319 | \r |
224752ec JB |
320 | ## The base address and size of the SEV Launch Secret Area provisioned\r |
321 | # after remote attestation. If this is set in the .fdf, the platform\r | |
322 | # is responsible for protecting the area from DXE phase overwrites.\r | |
323 | gUefiOvmfPkgTokenSpaceGuid.PcdSevLaunchSecretBase|0x0|UINT32|0x42\r | |
324 | gUefiOvmfPkgTokenSpaceGuid.PcdSevLaunchSecretSize|0x0|UINT32|0x43\r | |
325 | \r | |
0deeab36 JB |
326 | ## The base address and size of a hash table confirming allowed\r |
327 | # parameters to be passed in via the Qemu firmware configuration\r | |
328 | # device\r | |
329 | gUefiOvmfPkgTokenSpaceGuid.PcdQemuHashTableBase|0x0|UINT32|0x47\r | |
330 | gUefiOvmfPkgTokenSpaceGuid.PcdQemuHashTableSize|0x0|UINT32|0x48\r | |
331 | \r | |
80e67af9 BS |
332 | ## The base address and size of the work area used during the SEC\r |
333 | # phase by the SEV and TDX supports.\r | |
334 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaBase|0|UINT32|0x49\r | |
335 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaSize|0|UINT32|0x50\r | |
336 | \r | |
337 | ## The work area contains a fixed size header in the Include/WorkArea.h.\r | |
338 | # The size of this header is used early boot, and is provided through\r | |
339 | # a fixed PCD. It need to be kept in sync with any changes to the\r | |
340 | # header definition.\r | |
79019c7a | 341 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfConfidentialComputingWorkAreaHeader|4|UINT32|0x51\r |
80e67af9 | 342 | \r |
c9ec74a1 MX |
343 | ## The base address and size of the TDX Cfv base and size.\r |
344 | gUefiOvmfPkgTokenSpaceGuid.PcdCfvBase|0|UINT32|0x52\r | |
345 | gUefiOvmfPkgTokenSpaceGuid.PcdCfvRawDataOffset|0|UINT32|0x53\r | |
346 | gUefiOvmfPkgTokenSpaceGuid.PcdCfvRawDataSize|0|UINT32|0x54\r | |
347 | \r | |
348 | ## The base address and size of the TDX Bfv base and size.\r | |
349 | gUefiOvmfPkgTokenSpaceGuid.PcdBfvBase|0|UINT32|0x55\r | |
350 | gUefiOvmfPkgTokenSpaceGuid.PcdBfvRawDataOffset|0|UINT32|0x56\r | |
351 | gUefiOvmfPkgTokenSpaceGuid.PcdBfvRawDataSize|0|UINT32|0x57\r | |
80e67af9 | 352 | \r |
70c66df5 | 353 | [PcdsDynamic, PcdsDynamicEx]\r |
85c0b5ee | 354 | gUefiOvmfPkgTokenSpaceGuid.PcdEmuVariableEvent|0|UINT64|2\r |
9d35ac26 | 355 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable|FALSE|BOOLEAN|0x10\r |
d55004da | 356 | gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId|0|UINT16|0x1b\r |
6fbef93e | 357 | gUefiOvmfPkgTokenSpaceGuid.PcdQemuSmbiosValidated|FALSE|BOOLEAN|0x21\r |
49ba9447 | 358 | \r |
c4df7fd0 LE |
359 | ## The IO port aperture shared by all PCI root bridges.\r |
360 | #\r | |
361 | gUefiOvmfPkgTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x22\r | |
362 | gUefiOvmfPkgTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x23\r | |
363 | \r | |
03845e90 LE |
364 | ## The 32-bit MMIO aperture shared by all PCI root bridges.\r |
365 | #\r | |
366 | gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT64|0x24\r | |
367 | gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT64|0x25\r | |
368 | \r | |
7e5b1b67 LE |
369 | ## The 64-bit MMIO aperture shared by all PCI root bridges.\r |
370 | #\r | |
371 | gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x26\r | |
372 | gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x27\r | |
373 | \r | |
966dbaf4 | 374 | ## The following setting controls how many megabytes we configure as TSEG on\r |
d04b72c6 LE |
375 | # Q35, for SMRAM purposes. Permitted defaults are: 1, 2, 8. Other defaults\r |
376 | # cause undefined behavior. During boot, the PCD is updated by PlatformPei\r | |
377 | # to reflect the extended TSEG size, if one is advertized by QEMU.\r | |
966dbaf4 | 378 | #\r |
d04b72c6 | 379 | # This PCD is only accessed if PcdSmmSmramRequire is TRUE (see below).\r |
966dbaf4 LE |
380 | gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes|8|UINT16|0x20\r |
381 | \r | |
d74d56fc LE |
382 | ## Set to TRUE by PlatformPei if the Q35 board supports the "SMRAM at default\r |
383 | # SMBASE" feature.\r | |
384 | #\r | |
385 | # This PCD is only accessed if PcdSmmSmramRequire is TRUE (see below).\r | |
386 | gUefiOvmfPkgTokenSpaceGuid.PcdQ35SmramAtDefaultSmbase|FALSE|BOOLEAN|0x34\r | |
387 | \r | |
8ade9d42 AA |
388 | ## This PCD adds a communication channel between OVMF's SmmCpuFeaturesLib\r |
389 | # instance in PiSmmCpuDxeSmm, and CpuHotplugSmm.\r | |
390 | gUefiOvmfPkgTokenSpaceGuid.PcdCpuHotEjectDataAddress|0|UINT64|0x46\r | |
391 | \r | |
e05061c5 | 392 | [PcdsFeatureFlag]\r |
2f9c55cc | 393 | gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderPciTranslation|TRUE|BOOLEAN|0x1c\r |
43336916 | 394 | gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderMmioTranslation|FALSE|BOOLEAN|0x1d\r |
1f695483 LE |
395 | \r |
396 | ## This feature flag enables SMM/SMRAM support. Note that it also requires\r | |
397 | # such support from the underlying QEMU instance; if that support is not\r | |
398 | # present, the firmware will reject continuing after a certain point.\r | |
399 | #\r | |
400 | # The flag also acts as a general "security switch"; when TRUE, many\r | |
401 | # components will change behavior, with the goal of preventing a malicious\r | |
402 | # runtime OS from tampering with firmware structures (special memory ranges\r | |
403 | # used by OVMF, the varstore pflash chip, LockBox etc).\r | |
404 | gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire|FALSE|BOOLEAN|0x1e\r | |
50f911d2 LE |
405 | \r |
406 | ## Informs modules (including pre-DXE-phase modules) whether the platform\r | |
407 | # firmware contains a CSM (Compatibility Support Module).\r | |
408 | #\r | |
409 | gUefiOvmfPkgTokenSpaceGuid.PcdCsmEnable|FALSE|BOOLEAN|0x35\r |